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/trunk/Doc/UART_spec.pdf
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/trunk/CHANGES.txt
1,5 → 1,20
Note: This Changes file is being maintained since 25.5.2001. |
|
23.06.2001 |
~~~~~~~~~~ |
|
* With the help of Bob Kirstein another two bugs were fixed: |
1. Trasmitter was sending stop bit two 16xclock cycle slonger than needed. |
2. Receiver was losing 1 16xclock cycle on each character and went out of sync. |
|
* Major change: |
I have modified the divisor latch register to be 16-bit long instead of 32 as I thought was |
necessary for higher speed systems. Thanks to Rick Wright for pointing this out. |
So now, DL3 and DL4 register bytes are not used. |
Documentation is updated to follow this change. |
|
* Note that more than 1 stop bit in a byte i snot implemented. |
|
2.05.2001 |
~~~~~~~~~ |
|
/trunk/verilog/UART_regs.v
61,6 → 61,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.9 2001/05/31 20:08:01 gorban |
// FIFO changes and other corrections. |
// |
// Revision 1.8 2001/05/29 20:05:04 gorban |
// Fixed some bugs and synthesis problems. |
// |
83,8 → 86,6
|
`define DL1 7:0 |
`define DL2 15:8 |
`define DL3 23:16 |
`define DL4 31:24 |
|
module UART_regs (clk, |
wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, |
130,12 → 131,12
reg [7:0] lcr; |
reg [7:0] lsr; |
reg [7:0] msr; |
reg [31:0] dl; // 32-bit divisor latch |
reg [15:0] dl; // 32-bit divisor latch |
reg start_dlc; // activate dlc on writing to DL1 |
reg lsr_mask; |
reg msi_reset; // reset MSR 4 lower bits indicator |
reg threi_clear; // THRE interrupt clear flag |
reg [31:0] dlc; // 32-bit divisor latch counter |
reg [15:0] dlc; // 32-bit divisor latch counter |
reg int_o; |
|
reg [3:0] trigger_level; // trigger level of the receiver FIFO |
203,13 → 204,8
`REG_IE : wb_dat_o <= #1 dlab ? dl[`DL2] : ier; |
`REG_II : wb_dat_o <= #1 {4'b1100,iir}; |
`REG_LC : wb_dat_o <= #1 lcr; |
`REG_LS : if (dlab) |
wb_dat_o <= #1 dl[`DL4]; |
else |
wb_dat_o <= #1 lsr; |
`REG_LS : wb_dat_o <= #1 lsr; |
`REG_MS : wb_dat_o <= #1 msr; |
`REG_DL3: wb_dat_o <= #1 dlab ? dl[`DL3] : 8'b0; |
|
default: wb_dat_o <= #1 8'b0; // ?? |
endcase |
else |
312,18 → 308,12
tx_reset <= #1 0; |
end |
|
// Modem Control Register or DL3 |
// Modem Control Register |
always @(posedge clk or posedge wb_rst_i) |
if (wb_rst_i) |
begin |
mcr <= #1 5'b0; |
dl[`DL3] <= #1 8'b0; |
end |
else |
if (wb_we_i && wb_addr_i==`REG_MC) |
if (dlab) |
dl[`DL3] <= #1 wb_dat_i; |
else |
mcr <= #1 wb_dat_i[4:0]; |
|
// TX_FIFO or DL1 |
362,14 → 352,6
2'b11 : trigger_level = 14; |
endcase |
|
// DL4 write |
always @(posedge clk or posedge wb_rst_i) |
if (wb_rst_i) |
dl[`DL4] <= #1 8'b0; |
else |
if (wb_we_i && wb_addr_i==`REG_DL4) |
dl[`DL4] <= #1 wb_dat_i; |
|
// |
// STATUS REGISTERS // |
// |
412,7 → 394,7
begin |
if (wb_rst_i) |
begin |
dlc <= #1 32'hffffff00; |
dlc <= #1 0; |
enable <= #1 1'b0; |
end |
else |
424,9 → 406,9
end |
else |
begin |
if (dl!=32'b0) |
if (dl!=0) |
begin |
if ( (dlc-1)==32'b0 ) |
if ( (dlc-1)==0 ) |
begin |
enable <= #1 1'b1; |
dlc <= #1 dl; |
439,7 → 421,7
end |
else |
begin |
dlc <= #1 32'hffffff0A; |
dlc <= #1 0; |
enable <= #1 1'b0; |
end |
end |
/trunk/verilog/UART_receiver.v
62,6 → 62,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2001/06/02 14:28:14 gorban |
// Fixed receiver and transmitter. Major bug fixed. |
// |
// Revision 1.4 2001/05/31 20:08:01 gorban |
// FIFO changes and other corrections. |
// |
138,6 → 141,8
|
wire rcounter16_eq_7 = (rcounter16 == 4'd7); |
wire rcounter16_eq_0 = (rcounter16 == 4'd0); |
wire rcounter16_eq_1 = (rcounter16 == 4'd1); |
|
wire [3:0] rcounter16_minus_1 = rcounter16 - 4'd1; |
|
`define SR_IDLE 4'd0 |
279,7 → 284,7
rstate <= #1 `SR_LAST; |
end |
`SR_LAST : begin |
if (rcounter16_eq_0) |
if (rcounter16_eq_1) |
rstate <= #1 `SR_IDLE; |
rcounter16 <= #1 rcounter16_minus_1; |
rf_push <= #1 1'b0; |
/trunk/verilog/UART_transmitter.v
62,6 → 62,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2001/06/02 14:28:14 gorban |
// Fixed receiver and transmitter. Major bug fixed. |
// |
// Revision 1.4 2001/05/31 20:08:01 gorban |
// FIFO changes and other corrections. |
// |
251,7 → 254,7
end |
`S_SEND_STOP : begin |
if (~|counter16) |
counter16 <= #1 4'b1111; |
counter16 <= #1 4'b1101; |
else |
if (counter16 == 4'b0001) |
begin |