URL
https://opencores.org/ocsvn/ac97/ac97/trunk
Subversion Repositories ac97
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 13 to Rev 14
- ↔ Reverse comparison
Rev 13 → Rev 14
/trunk/rtl/verilog/ac97_sin.v
12,8 → 12,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
38,10 → 39,10
|
// CVS Log |
// |
// $Id: ac97_sin.v,v 1.1 2001-08-03 06:54:50 rudi Exp $ |
// $Id: ac97_sin.v,v 1.2 2002-09-19 06:30:56 rudi Exp $ |
// |
// $Date: 2001-08-03 06:54:50 $ |
// $Revision: 1.1 $ |
// $Date: 2002-09-19 06:30:56 $ |
// $Revision: 1.2 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 49,11
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/03 06:54:50 rudi |
// |
// |
// - Changed to new directory structure |
// |
// Revision 1.1.1.1 2001/05/19 02:29:15 rudi |
// Initial Checkin |
// |
/trunk/rtl/verilog/ac97_int.v
12,8 → 12,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
38,10 → 39,10
|
// CVS Log |
// |
// $Id: ac97_int.v,v 1.2 2002-03-05 04:44:05 rudi Exp $ |
// $Id: ac97_int.v,v 1.3 2002-09-19 06:30:56 rudi Exp $ |
// |
// $Date: 2002-03-05 04:44:05 $ |
// $Revision: 1.2 $ |
// $Date: 2002-09-19 06:30:56 $ |
// $Revision: 1.3 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 49,11
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/03/05 04:44:05 rudi |
// |
// - Fixed the order of the thrash hold bits to match the spec. |
// - Many minor synthesis cleanup items ... |
// |
// Revision 1.1 2001/08/03 06:54:50 rudi |
// |
// |
/trunk/rtl/verilog/ac97_sout.v
12,8 → 12,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
38,10 → 39,10
|
// CVS Log |
// |
// $Id: ac97_sout.v,v 1.1 2001-08-03 06:54:50 rudi Exp $ |
// $Id: ac97_sout.v,v 1.2 2002-09-19 06:30:56 rudi Exp $ |
// |
// $Date: 2001-08-03 06:54:50 $ |
// $Revision: 1.1 $ |
// $Date: 2002-09-19 06:30:56 $ |
// $Revision: 1.2 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 49,11
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/03 06:54:50 rudi |
// |
// |
// - Changed to new directory structure |
// |
// Revision 1.1.1.1 2001/05/19 02:29:15 rudi |
// Initial Checkin |
// |
/trunk/rtl/verilog/ac97_top.v
11,8 → 11,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
37,10 → 38,10
|
// CVS Log |
// |
// $Id: ac97_top.v,v 1.3 2002-03-05 04:44:05 rudi Exp $ |
// $Id: ac97_top.v,v 1.4 2002-09-19 06:30:56 rudi Exp $ |
// |
// $Date: 2002-03-05 04:44:05 $ |
// $Revision: 1.3 $ |
// $Date: 2002-09-19 06:30:56 $ |
// $Revision: 1.4 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 48,11
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/03/05 04:44:05 rudi |
// |
// - Fixed the order of the thrash hold bits to match the spec. |
// - Many minor synthesis cleanup items ... |
// |
// Revision 1.2 2001/08/10 08:09:42 rudi |
// |
// - Removed RTY_O output. |
/trunk/rtl/verilog/ac97_cra.v
12,8 → 12,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
36,12 → 37,13
//// //// |
///////////////////////////////////////////////////////////////////// |
|
|
// CVS Log |
// |
// $Id: ac97_cra.v,v 1.2 2002-03-05 04:44:05 rudi Exp $ |
// $Id: ac97_cra.v,v 1.3 2002-09-19 06:30:56 rudi Exp $ |
// |
// $Date: 2002-03-05 04:44:05 $ |
// $Revision: 1.2 $ |
// $Date: 2002-09-19 06:30:56 $ |
// $Revision: 1.3 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 50,11
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/03/05 04:44:05 rudi |
// |
// - Fixed the order of the thrash hold bits to match the spec. |
// - Many minor synthesis cleanup items ... |
// |
// Revision 1.1 2001/08/03 06:54:49 rudi |
// |
// |
93,20 → 100,16
// Local Wires |
// |
|
reg crac_wr; |
reg crac_rd; |
reg crac_rd_done; |
reg crac_wr; |
reg crac_rd; |
reg crac_rd_done; |
reg [15:0] crac_din; |
reg crac_we_r; |
reg valid_r; |
wire valid_ne; |
wire valid_pe; |
reg rdd1, rdd2, rdd3; |
|
reg crac_we_r; |
|
reg valid_r; |
reg crac_rd_r; |
|
wire valid_ne; |
wire valid_pe; |
|
reg rdd1, rdd2, rdd3; |
|
//////////////////////////////////////////////////////////////////// |
// |
// Codec Register Data Path |
122,7 → 125,12
assign out_slt2[3:0] = 4'h0; |
|
// Read Data |
assign crac_din = in_slt2[19:4]; |
always @(posedge clk or negedge rst) |
begin |
if(!rst) crac_din <= #1 16'h0; |
else |
if(crac_rd_done) crac_din <= #1 in_slt2[19:4]; |
end |
|
//////////////////////////////////////////////////////////////////// |
// |
151,11 → 159,11
if(rdd1 & valid_pe) crac_rd <= #1 1'b0; |
|
always @(posedge clk or negedge rst) |
if(!rst) rdd1 <= #1 1'b0; |
if(!rst) rdd1 <= #1 1'b0; |
else |
if(crac_rd & valid_ne) rdd1 <= #1 1'b1; |
if(crac_rd & valid_ne) rdd1 <= #1 1'b1; |
else |
if(!crac_rd) rdd1 <= #1 1'b0; |
if(!crac_rd) rdd1 <= #1 1'b0; |
|
always @(posedge clk or negedge rst) |
if(!rst) rdd2 <= #1 1'b0; |
165,11 → 173,11
if(crac_rd_done) rdd2 <= #1 1'b0; |
|
always @(posedge clk or negedge rst) |
if(!rst) rdd3 <= #1 1'b0; |
if(!rst) rdd3 <= #1 1'b0; |
else |
if(rdd2 & valid_pe) rdd3 <= #1 1'b1; |
if(rdd2 & valid_pe) rdd3 <= #1 1'b1; |
else |
if(crac_rd_done) rdd3 <= #1 1'b0; |
if(crac_rd_done) rdd3 <= #1 1'b0; |
|
always @(posedge clk) |
crac_rd_done <= #1 rdd3 & valid_pe; |
181,7 → 189,4
|
assign valid_pe = valid & !valid_r; |
|
always @(posedge clk) |
crac_rd_r <= #1 crac_rd & valid; |
|
endmodule |
/trunk/rtl/verilog/ac97_fifo_ctrl.v
12,8 → 12,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
38,10 → 39,10
|
// CVS Log |
// |
// $Id: ac97_fifo_ctrl.v,v 1.2 2002-03-05 04:44:05 rudi Exp $ |
// $Id: ac97_fifo_ctrl.v,v 1.3 2002-09-19 06:30:56 rudi Exp $ |
// |
// $Date: 2002-03-05 04:44:05 $ |
// $Revision: 1.2 $ |
// $Date: 2002-09-19 06:30:56 $ |
// $Revision: 1.3 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 49,11
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/03/05 04:44:05 rudi |
// |
// - Fixed the order of the thrash hold bits to match the spec. |
// - Many minor synthesis cleanup items ... |
// |
// Revision 1.1 2001/08/03 06:54:49 rudi |
// |
// |
/trunk/rtl/verilog/ac97_rf.v
12,8 → 12,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
38,10 → 39,10
|
// CVS Log |
// |
// $Id: ac97_rf.v,v 1.3 2002-03-05 04:44:05 rudi Exp $ |
// $Id: ac97_rf.v,v 1.4 2002-09-19 06:30:56 rudi Exp $ |
// |
// $Date: 2002-03-05 04:44:05 $ |
// $Revision: 1.3 $ |
// $Date: 2002-09-19 06:30:56 $ |
// $Revision: 1.4 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 49,11
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/03/05 04:44:05 rudi |
// |
// - Fixed the order of the thrash hold bits to match the spec. |
// - Many minor synthesis cleanup items ... |
// |
// Revision 1.2 2001/08/10 08:09:42 rudi |
// |
// - Removed RTY_O output. |
/trunk/rtl/verilog/ac97_dma_req.v
12,8 → 12,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
38,10 → 39,10
|
// CVS Log |
// |
// $Id: ac97_dma_req.v,v 1.2 2002-03-05 04:44:05 rudi Exp $ |
// $Id: ac97_dma_req.v,v 1.3 2002-09-19 06:30:56 rudi Exp $ |
// |
// $Date: 2002-03-05 04:44:05 $ |
// $Revision: 1.2 $ |
// $Date: 2002-09-19 06:30:56 $ |
// $Revision: 1.3 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 49,11
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/03/05 04:44:05 rudi |
// |
// - Fixed the order of the thrash hold bits to match the spec. |
// - Many minor synthesis cleanup items ... |
// |
// Revision 1.1 2001/08/03 06:54:49 rudi |
// |
// |
/trunk/rtl/verilog/ac97_in_fifo.v
12,8 → 12,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
38,10 → 39,10
|
// CVS Log |
// |
// $Id: ac97_in_fifo.v,v 1.3 2002-03-11 03:21:22 rudi Exp $ |
// $Id: ac97_in_fifo.v,v 1.4 2002-09-19 06:30:56 rudi Exp $ |
// |
// $Date: 2002-03-11 03:21:22 $ |
// $Revision: 1.3 $ |
// $Date: 2002-09-19 06:30:56 $ |
// $Revision: 1.4 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 49,10
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/03/11 03:21:22 rudi |
// |
// - Added defines to select fifo depth between 4, 8 and 16 entries. |
// |
// Revision 1.2 2002/03/05 04:44:05 rudi |
// |
// - Fixed the order of the thrash hold bits to match the spec. |
/trunk/rtl/verilog/ac97_out_fifo.v
12,8 → 12,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
38,10 → 39,10
|
// CVS Log |
// |
// $Id: ac97_out_fifo.v,v 1.3 2002-03-11 03:21:22 rudi Exp $ |
// $Id: ac97_out_fifo.v,v 1.4 2002-09-19 06:30:56 rudi Exp $ |
// |
// $Date: 2002-03-11 03:21:22 $ |
// $Revision: 1.3 $ |
// $Date: 2002-09-19 06:30:56 $ |
// $Revision: 1.4 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 49,10
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/03/11 03:21:22 rudi |
// |
// - Added defines to select fifo depth between 4, 8 and 16 entries. |
// |
// Revision 1.1 2001/08/03 06:54:50 rudi |
// |
// |
/trunk/rtl/verilog/ac97_defines.v
11,8 → 11,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
37,10 → 38,10
|
// CVS Log |
// |
// $Id: ac97_defines.v,v 1.4 2002-03-11 03:21:22 rudi Exp $ |
// $Id: ac97_defines.v,v 1.5 2002-09-19 06:30:56 rudi Exp $ |
// |
// $Date: 2002-03-11 03:21:22 $ |
// $Revision: 1.4 $ |
// $Date: 2002-09-19 06:30:56 $ |
// $Revision: 1.5 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 48,10
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2002/03/11 03:21:22 rudi |
// |
// - Added defines to select fifo depth between 4, 8 and 16 entries. |
// |
// Revision 1.3 2002/03/05 04:44:05 rudi |
// |
// - Fixed the order of the thrash hold bits to match the spec. |
/trunk/rtl/verilog/ac97_dma_if.v
12,8 → 12,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
38,10 → 39,10
|
// CVS Log |
// |
// $Id: ac97_dma_if.v,v 1.3 2002-03-05 04:44:05 rudi Exp $ |
// $Id: ac97_dma_if.v,v 1.4 2002-09-19 06:30:56 rudi Exp $ |
// |
// $Date: 2002-03-05 04:44:05 $ |
// $Revision: 1.3 $ |
// $Date: 2002-09-19 06:30:56 $ |
// $Revision: 1.4 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 49,11
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/03/05 04:44:05 rudi |
// |
// - Fixed the order of the thrash hold bits to match the spec. |
// - Many minor synthesis cleanup items ... |
// |
// Revision 1.2 2001/08/10 08:09:42 rudi |
// |
// - Removed RTY_O output. |
/trunk/rtl/verilog/ac97_prc.v
12,8 → 12,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
38,10 → 39,10
|
// CVS Log |
// |
// $Id: ac97_prc.v,v 1.3 2002-03-05 04:44:05 rudi Exp $ |
// $Id: ac97_prc.v,v 1.4 2002-09-19 06:30:56 rudi Exp $ |
// |
// $Date: 2002-03-05 04:44:05 $ |
// $Revision: 1.3 $ |
// $Date: 2002-09-19 06:30:56 $ |
// $Revision: 1.4 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 49,11
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/03/05 04:44:05 rudi |
// |
// - Fixed the order of the thrash hold bits to match the spec. |
// - Many minor synthesis cleanup items ... |
// |
// Revision 1.2 2001/08/10 08:09:42 rudi |
// |
// - Removed RTY_O output. |
/trunk/rtl/verilog/ac97_soc.v
12,8 → 12,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
38,10 → 39,10
|
// CVS Log |
// |
// $Id: ac97_soc.v,v 1.2 2002-03-05 04:44:05 rudi Exp $ |
// $Id: ac97_soc.v,v 1.3 2002-09-19 06:30:56 rudi Exp $ |
// |
// $Date: 2002-03-05 04:44:05 $ |
// $Revision: 1.2 $ |
// $Date: 2002-09-19 06:30:56 $ |
// $Revision: 1.3 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 49,11
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/03/05 04:44:05 rudi |
// |
// - Fixed the order of the thrash hold bits to match the spec. |
// - Many minor synthesis cleanup items ... |
// |
// Revision 1.1 2001/08/03 06:54:50 rudi |
// |
// |
90,6 → 96,7
reg valid; |
reg [2:0] in_valid; |
reg bit_clk_r; |
reg bit_clk_r1; |
reg bit_clk_e; |
reg suspended; |
wire to; |
155,9 → 162,12
bit_clk_r <= #1 clk; |
|
always @(posedge wclk) |
bit_clk_e <= #1 (clk & !bit_clk_r) | (!clk & bit_clk_r); |
bit_clk_r1 <= #1 bit_clk_r; |
|
always @(posedge wclk) |
bit_clk_e <= #1 (bit_clk_r & !bit_clk_r1) | (!bit_clk_r & bit_clk_r1); |
|
always @(posedge wclk) |
suspended <= #1 to; |
|
assign to = (to_cnt == `AC97_SUSP_DET); |
/trunk/rtl/verilog/ac97_wb_if.v
12,8 → 12,9
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Rudolf Usselmann //// |
//// rudi@asics.ws //// |
//// Copyright (C) 2000-2002 Rudolf Usselmann //// |
//// www.asics.ws //// |
//// rudi@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
38,10 → 39,10
|
// CVS Log |
// |
// $Id: ac97_wb_if.v,v 1.3 2002-03-05 04:44:05 rudi Exp $ |
// $Id: ac97_wb_if.v,v 1.4 2002-09-19 06:30:56 rudi Exp $ |
// |
// $Date: 2002-03-05 04:44:05 $ |
// $Revision: 1.3 $ |
// $Date: 2002-09-19 06:30:56 $ |
// $Revision: 1.4 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 49,11
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/03/05 04:44:05 rudi |
// |
// - Fixed the order of the thrash hold bits to match the spec. |
// - Many minor synthesis cleanup items ... |
// |
// Revision 1.2 2001/08/10 08:09:42 rudi |
// |
// - Removed RTY_O output. |