OpenCores
URL https://opencores.org/ocsvn/mem_ctrl/mem_ctrl/trunk

Subversion Repositories mem_ctrl

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 13 to Rev 14
    ↔ Reverse comparison
  •

Rev 13 → Rev 14

/trunk/bench/verilog/wb_mast_model.v
37,10 → 37,10
 
// CVS Log
//
// $Id: wb_mast_model.v,v 1.1 2001-07-29 07:34:40 rudi Exp $
// $Id: wb_mast_model.v,v 1.2 2001-11-11 01:52:03 rudi Exp $
//
// $Date: 2001-07-29 07:34:40 $
// $Revision: 1.1 $
// $Date: 2001-11-11 01:52:03 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/07/29 07:34:40 rudi
//
//
// 1) Changed Directory Structure
// 2) Fixed several minor bugs
//
// Revision 1.1.1.1 2001/05/13 09:36:33 rudi
// Created Directory Structure
//
135,7 → 141,7
 
begin
 
@(posedge clk);
//@(posedge clk);
#1;
adr = a;
dout = d;
502,7 → 508,7
 
begin
 
@(posedge clk);
//@(posedge clk);
#1;
adr = a;
cyc = 1;
/trunk/bench/verilog/test_bench_top.v
37,10 → 37,10
 
// CVS Log
//
// $Id: test_bench_top.v,v 1.3 2001-09-02 02:29:43 rudi Exp $
// $Id: test_bench_top.v,v 1.4 2001-11-11 01:52:02 rudi Exp $
//
// $Date: 2001-09-02 02:29:43 $
// $Revision: 1.3 $
// $Date: 2001-11-11 01:52:02 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,10
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/09/02 02:29:43 rudi
//
// Fixed the TMS register setup to be tight and correct.
//
// Revision 1.2 2001/08/10 08:16:21 rudi
//
// - Changed IO names to be more clear.
157,7 → 161,7
`define MEM_BASE4 32'h1000_0000
`define MEM_BASE5 32'h1400_0000
`define MEM_BASE6 32'h1800_0000
`define REG_BASE 32'hf000_0000
`define REG_BASE 32'h6000_0000
 
`define CSR 8'h00
`define POC 8'h04
213,7 → 217,7
error_cnt = 0;
clk = 1;
mc_clk = 0;
rst = 0;
rst = 1;
susp_req = 0;
resume_req = 0;
verbose = 1;
221,7 → 225,7
 
repeat(11) @(posedge clk);
#1;
rst = 1;
rst = 0;
repeat(10) @(posedge clk);
 
// HERE IS WHERE THE TEST CASES GO ...
316,10 → 320,11
sram_rmw1;
sram_rmw2;
`endif
scs_rdwr1(2);
//scs_rdwr1(2);
 
mc_reset;
end
else
//else
if(1) // Suspend resume testing
begin
$display(" ......................................................");
329,7 → 334,7
 
verbose = 0;
done = 0;
LVL = 1;
LVL = 2;
 
fork
 
374,6 → 379,7
sdram_wr5(LVL);
`endif
 
 
`ifdef FLASH
while(susp_req | suspended) @(posedge clk);
asc_rdwr1(LVL);
380,6 → 386,7
`endif
 
`ifdef SRAM
 
while(susp_req | suspended) @(posedge clk);
sram_rd1;
while(susp_req | suspended) @(posedge clk);
396,8 → 403,8
while(susp_req | suspended) @(posedge clk);
sram_rmw2;
`endif
while(susp_req | suspended) @(posedge clk);
scs_rdwr1(LVL);
//while(susp_req | suspended) @(posedge clk);
//scs_rdwr1(LVL);
 
 
done = 1;
412,11 → 419,11
end
end
join
 
mc_reset;
end
//else
mc_reset;
 
if(1) // Bus Request testing
if(0) // Bus Request testing
begin
$display(" ......................................................");
$display(" : :");
424,7 → 431,7
$display(" :....................................................:");
verbose = 0;
done = 0;
LVL = 1;
LVL = 2;
fork
 
begin
460,7 → 467,7
sram_rmw1;
sram_rmw2;
`endif
scs_rdwr1(LVL);
//scs_rdwr1(LVL);
 
done = 1;
end
490,10 → 497,43
`define POC 8'h04
`define BA_MASK 8'h08
 
`define CSR_MASK 32'hff00_07fe
`define BAM_MASK 32'h0000_07ff
`define CSC_MASK 32'hffff_ffff
`define TMS_MASK 32'hffff_ffff
 
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'hffff_ffff);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'hffff_ffff);
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'hffff_ffff);
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, 32'hffff_ffff);
m0.wb_wr1(`REG_BASE + `CSC1, 4'hf, 32'hffff_ffff);
m0.wb_wr1(`REG_BASE + `TMS1, 4'hf, 32'hffff_ffff);
m0.wb_wr1(`REG_BASE + `CSC2, 4'hf, 32'hffff_ffff);
m0.wb_wr1(`REG_BASE + `TMS2, 4'hf, 32'hffff_ffff);
m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'hffff_ffff);
m0.wb_wr1(`REG_BASE + `TMS3, 4'hf, 32'hffff_ffff);
 
m0.wb_rd1(`REG_BASE + `CSR, 4'hf, data);
m0.wb_rd1(`REG_BASE + `BA_MASK, 4'hf, data);
m0.wb_rd1(`REG_BASE + `CSC0, 4'hf, data);
m0.wb_rd1(`REG_BASE + `TMS0, 4'hf, data);
m0.wb_rd1(`REG_BASE + `CSC1, 4'hf, data);
m0.wb_rd1(`REG_BASE + `TMS1, 4'hf, data);
m0.wb_rd1(`REG_BASE + `CSC2, 4'hf, data);
m0.wb_rd1(`REG_BASE + `TMS2, 4'hf, data);
m0.wb_rd1(`REG_BASE + `CSC3, 4'hf, data);
m0.wb_rd1(`REG_BASE + `TMS3, 4'hf, data);
 
 
 
 
 
m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0000_0000);
//sdram_rmw2(2);
 
//sdram_rd1(2);
//sdram_wr1(2);
//asc_rdwr1(2);
//sram_rd1;
//sram_wr1;
//sram_rmw1;
//sram_rmw2;
//sram_wp;
500,10 → 540,6
 
//scs_rdwr1(2);
 
 
//sdram_rd3(2);
//sdram_wr3(2);
 
//asc_rdwr1(2);
//asc_rdwr1_x(2);
 
513,7 → 549,15
 
//sdram_rd2(2);
//sdram_wr2(2);
sdram_wr1(2);
 
//sdram_bo;
//sdram_rd1b(2);
 
//sdram_rd1(2);
//sdram_wr1(2);
 
//sdram_rd5(2);
//sdram_wr5(2);
/*
sdram_rd1(2);
sdram_wr1(2);
523,21 → 567,21
sdram_wr3(2);
sdram_rd4(2);
sdram_wr4(2);
 
sdram_rd5(2);
sdram_wr5(2);
 
sdram_wp(2);
sdram_rmw1(2);
sdram_rmw2(2);
sdram_rmw2(2);
 
*/
 
//sdram_rmw2(2);
 
 
repeat(100) @(posedge clk);
$finish;
end
else
else
begin
 
//
546,7 → 590,7
$display("\n\n");
$display("*****************************************************");
$display("*** Test Development ... ***");
$display("*****************************************************\n");
$display("*****************************************************\n" );
 
 
show_errors;
569,8 → 613,6
always #2.5 clk = ~clk;
 
always @(posedge clk)
//#0.5 mc_clk <= ~mc_clk;
//#4.5 mc_clk <= ~mc_clk;
mc_clk <= ~mc_clk;
 
/////////////////////////////////////////////////////////////////////
660,7 → 702,8
default: rst_dq_val = 32'hzzzz_zzzz;
endcase
 
assign #1 mc_dq = mc_data_oe ? mc_data_o : (~rst ? rst_dq_val : 32'hzzzz_zzzz);
/*
assign #1 mc_dq = mc_data_oe ? mc_data_o : (rst ? rst_dq_val : 32'hzzzz_zzzz);
assign #1 mc_data_i = mc_dq;
 
assign #1 mc_dqp = mc_data_oe ? mc_dp_o : 4'hz;
679,7 → 722,32
assign #1 mc_adsc_ = mc_c_oe ? _mc_adsc_ : 1'bz;
assign #1 mc_adv_ = mc_c_oe ? _mc_adv_ : 1'bz;
assign #1 mc_zz = mc_c_oe ? _mc_zz : 1'bz;
*/
 
 
assign mc_dq = mc_data_oe ? mc_data_o : (rst ? rst_dq_val : 32'hzzzz_zzzz);
assign mc_data_i = mc_dq;
 
assign mc_dqp = mc_data_oe ? mc_dp_o : 4'hz;
assign mc_dp_i = mc_dqp;
 
assign mc_addr = mc_c_oe ? _mc_addr : 24'bz;
assign mc_dqm = mc_c_oe ? _mc_dqm : 4'bz;
assign mc_oe_ = mc_c_oe ? _mc_oe_ : 1'bz;
assign mc_we_ = mc_c_oe ? _mc_we_ : 1'bz;
assign mc_cas_ = mc_c_oe ? _mc_cas_ : 1'bz;
assign mc_ras_ = mc_c_oe ? _mc_ras_ : 1'bz;
assign #1.5 mc_cke_ = mc_c_oe ? _mc_cke_ : 1'bz;
assign mc_cs_ = mc_c_oe ? _mc_cs_ : 8'bz;
assign mc_rp_ = mc_c_oe ? _mc_rp_ : 1'bz;
assign mc_vpen = mc_c_oe ? _mc_vpen : 1'bz;
assign mc_adsc_ = mc_c_oe ? _mc_adsc_ : 1'bz;
assign mc_adv_ = mc_c_oe ? _mc_adv_ : 1'bz;
assign mc_zz = mc_c_oe ? _mc_zz : 1'bz;
 
 
 
 
pullup p0(mc_cas_);
pullup p1(mc_ras_);
pullup p2(mc_oe_);
750,7 → 818,7
//
 
wb_mast m0( .clk( clk ),
.rst( rst ),
.rst( ~rst ),
.adr( wb_addr_i ),
.din( wb_data_o ),
.dout( wb_data_i ),
873,15 → 941,13
);
 
 
/*
 
mt48lc4m16a2 sdram1a(
mt48lc16m16a2 sdram1a(
.Dq( mc_dq[15:0] ),
.Addr( mc_addr[11:0] ),
.Addr( mc_addr[12:0] ),
.Ba( mc_addr[14:13] ),
.Clk( mc_clk ),
.Cke( mc_cke_ ),
.Cs_n( mc_cs_[1] ),
.Cs_n( mc_cs_[5] ),
.Ras_n( mc_ras_ ),
.Cas_n( mc_cas_ ),
.We_n( mc_we_ ),
888,13 → 954,13
.Dqm( mc_dqm[1:0] )
);
 
mt48lc4m16a2 sdram1b(
mt48lc16m16a2 sdram1b(
.Dq( mc_dq[31:16] ),
.Addr( mc_addr[11:0] ),
.Addr( mc_addr[12:0] ),
.Ba( mc_addr[14:13] ),
.Clk( mc_clk ),
.Cke( mc_cke_ ),
.Cs_n( mc_cs_[1] ),
.Cs_n( mc_cs_[5] ),
.Ras_n( mc_ras_ ),
.Cas_n( mc_cas_ ),
.We_n( mc_we_ ),
901,6 → 967,7
.Dqm( mc_dqm[3:2] )
);
 
/*
mt48lc8m8a2 sdram2a(
.Dq( mc_dq[07:00] ),
.Addr( mc_addr[11:0] ),
/trunk/bench/verilog/tests.v
37,10 → 37,10
 
// CVS Log
//
// $Id: tests.v,v 1.3 2001-09-02 02:29:43 rudi Exp $
// $Id: tests.v,v 1.4 2001-11-11 01:52:03 rudi Exp $
//
// $Date: 2001-09-02 02:29:43 $
// $Revision: 1.3 $
// $Date: 2001-11-11 01:52:03 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,10
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/09/02 02:29:43 rudi
//
// Fixed the TMS register setup to be tight and correct.
//
// Revision 1.2 2001/08/10 08:16:21 rudi
//
// - Changed IO names to be more clear.
67,6 → 71,263
//
 
 
 
task sdram_bo;
 
integer n;
integer del, size;
reg [7:0] mode;
reg [2:0] bs;
integer sz_inc;
integer sz_max, del_max;
integer write;
reg [31:0] mem_data;
reg [1:0] bas, kro;
 
begin
$display("\n\n");
$display("*****************************************************");
$display("*** SDRAM Bank Overflow test 1 ***");
$display("*****************************************************\n");
 
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0300);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
 
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
1'b0, // Burst Type (0=Seq;1=Inter)
3'd3 // Burst Length
});
 
//force sdram0.Debug = 1;
del = 1;
bas = 0;
kro = 1;
for(kro=0;kro<2;kro=kro+1)
for(bas=0;bas<2;bas=bas+1)
begin
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0021 | (bas<<9) | (kro<<10));
 
sdram0.mem_fill(1024);
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd8, // Trfc [27:24]
4'd3, // Trp [23:20]
3'd3, // Trcd [19:17]
2'd2, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
1'b0, // Burst Type (0=Seq;1=Inter)
3'd0 // Burst Length
});
 
$display("kro: %0d, bas: %0d", kro, bas);
 
m0.mem_fill;
for(n=250;n<260;n=n+1)
begin
 
m0.wb_rd_mult(`MEM_BASE + (n*4), 4'hf, del, 1);
 
if(!bas)
case(n[9:8])
0: mem_data = sdram0.Bank0[n];
1: mem_data = sdram0.Bank1[n-256];
2: mem_data = sdram0.Bank2[n];
3: mem_data = sdram0.Bank3[n];
endcase
else mem_data = sdram0.Bank0[n];
 
if((mem_data !== m0.rd_mem[n-250]) |
(|mem_data === 1'bx) |
(|m0.rd_mem[n-250] === 1'bx) )
begin
$display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
n, mem_data, m0.rd_mem[n-250], $time);
error_cnt = error_cnt + 1;
end
end
 
end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ... ***");
$display("*****************************************************\n\n");
end
endtask
 
 
 
 
task sdram_rd1b;
input quick;
 
integer quick;
integer n;
integer del, size;
reg [7:0] mode;
reg [2:0] bs;
integer sz_inc;
integer sz_max, del_max;
integer write;
reg [31:0] memd;
 
begin
$display("\n\n");
$display("*****************************************************");
$display("*** SDRAM Size, Delay & Mode Read test 1B ... ***");
$display("*****************************************************\n");
 
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0300);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS5, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
 
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
1'b0, // Burst Type (0=Seq;1=Inter)
3'd3 // Burst Length
});
 
//m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821);
m0.wb_wr1(`REG_BASE + `CSC5, 4'hf, 32'h0000_0091);
 
case(quick)
0: sz_max = 64;
1: sz_max = 32;
2: sz_max = 16;
endcase
 
case(quick)
0: del_max = 16;
1: del_max = 8;
2: del_max = 4;
endcase
 
size = 4;
del = 1;
mode = 0;
write = 0;
//force sdram0.Debug = 1;
 
for(mode=0;mode<10;mode=mode+1)
begin
sdram1a.mem_fill(1024);
sdram1b.mem_fill(1024);
//sdram0p.mem_fill(1024);
 
case(mode[3:1])
0: bs = 0;
1: bs = 1;
2: bs = 2;
3: bs = 3;
4: bs = 7;
endcase
case(mode[3:1])
0: sz_inc = 1;
1: sz_inc = 2;
2: sz_inc = 4;
3: sz_inc = 8;
4: sz_inc = 1;
endcase
 
 
/*
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2+mode[0], // CL
1'b0, // Burst Type (0=Seq;1=Inter)
3'd0+bs // Burst Length
});
*/
 
m0.wb_wr1(`REG_BASE + `TMS5, 4'hf, {
4'd0, // RESERVED [31:28]
4'd8, // Trfc [27:24]
4'd3, // Trp [23:20]
3'd3, // Trcd [19:17]
2'd2, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2+mode[0], // CL
1'b0, // Burst Type (0=Seq;1=Inter)
3'd0+bs // Burst Length
});
 
if(!verbose) $display("Mode: %b", mode);
for(del=0;del<del_max;del=del+1)
for(size=sz_inc;size<sz_max;size=size+sz_inc)
begin
m0.mem_fill;
 
if(verbose) $display("Mode: %b, Size: %0d, Delay: %0d", mode, size, del);
 
if(write) m0.wb_wr_mult(`MEM_BASE + 0, 4'hf, del, size);
m0.wb_rd_mult(`MEM_BASE + 0, 4'hf, del, size);
 
if(write) m0.wb_wr_mult(`MEM_BASE + size*1*4, 4'hf, del, size);
m0.wb_rd_mult(`MEM_BASE + size*1*4, 4'hf, del, size);
 
if(write) m0.wb_wr_mult(`MEM_BASE + size*2*4, 4'hf, del, size);
m0.wb_rd_mult(`MEM_BASE + size*2*4, 4'hf, del, size);
 
if(write) m0.wb_wr_mult(`MEM_BASE + size*3*4, 4'hf, del, size);
m0.wb_rd_mult(`MEM_BASE + size*3*4, 4'hf, del, size);
 
for(n=0;n<(size*4);n=n+1)
begin
memd = {sdram1b.Bank0[n], sdram1a.Bank0[n]};
 
if((memd !== m0.rd_mem[n]) |
(|memd === 1'bx) |
(|m0.rd_mem[n] === 1'bx) )
begin
$display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
n, memd, m0.rd_mem[n], $time);
error_cnt = error_cnt + 1;
end
end
end
 
end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ... ***");
$display("*****************************************************\n\n");
end
endtask
 
 
task sdram_rd1;
input quick;
 
120,11 → 381,11
 
size = 4;
del = 1;
mode = 2;
mode = 9;
write = 0;
//force sdram0.Debug = 1;
 
for(mode=0;mode<10;mode=mode+1)
//for(mode=0;mode<10;mode=mode+1)
begin
sdram0.mem_fill(1024);
//sdram0p.mem_fill(1024);
145,6 → 406,8
4: sz_inc = 1;
endcase
 
 
/*
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
158,7 → 421,22
1'b0, // Burst Type (0=Seq;1=Inter)
3'd0+bs // Burst Length
});
*/
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd8, // Trfc [27:24]
4'd3, // Trp [23:20]
3'd3, // Trcd [19:17]
2'd2, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2+mode[0], // CL
1'b0, // Burst Type (0=Seq;1=Inter)
3'd0+bs // Burst Length
});
 
if(!verbose) $display("Mode: %b", mode);
for(del=0;del<del_max;del=del+1)
for(size=sz_inc;size<sz_max;size=size+sz_inc)
254,11 → 532,11
 
size = 1;
del = 0;
mode = 0;
mode = 19;
read = 1;
//force sdram0.Debug = 1;
 
for(mode=0;mode<20;mode=mode+1)
//for(mode=0;mode<20;mode=mode+1)
begin
sdram0.mem_fill(1024);
 
297,8 → 575,8
 
if(!verbose) $display("Mode: %b", mode);
 
for(del=0;del<del_max;del=del+1)
for(size=sz_inc;size<sz_max;size=size+sz_inc)
//for(del=0;del<del_max;del=del+1)
//for(size=sz_inc;size<sz_max;size=size+sz_inc)
begin
m0.mem_fill;
 
1135,7 → 1413,7
m0.wb_rd_mult(`MEM_BASE + (page_size*3*4) + size*7*4, 4'hf, del, size);
 
for(m=0;m<4;m=m+1)
for(n=0;n<(size*2);n=n+1)
for(n=0;n<(size*2);n=n+1)
begin
adr = (m * page_size) + (m*(size*2)) + n;
 
1436,9 → 1714,9
m0.wb_wr1(`REG_BASE + `CSC1, 4'hf, 32'h0020_0021 | (bas[0]<<9));
m0.wb_wr1(`REG_BASE + `CSC2, 4'hf, 32'h0040_0421 | (bas[0]<<9));
 
size = 15;
del = 3;
mode = 9;
size = 2;
del = 0;
mode = 8;
write = 1;
if(0)
begin
1517,6 → 1795,7
 
for(del=0;del<del_max;del=del+1)
for(size=sz_inc;size<sz_max;size=size+sz_inc)
//for(size=sz_inc;size<8;size=size+sz_inc)
begin
m0.mem_fill;
if(verbose) $display("BAS: %0d, Mode: %b, Size: %0d, Delay: %0d",
1635,7 → 1914,7
(|m0.rd_mem[(m*size*6)+(s*size*2)+n] === 1'bx) )
begin
$display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
(m*size*2)+n, data, m0.rd_mem[(m*size*2)+n], $time);
(m*size*6)+(s*size*2)+n, data, m0.rd_mem[(m*size*6)+(s*size*2)+n], $time);
error_cnt = error_cnt + 1;
if(error_cnt > 25) $finish;
end
1751,8 → 2030,8
endcase
 
size = 5;
del = 0;
mode = 0;
del = 1;
mode = 6;
read = 1;
 
if(0)
1936,8 → 2215,6
$display("ERROR: WR Data[%0d-%0d] Mismatch: Expected: %x, Got: %x (%0t)",
s, (m*size*2)+n, data, m0.wr_mem[(m*size*2)+n], $time);
error_cnt = error_cnt + 1;
 
if(error_cnt > 25) $finish;
end
 
end
1994,13 → 2271,14
2: del_max = 4;
endcase
 
size = 1;
del = 0;
size = 16;
del = 4;
mode = 0;
read = 1;
write = 0;
write = 1;
 
 
sz_max = 6;
for(mode=0;mode<3;mode=mode+1)
begin
 
2015,8 → 2293,8
repeat(10) @(posedge clk);
if(!verbose) $display("Mode: %b", mode);
 
for(del=0;del<del_max;del=del+1)
for(size=1;size<sz_max;size=size+1)
//for(del=0;del<del_max;del=del+1)
//for(size=1;size<sz_max;size=size+1)
begin
m0.mem_fill;
for(n=0;n<1024;n=n+1)
2353,6 → 2631,7
endtask
 
 
`ifdef SRAM
task sram_rd1;
 
integer n,m,read,write;
2454,7 → 2733,7
m0.wb_wr1(`REG_BASE + `CSC4, 4'hf, 32'h0080_0803);
 
size = 4;
del = 26;
del = 4;
mode = 0;
read = 1;
write = 1;
2520,9 → 2799,9
 
end
endtask
`endif
 
 
 
task scs_rdwr1;
input quick;
 
2761,6 → 3040,7
endtask
 
 
`ifdef SRAM
task sram_wp;
 
integer n,m,read,write;
2848,6 → 3128,7
 
end
endtask
`endif
 
 
task sdram_rmw1;
2907,14 → 3188,14
3'd3 // Burst Length
});
 
kro = 0;
kro = 1;
for(kro=0;kro<2;kro=kro+1) // Don't Need this for this test
begin
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821 | (kro[0]<<10));
 
size = 4;
size = 2;
del = 0;
mode = 0;
mode = 8;
 
//force sdram0.Debug = 1;
 
3195,7 → 3476,7
endtask
 
 
 
`ifdef SRAM
task sram_rmw1;
 
integer n,m,read,write;
3325,11 → 3606,11
m0.wb_wr1(`REG_BASE + `CSC4, 4'hf, 32'h0080_0003);
 
size = 4;
del = 2;
del = 4;
 
repeat(1) @(posedge clk);
 
for(del=0;del<16;del=del+1)
//for(del=0;del<16;del=del+1)
for(size=1;size<18;size=size+1)
begin
m0.mem_fill;
3391,4 → 3672,5
end
endtask
 
`endif
 
/trunk/bench/verilog/test_lib.v
38,10 → 38,10
 
// CVS Log
//
// $Id: test_lib.v,v 1.2 2001-09-02 02:29:43 rudi Exp $
// $Id: test_lib.v,v 1.3 2001-11-11 01:52:03 rudi Exp $
//
// $Date: 2001-09-02 02:29:43 $
// $Revision: 1.2 $
// $Date: 2001-11-11 01:52:03 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,10
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/09/02 02:29:43 rudi
//
// Fixed the TMS register setup to be tight and correct.
//
// Revision 1.1 2001/07/29 07:34:40 rudi
//
//
200,9 → 204,9
 
begin
repeat(10) @(posedge clk);
rst = 1;
repeat(10) @(posedge clk);
rst = 0;
repeat(10) @(posedge clk);
rst = 1;
repeat(20) @(posedge clk);
end
endtask

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.