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URL https://opencores.org/ocsvn/ppx16/ppx16/trunk

Subversion Repositories ppx16

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 13 to Rev 14
    Reverse comparison

Rev 13 → Rev 14

/trunk/rtl/vhdl/PPX_Pack.vhd
1,7 → 1,7
--
-- PIC16xx compatible microcontroller core
--
-- Version : 0222
-- Version : 0224
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
38,7 → 38,7
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
-- http://www.opencores.org/cvsweb.shtml/ppx16/
--
-- Limitations :
--
74,6 → 74,7
);
port(
Clk : in std_logic;
Reset_n : in std_logic;
ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
Inst : in std_logic_vector(InstructionLength - 1 downto 0);
Skip : in std_logic;
/trunk/rtl/vhdl/PPX_Ctrl.vhd
1,7 → 1,7
--
-- PIC16xx compatible microcontroller core
--
-- Version : 0222
-- Version : 0224
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
38,7 → 38,7
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
-- http://www.opencores.org/cvsweb.shtml/ppx16/
--
-- Limitations :
-- Registers implemented in this entity are INDF, PCL, STATUS, FSR, (PCLATH)
56,6 → 56,7
);
port(
Clk : in std_logic;
Reset_n : in std_logic;
ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
Inst : in std_logic_vector(InstructionLength - 1 downto 0);
Skip : in std_logic;
86,9 → 87,9
Inst(11 downto 10) = "11" or
(Inst(11 downto 10) = "00" and Inst(5) = '0' and Inst(9 downto 6) /= "0000") else '0';
IRet <= '0';
process (Clk)
process (Reset_n, Clk)
begin
if Clk'event and Clk = '1' then
if Reset_n = '0' then
File_Wr <= '0';
Goto <= '0';
Push <= '0';
95,6 → 96,13
Pop <= '0';
A2Res <= '0';
B2Res <= '0';
elsif Clk'event and Clk = '1' then
File_Wr <= '0';
Goto <= '0';
Push <= '0';
Pop <= '0';
A2Res <= '0';
B2Res <= '0';
if Skip = '0' then
if (ROM_Data(InstructionLength - 1 downto InstructionLength - 2) = "00" and
ROM_Data(InstructionLength - 7) = '1') or
131,9 → 139,9
W_Wr <= '1' when Inst(13 downto 12) = "11" or
(Inst(13 downto 12) = "00" and Inst(7) = '0' and Inst(11 downto 8) /= "0000") else '0';
IRet <= '1' when Inst(13 downto 0) = "00000000001001" else '0'; -- RETFIE
process (Clk)
process (Reset_n, Clk)
begin
if Clk'event and Clk = '1' then
if Reset_n = '0' then
File_Wr <= '0';
Goto <= '0';
Push <= '0';
140,6 → 148,13
Pop <= '0';
A2Res <= '0';
B2Res <= '0';
elsif Clk'event and Clk = '1' then
File_Wr <= '0';
Goto <= '0';
Push <= '0';
Pop <= '0';
A2Res <= '0';
B2Res <= '0';
if Skip = '0' then
if (ROM_Data(InstructionLength - 1 downto InstructionLength - 2) = "00" and
ROM_Data(InstructionLength - 7) = '1') or
/trunk/rtl/vhdl/PPX16.vhd
1,7 → 1,7
--
-- PIC16xx compatible microcontroller core
--
-- Version : 0222
-- Version : 0224
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
38,7 → 38,7
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
-- http://www.opencores.org/cvsweb.shtml/ppx16/
--
-- Limitations :
-- Registers implemented in this entity are INDF, PCL, STATUS, FSR, (PCLATH)
291,6 → 291,7
generic map(InstructionLength => InstructionLength)
port map(
Clk => Clk,
Reset_n => Reset_n,
ROM_Data => ROM_Data,
Inst => Inst,
Skip => Inst_Skip,

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