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URL https://opencores.org/ocsvn/wb2axip/wb2axip/trunk

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    from Rev 13 to Rev 14
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Rev 13 → Rev 14

/wb2axip/trunk/rtl/wbm2axisp.v
28,7 → 28,7
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2016, Gisselquist Technology, LLC
// Copyright (C) 2016-2018, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
64,7 → 64,7
parameter [0:0] STRICT_ORDER = 1 // Reorder, or not? 0 -> Reorder
) (
input wire i_clk, // System clock
// input wire i_reset,// Wishbone reset signal--unused
input wire i_reset,// Reset signal,drives AXI rst
 
// AXI write address channel signals
input wire i_axi_awready, // Slave is ready to accept
165,7 → 165,7
assign o_axi_awqos = 4'h0; // Lowest quality of service (unused)
assign o_axi_arqos = 4'h0; // Lowest quality of service (unused)
 
reg wb_mid_cycle, wb_mid_abort;
reg wb_mid_cycle, wb_last_cyc_stb, wb_mid_abort, wb_cyc_stb;
wire wb_abort;
 
// Command logic
175,8 → 175,10
 
initial transaction_id = 0;
always @(posedge i_clk)
if ((i_wb_stb)&&(!o_wb_stall))
transaction_id <= transaction_id + 1'b1;
if (i_reset)
transaction_id <= 0;
else if ((i_wb_stb)&&(!o_wb_stall))
transaction_id <= transaction_id + 1'b1;
 
assign fifo_head = transaction_id;
 
190,6 → 192,9
 
initial o_axi_awvalid = 0;
always @(posedge i_clk)
if (i_reset)
o_axi_awvalid <= 0;
else
o_axi_awvalid <= (!o_wb_stall)&&(i_wb_stb)&&(i_wb_we)
||(o_axi_awvalid)&&(!i_axi_awready);
 
197,20 → 202,22
 
initial o_axi_awid = -1;
always @(posedge i_clk)
if ((i_wb_stb)&&(!o_wb_stall))
o_axi_awid <= transaction_id;
if (i_reset)
o_axi_awid <= -1;
else if ((i_wb_stb)&&(!o_wb_stall))
o_axi_awid <= transaction_id;
 
if (C_AXI_DATA_WIDTH == DW)
begin
always @(posedge i_clk)
if ((i_wb_stb)&&(!o_wb_stall)) // 26 bit address becomes 28 bit ...
o_axi_awaddr <= { i_wb_addr[AW-1:0], axi_bottom_addr };
if ((i_wb_stb)&&(!o_wb_stall)) // 26 bit address becomes 28 bit ...
o_axi_awaddr <= { i_wb_addr[AW-1:0], axi_bottom_addr };
end else if (C_AXI_DATA_WIDTH / DW == 2)
begin
 
always @(posedge i_clk)
if ((i_wb_stb)&&(!o_wb_stall)) // 26 bit address becomes 28 bit ...
o_axi_awaddr <= { i_wb_addr[AW-1:1], axi_bottom_addr };
if ((i_wb_stb)&&(!o_wb_stall)) // 26 bit address becomes 28 bit ...
o_axi_awaddr <= { i_wb_addr[AW-1:1], axi_bottom_addr };
 
end else if (C_AXI_DATA_WIDTH / DW == 4)
begin
227,6 → 234,9
assign o_axi_arsize = 3'b101; // maximum bytes per burst is 32
initial o_axi_arvalid = 1'b0;
always @(posedge i_clk)
if (i_reset)
o_axi_arvalid <= 1'b0;
else
o_axi_arvalid <= (!o_wb_stall)&&(i_wb_stb)&&(!i_wb_we)
||(o_axi_arvalid)&&(!i_axi_arready);
 
278,6 → 288,9
assign o_axi_wlast = 1'b1;
initial o_axi_wvalid = 0;
always @(posedge i_clk)
if (i_reset)
o_axi_wvalid <= 0;
else
o_axi_wvalid <= ((!o_wb_stall)&&(i_wb_stb)&&(i_wb_we))
||(o_axi_wvalid)&&(!i_axi_wready);
 
435,7 → 448,14
initial o_wb_ack = 0;
initial o_wb_err = 0;
always @(posedge i_clk)
if (i_reset)
begin
reorder_fifo_valid <= 0;
reorder_fifo_err <= 0;
o_wb_ack <= 0;
o_wb_err <= 0;
fifo_tail <= 0;
end else begin
if (axi_rd_ack)
begin
reorder_fifo_valid[i_axi_rid] <= 1'b1;
471,7 → 491,9
reg r_fifo_full;
initial r_fifo_full = 0;
always @(posedge i_clk)
begin
if (i_reset)
r_fifo_full <= 0;
else begin
if ((i_wb_stb)&&(!o_wb_stall)
&&(reorder_fifo_valid[fifo_tail]))
r_fifo_full <= (fifo_tail==n_fifo_head);
493,6 → 515,11
initial reorder_fifo_valid = 1'b0;
initial reorder_fifo_err = 1'b0;
always @(posedge i_clk)
if (i_reset)
begin
reorder_fifo_valid <= 0;
reorder_fifo_err <= 0;
end else begin
if (axi_rd_ack)
begin
reorder_fifo_valid <= 1'b1;
505,24 → 532,35
reorder_fifo_valid <= 1'b0;
reorder_fifo_err <= 1'b0;
end
end
 
initial fifo_tail = 0;
always @(posedge i_clk)
if (reorder_fifo_valid)
fifo_tail <= fifo_tail + 1'b1;
if (i_reset)
fifo_tail <= 0;
else if (reorder_fifo_valid)
fifo_tail <= fifo_tail + 1'b1;
 
initial o_wb_ack = 0;
always @(posedge i_clk)
if (i_reset)
o_wb_ack <= 0;
else
o_wb_ack <= (reorder_fifo_valid)&&(i_wb_cyc)&&(!wb_abort);
 
initial o_wb_err = 0;
always @(posedge i_clk)
if (i_reset)
o_wb_err <= 0;
else
o_wb_err <= (reorder_fifo_err)&&(i_wb_cyc)&&(!wb_abort);
 
reg r_fifo_full;
initial r_fifo_full = 0;
always @(posedge i_clk)
begin
if (i_reset)
r_fifo_full <= 0;
else begin
if ((i_wb_stb)&&(!o_wb_stall)
&&(reorder_fifo_valid))
r_fifo_full <= (fifo_tail==n_fifo_head);
546,22 → 584,35
// Wishbone abort logic
//
 
// Are we mid-cycle?
// Did we just accept something?
initial wb_cyc_stb = 1'b0;
always @(posedge i_clk)
if (i_reset)
wb_cyc_stb <= 1'b0;
else
wb_cyc_stb <= (i_wb_cyc)&&(i_wb_stb)&&(!o_wb_stall);
 
// Else, are we mid-cycle?
initial wb_mid_cycle = 0;
always @(posedge i_clk)
if ((fifo_head != fifo_tail)
||(o_axi_arvalid)||(o_axi_awvalid)
||(o_axi_wvalid)
||(i_wb_cyc)&&(i_wb_stb)&&(!o_wb_stall))
wb_mid_cycle <= 1'b1;
else
wb_mid_cycle <= 1'b0;
if (i_reset)
wb_mid_cycle <= 0;
else if ((fifo_head != fifo_tail)
||(o_axi_arvalid)||(o_axi_awvalid)
||(o_axi_wvalid)
||(i_wb_cyc)&&(i_wb_stb)&&(!o_wb_stall))
wb_mid_cycle <= 1'b1;
else
wb_mid_cycle <= 1'b0;
 
initial wb_mid_abort = 0;
always @(posedge i_clk)
if (wb_mid_cycle)
wb_mid_abort <= (wb_mid_abort)||(!i_wb_cyc);
else
wb_mid_abort <= 1'b0;
if (i_reset)
wb_mid_abort <= 0;
else if (wb_mid_cycle)
wb_mid_abort <= (wb_mid_abort)||(!i_wb_cyc);
else
wb_mid_abort <= 1'b0;
 
assign wb_abort = ((wb_mid_cycle)&&(!i_wb_cyc))||(wb_mid_abort);
 
575,12 → 626,6
||((o_axi_arvalid)&&(!i_axi_arready)));
 
 
// Make Verilator happy
// verilator lint_off UNUSED
wire [2:0] unused;
assign unused = { i_axi_bresp[0], i_axi_rresp[0], i_axi_rlast };
// verilator lint_on UNUSED
 
/////////////////////////////////////////////////////////////////////////
//
//

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