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URL https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk

Subversion Repositories axi4_tlm_bfm

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    from Rev 14 to Rev 15
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Rev 14 → Rev 15

/axi4_tlm_bfm/trunk/rtl/axi4-stream-bfm-master.vhdl
44,9 → 44,7
entity axiBfmMaster is --generic(constant maxTransactions:positive);
port(aclk,n_areset:in std_ulogic;
/* BFM signalling. */
/* FIXME Generic package defect. ModelSim currently can't make tauhop.axiTransactor.i_transactor visible. */
readRequest,writeRequest:in i_transactor.t_bfm:=((others=>'X'),(others=>'X'),false);
--readRequest,writeRequest:in i_transactor.t_bfm:=((others=>'X'),(others=>'X'),false);
readRequest,writeRequest:in i_transactor.t_bfm:=(address=>(others=>'X'), message=>(others=>'X'), trigger=>false);
readResponse,writeResponse:buffer i_transactor.t_bfm; -- use buffer until synthesis tools support reading from out ports.
/* AXI Master interface */
74,9 → 72,7
signal i_axiMaster_out:t_axi4StreamTransactor_m2s;
/* BFM signalling. */
signal i_readRequest:i_transactor.t_bfm:=((others=>'0'),(others=>'0'),false);
signal i_writeRequest:i_transactor.t_bfm:=((others=>'0'),(others=>'0'),false);
signal i_readRequest,i_writeRequest:i_transactor.t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
signal i_readResponse,i_writeResponse:i_transactor.t_bfm;
begin
90,19 → 86,6
elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
end if;
end if;
/* debug only. */
/*if falling_edge(aclk) then
if not n_areset then outstandingTransactions<=symbolsPerTransfer;
else
if outstandingTransactions<1 then
outstandingTransactions<=symbolsPerTransfer;
report "No more pending transactions." severity note;
elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
end if;
end if;
end if;
*/
end process;
/* next-state logic for AXI4-Stream Master Tx BFM. */
138,13 → 121,7
end if;
case next_axiTxState is
when idle=>
/* if writeRequest.trigger xor i_writeRequest.trigger then
i_axiMaster_out.tData<=writeRequest.message;
i_axiMaster_out.tValid<=true;
end if;
*/
null;
when idle=> null;
when payload=>
i_axiMaster_out.tData<=writeRequest.message;
i_axiMaster_out.tValid<=true;
163,7 → 140,6
/* state registers and pipelines for AXI4-Stream Tx BFM. */
process(n_areset,aclk) is begin
--if not n_areset then next_axiTxState<=idle;
if falling_edge(aclk) then
next_axiTxState<=axiTxState;
i_writeRequest<=writeRequest;
/axi4_tlm_bfm/trunk/rtl/user.vhdl
63,10 → 63,8
signal outstandingTransactions:i_transactor.t_cnt;
/* BFM signalling. */
signal readRequest:i_transactor.t_bfm:=((others=>'0'),(others=>'0'),false);
signal writeRequest:i_transactor.t_bfm:=((others=>'0'),(others=>'0'),false);
signal readResponse:i_transactor.t_bfm;
signal writeResponse:i_transactor.t_bfm;
signal readRequest,writeRequest:i_transactor.t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
signal readResponse,writeResponse:i_transactor.t_bfm;
type txStates is (idle,transmitting);
signal txFSM,i_txFSM:txStates;
/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/user.vhdl
92,7 → 92,7
begin
/* Bus functional models. */
axiMaster: entity work.axiBfmMaster(rtl)
axiMaster: entity tauhop.axiBfmMaster(rtl)
port map(
aclk=>irq_write, n_areset=>not reset,
112,7 → 112,7
/* Simulation Tester. */
/* PLL to generate tester's clock. */
f100MHz: entity altera.pll(syn) port map(
areset=>'0', --not reset, --not nReset,
areset=>'0', --not nReset,
inclk0=>clk,
c0=>testerClk,
locked=>open
142,8 → 142,8
end process por;
/* SignalTap II embedded logic analyser. Included as part of BiST architecture. */
anlysr_trigger<='1' when writeRequest.trigger else '0';
--anlysr_trigger<='1' when reset else '0';
--anlysr_trigger<='1' when writeRequest.trigger else '0';
anlysr_trigger<='1' when reset else '0';
/* Disable this for synthesis as this is not currently synthesisable.
Pull the framerFSM statemachine signal from lower down the hierarchy to this level instead.
174,7 → 174,7
/* Simulate only if you have compiled Altera's simulation libraries. */
i_bistFramer_stp_analyser: entity altera.stp(syn) port map(
i_bist_logicAnalyser: entity altera.stp(syn) port map(
acq_clk=>testerClk,
acq_data_in=>anlysr_dataIn,
acq_trigger_in=>"1",
/axi4_tlm_bfm/trunk/workspace/quartus/axi4-tlm.sdc
0,0 → 1,9
#create_clock -period 50MHz -name clk [get_ports {clk}]
derive_pll_clocks -create_base_clock
#if {$::quartus(nameofexecutable) == "quartus_fit"} {
#set_max_delay -from *symbolsPerTransfer* -to *i1_outstandingTransactions* -10.000
#set_min_delay -from *symbolsPerTransfer* -to *i1_outstandingTransactions* -10.000
 
##set_max_delay -to [get_clocks clk] 20
#}
 
/axi4_tlm_bfm/trunk/workspace/quartus/waves.stp
435,17 → 435,16
<net is_signal_inverted="no" name="acq_trigger_in[0]"/>
</setup_view>
</presentation>
<trigger CRC="A1D452D4" gap_record="true" is_expanded="true" name="trigger: 2013/09/25 02:14:11 #1" position="pre" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_port_is_pin="true" storage_qualifier_port_tap_mode="classic" trigger_in="falling edge" trigger_out="active high" trigger_type="circular">
<trigger CRC="A1D452D4" gap_record="true" is_expanded="true" name="trigger: 2013/09/25 02:14:11 #1" position="pre" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_port_is_pin="false" storage_qualifier_port_tap_mode="classic" trigger_in="falling edge" trigger_out="active high" trigger_type="circular">
<power_up_trigger position="pre" trigger_in="dont_care" trigger_out="active high"/>
<events use_custom_flow_control="no">
<level type="basic">
<power_up>
</power_up><op_node/>
<level type="basic"><power_up>
</power_up>
<op_node/>
</level>
</events>
<storage_qualifier>
<transitional>
<pwr_up_transitional/>
<transitional><pwr_up_transitional/>
</transitional>
</storage_qualifier>
<storage_qualifier_events>
464,7 → 463,8
</power_up>
<op_node/>
</storage_qualifier_level>
<transitional><pwr_up_transitional/>
<transitional>
<pwr_up_transitional/>
</transitional>
</storage_qualifier_events>
<log>
725,38 → 725,40
<net is_signal_inverted="no" name="acq_data_in[95]"/>
<net is_signal_inverted="no" name="acq_data_in[96]"/>
<net is_signal_inverted="no" name="acq_data_in[97]"/>
<bus is_signal_inverted="no" link="all" name="acq_data_in[98..101]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<bus alias="porCnt" is_signal_inverted="no" link="all" name="acq_data_in[98..101]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[98]"/>
<net is_signal_inverted="no" name="acq_data_in[99]"/>
<net is_signal_inverted="no" name="acq_data_in[100]"/>
<net is_signal_inverted="no" name="acq_data_in[101]"/>
</bus>
<net is_signal_inverted="no" name="acq_data_in[102]"/>
<net is_signal_inverted="no" name="acq_data_in[103]"/>
<net is_signal_inverted="no" name="acq_data_in[104]"/>
<net is_signal_inverted="no" name="acq_data_in[105]"/>
<net is_signal_inverted="no" name="acq_data_in[106]"/>
<net is_signal_inverted="no" name="acq_data_in[107]"/>
<net is_signal_inverted="no" name="acq_data_in[108]"/>
<net is_signal_inverted="no" name="acq_data_in[109]"/>
<net is_signal_inverted="no" name="acq_data_in[110]"/>
<net is_signal_inverted="no" name="acq_data_in[111]"/>
<net is_signal_inverted="no" name="acq_data_in[112]"/>
<net is_signal_inverted="no" name="acq_data_in[113]"/>
<net is_signal_inverted="no" name="acq_data_in[114]"/>
<net is_signal_inverted="no" name="acq_data_in[115]"/>
<net is_signal_inverted="no" name="acq_data_in[116]"/>
<net is_signal_inverted="no" name="acq_data_in[117]"/>
<net is_signal_inverted="no" name="acq_data_in[118]"/>
<net is_signal_inverted="no" name="acq_data_in[119]"/>
<net is_signal_inverted="no" name="acq_data_in[120]"/>
<net is_signal_inverted="no" name="acq_data_in[121]"/>
<net is_signal_inverted="no" name="acq_data_in[122]"/>
<net is_signal_inverted="no" name="acq_data_in[123]"/>
<net is_signal_inverted="no" name="acq_data_in[124]"/>
<net is_signal_inverted="no" name="acq_data_in[125]"/>
<net is_signal_inverted="no" name="acq_data_in[126]"/>
<net is_signal_inverted="no" name="acq_data_in[127]"/>
<bus is_signal_inverted="no" link="all" name="acq_data_in[102..127]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[102]"/>
<net is_signal_inverted="no" name="acq_data_in[103]"/>
<net is_signal_inverted="no" name="acq_data_in[104]"/>
<net is_signal_inverted="no" name="acq_data_in[105]"/>
<net is_signal_inverted="no" name="acq_data_in[106]"/>
<net is_signal_inverted="no" name="acq_data_in[107]"/>
<net is_signal_inverted="no" name="acq_data_in[108]"/>
<net is_signal_inverted="no" name="acq_data_in[109]"/>
<net is_signal_inverted="no" name="acq_data_in[110]"/>
<net is_signal_inverted="no" name="acq_data_in[111]"/>
<net is_signal_inverted="no" name="acq_data_in[112]"/>
<net is_signal_inverted="no" name="acq_data_in[113]"/>
<net is_signal_inverted="no" name="acq_data_in[114]"/>
<net is_signal_inverted="no" name="acq_data_in[115]"/>
<net is_signal_inverted="no" name="acq_data_in[116]"/>
<net is_signal_inverted="no" name="acq_data_in[117]"/>
<net is_signal_inverted="no" name="acq_data_in[118]"/>
<net is_signal_inverted="no" name="acq_data_in[119]"/>
<net is_signal_inverted="no" name="acq_data_in[120]"/>
<net is_signal_inverted="no" name="acq_data_in[121]"/>
<net is_signal_inverted="no" name="acq_data_in[122]"/>
<net is_signal_inverted="no" name="acq_data_in[123]"/>
<net is_signal_inverted="no" name="acq_data_in[124]"/>
<net is_signal_inverted="no" name="acq_data_in[125]"/>
<net is_signal_inverted="no" name="acq_data_in[126]"/>
<net is_signal_inverted="no" name="acq_data_in[127]"/>
</bus>
</data_view>
<setup_view>
<bus alias="symbolsPerTransfer" is_signal_inverted="no" link="all" name="acq_data_in[0..7]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
869,52 → 871,52
<net is_signal_inverted="no" name="acq_data_in[95]"/>
<net is_signal_inverted="no" name="acq_data_in[96]"/>
<net is_signal_inverted="no" name="acq_data_in[97]"/>
<bus is_signal_inverted="no" link="all" name="acq_data_in[98..101]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<bus alias="porCnt" is_signal_inverted="no" link="all" name="acq_data_in[98..101]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[98]"/>
<net is_signal_inverted="no" name="acq_data_in[99]"/>
<net is_signal_inverted="no" name="acq_data_in[100]"/>
<net is_signal_inverted="no" name="acq_data_in[101]"/>
</bus>
<net is_signal_inverted="no" name="acq_data_in[102]"/>
<net is_signal_inverted="no" name="acq_data_in[103]"/>
<net is_signal_inverted="no" name="acq_data_in[104]"/>
<net is_signal_inverted="no" name="acq_data_in[105]"/>
<net is_signal_inverted="no" name="acq_data_in[106]"/>
<net is_signal_inverted="no" name="acq_data_in[107]"/>
<net is_signal_inverted="no" name="acq_data_in[108]"/>
<net is_signal_inverted="no" name="acq_data_in[109]"/>
<net is_signal_inverted="no" name="acq_data_in[110]"/>
<net is_signal_inverted="no" name="acq_data_in[111]"/>
<net is_signal_inverted="no" name="acq_data_in[112]"/>
<net is_signal_inverted="no" name="acq_data_in[113]"/>
<net is_signal_inverted="no" name="acq_data_in[114]"/>
<net is_signal_inverted="no" name="acq_data_in[115]"/>
<net is_signal_inverted="no" name="acq_data_in[116]"/>
<net is_signal_inverted="no" name="acq_data_in[117]"/>
<net is_signal_inverted="no" name="acq_data_in[118]"/>
<net is_signal_inverted="no" name="acq_data_in[119]"/>
<net is_signal_inverted="no" name="acq_data_in[120]"/>
<net is_signal_inverted="no" name="acq_data_in[121]"/>
<net is_signal_inverted="no" name="acq_data_in[122]"/>
<net is_signal_inverted="no" name="acq_data_in[123]"/>
<net is_signal_inverted="no" name="acq_data_in[124]"/>
<net is_signal_inverted="no" name="acq_data_in[125]"/>
<net is_signal_inverted="no" name="acq_data_in[126]"/>
<net is_signal_inverted="no" name="acq_data_in[127]"/>
<bus is_signal_inverted="no" link="all" name="acq_data_in[102..127]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[102]"/>
<net is_signal_inverted="no" name="acq_data_in[103]"/>
<net is_signal_inverted="no" name="acq_data_in[104]"/>
<net is_signal_inverted="no" name="acq_data_in[105]"/>
<net is_signal_inverted="no" name="acq_data_in[106]"/>
<net is_signal_inverted="no" name="acq_data_in[107]"/>
<net is_signal_inverted="no" name="acq_data_in[108]"/>
<net is_signal_inverted="no" name="acq_data_in[109]"/>
<net is_signal_inverted="no" name="acq_data_in[110]"/>
<net is_signal_inverted="no" name="acq_data_in[111]"/>
<net is_signal_inverted="no" name="acq_data_in[112]"/>
<net is_signal_inverted="no" name="acq_data_in[113]"/>
<net is_signal_inverted="no" name="acq_data_in[114]"/>
<net is_signal_inverted="no" name="acq_data_in[115]"/>
<net is_signal_inverted="no" name="acq_data_in[116]"/>
<net is_signal_inverted="no" name="acq_data_in[117]"/>
<net is_signal_inverted="no" name="acq_data_in[118]"/>
<net is_signal_inverted="no" name="acq_data_in[119]"/>
<net is_signal_inverted="no" name="acq_data_in[120]"/>
<net is_signal_inverted="no" name="acq_data_in[121]"/>
<net is_signal_inverted="no" name="acq_data_in[122]"/>
<net is_signal_inverted="no" name="acq_data_in[123]"/>
<net is_signal_inverted="no" name="acq_data_in[124]"/>
<net is_signal_inverted="no" name="acq_data_in[125]"/>
<net is_signal_inverted="no" name="acq_data_in[126]"/>
<net is_signal_inverted="no" name="acq_data_in[127]"/>
</bus>
<net is_signal_inverted="no" name="acq_trigger_in[0]"/>
</setup_view>
</presentation>
<trigger CRC="A1D452D4" attribute_mem_mode="false" gap_record="true" global_temp="1" is_expanded="true" name="trigger: 2013/09/25 02:14:11 #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="true" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_in="rising edge" trigger_out="active high" trigger_type="circular">
<trigger CRC="A1D452D4" attribute_mem_mode="false" gap_record="true" global_temp="1" is_expanded="true" name="trigger: 2013/09/25 02:14:11 #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="false" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_in="rising edge" trigger_out="active high" trigger_type="circular">
<power_up_trigger position="pre" storage_qualifier_disabled="no" trigger_in="dont_care" trigger_out="active high"/>
<events use_custom_flow_control="no">
<level enabled="yes" name="condition1" type="basic">
<power_up enabled="yes">
<level enabled="yes" name="condition1" type="basic"><power_up enabled="yes">
</power_up><op_node/>
</level>
</events>
<storage_qualifier>
<transitional>
<pwr_up_transitional/>
<transitional><pwr_up_transitional/>
</transitional>
<storage_qualifier_level type="basic">
<power_up>
948,7 → 950,8
</power_up>
<op_node/>
</storage_qualifier_level>
<transitional><pwr_up_transitional/>
<transitional>
<pwr_up_transitional/>
</transitional>
</storage_qualifier_events>
<log>
977,7 → 980,7
<single attribute="hierarchy widget visible" value="1"/>
<single attribute="instance widget visible" value="1"/>
<single attribute="jtag widget visible" value="1"/>
<multi attribute="column width" size="23" value="34,154,108,74,68,70,88,88,98,98,88,88,110,101,101,101,101,101,101,101,101,107,78"/>
<multi attribute="column width" size="23" value="34,147,236,74,68,70,88,88,98,98,88,88,110,101,101,101,101,101,101,101,101,107,78"/>
<multi attribute="frame size" size="2" value="1600,1178"/>
<multi attribute="jtag widget size" size="2" value="398,145"/>
</global_info>

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