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    from Rev 14 to Rev 15
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Rev 14 → Rev 15

/trunk/r2000pl/rtl/verilog/r2000/define.h
59,7 → 59,7
`define ICACHE // Use the Instruction Cache
`define DCACHE // Use the Data Cache
 
`define CP0 // Co processor 0
`define EXCEPTION // Co processor 0
 
/* Length of memories */
`define TAILLE_CODE 100*1024
270,7 → 270,7
`define valid 32 // position
`define dirty 33 // position
 
`ifdef CP0
`ifdef EXCEPTION
/* ************** */
/* Co-Processor 0 */
/* ************** */
290,7 → 290,7
`define GRL_VECTOR_BEV `dw'hBFC0_0380
`define GRL_VECTOR `dw'h0000_0ec0//`dw'h8000_0180
`endif //CP0
`endif //EXCEPTION
 
// I/O
`define UART_WRITE 32'h01000000//32'h20000000
302,7 → 302,7
/* ******************* */
/* BRANCH DECODER MUXC */
/* ******************* */
`ifdef CP0
`ifdef EXCEPTION
`define SELWIDTH 3
`else
`define SELWIDTH 2
312,7 → 312,7
`define BRANCH_REG `SELWIDTH'd1
`define BRANCH_COND `SELWIDTH'd2
`define BRANCH_UNCOND `SELWIDTH'd3
`ifdef CP0
`ifdef EXCEPTION
`define BRANCH_EXCEPTION `SELWIDTH'd4
`endif
 
342,4 → 342,7
/* ************************* */
/* MULTIPLE ARITHEMTIC UNITS */
/* ************************* */
//`define MULTIPLE_ALU
`ifdef EXCEPTION
`else
`define MULTIPLE_ALU
`endif
/trunk/r2000pl/rtl/verilog/r2000/r2000_bradecoder.v
56,9 → 56,9
BranchType_i , // Branch Type from instruction decoder
CondSel_i , // Branch Condition from instruction decoder
Status_i , // Status flags grom the Alu (or comparator)
`ifdef CP0
`ifdef EXCEPTION
Exception_i , // Exception has occured
`endif //CP0
`endif //EXCEPTION
/* Output */
// BrDetect,
BranchSel_o // Selection value for the mux pc
71,9 → 71,9
input [3:0] CondSel_i ;
input [3:0] Status_i ;
`ifdef CP0
`ifdef EXCEPTION
input Exception_i ;
`endif //CP0
`endif //EXCEPTION
 
output[`SELWIDTH-1:0] BranchSel_o ;
// output BrDetect ;
155,9 → 155,9
;
*/
assign BranchSel_o =
`ifdef CP0
`ifdef EXCEPTION
(Exception_i) ? `BRANCH_EXCEPTION:
`endif //CP0
`endif //EXCEPTION
rBranchSel;
endmodule
/trunk/r2000pl/rtl/verilog/r2000/r2000_cpu_pipe.v
85,10 → 85,10
mem_data_bheh_o , // Byte Memory High Enable
`endif// DCACHE
`ifdef CP0
`ifdef EXCEPTION
sig_int_i , // Interrupt exception
sig_si_i , // Software Interrupt
`endif //CP0
`endif //EXCEPTION
 
clk_i , // Clock
rst_i // Reset
117,10 → 117,10
output mem_data_bleh_o ;
`endif// DCACHE
`ifdef CP0
`ifdef EXCEPTION
input[5:0] sig_int_i ;
input[1:0] sig_si_i ;
`endif //CP0
`endif //EXCEPTION
 
input clk_i ;
input rst_i ;
159,10 → 159,10
wire [3:0] ID_ctl_branch_cond ;
wire [3:0] ID_cmp_status ;
wire [`SELWIDTH-1:0]ID_mux_branch_sel
`ifdef CP0
`ifdef EXCEPTION
, EX_mux_branch_sel , MEM_mux_branch_sel ;
reg MEM_branch_Slot // Detect branch slot when exception
`endif //CP0
`endif //EXCEPTION
;
// alu unit
246,7 → 246,7
wire ID_clt_rfe , EX_clt_rfe , MEM_clt_rfe ;
wire ID_clt_CoMf ;
wire ID_clt_CoMt , EX_clt_CoMt , MEM_clt_CoMt ;
`ifdef CP0
`ifdef EXCEPTION
wire [`dw-1:0] IF_EPC , ID_EPC , EX_EPC , MEM_EPC ;
reg [4:0] IF_EXC , ID_EXC , EX_EXC , MEM_EXC ;
wire [`dw-1:0] wEPC_Vector ;
261,7 → 261,7
wire wException ;
wire [`dw-1:0] MEM_cp0_dout ;
`endif //CP0
`endif //EXCEPTION
/* --------------------------------------------------------------
instances, statements
339,10 → 339,10
r2000_pipe #(`dw) IFID_pc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IFID_stall) , .flush_i(IFID_flush) , .D_i(IF_PCplus4) , .Q_o(ID_PCplus4) );
r2000_pipe #(`dw) IFID_inst_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IFID_stall) , .flush_i(IFID_flush) , .D_i(mem_code_inst_i) , .Q_o(ID_inst) );
 
`ifdef CP0
`ifdef EXCEPTION
assign IF_EPC = wPC;
r2000_pipe #(`dw) IFID_epc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IFID_stall) , .flush_i(IFID_flush) , .D_i(IF_EPC) , .Q_o(ID_EPC) );
`endif //CP0
`endif //EXCEPTION
 
/*======================================================================================================================================================*/
/* ID:Instruction Decode STAGE */
429,17 → 429,17
assign ID_reg_rs_forward = (rs_sel == 1) ? EX_result_operation :
(rs_sel == 2) ? MEM_RegDatain :
(rs_sel == 3) ? WB_RegDatain :
`ifdef CP0
`ifdef EXCEPTION
(ID_clt_CoMt || ID_clt_CoMf) ? `ZERO : //Suppress the influence of rs field wich is MT=00100
`endif //CP0
`endif //EXCEPTION
ID_reg_rs ;
assign ID_reg_rt_forward = (rt_sel == 1) ? EX_result_operation :
(rt_sel == 2) ? MEM_RegDatain :
(rt_sel == 3) ? WB_RegDatain :
`ifdef CP0
`ifdef EXCEPTION
(ID_clt_CoMf) ? MEM_cp0_dout :
`endif //CP0
`endif //EXCEPTION
ID_reg_rt ;
 
/* *********************** */
451,7 → 451,7
assign wTargetBranch = { {14{wAdresse16[15]}}, wAdresse16, 2'b0 }; // -- Branch value
assign wTargetJump = { ID_PCplus4[31:28] , wAdresse26, 2'b0 }; // -- Jump value
`ifdef CP0
`ifdef EXCEPTION
r2000_mux5 #(`aw) mux_pc
( /* Input */
.in0_i (IF_PCplus4), // from the pc + 4...
475,7 → 475,7
/* Output */
.out_o (ID_mux_pc_out) // the new pc value choice
);
`endif //CP0
`endif //EXCEPTION
 
assign ID_PCplus8 = ID_PCplus4 + 4; // the pc + 4 was executed in the delay slot so store the pc + 8
494,9 → 494,9
.BranchType_i (ID_ctl_branch_type), // branch type
.CondSel_i (ID_ctl_branch_cond), // branch condition
.Status_i (ID_cmp_status) , // status flags from the alu
`ifdef CP0
`ifdef EXCEPTION
.Exception_i (wException) , // Exception has occured
`endif //CP0
`endif //EXCEPTION
/* Output */
.BranchSel_o (ID_mux_branch_sel) // the branch type of the pc
);
583,7 → 583,7
r2000_pipe #(`dw) IDEX_up_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_imup) , .Q_o(EX_imup) );
r2000_pipe #(`iw) IDEX_rd_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_mux_rd_index_out) , .Q_o(EX_rd_index) );
`ifdef CP0
`ifdef EXCEPTION
r2000_pipe #( 1) IDEX_sig_brk_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(`CLEAR) , .flush_i(`CLEAR) , .D_i(ID_sig_clt_brk) , .Q_o(EX_sig_clt_brk) );
r2000_pipe #( 1) IDEX_sig_sys_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(`CLEAR) , .flush_i(`CLEAR) , .D_i(ID_sig_clt_sys) , .Q_o(EX_sig_clt_sys) );
591,7 → 591,7
r2000_pipe #( 1) IDEX_comt_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_clt_CoMt) , .Q_o(EX_clt_CoMt) );
r2000_pipe #(`dw) IDEX_epc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_EPC) , .Q_o(EX_EPC) );
r2000_pipe #(`SELWIDTH) IDEX_brc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_mux_branch_sel) , .Q_o(EX_mux_branch_sel) );
`endif //CP0
`endif //EXCEPTION
/*======================================================================================================================================================*/
/* EX:Execution STAGE */
/*======================================================================================================================================================*/
633,10 → 633,10
.AluOut_o (EX_alu_out) , // alu result
.Status_o (EX_AluStatus) // status flags
);
`ifdef CP0
`ifdef EXCEPTION
assign {EX_Carry, EX_Zero, EX_Neg, EX_ovf} = EX_AluStatus; // Alu Status
assign EX_sig_ovf = EX_ovf;
`endif //CP0
`endif //EXCEPTION
/* SHIFTER AMOUNT SOURCE */
r2000_mux2 #(5) mux_shift_variable
716,7 → 716,7
r2000_pipe #(`iw) EXMEM_rd_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(EXMEM_stall) , .flush_i(EXMEM_flush) , .D_i(EX_rd_index) , .Q_o(MEM_rd_index) );
r2000_pipe #(`dw) EXMEM_rt_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(EXMEM_stall) , .flush_i(EXMEM_flush) , .D_i(EX_reg_rt) , .Q_o(MEM_reg_rt) );
`ifdef CP0
`ifdef EXCEPTION
r2000_pipe #( 1) EXMEM_sig_brk_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(`CLEAR) , .flush_i(`CLEAR) , .D_i(EX_sig_clt_brk) , .Q_o(MEM_sig_clt_brk) );
r2000_pipe #( 1) EXMEM_sig_sys_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(`CLEAR) , .flush_i(`CLEAR) , .D_i(EX_sig_clt_sys) , .Q_o(MEM_sig_clt_sys) );
r2000_pipe #( 6) EXMEM_sig_int_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(`CLEAR) , .flush_i(`CLEAR) , .D_i(sig_int_i) , .Q_o(MEM_sig_int) );
727,7 → 727,7
r2000_pipe #( 1) EXMEM_rfe_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(EXMEM_stall) , .flush_i(EXMEM_flush) , .D_i(EX_clt_rfe) , .Q_o(MEM_clt_rfe) );
r2000_pipe #(`dw) EXMEM_epc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(EXMEM_stall) , .flush_i(EXMEM_flush) , .D_i(EX_EPC) , .Q_o(MEM_EPC) );
r2000_pipe #(`SELWIDTH) EXMEM_brc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(EXMEM_stall) , .flush_i(EXMEM_flush) , .D_i(EX_mux_branch_sel) , .Q_o(MEM_mux_branch_sel) );
`endif //CP0
`endif //EXCEPTION
/*======================================================================================================================================================*/
/* MEM:Memory STAGE */
/*======================================================================================================================================================*/
805,7 → 805,7
.out_o (MEM_RegDatain) // the result write back to the registerfile
);
 
`ifdef CP0
`ifdef EXCEPTION
always@(`CLOCK_EDGE clk_i, `RESET_EDGE rst_i)
begin
if (rst_i == `RESET_ON)
848,7 → 848,7
.rst_i (rst_i) ,
.clk_i (~clk_i)
);
`endif //CP0
`endif //EXCEPTION
 
/* *************** */
/* MEM/WB PIPELINE */
/trunk/r2000pl/rtl/verilog/r2000/r2000_decoder.v
346,11 → 346,11
`jal : RegDst_o <= 2;
`regimm : if ((ct == `bgezal) || (ct == `bltzal))
RegDst_o <= 2; else RegDst_o <= 0;
`ifdef CP0
`ifdef EXCEPTION
`cop0 : if (rs ==`mf) //MFC0
RegDst_o <= 1; else
RegDst_o <= 0;
`endif //CP0
`endif //EXCEPTION
default : RegDst_o <= 0;
endcase
end
/trunk/r2000pl/rtl/verilog/r2000/r2000_pipe_ctrl.v
165,7 → 165,7
{ EX_freeze , MEM_freeze , WB_freeze} = { `HIGH, `HIGH, `HIGH};
{ IFID_flush , IDEX_flush , EXMEM_flush , MEMWB_flush} = { `LOW, `LOW, `LOW, `LOW};
`ifdef CP0
`ifdef EXCEPTION
 
if (Event_Exception) begin
{ IFID_flush , IDEX_flush , EXMEM_flush , MEMWB_flush} = { `HIGH, `HIGH, `HIGH, `HIGH};
173,7 → 173,7
// else
// Exception event must be treated CONCURRENTLY with the other event that stall the pipeline.
`endif //CP0
`endif //EXCEPTION
 
if(Event_DCacheMiss) begin
{IF_stall, IFID_stall , IDEX_stall , EXMEM_stall , MEMWB_flush} = { `HIGH, `HIGH, `HIGH, `HIGH, `HIGH};
/trunk/r2000pl/rtl/verilog/r2000/r2000_cp0.v
112,7 → 112,7
input rst_i ;
input clk_i ;
`ifdef CP0
`ifdef EXCEPTION
 
/* -------------------------------------------------------------- */
/* registers, wires declaration */
257,5 → 257,5
assign PC_vec_o = rPC_vec;
`endif //CP0
`endif //EXCEPTION
endmodule
/trunk/r2000pl/rtl/verilog/r2000/r2000_cpu.v
82,10 → 82,10
WB_D_RTY ,
WB_D_ERR ,
`ifdef CP0
`ifdef EXCEPTION
SIG_int_i , // Interrupt exception
SIG_si_i , // Software Interrupt
`endif //CP0
`endif //EXCEPTION
 
clk_i , // Clock
rst_i // Reset
111,10 → 111,10
input WB_D_ACK, WB_D_RTY ;
input WB_D_ERR ;
`ifdef CP0
`ifdef EXCEPTION
input[5:0] SIG_int_i ;
input[1:0] SIG_si_i ;
`endif //CP0
`endif //EXCEPTION
 
input clk_i ;
input rst_i ;
208,10 → 208,10
.mem_data_en_o (wMem_data_en) ,
.mem_data_width_o (wMem_data_width), // Byte Memory Width
 
`ifdef CP0
`ifdef EXCEPTION
.sig_int_i (SIG_int_i) , // Interrupt exception
.sig_si_i (SIG_si_i) , // Software Interrupt
`endif //CP0
`endif //EXCEPTION
/* ~~~~~~~~~~~~~ */
/* CLOCK & RESET */
/* ~~~~~~~~~~~~~ */
/trunk/r2000pl/rtl/verilog/r2000_soc.v
67,10 → 67,10
RAM_bleh_o , // Byte Memory Low enable
RAM_bheh_o , // Byte Memory High Enable
`ifdef CP0
`ifdef EXCEPTION
SIG_int_i , // Interrupt exception
SIG_si_i , // Software Interrupt
`endif //CP0
`endif //EXCEPTION
 
clk_i , // Clock
rst_i // Reset
93,10 → 93,10
output RAM_bleh_o ;
output RAM_bheh_o ;
`ifdef CP0
`ifdef EXCEPTION
input[5:0] SIG_int_i ;
input[1:0] SIG_si_i ;
`endif //CP0
`endif //EXCEPTION
 
input clk_i ;
input rst_i ;
186,10 → 186,10
.WB_D_RTY (WB_D_RTY ),
.WB_D_ERR (WB_D_ERR ),
 
`ifdef CP0
`ifdef EXCEPTION
.SIG_int_i (SIG_int_i ), // Interrupt exception
.SIG_si_i (SIG_si_i ), // Software Interrupt
`endif //CP0
`endif //EXCEPTION
 
.clk_i (clk_i ), // Clock
.rst_i (rst_i ) // Reset

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