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B"H

-

Description -of single_port memory and test environment.

-

Abstract:

-

A single port memory with testbench is described. The memory is -implemented as three different architectures.

-

Port Interface:

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

- Port Name -	- Type -	- Description -
- rnwtQ -	- Time -	- Time delay from rnw = read until data appears on q data bus. -
- d -	- data_inter_typ -	- Input data bus, type specified in single_port_pkg -
- q -	- data_inter_typ -	- Output data bus, type specified in single_port_pkg -
- a -	- addr_inter_typ -	- Address bus, type specified in single_port_pkg -
- rnw -	- STD_LOGIC -	- Read not write port -
- dealloc_mem -	- BOOLEAN -	- When set to true, deallocate linked list memory. -

-

Functional Description:

-

The single_port memory is implemented as three different -architecures. The first architecture is called ArrayMemNoFlag, and -implements the memory core as an array of STD_LOGIC_VECTOR. The memory -is asynchronous and triggered on rnw'transaction. When rnw = '0', the -data on bus "d" is loaded into the memory at the location specified by -the addres bus "a". When rnw = '1', the data located in memory address -"a" is loaded onto the output data bus "q". If a memory location is read -which was not written to during the current simulation, 'U' are loaded -onto the memory bus.

-

The second architecture is called ArrayMem, and implements the -memory core as an array of BIT_VECTOR. This arrangement allows less -workstation memory to be used than the ArrayMemNoFlag architecture. The -memory is asynchronous and triggered on rnw'transaction. When rnw = '0', -the data on bus "d" is loaded into the memory at the location specified -by the addres bus "a". When rnw = '1', the data located in memory -address "a" is loaded onto the output data bus "q". If a memory location -is read which was not written to during the current simulation, 'U' are -loaded onto the memory bus.

-

The third architecture is called LinkedList, and implements the -memory core as a linked list of arrays of BIT_VECTOR. Each array in the -linked list is a page of memory whose size is specified in -single_port_pkg. This arrangement allows less workstation memory to be -used than either the ArrayMemNoFlag or ArrayMem architectures. The -memory is asynchronous and triggered on rnw'transaction. When rnw = '0', -the data on bus "d" is loaded into the memory at the location specified -by the addres bus "a". When rnw = '1', the data located in memory -address "a" is loaded onto the output data bus "q". If a memory location -is read which was not written to during the current simulation, 'U' are -loaded onto the memory bus. To de-allocate the memory in the linked -list, set dealloc_mem to true.

-

Functional Timing:

-

The single port memory is asynchronous and is triggered on -rnw'transaction. When rnw is cleared to '0', the write occurs at the -same time as rnw'transaction. When a read occurs, with rnw = '1' , data -appears on the Q bus rnwtQ ns after rnw is set to '1'. The below sample -timing diagram illustrates both a read and write operation.

-

Testbench Description:

-

The test bench is arranged as a client server architecture as -specified by Bergeron¹. A diagram illustrating the -testbench is given below.
-
-
-Two tests are specified in tc_single_port component. The first test -writes data to two logical memory pages, and then reads them back -verifying the correct data. The test case writes an error message to the -console for every miscompare. The second case verifies that the -single_port memory model outputs unknowns to the q bus if a read occurs -for an unwritten memory location. Six configurations are specified in -the test bench architecture tb_single_port, running both tests for each -single_port architecture.
-

-

Usage:

-

A Makefile is used to compile and run all of the tests in a Unix or -like environment, such as Cygwin. The compilation and simulation is -targetted to the SymphonyEDA tool available at www.symphonyeda.com .

-

The source files and Makefile are located in {top}/VHDL
-
-To compile: make com

-

To simulate all of the tests: make sim
-

-

To clean the compiled library: make clean

-

The tests are labeled :

-

ll_error
ll_main
mem_main
-
mem_error
-
memnoflag_main
-
memnoflag_error
-

-

To simulate any of these tests, type make {testname}

-

Please contact Robert Paley at rpaley_yid@opencores.org -if you have any questions or comments.

-

1Writing - Testbenches , Functional Verification of HDL Testbenches. Chapter 6 – -ISBN 0-7923-7766-4

-

- - Index: tags/REL/VHDL/tb_single_port.vhd =================================================================== --- tags/REL/VHDL/tb_single_port.vhd (revision 14) +++ tags/REL/VHDL/tb_single_port.vhd (nonexistent) @@ -1,191 +0,0 @@ --- $Author: rpaley_yid $ --- $Date: 2003-01-14 21:48:11 $ --- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/tb_single_port.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $ --- $Locker --- $Revision: 1.1.1.1 $ --- $State: Exp $ - --- -------------------------------------------------------------------------- --- --- Purpose: This file specifies test bench harness for the single_port --- Memory. It also contains the configuration files for all the --- tests. --- --- --- References: --- 1. The Designer's Guide to VHDL by Peter Ashenden --- ISBN: 1-55860-270-4 (pbk.) --- 2. Writing Testbenches - Functional Verification of HDL models by --- Janick Bergeron | ISBN: 0-7923-7766-4 --- --- Notes: --- --- -------------------------------------------------------------------------- -LIBRARY IEEE; -LIBRARY WORK; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE WORK.linked_list_mem_pkg.ALL; -USE WORK.single_port_pkg.all; -USE STD.TEXTIO.ALL; - -ENTITY tb_single_port IS -END ENTITY tb_single_port; - -ARCHITECTURE BHV of tb_single_port IS - -COMPONENT single_port IS - GENERIC ( - rnwtQ : TIME := 1 NS - ); - PORT ( - d : IN data_inter_typ; - q : OUT data_inter_typ; - a : IN addr_inter_typ; - rnw : IN STD_LOGIC; - dealloc_mem : BOOLEAN -); -END COMPONENT single_port; - -COMPONENT tc_single_port IS - PORT ( - to_srv : OUT to_srv_typ; - frm_srv : IN frm_srv_typ -); -END COMPONENT tc_single_port; - -SIGNAL d : data_inter_typ; -SIGNAL q : data_inter_typ; -SIGNAL a : addr_inter_typ; -SIGNAL rnw : STD_LOGIC; -SIGNAL dealloc_mem : BOOLEAN; -SIGNAL to_srv : to_srv_typ; -SIGNAL frm_srv : frm_srv_typ; -SIGNAL tie_vdd : STD_LOGIC := '1'; -BEGIN - dut : single_port - PORT MAP ( - d => d, - a => a, - q => q, - rnw => rnw, - dealloc_mem => dealloc_mem - ); - - tc : tc_single_port - PORT MAP ( - to_srv => to_srv, - frm_srv => frm_srv - ); - - single_port_server : PROCESS - VARIABLE frm_srv_v : frm_srv_typ; - CONSTANT ACCESS_DELAY : TIME := 5 NS; - BEGIN - -- Wait until the test case is finished setting up the next memory access. - WAIT ON to_srv'TRANSACTION; - CASE to_srv.do IS - WHEN init => - ASSERT FALSE - REPORT "initialized" - SEVERITY NOTE; - WHEN read => -- perform memory read - d <= to_srv.data; - a <= to_srv.addr; - rnw <= '1'; - -- Wait for data to appear - WAIT FOR ACCESS_DELAY; - WHEN write => -- perform memory write - d <= to_srv.data; - a <= to_srv.addr; - rnw <= '0'; - WAIT FOR ACCESS_DELAY; - WHEN dealloc => -- deallocate the linked list for the LL architecture - dealloc_mem <= true; - WHEN end_test => -- reached the end of the test case - WAIT; - END CASE; - frm_srv_v.data := q; - -- Send message to test case to continue the test. - frm_srv <= frm_srv_v ; WAIT FOR 0 NS; - END PROCESS single_port_server; -END BHV; - -CONFIGURATION ll_main_cfg OF TB_SINGLE_PORT IS - FOR BHV - FOR dut : single_port - USE ENTITY work.single_port(LinkedList); - END FOR; -- dut - FOR tc : tc_single_port - USE ENTITY work.tc_single_port(TC0); - END FOR; -- tc; - END FOR; -- BHV -END CONFIGURATION ll_main_cfg; - -CONFIGURATION ll_error_cfg OF TB_SINGLE_PORT IS - FOR BHV - FOR dut : single_port - USE ENTITY work.single_port(LinkedList); - END FOR; -- dut - FOR tc : tc_single_port - USE ENTITY work.tc_single_port(TC1); - END FOR; -- tc; - END FOR; -- BHV -END CONFIGURATION ll_error_cfg ; - -CONFIGURATION mem_main_cfg of TB_SINGLE_PORT IS - FOR BHV - FOR dut : single_port - USE ENTITY work.single_port(ArrayMem); - END FOR; -- dut - FOR tc : tc_single_port - USE ENTITY work.tc_single_port(TC0); - END FOR; -- tc; - END FOR; -- BHV -END CONFIGURATION mem_main_cfg; - -CONFIGURATION mem_error_cfg of TB_SINGLE_PORT IS - FOR BHV - FOR dut : single_port - USE ENTITY work.single_port(ArrayMem); - END FOR; -- dut - FOR tc : tc_single_port - USE ENTITY work.tc_single_port(TC1); - END FOR; -- tc; - END FOR; -- BHV -END CONFIGURATION mem_error_cfg; - -CONFIGURATION memnoflag_main_cfg of TB_SINGLE_PORT IS - FOR BHV - FOR dut : single_port - USE ENTITY work.single_port(ArrayMemNoFlag); - END FOR; -- dut - FOR tc : tc_single_port - USE ENTITY work.tc_single_port(TC0); - END FOR; -- tc; - END FOR; -- BHV -END CONFIGURATION memnoflag_main_cfg; - -CONFIGURATION memnoflag_error_cfg of TB_SINGLE_PORT IS - FOR BHV - FOR dut : single_port - USE ENTITY work.single_port(ArrayMemNoFlag); - END FOR; -- dut - FOR tc : tc_single_port - USE ENTITY work.tc_single_port(TC1); - END FOR; -- tc; - END FOR; -- BHV -END CONFIGURATION memnoflag_error_cfg; - --- $Log: not supported by cvs2svn $ --- Revision 1.1 2003/01/14 17:49:04 Default --- Initial revision --- --- Revision 1.2 2002/12/31 19:19:43 Default --- Updated 'transaction statements for fixed simulator. --- --- Revision 1.1 2002/12/24 18:10:18 Default --- Initial revision --- - - Index: tags/REL/VHDL/tc_single_port.vhd =================================================================== --- tags/REL/VHDL/tc_single_port.vhd (revision 14) +++ tags/REL/VHDL/tc_single_port.vhd (nonexistent) @@ -1,194 +0,0 @@ --- $Author: rpaley_yid $ --- $Date: 2003-01-14 21:48:11 $ --- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/tc_single_port.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $ --- $Locker --- $Revision: 1.1.1.1 $ --- $State: Exp $ - --- -------------------------------------------------------------------------- --- --- Purpose: This file specifies test cases for the single_port --- Memory. --- --- --- References: --- 1. The Designer's Guide to VHDL by Peter Ashenden --- ISBN: 1-55860-270-4 (pbk.) --- 2. Writing Testbenches - Functional Verification of HDL models by --- Janick Bergeron | ISBN: 0-7923-7766-4 --- --- Notes: --- --- -------------------------------------------------------------------------- -LIBRARY IEEE; -LIBRARY WORK; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE WORK.SINGLE_PORT_PKG.ALL; -USE WORK.PKG_IMAGE.ALL; - -ENTITY tc_single_port IS -PORT ( - to_srv : OUT to_srv_typ; - frm_srv : IN frm_srv_typ -); -END ENTITY tc_single_port; - --- -------------------------------------------------- --- Test Case TC0 --- This test case is to check two pages of memory --- Starting at physical address 0x0 , --- Write a '1' to bit position 0, leaving all other bits 0. --- Increment the address, --- Write a '1' to bit position 1, leaving all other bits 0. --- Increment the address. --- Write a '1' to bit position 2, leaving all other bits 0. --- Continue in this fasion, until write a 1 to the MSB. --- increment the address, --- Write a '1' to bit position 0, leaving all other bits 0. --- Continue until the entire page is written to. --- Read back all addresses in the page, ensuring the --- correct data is read back. --- -------------------------------------------------- - - -ARCHITECTURE TC0 OF tc_single_port IS -BEGIN - MAIN : PROCESS - VARIABLE to_srv_v : to_srv_typ; - VARIABLE frm_srv_v : frm_srv_typ; - VARIABLE dv : data_inter_typ := - STD_LOGIC_VECTOR(TO_UNSIGNED(1,data_inter_typ'length)); - VARIABLE offset_v : INTEGER; - BEGIN - offset_v := 0; - -- Run this write/read test 10 times for benchmark - -- purposes. - for i in 0 to 9 loop - for index in 0 to 2*PAGEDEPTH-1 loop - -- Specify to testbench server to perform write operation; - to_srv_v.do := write; - to_srv_v.data := dv; -- specify data to write - dv := To_StdLogicVector(TO_BitVector(dv) rol 1); -- ROL 1 for next write - -- Specify physical address. - to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(index+offset_v, - ADDRESS_WIDTH)); - to_srv <= to_srv_v ; WAIT FOR 0 NS; - WAIT ON frm_srv'TRANSACTION; - end loop; - -- Reset data to 1. - dv := STD_LOGIC_VECTOR(TO_UNSIGNED(1,data_inter_typ'length)); - for index in 0 to 2*PAGEDEPTH-1 loop - -- Perform read operation. - to_srv_v.do := read; - -- Specify physical address. - to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(index+offset_v, - ADDRESS_WIDTH)); - to_srv <= to_srv_v ; WAIT FOR 0 NS; - WAIT ON frm_srv'TRANSACTION; - -- Compare actual with expected read back data, if the - -- the expected and actual to not compare, print the - -- expected and actual values. - ASSERT frm_srv.data = dv - REPORT "Expected: " & HexImage(frm_srv.data) & - " did not equal Actual: " & HexImage(dv) - SEVERITY ERROR; - -- Set expected data for next read. - dv := TO_STDLOGICVECTOR(TO_BITVECTOR(dv) rol 1); - end loop; - end loop; - to_srv_v.do := dealloc; -- Deallocate memory - -- - to_srv <= to_srv_v ; WAIT FOR 0 NS; - -- Tell test bench server process test completed. - to_srv_v.do := end_test; - to_srv <= to_srv_v; - ASSERT FALSE - REPORT "Completed Test TC0" - SEVERITY NOTE; - WAIT; - END PROCESS main; -END TC0; - --- -------------------------------------------------- --- Test Case TC1 --- This test case is to check if the test bench will --- return 'U' for invalid memory locations for --- single_port architectures ArrayMEm and LinkedList --- -------------------------------------------------- -ARCHITECTURE TC1 OF tc_single_port IS -BEGIN - MAIN : PROCESS - VARIABLE to_srv_v : to_srv_typ; - VARIABLE frm_srv_v : frm_srv_typ; - VARIABLE dv : data_inter_typ := (OTHERS => 'U'); - BEGIN - -- Perform read operation. - to_srv_v.do := read; - -- Specify physical address. - to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(0, - ADDRESS_WIDTH)); - to_srv <= to_srv_v; WAIT FOR 0 NS; - WAIT ON frm_srv'TRANSACTION; - -- Compare actual with expected read back data, if the - -- the expected and actual to not compare, print the - -- expected and actual values. - ASSERT frm_srv.data = dv - REPORT "Expected: " & HexImage(frm_srv.data) & - " did not equal Actual: " & HexImage(dv) - SEVERITY ERROR; - - -- Write and read back from same address. - - -- Specify to testbench server to perform write operation; - to_srv_v.do := write; - dv := X"a5a5a5a5"; - to_srv_v.data := dv; -- specify data to write - -- Specify physical address. - to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(0, - ADDRESS_WIDTH)); - to_srv <= to_srv_v; WAIT FOR 0 NS; - -- Wait until the test bench server finished with the write. - -- WAIT UNTIL frm_srv.event = true; - WAIT ON frm_srv'transaction; - - to_srv_v.do := read; - -- Specify physical address. - to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(0, - ADDRESS_WIDTH)); - to_srv <= to_srv_v; WAIT FOR 0 NS; - WAIT ON frm_srv'transaction; - - -- Compare actual with expected read back data, if the - -- the expected and actual to not compare, print the - -- expected and actual values. - ASSERT frm_srv.data = dv - REPORT "Expected: " & HexImage(frm_srv.data) & - " did not equal Actual: " & HexImage(dv) - SEVERITY ERROR; - - to_srv_v.do := dealloc; -- Deallocate memory - -- - to_srv <= to_srv_v; WAIT FOR 0 NS; - -- Tell test bench server process test completed. - to_srv_v.do := end_test; - to_srv <= to_srv_v; WAIT FOR 0 NS; - - ASSERT FALSE - REPORT "Completed Test TC1" - SEVERITY NOTE; - WAIT; - END PROCESS main; -END TC1; - --- $Log: not supported by cvs2svn $ --- Revision 1.1 2003/01/14 17:49:04 Default --- Initial revision --- --- Revision 1.2 2002/12/31 19:19:43 Default --- Updated 'transaction statements for fixed simulator. --- --- Revision 1.1 2002/12/24 18:13:50 Default --- Initial revision --- - Index: tags/REL/VHDL/Makefile =================================================================== --- tags/REL/VHDL/Makefile (revision 14) +++ tags/REL/VHDL/Makefile (nonexistent) @@ -1,161 +0,0 @@ -# -# Description: Top level make file for single_port test project. -# make com to compile -# make sim to simulate all tests -# make ll_error to run this test only -# make ll_main to run this test only -# make mem_main to run this test only -# make mem_error to run this test only -# make memnoflag_main to run this test -# make memnoflag_error to run this test -# $Author: rpaley_yid $ -# $Date: 2003-01-14 21:48:11 $ -# $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/Makefile,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $ -# $Locker: $ -# $Revision: 1.1.1.1 $ -# $State: Exp $ - -# VCOM , VSIM , and WORK variables are set for Sonata simulator, -# Change appropriately for your simulator. Ex.for Modeltech, -# VCOM = vcom -# VSIM = vsim -# WORK = work - -SHELL = /bin/sh -VCOM = vhdlp -VCOMOPT = -s -VSIM = vhdle -VSIMOPT = -WORK = work.sym -## Need to figure out how to put Bourne shell stuff in Makefile -## will do so to generate log files in -## LOGDIR = ../LOG/ -## For now, log files are in VHDL directory. - - -# List of main compiled objects, does not include configurations, -# which are included in the tb_single_port.vhd file. -# These targets are for the Sonata simulator, adjust accordingly for -# your simulator. - -SINGLE_PORT_PKG_OBJ = $(WORK)/single_port_pkg/prim.var -LINKED_LIST_MEM_OBJ = $(WORK)/linked_list_mem_pkg/prim.var -PKG_IMAGE_OBJ = $(WORK)/pkg_image/prim.var -SINGLE_PORT_OBJ = $(WORK)/single_port/prim.var -TC_SINGLE_PORT_OBJ = $(WORK)/tc_single_port/prim.var -TB_SINGLE_PORT_OBJ = $(WORK)/tb_single_port/prim.var -LL_ERROR_DEP = $(WORK)/ll_error_cfg/prim.var -LL_MAIN_DEP = $(WORK)/ll_main_cfg/prim.var -MEM_MAIN_DEP = $(WORK)/mem_main_cfg/prim.var -MEM_ERROR_DEP = $(WORK)/mem_error_cfg/prim.var -MEMNOFLAG_MAIN_DEP = $(WORK)/memnoflag_main_cfg/prim.var -MEMNOFLAG_ERROR_DEP = $(WORK)/memnoflag_error_cfg/prim.var - -LL_ERROR = $(LOGDIR)ll_error.log -LL_MAIN = ll_main.log -MEM_MAIN = mem_main.log -MEM_ERROR = mem_error.log -MEMNOFLAG_MAIN = memnoflag_main.log -MEMNOFLAG_ERROR = memnoflag_error.log - -OBJS = $(SINGLE_PORT_PKG_OBJ) \ - $(LINKED_LIST_MEM_OBJ) \ - $(PKG_IMAGE_OBJ) \ - $(SINGLE_PORT_OBJ) \ - $(TC_SINGLE_PORT_OBJ) \ - $(TB_SINGLE_PORT_OBJ) - -SIMOBJS = $(LL_ERROR) \ - $(LL_MAIN) \ - $(MEM_MAIN) \ - $(MEM_ERROR) \ - $(MEMNOFLAG_MAIN) \ - $(MEMNOFLAG_ERROR) - -# Compile the project -com: $(OBJS) - -# Clean the library -clean:: $(WORK) - -# Simulate all tests -sim: $(SIMOBJS) - -## Run only ll_error test -ll_error: $(LL_ERROR) - -# Run onle ll_main test -ll_main: $(LL_MAIN) - -# Run only mem_main test -mem_main: $(MEM_MAIN) - -# Run only mem_error test -mem_error: $(MEM_ERROR) - -# Run only memnoflag_main test -memnoflag_main: $(MEMNOFLAG_MAIN) - -# Run only memnoflag_error test -memnoflag_error: $(MEMNOFLAG_ERROR) - -# Target dependency rules to run tests -$(LL_ERROR) : $(LL_ERROR_DEP) - $(VSIM) $(VSIMOPT) ll_error_cfg | tee $@ - -$(LL_MAIN) : $(LL_MAIN_DEP) - $(VSIM) $(VSIMOPT) ll_main_cfg | tee $@ - -$(MEM_MAIN) : $(MEM_MAIN_DEP) - $(VSIM) $(VSIMOPT) mem_main_cfg | tee $@ - -$(MEM_ERROR) : $(MEM_ERROR_DEP) - $(VSIM) $(VSIMOPT) mem_error_cfg | tee $@ - -$(MEMNOFLAG_MAIN) : $(MEMNOFLAG_MAIN_DEP) - $(VSIM) $(VSIMOPT) memnoflag_main_cfg | tee $@ - -$(MEMNOFLAG_ERROR) : $(MEMNOFLAG_ERROR_DEP) - $(VSIM) $(VSIMOPT) memnoflag_error_cfg | tee $@ - -# Target dependency rules to compile tests - -$(SINGLE_PORT_PKG_OBJ) : single_port_pkg.vhd - $(VCOM) $(VCOMOPT) $< - -$(LINKED_LIST_MEM_OBJ) : linked_list_mem_pkg.vhd \ - $(SINGLE_PORT_PKG_OBJ) - $(VCOM) $(VCOMOPT) $< - -$(PKG_IMAGE_OBJ) : pkg_image.vhd - $(VCOM) $(VCOMOPT) $< - -$(SINGLE_PORT_OBJ) : single_port.vhd \ - $(SINGLE_PORT_PKG_OBJ) \ - $(LINKED_LIST_MEM_OBJ) - $(VCOM) $(VCOMOPT) $< - -$(TC_SINGLE_PORT_OBJ) : tc_single_port.vhd \ - $(SINGLE_PORT_PKG_OBJ) \ - $(PKG_IMAGE_OBJ) \ - $(SINGLE_PORT_OBJ) - $(VCOM) $(VCOMOPT) $< - -$(TB_SINGLE_PORT_OBJ) : tb_single_port.vhd \ - $(SINGLE_PORT_PKG_OBJ) \ - $(LINKED_LIST_MEM_OBJ) \ - $(SINGLE_PORT_OBJ) \ - $(TC_SINGLE_PORT_OBJ) - $(VCOM) $(VCOMOPT) $< - -$(WORK) :: - rm -rf $(WORK)/* - - -#################################################################### -# $Log: not supported by cvs2svn $ -# Revision 1.1 2002/12/31 19:21:59 Default -# Initial revision -# -# - Index: tags/REL/VHDL/linked_list_mem_pkg.vhd =================================================================== --- tags/REL/VHDL/linked_list_mem_pkg.vhd (revision 14) +++ tags/REL/VHDL/linked_list_mem_pkg.vhd (nonexistent) @@ -1,147 +0,0 @@ --- $Author: rpaley_yid $ --- $Date: 2003-01-14 21:48:10 $ --- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/linked_list_mem_pkg.vhd,v 1.1.1.1 2003-01-14 21:48:10 rpaley_yid Exp $ --- $Locker --- $Revision: 1.1.1.1 $ --- $State: Exp $ - --- -------------------------------------------------------------------------- --- --- Purpose: This package implements functions to allocate, write, read, and --- deallocate a linked list based memory. --- --- --- References: --- 1. The Designer's Guide to VHDL by Peter Ashenden --- ISBN: 1-55860-270-4 (pbk.) --- 2. Writing Testbenches - Functional Verification of HDL models by --- Janick Bergeron | ISBN: 0-7923-7766-4 --- --- Notes: --- --- -------------------------------------------------------------------------- - -LIBRARY IEEE; -LIBRARY WORK; -USE IEEE.STD_LOGIC_1164.ALL; -USE WORK.single_port_pkg.all; - -PACKAGE linked_list_mem_pkg IS - -- data memory array type definition - TYPE mem_array_typ IS ARRAY (0 TO PAGEDEPTH-1) OF data_typ; - -- Define memory page linked list cell. This cell contains, - -- the mem_array, starting page address, valid data array, and - -- the pointer to the next element in the linked list. - TYPE mem_page_typ; - -- pointer to next item in the linked list. - TYPE mem_page_ptr IS ACCESS mem_page_typ; - TYPE mem_page_typ IS RECORD - mem_array : mem_array_typ; -- data memory - -- This array is a flag which indicates if the corresponding - -- address location inside mem_array contains valid data. - data_valid_array : BIT_VECTOR( 0 TO PAGEDEPTH-1); - page_address : addr_typ; - next_cell : mem_page_ptr; - END RECORD mem_page_typ; - PROCEDURE rw_mem ( - VARIABLE data : INOUT data_inter_typ; - VARIABLE addr : addr_typ; - VARIABLE write_flag : BOOLEAN; - VARIABLE next_cell : INOUT mem_page_ptr - ); - PROCEDURE deallocate_mem ( - VARIABLE next_cell : INOUT mem_page_ptr - ); - -END PACKAGE linked_list_mem_pkg; - -PACKAGE BODY LINKED_LIST_MEM_PKG IS - -- -------------------------------------------------- - -- The purpose of this procedure is to write a memory location from - -- the linked list, if the particular page does not exist, create it. - -- -------------------------------------------------- - PROCEDURE rw_mem ( - VARIABLE data : INOUT data_inter_typ; - VARIABLE addr : addr_typ; - VARIABLE write_flag : BOOLEAN; - VARIABLE next_cell : INOUT mem_page_ptr - ) IS - VARIABLE current_cell_v : mem_page_ptr; -- current page pointer - VARIABLE page_address_v : addr_typ; -- calculated page address - VARIABLE index_v : INTEGER; -- address within the memory page - VARIABLE mem_array_v : mem_array_typ; - VARIABLE data_valid_array_v : BIT_VECTOR(0 TO PAGEDEPTH-1); - BEGIN - -- Copy the top of the linked list pointer to a working pointer - current_cell_v := next_cell; - -- Calculate the index within the page from the given address - index_v := addr MOD PAGEDEPTH; - -- Calculate the page address from the given address - page_address_v := addr - index_v; - -- Search through the memory to determine if the calculated - -- memory page exists. Stop searching when reach the end of - -- the linked list. - WHILE ( current_cell_v /= NULL - AND current_cell_v.page_address /= page_address_v) LOOP - current_cell_v := current_cell_v.next_cell; - END LOOP; - - IF write_flag THEN - IF ( current_cell_v /= NULL AND -- Check if address exists in memory. - current_cell_v.page_address = page_address_v - ) THEN - -- Found the memory page the particular address belongs to - current_cell_v.mem_array(index_v) := TO_BITVECTOR(data); - -- set memory location valid flag - current_cell_v.data_valid_array(index_v) := '1'; - ELSE - -- The memory page the address belongs to was not allocated in memory. - -- Allocate page here and assign data. - mem_array_v(index_v) := TO_BITVECTOR(data); - data_valid_array_v(index_v) := '1'; - next_cell := NEW mem_page_typ'( mem_array => mem_array_v, - data_valid_array => data_valid_array_v, - page_address => page_address_v, - next_cell => next_cell - ); - END IF; - ELSE -- Read memory - IF ( current_cell_v /= NULL AND -- Check if address exists in memory. - current_cell_v.page_address = page_address_v AND - current_cell_v.data_valid_array(index_v) = '1' - ) THEN - -- Found the memory page the particular address belongs to, - -- and the memory location has valid data. - data := TO_STDLOGICVECTOR(current_cell_v.mem_array(index_v)); - ELSE - -- Trying to read from unwritten or unallocated - -- memory location, return 'U'; - data := (OTHERS => 'U'); - END IF; - END IF; - END PROCEDURE rw_mem; - - PROCEDURE deallocate_mem ( - VARIABLE next_cell : INOUT mem_page_ptr - ) IS - VARIABLE delete_cell_v : mem_page_ptr; - BEGIN - -- Deallocate the linked link memory from work station memory. - WHILE next_cell /= NULL LOOP -- while not reached the end of the LL - delete_cell_v := next_cell; -- Copy pointer to record for deleting - next_cell := next_cell.next_cell; -- set pointer to next cell in LL - deallocate(delete_cell_v); -- Deallocate current cell from memory. - END LOOP; - END PROCEDURE deallocate_mem; -END PACKAGE BODY LINKED_LIST_MEM_PKG; - --- $Log: not supported by cvs2svn $ --- Revision 1.1 2003/01/14 17:47:32 Default --- Initial revision --- --- Revision 1.1 2002/12/24 18:03:50 Default --- Initial revision --- - - - Index: tags/REL/VHDL/pkg_image.vhd =================================================================== --- tags/REL/VHDL/pkg_image.vhd (revision 14) +++ tags/REL/VHDL/pkg_image.vhd (nonexistent) @@ -1,307 +0,0 @@ --- $Author: rpaley_yid $ --- $Date: 2003-01-14 21:48:10 $ --- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/pkg_image.vhd,v 1.1.1.1 2003-01-14 21:48:10 rpaley_yid Exp $ --- $Locker --- $Revision: 1.1.1.1 $ --- $State: Exp $ - --- Copyright (c) 1997 Ben Cohen. All rights reserved. --- This model can be used in conjunction with the Kluwer Academic books --- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0 --- "VHDL Amswers to Frequently Asked Questions", Kluwer Academic --- by Ben Cohen. email: vhdlcohen@aol.com --- --- This source file for the Image Package --- may be used and distributed without restriction provided --- that this copyright statement is not removed from the file --- and that any derivative work contains this copyright notice. --- --- --- Original Author: Ben Cohen --- Description: --- Convert VHDL types to string for printing. This is especially useful when --- compiling with VHDL-87 - ---------------------------------------------------------------- -LIBRARY IEEE; - USE IEEE.STD_LOGIC_1164.ALL; - USE IEEE.STD_LOGIC_TEXTIO.ALL; - USE IEEE.NUMERIC_STD.ALL; - -LIBRARY STD; - USE STD.TEXTIO.ALL; - -package pkg_image is - function Image(In_Image : Time) return String; - function Image(In_Image : Bit) return String; - function Image(In_Image : Bit_Vector) return String; - function Image(In_Image : Integer) return String; - function Image(In_Image : Real) return String; - function Image(In_Image : Std_uLogic) return String; - function Image(In_Image : Std_uLogic_Vector) return String; - function Image(In_Image : Std_Logic_Vector) return String; - function Image(In_Image : Signed) return String; - function Image(In_Image : UnSigned) return String; - - function HexImage(InStrg : String) return String; - function HexImage(In_Image : Bit_Vector) return String; - function HexImage(In_Image : Std_uLogic_Vector) return String; - function HexImage(In_Image : Std_Logic_Vector) return String; - function HexImage(In_Image : Signed) return String; - function HexImage(In_Image : UnSigned) return String; - - function DecImage(In_Image : Bit_Vector) return String; - function DecImage(In_Image : Std_uLogic_Vector) return String; - function DecImage(In_Image : Std_Logic_Vector) return String; - function DecImage(In_Image : Signed) return String; - function DecImage(In_Image : UnSigned) return String; -end pkg_image; - -package body pkg_image is - function Image(In_Image : Time) return String is - variable L : Line; -- access type - variable W : String(1 to 14) := (others => ' '); - -- Long enough to hold a time string - begin - -- the WRITE procedure creates an object with "NEW". - -- L is passed as an output of the procedure. - Std.TextIO.WRITE(L, in_image); - -- Copy L.all onto W - W(L.all'range) := L.all; - Deallocate(L); - return W; - end Image; - - function Image(In_Image : Bit) return String is - variable L : Line; -- access type - variable W : String(1 to 3) := (others => ' '); - begin - Std.TextIO.WRITE(L, in_image); - W(L.all'range) := L.all; - Deallocate(L); - return W; - end Image; - - function Image(In_Image : Bit_Vector) return String is - variable L : Line; -- access type - variable W : String(1 to In_Image'length) := (others => ' '); - begin - Std.TextIO.WRITE(L, in_image); - W(L.all'range) := L.all; - Deallocate(L); - return W; - end Image; - - function Image(In_Image : Integer) return String is - variable L : Line; -- access type - variable W : String(1 to 32) := (others => ' '); - -- Long enough to hold a time string - begin - Std.TextIO.WRITE(L, in_image); - W(L.all'range) := L.all; - Deallocate(L); - return W; - end Image; - - function Image(In_Image : Real) return String is - variable L : Line; -- access type - variable W : String(1 to 32) := (others => ' '); - -- Long enough to hold a time string - begin - Std.TextIO.WRITE(L, in_image); - W(L.all'range) := L.all; - Deallocate(L); - return W; - end Image; - - function Image(In_Image : Std_uLogic) return String is - variable L : Line; -- access type - variable W : String(1 to 3) := (others => ' '); - begin - IEEE.Std_Logic_Textio.WRITE(L, in_image); - W(L.all'range) := L.all; - Deallocate(L); - return W; - end Image; - - function Image(In_Image : Std_uLogic_Vector) return String is - variable L : Line; -- access type - variable W : String(1 to In_Image'length) := (others => ' '); - begin - IEEE.Std_Logic_Textio.WRITE(L, in_image); - W(L.all'range) := L.all; - Deallocate(L); - return W; - end Image; - - function Image(In_Image : Std_Logic_Vector) return String is - variable L : Line; -- access type - variable W : String(1 to In_Image'length) := (others => ' '); - begin - IEEE.Std_Logic_TextIO.WRITE(L, In_Image); - W(L.all'range) := L.all; - Deallocate(L); - return W; - end Image; - - function Image(In_Image : Signed) return String is - begin - return Image(Std_Logic_Vector(In_Image)); - end Image; - - function Image(In_Image : UnSigned) return String is - begin - return Image(Std_Logic_Vector(In_Image)); - end Image; - - function HexImage(InStrg : String) return String is - subtype Int03_Typ is Integer range 0 to 3; - variable Result : string(1 to ((InStrg'length - 1)/4)+1) := - (others => '0'); - variable StrTo4 : string(1 to Result'length * 4) := - (others => '0'); - variable MTspace : Int03_Typ; -- Empty space to fill in - variable Str4 : String(1 to 4); - variable Group_v : Natural := 0; - begin - MTspace := Result'length * 4 - InStrg'length; - StrTo4(MTspace + 1 to StrTo4'length) := InStrg; -- padded with '0' - Cnvrt_Lbl : for I in Result'range loop - Group_v := Group_v + 4; -- identifies end of bit # in a group of 4 - Str4 := StrTo4(Group_v - 3 to Group_v); -- get next 4 characters - case Str4 is - when "0000" => Result(I) := '0'; - when "0001" => Result(I) := '1'; - when "0010" => Result(I) := '2'; - when "0011" => Result(I) := '3'; - when "0100" => Result(I) := '4'; - when "0101" => Result(I) := '5'; - when "0110" => Result(I) := '6'; - when "0111" => Result(I) := '7'; - when "1000" => Result(I) := '8'; - when "1001" => Result(I) := '9'; - when "1010" => Result(I) := 'A'; - when "1011" => Result(I) := 'B'; - when "1100" => Result(I) := 'C'; - when "1101" => Result(I) := 'D'; - when "1110" => Result(I) := 'E'; - when "1111" => Result(I) := 'F'; - when others => Result(I) := 'X'; - end case; -- Str4 - end loop Cnvrt_Lbl; - - return Result; - end HexImage; - - - function HexImage(In_Image : Bit_Vector) return String is - begin - return HexImage(Image(In_Image)); - end HexImage; - - function HexImage(In_Image : Std_uLogic_Vector) return String is - begin - return HexImage(Image(In_Image)); - end HexImage; - - function HexImage(In_Image : Std_Logic_Vector) return String is - begin - return HexImage(Image(In_Image)); - end HexImage; - - function HexImage(In_Image : Signed) return String is - begin - return HexImage(Image(In_Image)); - end HexImage; - - function HexImage(In_Image : UnSigned) return String is - begin - return HexImage(Image(In_Image)); - end HexImage; - - function DecImage(In_Image : Bit_Vector) return String is - variable In_Image_v : Bit_Vector(In_Image'length downto 1) := In_Image; - begin - if In_Image'length > 31 then - assert False - report "Number too large for Integer, clipping to 31 bits" - severity Warning; - return Image(To_Integer - (Unsigned(To_StdLogicVector - (In_Image_v(31 downto 1))))); - else - return Image(To_Integer(Unsigned(To_StdLogicVector(In_Image)))); - end if; - end DecImage; - - function DecImage(In_Image : Std_uLogic_Vector) return String is - variable In_Image_v : Std_uLogic_Vector(In_Image'length downto 1) - := In_Image; - begin - if In_Image'length > 31 then - assert False - report "Number too large for Integer, clipping to 31 bits" - severity Warning; - return Image(To_Integer(Unsigned(In_Image_v(31 downto 1)))); - else - return Image(To_Integer(Unsigned(In_Image))); - end if; - end DecImage; - - function DecImage(In_Image : Std_Logic_Vector) return String is - variable In_Image_v : Std_Logic_Vector(In_Image'length downto 1) - := In_Image; - begin - if In_Image'length > 31 then - assert False - report "Number too large for Integer, clipping to 31 bits" - severity Warning; - return Image(To_Integer(Unsigned(In_Image_v(31 downto 1)))); - else - return Image(To_Integer(Unsigned(In_Image))); - end if; - end DecImage; - - function DecImage(In_Image : Signed) return String is - variable In_Image_v : Signed(In_Image'length downto 1) := In_Image; - begin - if In_Image'length > 31 then - assert False - report "Number too large for Integer, clipping to 31 bits" - severity Warning; - return Image(To_Integer(In_Image_v(31 downto 1))); - else - return Image(To_Integer(In_Image)); - end if; - end DecImage; - - function DecImage(In_Image : UnSigned) return String is - variable In_Image_v : UnSigned(In_Image'length downto 1) := In_Image; - begin - if In_Image'length > 31 then - assert False - report "Number too large for Integer, clipping to 31 bits" - severity Warning; - return Image(To_Integer(In_Image_v(31 downto 1))); - else - return Image(To_Integer(In_Image)); - end if; - end DecImage; - -end pkg_image; - --- $Log: not supported by cvs2svn $ --- Revision 1.1 2003/01/14 17:48:44 Default --- Initial revision --- --- Revision 1.1 2002/12/24 18:07:50 Default --- Initial revision --- - - - - - - - - Index: tags/REL/VHDL/single_port.vhd =================================================================== --- tags/REL/VHDL/single_port.vhd (revision 14) +++ tags/REL/VHDL/single_port.vhd (nonexistent) @@ -1,131 +0,0 @@ --- $Author: rpaley_yid $ --- $Date: 2003-01-14 21:48:11 $ --- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/single_port.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $ --- $Locker --- $Revision: 1.1.1.1 $ --- $State: Exp $ - --- -------------------------------------------------------------------------- --- --- Purpose: This is a single port asynchronous memory. This files --- describes three architectures. Two architectures are traditional --- array based memories. One describes the memory as an array of --- STD_LOGIC_VECTOR, and the other describes the ARRAY as BIT_VECTOR. --- The third architecture describes the memory arranged as a linked --- list in order to conserve computer memory usage. The memory --- is organized as a linked list of BIT_VECTOR arrays whose size --- is defined PAGEDEPTH in single_port_pkg.vhd. --- --- --- References: --- 1. The Designer's Guide to VHDL by Peter Ashenden --- ISBN: 1-55860-270-4 (pbk.) --- 2. Writing Testbenches - Functional Verification of HDL models by --- Janick Bergeron | ISBN: 0-7923-7766-4 --- --- Notes: --- --- -------------------------------------------------------------------------- -LIBRARY IEEE; -LIBRARY WORK; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE WORK.single_port_pkg.ALL; -USE WORK.linked_list_mem_pkg.ALL; - -ENTITY single_port IS - GENERIC ( - rnwtQ : TIME := 1 NS - ); - PORT ( - d : IN data_inter_typ; - q : OUT data_inter_typ; - a : IN addr_inter_typ; - rnw : IN STD_LOGIC; - dealloc_mem : IN BOOLEAN - ); -END ENTITY single_port; - -ARCHITECTURE ArrayMemNoFlag OF single_port IS -BEGIN - - mem_proc : PROCESS - TYPE mem_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1) OF data_inter_typ; - VARIABLE mem : mem_typ; - BEGIN - WAIT on rnw'transaction; - IF ( rnw = '0') THEN -- Write - mem(TO_INTEGER(unsigned(a))) := d; - ELSE -- Read - q <= mem(TO_INTEGER(unsigned(a))) AFTER rnwtQ; - END IF; - END PROCESS mem_proc; - -END ArrayMemNoFlag; - -ARCHITECTURE ArrayMem OF single_port IS -BEGIN - - mem_proc : PROCESS - TYPE mem_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF data_typ; - TYPE flag_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF BOOLEAN; - VARIABLE mem : mem_typ; - VARIABLE flag : flag_typ; - BEGIN - WAIT ON rnw'transaction; - IF ( rnw = '0') THEN -- Write - mem(TO_INTEGER(unsigned(a))) := TO_BITVECTOR(d); - flag(TO_INTEGER(unsigned(a))) := true; -- set valid memory location flag - ELSE -- read data, either valid or 'U' - IF ( flag(TO_INTEGER(unsigned(a))) = true ) THEN - q <= TO_STDLOGICVECTOR(mem(TO_INTEGER(unsigned(a)))) AFTER rnwtQ; - ELSE -- reading invalid memory location - q <= (OTHERS => 'U') after rnwtQ; - END IF; - END IF; - END PROCESS mem_proc; -END ArrayMem; - -ARCHITECTURE LinkedList OF single_port IS - BEGIN - - mem_proc : PROCESS - VARIABLE mem_page_v : mem_page_ptr; - VARIABLE d_v : data_inter_typ; - VARIABLE a_v : addr_typ; - VARIABLE WRITE_MEM_v : BOOLEAN := true; - VARIABLE READ_MEM_v : BOOLEAN := false; - BEGIN - WAIT ON dealloc_mem'transaction , rnw'TRANSACTION; - IF NOT dealloc_mem THEN - d_v := d; - a_v := TO_INTEGER(unsigned(a)); - IF ( rnw = '0' ) THEN -- write to linked list memory - rw_mem( data => d_v, - addr => a_v, - write_flag => WRITE_MEM_v, - next_cell => mem_page_v - ); - ELSE -- read from linked list memory - rw_mem( data => d_v, - addr => a_v, - write_flag => READ_MEM_v, - next_cell => mem_page_v - ); - q <= d_v after rnwtQ; - END IF; - ELSE -- Deallocate memory from work station memory. - deallocate_mem(mem_page_v); - END IF; - END PROCESS mem_proc; - -END LinkedList; - --- $Log: not supported by cvs2svn $ --- Revision 1.1 2003/01/14 17:48:31 Default --- Initial revision --- --- Revision 1.1 2002/12/24 18:09:05 Default --- Initial revision --- - Index: tags/REL/VHDL/single_port_pkg.vhd =================================================================== --- tags/REL/VHDL/single_port_pkg.vhd (revision 14) +++ tags/REL/VHDL/single_port_pkg.vhd (nonexistent) @@ -1,70 +0,0 @@ --- $Author: rpaley_yid $ --- $Date: 2003-01-14 21:48:11 $ --- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/single_port_pkg.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $ --- $Locker: $ --- $Revision: 1.1.1.1 $ --- $State: Exp $ - --- -------------------------------------------------------------------------- --- --- Purpose: Package file for single_port memory and testbench --- --- References: --- 1. The Designer's Guide to VHDL by Peter Ashenden --- ISBN: 1-55860-270-4 (pbk.) --- 2. Writing Testbenches - Functional Verification of HDL models by --- Janick Bergeron | ISBN: 0-7923-7766-4 --- --- Notes: --- --- -------------------------------------------------------------------------- - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -PACKAGE single_port_pkg IS -CONSTANT PAGEDEPTH : INTEGER := 256; -- memory page depth -CONSTANT PAGENUM : INTEGER := 4096; -- number of pages in memory. -CONSTANT DATA_WIDTH : INTEGER := 32; -- memory data bus width -CONSTANT ADDRESS_WIDTH : INTEGER := 16; -- memory address bus width --- Data bus type for memory interface -SUBTYPE data_inter_typ IS STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0); --- Data bus type for internal memory -SUBTYPE data_typ IS BIT_VECTOR(DATA_WIDTH-1 DOWNTO 0); --- Address bus type for memory interface -SUBTYPE addr_inter_typ IS STD_LOGIC_VECTOR(ADDRESS_WIDTH-1 DOWNTO 0); --- Address bus type for internal memory -SUBTYPE addr_typ IS NATURAL; --- Operations testbench can do. -TYPE do_typ IS ( init , read , write , dealloc , end_test ); - -TYPE to_srv_typ IS RECORD -- Record passed from test case to test bench - do : do_typ; - addr : addr_inter_typ; - data : data_inter_typ; - event : BOOLEAN; -END RECORD to_srv_typ; - -TYPE frm_srv_typ IS RECORD -- Record passed from test bench to test case - data : data_inter_typ; - event : BOOLEAN; -END RECORD frm_srv_typ; - - -END PACKAGE single_port_pkg; - -PACKAGE BODY single_port_pkg IS - -END PACKAGE BODY single_port_pkg; - --- $Log: not supported by cvs2svn $ --- Revision 1.1 2003/01/14 17:48:44 Default --- Initial revision --- --- Revision 1.1 2002/12/24 17:58:49 Default --- Initial revision --- - - - Index: trunk/images/tbschematic.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/images/tbschematic.png =================================================================== --- trunk/images/tbschematic.png (revision 14) +++ trunk/images/tbschematic.png (nonexistent)

trunk/images/tbschematic.png Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/images/timing.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/images/timing.png =================================================================== --- trunk/images/timing.png (revision 14) +++ trunk/images/timing.png (nonexistent)

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trunk/images/timing.dia Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/doc/copying.txt =================================================================== --- trunk/doc/copying.txt (revision 14) +++ trunk/doc/copying.txt (nonexistent) @@ -1,504 +0,0 @@ - GNU LESSER GENERAL PUBLIC LICENSE - Version 2.1, February 1999 - - Copyright (C) 1991, 1999 Free Software Foundation, Inc. - 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - -[This is the first released version of the Lesser GPL. It also counts - as the successor of the GNU Library Public License, version 2, hence - the version number 2.1.] - - Preamble - - The licenses for most software are designed to take away your -freedom to share and change it. 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See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - -Also add information on how to contact you by electronic and paper mail. - -You should also get your employer (if you work as a programmer) or your -school, if any, to sign a "copyright disclaimer" for the library, if -necessary. Here is a sample; alter the names: - - Yoyodyne, Inc., hereby disclaims all copyright interest in the - library `Frob' (a library for tweaking knobs) written by James Random Hacker. - - , 1 April 1990 - Ty Coon, President of Vice - -That's all there is to it! - - Index: trunk/doc/single_port.html =================================================================== --- trunk/doc/single_port.html (revision 14) +++ trunk/doc/single_port.html (nonexistent) @@ -1,366 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - -

- -

Description - of single_port memory and test environment.

- -

Abstract:

- -

A VHDL simulation model for an asynchronous static single - port memory is described. The memory is implemented as three different - architectures, a simple one and 2 ones which are optimized for efficient - use of simulator memory. Data and address buses are unconstrained, so -multiple instances with different address and data bus widths can be implemented -in one single design. A testbench is also provided.
-

- -

Port Interface:

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

- - Port Name -	- - Type -	- - Description -
- - rnwtQ -	- - Time -	- - Time delay until data or tristate appears on q data bus. -
- - d -	STD_LOGIC_VECTOR -	- - Input data bus, unconstrained -
- - q -	- - STD_LOGIC_VECTOR - -	- - Output data bus, unconstrained -
- - a -	- - STD_LOGIC_VECTOR - -	- - Address bus, unconstrained -
- - nce -	- - STD_LOGIC -	- - not chip enable -
nwe -	STD_LOGIC -	not write enable -
noe -	STD_LOGIC -	not output enable -
- - dealloc_mem -	- - BOOLEAN -	- - When set to true, deallocate linked list memory. -

- -

Functional Description:

- -

All 3 architectures functionally behave like commercially - available asynchronous SRAMs if you connect d and q to the same bus. If a memory location is read which was not written to during the - current simulation, 'U's are loaded onto the memory bus.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

nce -	nwe -	noe -	d -	q -	Mode -
1 -	don't care -	don't care -	don't care -	high Z -	deselected -
0 -	1 -	1 -	don't care -	high Z -	output disabled -
0 -	0 -	don't care -	input data -	high Z -	write -
0 -	1 -	0 -	don't care -	RAM content -	read -

- -

Architecture ArrayMemNoFlag

- -

This architecture implements the memory core as an array - of STD_LOGIC_VECTOR. This is the simplest architecture. It is provided - for comparison with the models below but not recommended for use in your - design.

- -

Architecture ArrayMem

- -

This architecture implements the - memory core as an array of BIT_VECTOR. This arrangement allows less workstation - memory to be used than the ArrayMemNoFlag architecture. Use this architecture - if most addresses in the simulated memory are written at least once.
-

- -

Architecture LinkedList

- -

- This architecture implements the memory core as a linked - list of arrays of BIT_VECTOR. Each array in the linked list is a page -of memory whose size is specified with the constant PAGEDEPTH in the package - linked_list_mem_pkg. This arrangement allows less workstation memory -to be used than either the ArrayMemNoFlag or ArrayMem architectures because - memory representing the array data is only allocated if the memory is -actually written to. To de-allocate the memory in the linked list, set -dealloc_mem to true. A short pulse is sufficient. Use this architecture - if a significant portion of your simulated memory (which need not be -contiguous) is never written to. -

Example Timing:

- -

Clearing both nce and nwe to to '0' immediately causes -a write operation. Changing the address while nce and nwe are asserted causes - a write to the new address, too (But don't do that with real RAMs because - you could destroy more memory locations while the address bus settles). -Every read (and tristate) operation is delayed rnwtQ ns. The below sample - timing diagram illustrates both a read and write operation.

- -

Timing diagram -
-

- -

Testbench Description:

- -

The test bench is arranged as a client server architecture as specified - by Bergeron¹. A diagram illustrating the testbench - is given below.

- -

Testbench schematic -
- Two tests are specified in tc_single_port component. The first test - writes data to two logical memory pages, and then reads them back verifying - the correct data. The test case writes an error message to the console -for every miscompare. The second case verifies that the single_port memory -model outputs unknowns to the q bus if a read occurs for an unwritten memory -location. Six configurations are specified in the test bench architecture -tb_single_port, running both tests for each single_port architecture.
-

- -

Usage:

- -

A Makefile is used to compile and run all of the tests in a Unix or like - environment, such as Cygwin. The compilation and simulation is targetted - to the SymphonyEDA tool available at www.symphonyeda.com.

- -

The source files and Makefile are located in {top}/VHDL
-
- To compile: make com

- -

To simulate all of the tests: make sim
-

- -

To clean the compiled library: make clean

- -

The tests are labeled :

- -

ll_error
ll_main
mem_main
-
mem_error
-
memnoflag_main
-
memnoflag_error
-

- -

To simulate any of these tests, type make {testname}

- -

Please contact Robert Paley at rpaley_yid@opencores.org - or Michael Geng at vhdl@michaelgeng.de - if you have any questions or comments.

- -

-

1Writing - Testbenches , Functional Verification of HDL Testbenches. Chapter 6 – - ISBN 0-7923-7766-4
-

-

-
-
-
- - Index: trunk/VHDL/linked_list_mem_pkg.vhd =================================================================== --- trunk/VHDL/linked_list_mem_pkg.vhd (revision 14) +++ trunk/VHDL/linked_list_mem_pkg.vhd (nonexistent) @@ -1,174 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- Single port asynchronous RAM simulation model ---- ----- ---- ----- This file is part of the single_port project ---- ----- ---- ----- Description ---- ----- This package implements functions to allocate, write, read ---- ----- and deallocate a linked list based memory. ---- ----- ---- ----- Authors: ---- ----- - Robert Paley, rpaley_yid@yahoo.com ---- ----- - Michael Geng, vhdl@MichaelGeng.de ---- ----- ---- ----- References: ---- ----- 1. The Designer's Guide to VHDL by Peter Ashenden ---- ----- ISBN: 1-55860-270-4 (pbk.) ---- ----- 2. Writing Testbenches - Functional Verification of HDL ---- ----- models by Janick Bergeron | ISBN: 0-7923-7766-4 ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2005 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- --- --- CVS Revision History --- --- $Log: not supported by cvs2svn $ --- Revision 1.2 2005/10/12 19:39:27 mgeng --- Buses unconstrained, LGPL header added --- --- Revision 1.1.1.1 2003/01/14 21:48:10 rpaley_yid --- initial checkin --- --- Revision 1.1 2003/01/14 17:47:32 Default --- Initial revision --- --- Revision 1.1 2002/12/24 18:03:50 Default --- Initial revision --- -LIBRARY IEEE; -LIBRARY WORK; -USE IEEE.STD_LOGIC_1164.ALL; -USE WORK.single_port_pkg.all; - -PACKAGE linked_list_mem_pkg IS - CONSTANT PAGEDEPTH : INTEGER := 256; -- memory page depth - -- pointer to one data word in the memory - -- The reason for using a pointer here is that it seems to be the only way to keep the model - -- independent of the data width - TYPE data_ptr IS ACCESS BIT_VECTOR; - -- data memory array type definition - TYPE mem_array_typ IS ARRAY (0 TO PAGEDEPTH-1) OF data_ptr; - -- Define memory page linked list cell. This cell contains - -- the mem_array, starting page address, valid data array and - -- the pointer to the next element in the linked list. - TYPE mem_page_typ; - -- pointer to next item in the linked list. - TYPE mem_page_ptr IS ACCESS mem_page_typ; - TYPE mem_page_typ IS RECORD - mem_array : mem_array_typ; -- data memory - page_address : addr_typ; - next_cell : mem_page_ptr; - END RECORD mem_page_typ; - PROCEDURE rw_mem ( - VARIABLE data : INOUT STD_LOGIC_VECTOR; - VARIABLE addr : IN addr_typ; - VARIABLE next_cell : INOUT mem_page_ptr; - CONSTANT write_flag : IN BOOLEAN); - PROCEDURE deallocate_mem ( - VARIABLE next_cell : INOUT mem_page_ptr); - -END PACKAGE linked_list_mem_pkg; - -PACKAGE BODY linked_list_mem_pkg IS - -- -------------------------------------------------- - -- The purpose of this procedure is to write a memory location from - -- the linked list, if the particular page does not exist, create it. - -- -------------------------------------------------- - PROCEDURE rw_mem ( - VARIABLE data : INOUT STD_LOGIC_VECTOR; - VARIABLE addr : IN addr_typ; - VARIABLE next_cell : INOUT mem_page_ptr; - CONSTANT write_flag : IN BOOLEAN) IS - VARIABLE current_cell_v : mem_page_ptr; -- current page pointer - VARIABLE page_address_v : addr_typ; -- calculated page address - VARIABLE index_v : INTEGER; -- address within the memory page - VARIABLE mem_array_v : mem_array_typ; - BEGIN - -- Copy the top of the linked list pointer to a working pointer - current_cell_v := next_cell; - -- Calculate the index within the page from the given address - index_v := addr MOD PAGEDEPTH; - -- Calculate the page address from the given address - page_address_v := addr - index_v; - -- Search through the memory to determine if the calculated - -- memory page exists. Stop searching when reach the end of - -- the linked list. - WHILE ( current_cell_v /= NULL AND - current_cell_v.page_address /= page_address_v) LOOP - current_cell_v := current_cell_v.next_cell; - END LOOP; - - IF write_flag THEN - IF ( current_cell_v /= NULL AND -- Check if address exists in memory. - current_cell_v.page_address = page_address_v ) THEN - -- Found the memory page the particular address belongs to - IF ( current_cell_v.mem_array(index_v) /= NULL ) THEN - current_cell_v.mem_array(index_v).ALL := TO_BITVECTOR(data); - ELSE - current_cell_v.mem_array(index_v) := NEW BIT_VECTOR'(TO_BITVECTOR(data)); - END IF; - ELSE - -- The memory page the address belongs to was not allocated in memory. - -- Allocate page here and assign data. - mem_array_v(index_v) := NEW BIT_VECTOR'(TO_BITVECTOR(data)); - next_cell := NEW mem_page_typ'( mem_array => mem_array_v, - page_address => page_address_v, - next_cell => next_cell); - END IF; - ELSE -- Read memory - IF ( current_cell_v /= NULL AND -- Check if address exists in memory. - current_cell_v.page_address = page_address_v AND - current_cell_v.mem_array(index_v) /= NULL ) THEN - -- Found the memory page the particular address belongs to, - -- and the memory location has valid data. - data := TO_STDLOGICVECTOR(current_cell_v.mem_array(index_v).ALL); - ELSE - -- Trying to read from unwritten or unallocated - -- memory location, return 'U'; - data := (data'RANGE => 'U'); - END IF; - END IF; - END PROCEDURE rw_mem; - - PROCEDURE deallocate_mem ( - VARIABLE next_cell : INOUT mem_page_ptr) IS - VARIABLE delete_cell_v : mem_page_ptr; - BEGIN - -- Deallocate the linked link memory from work station memory. - WHILE next_cell /= NULL LOOP -- while not reached the end of the LL - delete_cell_v := next_cell; -- Copy pointer to record for deleting - FOR i IN 0 TO PAGEDEPTH-1 LOOP - IF delete_cell_v.mem_array(i) /= NULL THEN - deallocate(delete_cell_v.mem_array(i)); - END IF; - END LOOP; - next_cell := next_cell.next_cell; -- set pointer to next cell in LL - deallocate(delete_cell_v); -- Deallocate current cell from memory. - END LOOP; - END PROCEDURE deallocate_mem; -END PACKAGE BODY linked_list_mem_pkg; Index: trunk/VHDL/pkg_image.vhd =================================================================== --- trunk/VHDL/pkg_image.vhd (revision 14) +++ trunk/VHDL/pkg_image.vhd (nonexistent) @@ -1,307 +0,0 @@ --- $Author: rpaley_yid $ --- $Date: 2003-01-14 21:48:10 $ --- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/pkg_image.vhd,v 1.1.1.1 2003-01-14 21:48:10 rpaley_yid Exp $ --- $Locker --- $Revision: 1.1.1.1 $ --- $State: Exp $ - --- Copyright (c) 1997 Ben Cohen. All rights reserved. --- This model can be used in conjunction with the Kluwer Academic books --- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0 --- "VHDL Amswers to Frequently Asked Questions", Kluwer Academic --- by Ben Cohen. email: vhdlcohen@aol.com --- --- This source file for the Image Package --- may be used and distributed without restriction provided --- that this copyright statement is not removed from the file --- and that any derivative work contains this copyright notice. --- --- --- Original Author: Ben Cohen --- Description: --- Convert VHDL types to string for printing. This is especially useful when --- compiling with VHDL-87 - ---------------------------------------------------------------- -LIBRARY IEEE; - USE IEEE.STD_LOGIC_1164.ALL; - USE IEEE.STD_LOGIC_TEXTIO.ALL; - USE IEEE.NUMERIC_STD.ALL; - -LIBRARY STD; - USE STD.TEXTIO.ALL; - -package pkg_image is - function Image(In_Image : Time) return String; - function Image(In_Image : Bit) return String; - function Image(In_Image : Bit_Vector) return String; - function Image(In_Image : Integer) return String; - function Image(In_Image : Real) return String; - function Image(In_Image : Std_uLogic) return String; - function Image(In_Image : Std_uLogic_Vector) return String; - function Image(In_Image : Std_Logic_Vector) return String; - function Image(In_Image : Signed) return String; - function Image(In_Image : UnSigned) return String; - - function HexImage(InStrg : String) return String; - function HexImage(In_Image : Bit_Vector) return String; - function HexImage(In_Image : Std_uLogic_Vector) return String; - function HexImage(In_Image : Std_Logic_Vector) return String; - function HexImage(In_Image : Signed) return String; - function HexImage(In_Image : UnSigned) return String; - - function DecImage(In_Image : Bit_Vector) return String; - function DecImage(In_Image : Std_uLogic_Vector) return String; - function DecImage(In_Image : Std_Logic_Vector) return String; - function DecImage(In_Image : Signed) return String; - function DecImage(In_Image : UnSigned) return String; -end pkg_image; - -package body pkg_image is - function Image(In_Image : Time) return String is - variable L : Line; -- access type - variable W : String(1 to 14) := (others => ' '); - -- Long enough to hold a time string - begin - -- the WRITE procedure creates an object with "NEW". - -- L is passed as an output of the procedure. - Std.TextIO.WRITE(L, in_image); - -- Copy L.all onto W - W(L.all'range) := L.all; - Deallocate(L); - return W; - end Image; - - function Image(In_Image : Bit) return String is - variable L : Line; -- access type - variable W : String(1 to 3) := (others => ' '); - begin - Std.TextIO.WRITE(L, in_image); - W(L.all'range) := L.all; - Deallocate(L); - return W; - end Image; - - function Image(In_Image : Bit_Vector) return String is - variable L : Line; -- access type - variable W : String(1 to In_Image'length) := (others => ' '); - begin - Std.TextIO.WRITE(L, in_image); - W(L.all'range) := L.all; - Deallocate(L); - return W; - end Image; - - function Image(In_Image : Integer) return String is - variable L : Line; -- access type - variable W : String(1 to 32) := (others => ' '); - -- Long enough to hold a time string - begin - Std.TextIO.WRITE(L, in_image); - W(L.all'range) := L.all; - Deallocate(L); - return W; - end Image; - - function Image(In_Image : Real) return String is - variable L : Line; -- access type - variable W : String(1 to 32) := (others => ' '); - -- Long enough to hold a time string - begin - Std.TextIO.WRITE(L, in_image); - W(L.all'range) := L.all; - Deallocate(L); - return W; - end Image; - - function Image(In_Image : Std_uLogic) return String is - variable L : Line; -- access type - variable W : String(1 to 3) := (others => ' '); - begin - IEEE.Std_Logic_Textio.WRITE(L, in_image); - W(L.all'range) := L.all; - Deallocate(L); - return W; - end Image; - - function Image(In_Image : Std_uLogic_Vector) return String is - variable L : Line; -- access type - variable W : String(1 to In_Image'length) := (others => ' '); - begin - IEEE.Std_Logic_Textio.WRITE(L, in_image); - W(L.all'range) := L.all; - Deallocate(L); - return W; - end Image; - - function Image(In_Image : Std_Logic_Vector) return String is - variable L : Line; -- access type - variable W : String(1 to In_Image'length) := (others => ' '); - begin - IEEE.Std_Logic_TextIO.WRITE(L, In_Image); - W(L.all'range) := L.all; - Deallocate(L); - return W; - end Image; - - function Image(In_Image : Signed) return String is - begin - return Image(Std_Logic_Vector(In_Image)); - end Image; - - function Image(In_Image : UnSigned) return String is - begin - return Image(Std_Logic_Vector(In_Image)); - end Image; - - function HexImage(InStrg : String) return String is - subtype Int03_Typ is Integer range 0 to 3; - variable Result : string(1 to ((InStrg'length - 1)/4)+1) := - (others => '0'); - variable StrTo4 : string(1 to Result'length * 4) := - (others => '0'); - variable MTspace : Int03_Typ; -- Empty space to fill in - variable Str4 : String(1 to 4); - variable Group_v : Natural := 0; - begin - MTspace := Result'length * 4 - InStrg'length; - StrTo4(MTspace + 1 to StrTo4'length) := InStrg; -- padded with '0' - Cnvrt_Lbl : for I in Result'range loop - Group_v := Group_v + 4; -- identifies end of bit # in a group of 4 - Str4 := StrTo4(Group_v - 3 to Group_v); -- get next 4 characters - case Str4 is - when "0000" => Result(I) := '0'; - when "0001" => Result(I) := '1'; - when "0010" => Result(I) := '2'; - when "0011" => Result(I) := '3'; - when "0100" => Result(I) := '4'; - when "0101" => Result(I) := '5'; - when "0110" => Result(I) := '6'; - when "0111" => Result(I) := '7'; - when "1000" => Result(I) := '8'; - when "1001" => Result(I) := '9'; - when "1010" => Result(I) := 'A'; - when "1011" => Result(I) := 'B'; - when "1100" => Result(I) := 'C'; - when "1101" => Result(I) := 'D'; - when "1110" => Result(I) := 'E'; - when "1111" => Result(I) := 'F'; - when others => Result(I) := 'X'; - end case; -- Str4 - end loop Cnvrt_Lbl; - - return Result; - end HexImage; - - - function HexImage(In_Image : Bit_Vector) return String is - begin - return HexImage(Image(In_Image)); - end HexImage; - - function HexImage(In_Image : Std_uLogic_Vector) return String is - begin - return HexImage(Image(In_Image)); - end HexImage; - - function HexImage(In_Image : Std_Logic_Vector) return String is - begin - return HexImage(Image(In_Image)); - end HexImage; - - function HexImage(In_Image : Signed) return String is - begin - return HexImage(Image(In_Image)); - end HexImage; - - function HexImage(In_Image : UnSigned) return String is - begin - return HexImage(Image(In_Image)); - end HexImage; - - function DecImage(In_Image : Bit_Vector) return String is - variable In_Image_v : Bit_Vector(In_Image'length downto 1) := In_Image; - begin - if In_Image'length > 31 then - assert False - report "Number too large for Integer, clipping to 31 bits" - severity Warning; - return Image(To_Integer - (Unsigned(To_StdLogicVector - (In_Image_v(31 downto 1))))); - else - return Image(To_Integer(Unsigned(To_StdLogicVector(In_Image)))); - end if; - end DecImage; - - function DecImage(In_Image : Std_uLogic_Vector) return String is - variable In_Image_v : Std_uLogic_Vector(In_Image'length downto 1) - := In_Image; - begin - if In_Image'length > 31 then - assert False - report "Number too large for Integer, clipping to 31 bits" - severity Warning; - return Image(To_Integer(Unsigned(In_Image_v(31 downto 1)))); - else - return Image(To_Integer(Unsigned(In_Image))); - end if; - end DecImage; - - function DecImage(In_Image : Std_Logic_Vector) return String is - variable In_Image_v : Std_Logic_Vector(In_Image'length downto 1) - := In_Image; - begin - if In_Image'length > 31 then - assert False - report "Number too large for Integer, clipping to 31 bits" - severity Warning; - return Image(To_Integer(Unsigned(In_Image_v(31 downto 1)))); - else - return Image(To_Integer(Unsigned(In_Image))); - end if; - end DecImage; - - function DecImage(In_Image : Signed) return String is - variable In_Image_v : Signed(In_Image'length downto 1) := In_Image; - begin - if In_Image'length > 31 then - assert False - report "Number too large for Integer, clipping to 31 bits" - severity Warning; - return Image(To_Integer(In_Image_v(31 downto 1))); - else - return Image(To_Integer(In_Image)); - end if; - end DecImage; - - function DecImage(In_Image : UnSigned) return String is - variable In_Image_v : UnSigned(In_Image'length downto 1) := In_Image; - begin - if In_Image'length > 31 then - assert False - report "Number too large for Integer, clipping to 31 bits" - severity Warning; - return Image(To_Integer(In_Image_v(31 downto 1))); - else - return Image(To_Integer(In_Image)); - end if; - end DecImage; - -end pkg_image; - --- $Log: not supported by cvs2svn $ --- Revision 1.1 2003/01/14 17:48:44 Default --- Initial revision --- --- Revision 1.1 2002/12/24 18:07:50 Default --- Initial revision --- - - - - - - - - Index: trunk/VHDL/single_port.vhd =================================================================== --- trunk/VHDL/single_port.vhd (revision 14) +++ trunk/VHDL/single_port.vhd (nonexistent) @@ -1,178 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- Single port asynchronous RAM simulation model ---- ----- ---- ----- This file is part of the single_port project ---- ----- ---- ----- Description ---- ----- This is a single port asynchronous memory. This files ---- ----- describes three architectures. Two architectures are ---- ----- traditional array based memories. One describes the memory ---- ----- as an array of STD_LOGIC_VECTOR, and the other describes ---- ----- the ARRAY as BIT_VECTOR. ---- ----- The third architecture describes the memory arranged as a ---- ----- linked list in order to conserve computer memory usage. The ---- ----- memory is organized as a linked list of BIT_VECTOR arrays ---- ----- whose size is defined by the constant PAGEDEPTH in ---- ----- single_port_pkg.vhd. ---- ----- ---- ----- Authors: ---- ----- - Robert Paley, rpaley_yid@yahoo.com ---- ----- - Michael Geng, vhdl@MichaelGeng.de ---- ----- ---- ----- References: ---- ----- 1. The Designer's Guide to VHDL by Peter Ashenden ---- ----- ISBN: 1-55860-270-4 (pbk.) ---- ----- 2. Writing Testbenches - Functional Verification of HDL ---- ----- models by Janick Bergeron | ISBN: 0-7923-7766-4 ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2005 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- --- --- CVS Revision History --- --- $Log: not supported by cvs2svn $ --- Revision 1.4 2005/11/19 15:18:54 mgeng --- rnw replaced by nce, nwe and noe, tristate drivers added --- --- Revision 1.3 2005/10/25 18:26:52 mgeng --- PAGENUM constant removed because the address bus width provides this information --- --- Revision 1.2 2005/10/12 19:39:27 mgeng --- Buses unconstrained, LGPL header added --- --- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid --- initial checkin --- --- Revision 1.1 2003/01/14 17:48:31 Default --- Initial revision --- --- Revision 1.1 2002/12/24 18:09:05 Default --- Initial revision --- -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE WORK.single_port_pkg.ALL; -USE WORK.linked_list_mem_pkg.ALL; - -ENTITY single_port IS - GENERIC ( - rnwtQ : TIME := 1 NS); - PORT ( - d : IN STD_LOGIC_VECTOR; -- data bus input - q : OUT STD_LOGIC_VECTOR; -- data bus output - a : IN STD_LOGIC_VECTOR; -- address bus - nce : IN STD_LOGIC; -- not chip enable - nwe : IN STD_LOGIC; -- not write enable - noe : IN STD_LOGIC; -- not output enable - dealloc_mem : IN BOOLEAN := FALSE); -- control signal for deallocating memory, - -- only used in the linked list implementation -END ENTITY single_port; - -ARCHITECTURE ArrayMemNoFlag OF single_port IS -BEGIN - - mem_proc : PROCESS(d, a, nce, nwe, noe) - TYPE mem_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF STD_LOGIC_VECTOR(d'RANGE); - VARIABLE mem : mem_typ; - BEGIN - IF ( nce = '0' ) AND ( nwe = '0' ) THEN -- Write - mem(TO_INTEGER(unsigned(a))) := d; - END IF; - - IF ( nce = '0' ) AND ( noe = '0' ) THEN -- Read - q <= mem(TO_INTEGER(unsigned(a))) AFTER rnwtQ; - ELSE - q <= (q'RANGE => 'Z') AFTER rnwtQ; - END IF; - END PROCESS mem_proc; - -END ArrayMemNoFlag; - -ARCHITECTURE ArrayMem OF single_port IS -BEGIN - - mem_proc : PROCESS(d, a, nce, nwe, noe) - TYPE mem_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF BIT_VECTOR(d'RANGE); - TYPE flag_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF BOOLEAN; - VARIABLE mem : mem_typ; - VARIABLE flag : flag_typ; - BEGIN - IF ( nce = '0' ) AND ( nwe = '0' ) THEN -- Write - mem( TO_INTEGER(unsigned(a))) := TO_BITVECTOR(d); - flag(TO_INTEGER(unsigned(a))) := true; -- set valid memory location flag - END IF; - - IF ( nce = '0' ) AND ( noe = '0' ) THEN -- Read - IF ( flag(TO_INTEGER(unsigned(a))) = true ) THEN -- read data, either valid or 'U' - q <= TO_STDLOGICVECTOR(mem(TO_INTEGER(unsigned(a)))) AFTER rnwtQ; - ELSE -- reading invalid memory location - q <= (q'RANGE => 'U') AFTER rnwtQ; - END IF; - ELSE - q <= (q'RANGE => 'Z') AFTER rnwtQ; - END IF; - END PROCESS mem_proc; -END ArrayMem; - -ARCHITECTURE LinkedList OF single_port IS - CONSTANT WRITE_MEM : BOOLEAN := true; - CONSTANT READ_MEM : BOOLEAN := false; -BEGIN - - mem_proc : PROCESS(d, a, nce, nwe, noe, dealloc_mem) - VARIABLE mem_page_v : mem_page_ptr; - VARIABLE d_v : STD_LOGIC_VECTOR(d'RANGE); - VARIABLE a_v : addr_typ; - BEGIN - IF NOT dealloc_mem THEN - d_v := d; - if (nce = '0') then - a_v := TO_INTEGER(unsigned(a)); - end if; - IF ( nce = '0' ) AND ( nwe = '0' ) THEN -- Write - rw_mem( data => d_v, - addr => a_v, - next_cell => mem_page_v, - write_flag => WRITE_MEM); - END IF; - - IF ( nce = '0' ) AND ( noe = '0' ) THEN -- Read - rw_mem( data => d_v, - addr => a_v, - next_cell => mem_page_v, - write_flag => READ_MEM); - q <= d_v AFTER rnwtQ; - ELSE - q <= (q'RANGE => 'Z') AFTER rnwtQ; - END IF; - ELSE -- Deallocate memory from work station memory. - deallocate_mem(mem_page_v); - END IF; - END PROCESS mem_proc; -END LinkedList; Index: trunk/VHDL/single_port_pkg.vhd =================================================================== --- trunk/VHDL/single_port_pkg.vhd (revision 14) +++ trunk/VHDL/single_port_pkg.vhd (nonexistent) @@ -1,84 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- Single port asynchronous RAM simulation model ---- ----- ---- ----- This file is part of the single_port project ---- ----- ---- ----- Description ---- ----- Package file for single_port memory and testbench ---- ----- ---- ----- Authors: ---- ----- - Robert Paley, rpaley_yid@yahoo.com ---- ----- - Michael Geng, vhdl@MichaelGeng.de ---- ----- ---- ----- References: ---- ----- 1. The Designer's Guide to VHDL by Peter Ashenden ---- ----- ISBN: 1-55860-270-4 (pbk.) ---- ----- 2. Writing Testbenches - Functional Verification of HDL ---- ----- models by Janick Bergeron | ISBN: 0-7923-7766-4 ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2005 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- --- --- CVS Revision History --- --- $Log: not supported by cvs2svn $ --- Revision 1.3 2005/10/25 18:26:52 mgeng --- PAGENUM constant removed because the address bus width provides this information --- --- Revision 1.2 2005/10/12 19:39:27 mgeng --- Buses unconstrained, LGPL header added --- --- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid --- initial checkin --- --- Revision 1.1 2003/01/14 17:48:44 Default --- Initial revision --- --- Revision 1.1 2002/12/24 17:58:49 Default --- Initial revision --- -LIBRARY IEEE; - USE IEEE.STD_LOGIC_1164.ALL; - USE IEEE.NUMERIC_STD.ALL; - -PACKAGE single_port_pkg IS - -- Address bus type for internal memory - SUBTYPE addr_typ IS NATURAL; - -- Operations testbench can do. - TYPE do_typ IS ( init , read , write , dealloc , end_test ); - - TYPE to_srv_typ IS RECORD -- Record passed from test case to test bench - do : do_typ; - addr : INTEGER; - data : INTEGER; - event : BOOLEAN; - END RECORD to_srv_typ; -END PACKAGE single_port_pkg; - -PACKAGE BODY single_port_pkg IS -END PACKAGE BODY single_port_pkg; Index: trunk/VHDL/tb_single_port.vhd =================================================================== --- trunk/VHDL/tb_single_port.vhd (revision 14) +++ trunk/VHDL/tb_single_port.vhd (nonexistent) @@ -1,225 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- Single port asynchronous RAM simulation model ---- ----- ---- ----- This file is part of the single_port project ---- ----- ---- ----- Description ---- ----- This file specifies test bench harness for the single_port ---- ----- Memory. It also contains the configuration files for all the ---- ----- tests. ---- ----- ---- ----- Authors: ---- ----- - Robert Paley, rpaley_yid@yahoo.com ---- ----- - Michael Geng, vhdl@MichaelGeng.de ---- ----- ---- ----- References: ---- ----- 1. The Designer's Guide to VHDL by Peter Ashenden ---- ----- ISBN: 1-55860-270-4 (pbk.) ---- ----- 2. Writing Testbenches - Functional Verification of HDL ---- ----- models by Janick Bergeron | ISBN: 0-7923-7766-4 ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2005 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- --- --- CVS Revision History --- --- $Log: not supported by cvs2svn $ --- Revision 1.2 2005/10/12 19:39:27 mgeng --- Buses unconstrained, LGPL header added --- --- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid --- initial checkin --- --- Revision 1.1 2003/01/14 17:49:04 Default --- Initial revision --- --- Revision 1.2 2002/12/31 19:19:43 Default --- Updated 'transaction statements for fixed simulator. --- --- Revision 1.1 2002/12/24 18:10:18 Default --- Initial revision --- -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE WORK.linked_list_mem_pkg.ALL; -USE WORK.single_port_pkg.all; -USE STD.TEXTIO.ALL; - -ENTITY tb_single_port IS -END ENTITY tb_single_port; - -ARCHITECTURE BHV of tb_single_port IS - -COMPONENT single_port IS - GENERIC ( - rnwtQ : TIME := 1 NS); - PORT ( - d : IN STD_LOGIC_VECTOR; - q : OUT STD_LOGIC_VECTOR; - a : IN STD_LOGIC_VECTOR; - nce : IN STD_LOGIC; - nwe : IN STD_LOGIC; - noe : IN STD_LOGIC; - dealloc_mem : BOOLEAN); -END COMPONENT single_port; - -COMPONENT tc_single_port IS - PORT ( - to_srv : OUT to_srv_typ; - frm_srv : IN STD_LOGIC_VECTOR); -END COMPONENT tc_single_port; - CONSTANT DATA_WIDTH : INTEGER := 32; - CONSTANT ADDR_WIDTH : INTEGER := 16; - - SIGNAL d : STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0); - SIGNAL q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0); - SIGNAL a : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0); - SIGNAL nce, nwe, noe : STD_LOGIC; - SIGNAL dealloc_mem : BOOLEAN; - SIGNAL to_srv : to_srv_typ; - SIGNAL frm_srv : STD_LOGIC_VECTOR(d'RANGE); - SIGNAL tie_vdd : STD_LOGIC := '1'; -BEGIN - dut : single_port - PORT MAP ( - d => d, - a => a, - q => q, - nce => nce, - nwe => nwe, - noe => noe, - dealloc_mem => dealloc_mem); - - tc : tc_single_port - PORT MAP ( - to_srv => to_srv, - frm_srv => frm_srv); - - single_port_server : PROCESS - VARIABLE frm_srv_v : STD_LOGIC_VECTOR(d'RANGE); - CONSTANT ACCESS_DELAY : TIME := 5 NS; - BEGIN - -- Wait until the test case is finished setting up the next memory access. - WAIT ON to_srv'TRANSACTION; - CASE to_srv.do IS - WHEN init => - ASSERT FALSE - REPORT "initialized" - SEVERITY NOTE; - WHEN read => -- perform memory read - d <= STD_LOGIC_VECTOR(TO_SIGNED(to_srv.data, d'length)); - a <= STD_LOGIC_VECTOR(TO_UNSIGNED(to_srv.addr, a'length)); - nce <= '0'; - noe <= '0'; - nwe <= '1'; - -- Wait for data to appear - WAIT FOR ACCESS_DELAY; - WHEN write => -- perform memory write - d <= STD_LOGIC_VECTOR(TO_SIGNED(to_srv.data, d'length)); - a <= STD_LOGIC_VECTOR(TO_UNSIGNED(to_srv.addr, a'length)); - nce <= '0'; - noe <= '1'; - nwe <= '0'; - WAIT FOR ACCESS_DELAY; - WHEN dealloc => -- deallocate the linked list for the LL architecture - dealloc_mem <= true; - WHEN end_test => -- reached the end of the test case - WAIT; - END CASE; - frm_srv_v := q; - -- Send message to test case to continue the test. - frm_srv <= frm_srv_v ; WAIT FOR 0 NS; - END PROCESS single_port_server; -END BHV; - -CONFIGURATION ll_main_cfg OF TB_SINGLE_PORT IS - FOR BHV - FOR dut : single_port - USE ENTITY work.single_port(LinkedList); - END FOR; -- dut - FOR tc : tc_single_port - USE ENTITY work.tc_single_port(TC0); - END FOR; -- tc; - END FOR; -- BHV -END CONFIGURATION ll_main_cfg; - -CONFIGURATION ll_error_cfg OF TB_SINGLE_PORT IS - FOR BHV - FOR dut : single_port - USE ENTITY work.single_port(LinkedList); - END FOR; -- dut - FOR tc : tc_single_port - USE ENTITY work.tc_single_port(TC1); - END FOR; -- tc; - END FOR; -- BHV -END CONFIGURATION ll_error_cfg ; - -CONFIGURATION mem_main_cfg of TB_SINGLE_PORT IS - FOR BHV - FOR dut : single_port - USE ENTITY work.single_port(ArrayMem); - END FOR; -- dut - FOR tc : tc_single_port - USE ENTITY work.tc_single_port(TC0); - END FOR; -- tc; - END FOR; -- BHV -END CONFIGURATION mem_main_cfg; - -CONFIGURATION mem_error_cfg of TB_SINGLE_PORT IS - FOR BHV - FOR dut : single_port - USE ENTITY work.single_port(ArrayMem); - END FOR; -- dut - FOR tc : tc_single_port - USE ENTITY work.tc_single_port(TC1); - END FOR; -- tc; - END FOR; -- BHV -END CONFIGURATION mem_error_cfg; - -CONFIGURATION memnoflag_main_cfg of TB_SINGLE_PORT IS - FOR BHV - FOR dut : single_port - USE ENTITY work.single_port(ArrayMemNoFlag); - END FOR; -- dut - FOR tc : tc_single_port - USE ENTITY work.tc_single_port(TC0); - END FOR; -- tc; - END FOR; -- BHV -END CONFIGURATION memnoflag_main_cfg; - -CONFIGURATION memnoflag_error_cfg of TB_SINGLE_PORT IS - FOR BHV - FOR dut : single_port - USE ENTITY work.single_port(ArrayMemNoFlag); - END FOR; -- dut - FOR tc : tc_single_port - USE ENTITY work.tc_single_port(TC1); - END FOR; -- tc; - END FOR; -- BHV -END CONFIGURATION memnoflag_error_cfg; Index: trunk/VHDL/tc_single_port.vhd =================================================================== --- trunk/VHDL/tc_single_port.vhd (revision 14) +++ trunk/VHDL/tc_single_port.vhd (nonexistent) @@ -1,214 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- Single port asynchronous RAM simulation model ---- ----- ---- ----- This file is part of the single_port project ---- ----- ---- ----- Description ---- ----- This file specifies test cases for the single_port Memory. ---- ----- ---- ----- Authors: ---- ----- - Robert Paley, rpaley_yid@yahoo.com ---- ----- - Michael Geng, vhdl@MichaelGeng.de ---- ----- ---- ----- References: ---- ----- 1. The Designer's Guide to VHDL by Peter Ashenden ---- ----- ISBN: 1-55860-270-4 (pbk.) ---- ----- 2. Writing Testbenches - Functional Verification of HDL ---- ----- models by Janick Bergeron | ISBN: 0-7923-7766-4 ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2005 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.opencores.org/lgpl.shtml ---- ----- ---- ----------------------------------------------------------------------- --- --- CVS Revision History --- --- $Log: not supported by cvs2svn $ --- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid --- initial checkin --- --- Revision 1.1 2003/01/14 17:49:04 Default --- Initial revision --- --- Revision 1.2 2002/12/31 19:19:43 Default --- Updated 'transaction statements for fixed simulator. --- --- Revision 1.1 2002/12/24 18:13:50 Default --- Initial revision --- -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE WORK.SINGLE_PORT_PKG.ALL; -USE WORK.PKG_IMAGE.ALL; - -ENTITY tc_single_port IS -PORT ( - to_srv : OUT to_srv_typ; - frm_srv : IN STD_LOGIC_VECTOR); -END ENTITY tc_single_port; - --- -------------------------------------------------- --- Test Case TC0 --- This test case is to check two pages of memory --- Starting at physical address 0x0 , --- Write a '1' to bit position 0, leaving all other bits 0. --- Increment the address, --- Write a '1' to bit position 1, leaving all other bits 0. --- Increment the address. --- Write a '1' to bit position 2, leaving all other bits 0. --- Continue in this fasion, until write a 1 to the MSB. --- increment the address, --- Write a '1' to bit position 0, leaving all other bits 0. --- Continue until the entire page is written to. --- Read back all addresses in the page, ensuring the --- correct data is read back. --- -------------------------------------------------- - - -ARCHITECTURE TC0 OF tc_single_port IS -BEGIN - MAIN : PROCESS - VARIABLE to_srv_v : to_srv_typ; - VARIABLE frm_srv_v : STD_LOGIC_VECTOR(frm_srv'RANGE); - VARIABLE dv : STD_LOGIC_VECTOR(frm_srv'RANGE) := - STD_LOGIC_VECTOR(TO_UNSIGNED(1, frm_srv'length)); - VARIABLE offset_v : INTEGER; - BEGIN - offset_v := 0; - -- Run this write/read test 10 times for benchmark - -- purposes. - FOR i IN 0 to 9 LOOP - FOR index IN 0 to 2*PAGEDEPTH-1 LOOP - -- Specify to testbench server to perform write operation; - to_srv_v.do := write; - to_srv_v.data := TO_INTEGER(SIGNED(dv)); -- specify data to write - dv := To_StdLogicVector(TO_BitVector(dv) ROL 1); -- ROL 1 for next write - -- Specify physical address. - to_srv_v.addr := index+offset_v; - to_srv <= to_srv_v; - WAIT ON frm_srv'TRANSACTION; - END LOOP; - -- Reset data to 1. - dv := STD_LOGIC_VECTOR(TO_UNSIGNED(1,frm_srv'length)); - FOR index IN 0 to 2*PAGEDEPTH-1 LOOP - -- Perform read operation. - to_srv_v.do := read; - -- Specify physical address. - to_srv_v.addr := index+offset_v; - to_srv <= to_srv_v; - WAIT ON frm_srv'TRANSACTION; - -- Compare actual with expected read back data, if the - -- the expected and actual to not compare, print the - -- expected and actual values. - ASSERT frm_srv = dv - REPORT "Expected: " & HexImage(frm_srv) & - " did not equal Actual: " & HexImage(dv) - SEVERITY ERROR; - -- Set expected data for next read. - dv := TO_STDLOGICVECTOR(TO_BITVECTOR(dv) ROL 1); - END LOOP; - END LOOP; - to_srv_v.do := dealloc; -- Deallocate memory - -- - to_srv <= to_srv_v; - -- Tell test bench server process test completed. - to_srv_v.do := end_test; - to_srv <= to_srv_v; - ASSERT FALSE - REPORT "Completed Test TC0" - SEVERITY NOTE; - WAIT; - END PROCESS main; -END TC0; - --- -------------------------------------------------- --- Test Case TC1 --- This test case is to check if the test bench will --- return 'U' for invalid memory locations for --- single_port architectures ArrayMem and LinkedList --- -------------------------------------------------- -ARCHITECTURE TC1 OF tc_single_port IS -BEGIN - MAIN : PROCESS - VARIABLE to_srv_v : to_srv_typ; - VARIABLE frm_srv_v : STD_LOGIC_VECTOR(frm_srv'RANGE); - VARIABLE dv : STD_LOGIC_VECTOR(frm_srv'RANGE) := (OTHERS => 'U'); - BEGIN - -- Perform read operation. - to_srv_v.do := read; - -- Specify physical address. - to_srv_v.addr := 0; - to_srv <= to_srv_v; - WAIT ON frm_srv'TRANSACTION; - -- Compare actual with expected read back data, if the - -- the expected and actual to not compare, print the - -- expected and actual values. - ASSERT frm_srv = dv - REPORT "Expected: " & HexImage(frm_srv) & - " did not equal Actual: " & HexImage(dv) - SEVERITY ERROR; - - -- Write and read back from same address. - - -- Specify to testbench server to perform write operation; - to_srv_v.do := write; - dv := X"a5a5a5a5"; - to_srv_v.data := TO_INTEGER(SIGNED(dv)); -- specify data to write - -- Specify physical address. - to_srv_v.addr := 0; - to_srv <= to_srv_v; - -- Wait until the test bench server finished with the write. - -- WAIT UNTIL frm_srv.event = true; - WAIT ON frm_srv'TRANSACTION; - - to_srv_v.do := read; - -- Specify physical address. - to_srv_v.addr := 0; - to_srv <= to_srv_v; - WAIT ON frm_srv'TRANSACTION; - - -- Compare actual with expected read back data, if the - -- the expected and actual to not compare, print the - -- expected and actual values. - ASSERT frm_srv = dv - REPORT "Expected: " & HexImage(frm_srv) & - " did not equal Actual: " & HexImage(dv) - SEVERITY ERROR; - - to_srv_v.do := dealloc; -- Deallocate memory - -- - to_srv <= to_srv_v; - -- Tell test bench server process test completed. - to_srv_v.do := end_test; - to_srv <= to_srv_v; - - ASSERT FALSE - REPORT "Completed Test TC1" - SEVERITY NOTE; - WAIT; - END PROCESS main; -END TC1; Index: trunk/VHDL/Makefile =================================================================== --- trunk/VHDL/Makefile (revision 14) +++ trunk/VHDL/Makefile (nonexistent) @@ -1,161 +0,0 @@ -# -# Description: Top level make file for single_port test project. -# make com to compile -# make sim to simulate all tests -# make ll_error to run this test only -# make ll_main to run this test only -# make mem_main to run this test only -# make mem_error to run this test only -# make memnoflag_main to run this test -# make memnoflag_error to run this test -# $Author: rpaley_yid $ -# $Date: 2003-01-14 21:48:11 $ -# $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/Makefile,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $ -# $Locker: $ -# $Revision: 1.1.1.1 $ -# $State: Exp $ - -# VCOM , VSIM , and WORK variables are set for Sonata simulator, -# Change appropriately for your simulator. Ex.for Modeltech, -# VCOM = vcom -# VSIM = vsim -# WORK = work - -SHELL = /bin/sh -VCOM = vhdlp -VCOMOPT = -s -VSIM = vhdle -VSIMOPT = -WORK = work.sym -## Need to figure out how to put Bourne shell stuff in Makefile -## will do so to generate log files in -## LOGDIR = ../LOG/ -## For now, log files are in VHDL directory. - - -# List of main compiled objects, does not include configurations, -# which are included in the tb_single_port.vhd file. -# These targets are for the Sonata simulator, adjust accordingly for -# your simulator. - -SINGLE_PORT_PKG_OBJ = $(WORK)/single_port_pkg/prim.var -LINKED_LIST_MEM_OBJ = $(WORK)/linked_list_mem_pkg/prim.var -PKG_IMAGE_OBJ = $(WORK)/pkg_image/prim.var -SINGLE_PORT_OBJ = $(WORK)/single_port/prim.var -TC_SINGLE_PORT_OBJ = $(WORK)/tc_single_port/prim.var -TB_SINGLE_PORT_OBJ = $(WORK)/tb_single_port/prim.var -LL_ERROR_DEP = $(WORK)/ll_error_cfg/prim.var -LL_MAIN_DEP = $(WORK)/ll_main_cfg/prim.var -MEM_MAIN_DEP = $(WORK)/mem_main_cfg/prim.var -MEM_ERROR_DEP = $(WORK)/mem_error_cfg/prim.var -MEMNOFLAG_MAIN_DEP = $(WORK)/memnoflag_main_cfg/prim.var -MEMNOFLAG_ERROR_DEP = $(WORK)/memnoflag_error_cfg/prim.var - -LL_ERROR = $(LOGDIR)ll_error.log -LL_MAIN = ll_main.log -MEM_MAIN = mem_main.log -MEM_ERROR = mem_error.log -MEMNOFLAG_MAIN = memnoflag_main.log -MEMNOFLAG_ERROR = memnoflag_error.log - -OBJS = $(SINGLE_PORT_PKG_OBJ) \ - $(LINKED_LIST_MEM_OBJ) \ - $(PKG_IMAGE_OBJ) \ - $(SINGLE_PORT_OBJ) \ - $(TC_SINGLE_PORT_OBJ) \ - $(TB_SINGLE_PORT_OBJ) - -SIMOBJS = $(LL_ERROR) \ - $(LL_MAIN) \ - $(MEM_MAIN) \ - $(MEM_ERROR) \ - $(MEMNOFLAG_MAIN) \ - $(MEMNOFLAG_ERROR) - -# Compile the project -com: $(OBJS) - -# Clean the library -clean:: $(WORK) - -# Simulate all tests -sim: $(SIMOBJS) - -## Run only ll_error test -ll_error: $(LL_ERROR) - -# Run onle ll_main test -ll_main: $(LL_MAIN) - -# Run only mem_main test -mem_main: $(MEM_MAIN) - -# Run only mem_error test -mem_error: $(MEM_ERROR) - -# Run only memnoflag_main test -memnoflag_main: $(MEMNOFLAG_MAIN) - -# Run only memnoflag_error test -memnoflag_error: $(MEMNOFLAG_ERROR) - -# Target dependency rules to run tests -$(LL_ERROR) : $(LL_ERROR_DEP) - $(VSIM) $(VSIMOPT) ll_error_cfg | tee $@ - -$(LL_MAIN) : $(LL_MAIN_DEP) - $(VSIM) $(VSIMOPT) ll_main_cfg | tee $@ - -$(MEM_MAIN) : $(MEM_MAIN_DEP) - $(VSIM) $(VSIMOPT) mem_main_cfg | tee $@ - -$(MEM_ERROR) : $(MEM_ERROR_DEP) - $(VSIM) $(VSIMOPT) mem_error_cfg | tee $@ - -$(MEMNOFLAG_MAIN) : $(MEMNOFLAG_MAIN_DEP) - $(VSIM) $(VSIMOPT) memnoflag_main_cfg | tee $@ - -$(MEMNOFLAG_ERROR) : $(MEMNOFLAG_ERROR_DEP) - $(VSIM) $(VSIMOPT) memnoflag_error_cfg | tee $@ - -# Target dependency rules to compile tests - -$(SINGLE_PORT_PKG_OBJ) : single_port_pkg.vhd - $(VCOM) $(VCOMOPT) $< - -$(LINKED_LIST_MEM_OBJ) : linked_list_mem_pkg.vhd \ - $(SINGLE_PORT_PKG_OBJ) - $(VCOM) $(VCOMOPT) $< - -$(PKG_IMAGE_OBJ) : pkg_image.vhd - $(VCOM) $(VCOMOPT) $< - -$(SINGLE_PORT_OBJ) : single_port.vhd \ - $(SINGLE_PORT_PKG_OBJ) \ - $(LINKED_LIST_MEM_OBJ) - $(VCOM) $(VCOMOPT) $< - -$(TC_SINGLE_PORT_OBJ) : tc_single_port.vhd \ - $(SINGLE_PORT_PKG_OBJ) \ - $(PKG_IMAGE_OBJ) \ - $(SINGLE_PORT_OBJ) - $(VCOM) $(VCOMOPT) $< - -$(TB_SINGLE_PORT_OBJ) : tb_single_port.vhd \ - $(SINGLE_PORT_PKG_OBJ) \ - $(LINKED_LIST_MEM_OBJ) \ - $(SINGLE_PORT_OBJ) \ - $(TC_SINGLE_PORT_OBJ) - $(VCOM) $(VCOMOPT) $< - -$(WORK) :: - rm -rf $(WORK)/* - - -#################################################################### -# $Log: not supported by cvs2svn $ -# Revision 1.1 2002/12/31 19:21:59 Default -# Initial revision -# -# - Index: single_port/trunk/VHDL/single_port.vhd =================================================================== --- single_port/trunk/VHDL/single_port.vhd (nonexistent) +++ single_port/trunk/VHDL/single_port.vhd (revision 15) @@ -0,0 +1,178 @@ +---------------------------------------------------------------------- +---- ---- +---- Single port asynchronous RAM simulation model ---- +---- ---- +---- This file is part of the single_port project ---- +---- ---- +---- Description ---- +---- This is a single port asynchronous memory. This files ---- +---- describes three architectures. Two architectures are ---- +---- traditional array based memories. One describes the memory ---- +---- as an array of STD_LOGIC_VECTOR, and the other describes ---- +---- the ARRAY as BIT_VECTOR. ---- +---- The third architecture describes the memory arranged as a ---- +---- linked list in order to conserve computer memory usage. The ---- +---- memory is organized as a linked list of BIT_VECTOR arrays ---- +---- whose size is defined by the constant PAGEDEPTH in ---- +---- single_port_pkg.vhd. ---- +---- ---- +---- Authors: ---- +---- - Robert Paley, rpaley_yid@yahoo.com ---- +---- - Michael Geng, vhdl@MichaelGeng.de ---- +---- ---- +---- References: ---- +---- 1. The Designer's Guide to VHDL by Peter Ashenden ---- +---- ISBN: 1-55860-270-4 (pbk.) ---- +---- 2. Writing Testbenches - Functional Verification of HDL ---- +---- models by Janick Bergeron | ISBN: 0-7923-7766-4 ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2005 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.4 2005/11/19 15:18:54 mgeng +-- rnw replaced by nce, nwe and noe, tristate drivers added +-- +-- Revision 1.3 2005/10/25 18:26:52 mgeng +-- PAGENUM constant removed because the address bus width provides this information +-- +-- Revision 1.2 2005/10/12 19:39:27 mgeng +-- Buses unconstrained, LGPL header added +-- +-- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid +-- initial checkin +-- +-- Revision 1.1 2003/01/14 17:48:31 Default +-- Initial revision +-- +-- Revision 1.1 2002/12/24 18:09:05 Default +-- Initial revision +-- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE WORK.single_port_pkg.ALL; +USE WORK.linked_list_mem_pkg.ALL; + +ENTITY single_port IS + GENERIC ( + rnwtQ : TIME := 1 NS); + PORT ( + d : IN STD_LOGIC_VECTOR; -- data bus input + q : OUT STD_LOGIC_VECTOR; -- data bus output + a : IN STD_LOGIC_VECTOR; -- address bus + nce : IN STD_LOGIC; -- not chip enable + nwe : IN STD_LOGIC; -- not write enable + noe : IN STD_LOGIC; -- not output enable + dealloc_mem : IN BOOLEAN := FALSE); -- control signal for deallocating memory, + -- only used in the linked list implementation +END ENTITY single_port; + +ARCHITECTURE ArrayMemNoFlag OF single_port IS +BEGIN + + mem_proc : PROCESS(d, a, nce, nwe, noe) + TYPE mem_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF STD_LOGIC_VECTOR(d'RANGE); + VARIABLE mem : mem_typ; + BEGIN + IF ( nce = '0' ) AND ( nwe = '0' ) THEN -- Write + mem(TO_INTEGER(unsigned(a))) := d; + END IF; + + IF ( nce = '0' ) AND ( noe = '0' ) THEN -- Read + q <= mem(TO_INTEGER(unsigned(a))) AFTER rnwtQ; + ELSE + q <= (q'RANGE => 'Z') AFTER rnwtQ; + END IF; + END PROCESS mem_proc; + +END ArrayMemNoFlag; + +ARCHITECTURE ArrayMem OF single_port IS +BEGIN + + mem_proc : PROCESS(d, a, nce, nwe, noe) + TYPE mem_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF BIT_VECTOR(d'RANGE); + TYPE flag_typ IS ARRAY ( 0 TO 2**a'length-1 ) OF BOOLEAN; + VARIABLE mem : mem_typ; + VARIABLE flag : flag_typ; + BEGIN + IF ( nce = '0' ) AND ( nwe = '0' ) THEN -- Write + mem( TO_INTEGER(unsigned(a))) := TO_BITVECTOR(d); + flag(TO_INTEGER(unsigned(a))) := true; -- set valid memory location flag + END IF; + + IF ( nce = '0' ) AND ( noe = '0' ) THEN -- Read + IF ( flag(TO_INTEGER(unsigned(a))) = true ) THEN -- read data, either valid or 'U' + q <= TO_STDLOGICVECTOR(mem(TO_INTEGER(unsigned(a)))) AFTER rnwtQ; + ELSE -- reading invalid memory location + q <= (q'RANGE => 'U') AFTER rnwtQ; + END IF; + ELSE + q <= (q'RANGE => 'Z') AFTER rnwtQ; + END IF; + END PROCESS mem_proc; +END ArrayMem; + +ARCHITECTURE LinkedList OF single_port IS + CONSTANT WRITE_MEM : BOOLEAN := true; + CONSTANT READ_MEM : BOOLEAN := false; +BEGIN + + mem_proc : PROCESS(d, a, nce, nwe, noe, dealloc_mem) + VARIABLE mem_page_v : mem_page_ptr; + VARIABLE d_v : STD_LOGIC_VECTOR(d'RANGE); + VARIABLE a_v : addr_typ; + BEGIN + IF NOT dealloc_mem THEN + d_v := d; + if (nce = '0') then + a_v := TO_INTEGER(unsigned(a)); + end if; + IF ( nce = '0' ) AND ( nwe = '0' ) THEN -- Write + rw_mem( data => d_v, + addr => a_v, + next_cell => mem_page_v, + write_flag => WRITE_MEM); + END IF; + + IF ( nce = '0' ) AND ( noe = '0' ) THEN -- Read + rw_mem( data => d_v, + addr => a_v, + next_cell => mem_page_v, + write_flag => READ_MEM); + q <= d_v AFTER rnwtQ; + ELSE + q <= (q'RANGE => 'Z') AFTER rnwtQ; + END IF; + ELSE -- Deallocate memory from work station memory. + deallocate_mem(mem_page_v); + END IF; + END PROCESS mem_proc; +END LinkedList; Index: single_port/trunk/VHDL/tb_single_port.vhd =================================================================== --- single_port/trunk/VHDL/tb_single_port.vhd (nonexistent) +++ single_port/trunk/VHDL/tb_single_port.vhd (revision 15) @@ -0,0 +1,225 @@ +---------------------------------------------------------------------- +---- ---- +---- Single port asynchronous RAM simulation model ---- +---- ---- +---- This file is part of the single_port project ---- +---- ---- +---- Description ---- +---- This file specifies test bench harness for the single_port ---- +---- Memory. It also contains the configuration files for all the ---- +---- tests. ---- +---- ---- +---- Authors: ---- +---- - Robert Paley, rpaley_yid@yahoo.com ---- +---- - Michael Geng, vhdl@MichaelGeng.de ---- +---- ---- +---- References: ---- +---- 1. The Designer's Guide to VHDL by Peter Ashenden ---- +---- ISBN: 1-55860-270-4 (pbk.) ---- +---- 2. Writing Testbenches - Functional Verification of HDL ---- +---- models by Janick Bergeron | ISBN: 0-7923-7766-4 ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2005 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.2 2005/10/12 19:39:27 mgeng +-- Buses unconstrained, LGPL header added +-- +-- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid +-- initial checkin +-- +-- Revision 1.1 2003/01/14 17:49:04 Default +-- Initial revision +-- +-- Revision 1.2 2002/12/31 19:19:43 Default +-- Updated 'transaction statements for fixed simulator. +-- +-- Revision 1.1 2002/12/24 18:10:18 Default +-- Initial revision +-- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE WORK.linked_list_mem_pkg.ALL; +USE WORK.single_port_pkg.all; +USE STD.TEXTIO.ALL; + +ENTITY tb_single_port IS +END ENTITY tb_single_port; + +ARCHITECTURE BHV of tb_single_port IS + +COMPONENT single_port IS + GENERIC ( + rnwtQ : TIME := 1 NS); + PORT ( + d : IN STD_LOGIC_VECTOR; + q : OUT STD_LOGIC_VECTOR; + a : IN STD_LOGIC_VECTOR; + nce : IN STD_LOGIC; + nwe : IN STD_LOGIC; + noe : IN STD_LOGIC; + dealloc_mem : BOOLEAN); +END COMPONENT single_port; + +COMPONENT tc_single_port IS + PORT ( + to_srv : OUT to_srv_typ; + frm_srv : IN STD_LOGIC_VECTOR); +END COMPONENT tc_single_port; + CONSTANT DATA_WIDTH : INTEGER := 32; + CONSTANT ADDR_WIDTH : INTEGER := 16; + + SIGNAL d : STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0); + SIGNAL q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 DOWNTO 0); + SIGNAL a : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0); + SIGNAL nce, nwe, noe : STD_LOGIC; + SIGNAL dealloc_mem : BOOLEAN; + SIGNAL to_srv : to_srv_typ; + SIGNAL frm_srv : STD_LOGIC_VECTOR(d'RANGE); + SIGNAL tie_vdd : STD_LOGIC := '1'; +BEGIN + dut : single_port + PORT MAP ( + d => d, + a => a, + q => q, + nce => nce, + nwe => nwe, + noe => noe, + dealloc_mem => dealloc_mem); + + tc : tc_single_port + PORT MAP ( + to_srv => to_srv, + frm_srv => frm_srv); + + single_port_server : PROCESS + VARIABLE frm_srv_v : STD_LOGIC_VECTOR(d'RANGE); + CONSTANT ACCESS_DELAY : TIME := 5 NS; + BEGIN + -- Wait until the test case is finished setting up the next memory access. + WAIT ON to_srv'TRANSACTION; + CASE to_srv.do IS + WHEN init => + ASSERT FALSE + REPORT "initialized" + SEVERITY NOTE; + WHEN read => -- perform memory read + d <= STD_LOGIC_VECTOR(TO_SIGNED(to_srv.data, d'length)); + a <= STD_LOGIC_VECTOR(TO_UNSIGNED(to_srv.addr, a'length)); + nce <= '0'; + noe <= '0'; + nwe <= '1'; + -- Wait for data to appear + WAIT FOR ACCESS_DELAY; + WHEN write => -- perform memory write + d <= STD_LOGIC_VECTOR(TO_SIGNED(to_srv.data, d'length)); + a <= STD_LOGIC_VECTOR(TO_UNSIGNED(to_srv.addr, a'length)); + nce <= '0'; + noe <= '1'; + nwe <= '0'; + WAIT FOR ACCESS_DELAY; + WHEN dealloc => -- deallocate the linked list for the LL architecture + dealloc_mem <= true; + WHEN end_test => -- reached the end of the test case + WAIT; + END CASE; + frm_srv_v := q; + -- Send message to test case to continue the test. + frm_srv <= frm_srv_v ; WAIT FOR 0 NS; + END PROCESS single_port_server; +END BHV; + +CONFIGURATION ll_main_cfg OF TB_SINGLE_PORT IS + FOR BHV + FOR dut : single_port + USE ENTITY work.single_port(LinkedList); + END FOR; -- dut + FOR tc : tc_single_port + USE ENTITY work.tc_single_port(TC0); + END FOR; -- tc; + END FOR; -- BHV +END CONFIGURATION ll_main_cfg; + +CONFIGURATION ll_error_cfg OF TB_SINGLE_PORT IS + FOR BHV + FOR dut : single_port + USE ENTITY work.single_port(LinkedList); + END FOR; -- dut + FOR tc : tc_single_port + USE ENTITY work.tc_single_port(TC1); + END FOR; -- tc; + END FOR; -- BHV +END CONFIGURATION ll_error_cfg ; + +CONFIGURATION mem_main_cfg of TB_SINGLE_PORT IS + FOR BHV + FOR dut : single_port + USE ENTITY work.single_port(ArrayMem); + END FOR; -- dut + FOR tc : tc_single_port + USE ENTITY work.tc_single_port(TC0); + END FOR; -- tc; + END FOR; -- BHV +END CONFIGURATION mem_main_cfg; + +CONFIGURATION mem_error_cfg of TB_SINGLE_PORT IS + FOR BHV + FOR dut : single_port + USE ENTITY work.single_port(ArrayMem); + END FOR; -- dut + FOR tc : tc_single_port + USE ENTITY work.tc_single_port(TC1); + END FOR; -- tc; + END FOR; -- BHV +END CONFIGURATION mem_error_cfg; + +CONFIGURATION memnoflag_main_cfg of TB_SINGLE_PORT IS + FOR BHV + FOR dut : single_port + USE ENTITY work.single_port(ArrayMemNoFlag); + END FOR; -- dut + FOR tc : tc_single_port + USE ENTITY work.tc_single_port(TC0); + END FOR; -- tc; + END FOR; -- BHV +END CONFIGURATION memnoflag_main_cfg; + +CONFIGURATION memnoflag_error_cfg of TB_SINGLE_PORT IS + FOR BHV + FOR dut : single_port + USE ENTITY work.single_port(ArrayMemNoFlag); + END FOR; -- dut + FOR tc : tc_single_port + USE ENTITY work.tc_single_port(TC1); + END FOR; -- tc; + END FOR; -- BHV +END CONFIGURATION memnoflag_error_cfg; Index: single_port/trunk/VHDL/linked_list_mem_pkg.vhd =================================================================== --- single_port/trunk/VHDL/linked_list_mem_pkg.vhd (nonexistent) +++ single_port/trunk/VHDL/linked_list_mem_pkg.vhd (revision 15) @@ -0,0 +1,174 @@ +---------------------------------------------------------------------- +---- ---- +---- Single port asynchronous RAM simulation model ---- +---- ---- +---- This file is part of the single_port project ---- +---- ---- +---- Description ---- +---- This package implements functions to allocate, write, read ---- +---- and deallocate a linked list based memory. ---- +---- ---- +---- Authors: ---- +---- - Robert Paley, rpaley_yid@yahoo.com ---- +---- - Michael Geng, vhdl@MichaelGeng.de ---- +---- ---- +---- References: ---- +---- 1. The Designer's Guide to VHDL by Peter Ashenden ---- +---- ISBN: 1-55860-270-4 (pbk.) ---- +---- 2. Writing Testbenches - Functional Verification of HDL ---- +---- models by Janick Bergeron | ISBN: 0-7923-7766-4 ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2005 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.2 2005/10/12 19:39:27 mgeng +-- Buses unconstrained, LGPL header added +-- +-- Revision 1.1.1.1 2003/01/14 21:48:10 rpaley_yid +-- initial checkin +-- +-- Revision 1.1 2003/01/14 17:47:32 Default +-- Initial revision +-- +-- Revision 1.1 2002/12/24 18:03:50 Default +-- Initial revision +-- +LIBRARY IEEE; +LIBRARY WORK; +USE IEEE.STD_LOGIC_1164.ALL; +USE WORK.single_port_pkg.all; + +PACKAGE linked_list_mem_pkg IS + CONSTANT PAGEDEPTH : INTEGER := 256; -- memory page depth + -- pointer to one data word in the memory + -- The reason for using a pointer here is that it seems to be the only way to keep the model + -- independent of the data width + TYPE data_ptr IS ACCESS BIT_VECTOR; + -- data memory array type definition + TYPE mem_array_typ IS ARRAY (0 TO PAGEDEPTH-1) OF data_ptr; + -- Define memory page linked list cell. This cell contains + -- the mem_array, starting page address, valid data array and + -- the pointer to the next element in the linked list. + TYPE mem_page_typ; + -- pointer to next item in the linked list. + TYPE mem_page_ptr IS ACCESS mem_page_typ; + TYPE mem_page_typ IS RECORD + mem_array : mem_array_typ; -- data memory + page_address : addr_typ; + next_cell : mem_page_ptr; + END RECORD mem_page_typ; + PROCEDURE rw_mem ( + VARIABLE data : INOUT STD_LOGIC_VECTOR; + VARIABLE addr : IN addr_typ; + VARIABLE next_cell : INOUT mem_page_ptr; + CONSTANT write_flag : IN BOOLEAN); + PROCEDURE deallocate_mem ( + VARIABLE next_cell : INOUT mem_page_ptr); + +END PACKAGE linked_list_mem_pkg; + +PACKAGE BODY linked_list_mem_pkg IS + -- -------------------------------------------------- + -- The purpose of this procedure is to write a memory location from + -- the linked list, if the particular page does not exist, create it. + -- -------------------------------------------------- + PROCEDURE rw_mem ( + VARIABLE data : INOUT STD_LOGIC_VECTOR; + VARIABLE addr : IN addr_typ; + VARIABLE next_cell : INOUT mem_page_ptr; + CONSTANT write_flag : IN BOOLEAN) IS + VARIABLE current_cell_v : mem_page_ptr; -- current page pointer + VARIABLE page_address_v : addr_typ; -- calculated page address + VARIABLE index_v : INTEGER; -- address within the memory page + VARIABLE mem_array_v : mem_array_typ; + BEGIN + -- Copy the top of the linked list pointer to a working pointer + current_cell_v := next_cell; + -- Calculate the index within the page from the given address + index_v := addr MOD PAGEDEPTH; + -- Calculate the page address from the given address + page_address_v := addr - index_v; + -- Search through the memory to determine if the calculated + -- memory page exists. Stop searching when reach the end of + -- the linked list. + WHILE ( current_cell_v /= NULL AND + current_cell_v.page_address /= page_address_v) LOOP + current_cell_v := current_cell_v.next_cell; + END LOOP; + + IF write_flag THEN + IF ( current_cell_v /= NULL AND -- Check if address exists in memory. + current_cell_v.page_address = page_address_v ) THEN + -- Found the memory page the particular address belongs to + IF ( current_cell_v.mem_array(index_v) /= NULL ) THEN + current_cell_v.mem_array(index_v).ALL := TO_BITVECTOR(data); + ELSE + current_cell_v.mem_array(index_v) := NEW BIT_VECTOR'(TO_BITVECTOR(data)); + END IF; + ELSE + -- The memory page the address belongs to was not allocated in memory. + -- Allocate page here and assign data. + mem_array_v(index_v) := NEW BIT_VECTOR'(TO_BITVECTOR(data)); + next_cell := NEW mem_page_typ'( mem_array => mem_array_v, + page_address => page_address_v, + next_cell => next_cell); + END IF; + ELSE -- Read memory + IF ( current_cell_v /= NULL AND -- Check if address exists in memory. + current_cell_v.page_address = page_address_v AND + current_cell_v.mem_array(index_v) /= NULL ) THEN + -- Found the memory page the particular address belongs to, + -- and the memory location has valid data. + data := TO_STDLOGICVECTOR(current_cell_v.mem_array(index_v).ALL); + ELSE + -- Trying to read from unwritten or unallocated + -- memory location, return 'U'; + data := (data'RANGE => 'U'); + END IF; + END IF; + END PROCEDURE rw_mem; + + PROCEDURE deallocate_mem ( + VARIABLE next_cell : INOUT mem_page_ptr) IS + VARIABLE delete_cell_v : mem_page_ptr; + BEGIN + -- Deallocate the linked link memory from work station memory. + WHILE next_cell /= NULL LOOP -- while not reached the end of the LL + delete_cell_v := next_cell; -- Copy pointer to record for deleting + FOR i IN 0 TO PAGEDEPTH-1 LOOP + IF delete_cell_v.mem_array(i) /= NULL THEN + deallocate(delete_cell_v.mem_array(i)); + END IF; + END LOOP; + next_cell := next_cell.next_cell; -- set pointer to next cell in LL + deallocate(delete_cell_v); -- Deallocate current cell from memory. + END LOOP; + END PROCEDURE deallocate_mem; +END PACKAGE BODY linked_list_mem_pkg; Index: single_port/trunk/VHDL/single_port_pkg.vhd =================================================================== --- single_port/trunk/VHDL/single_port_pkg.vhd (nonexistent) +++ single_port/trunk/VHDL/single_port_pkg.vhd (revision 15) @@ -0,0 +1,84 @@ +---------------------------------------------------------------------- +---- ---- +---- Single port asynchronous RAM simulation model ---- +---- ---- +---- This file is part of the single_port project ---- +---- ---- +---- Description ---- +---- Package file for single_port memory and testbench ---- +---- ---- +---- Authors: ---- +---- - Robert Paley, rpaley_yid@yahoo.com ---- +---- - Michael Geng, vhdl@MichaelGeng.de ---- +---- ---- +---- References: ---- +---- 1. The Designer's Guide to VHDL by Peter Ashenden ---- +---- ISBN: 1-55860-270-4 (pbk.) ---- +---- 2. Writing Testbenches - Functional Verification of HDL ---- +---- models by Janick Bergeron | ISBN: 0-7923-7766-4 ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2005 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.3 2005/10/25 18:26:52 mgeng +-- PAGENUM constant removed because the address bus width provides this information +-- +-- Revision 1.2 2005/10/12 19:39:27 mgeng +-- Buses unconstrained, LGPL header added +-- +-- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid +-- initial checkin +-- +-- Revision 1.1 2003/01/14 17:48:44 Default +-- Initial revision +-- +-- Revision 1.1 2002/12/24 17:58:49 Default +-- Initial revision +-- +LIBRARY IEEE; + USE IEEE.STD_LOGIC_1164.ALL; + USE IEEE.NUMERIC_STD.ALL; + +PACKAGE single_port_pkg IS + -- Address bus type for internal memory + SUBTYPE addr_typ IS NATURAL; + -- Operations testbench can do. + TYPE do_typ IS ( init , read , write , dealloc , end_test ); + + TYPE to_srv_typ IS RECORD -- Record passed from test case to test bench + do : do_typ; + addr : INTEGER; + data : INTEGER; + event : BOOLEAN; + END RECORD to_srv_typ; +END PACKAGE single_port_pkg; + +PACKAGE BODY single_port_pkg IS +END PACKAGE BODY single_port_pkg; Index: single_port/trunk/VHDL/tc_single_port.vhd =================================================================== --- single_port/trunk/VHDL/tc_single_port.vhd (nonexistent) +++ single_port/trunk/VHDL/tc_single_port.vhd (revision 15) @@ -0,0 +1,214 @@ +---------------------------------------------------------------------- +---- ---- +---- Single port asynchronous RAM simulation model ---- +---- ---- +---- This file is part of the single_port project ---- +---- ---- +---- Description ---- +---- This file specifies test cases for the single_port Memory. ---- +---- ---- +---- Authors: ---- +---- - Robert Paley, rpaley_yid@yahoo.com ---- +---- - Michael Geng, vhdl@MichaelGeng.de ---- +---- ---- +---- References: ---- +---- 1. The Designer's Guide to VHDL by Peter Ashenden ---- +---- ISBN: 1-55860-270-4 (pbk.) ---- +---- 2. Writing Testbenches - Functional Verification of HDL ---- +---- models by Janick Bergeron | ISBN: 0-7923-7766-4 ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2005 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid +-- initial checkin +-- +-- Revision 1.1 2003/01/14 17:49:04 Default +-- Initial revision +-- +-- Revision 1.2 2002/12/31 19:19:43 Default +-- Updated 'transaction statements for fixed simulator. +-- +-- Revision 1.1 2002/12/24 18:13:50 Default +-- Initial revision +-- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE WORK.SINGLE_PORT_PKG.ALL; +USE WORK.PKG_IMAGE.ALL; + +ENTITY tc_single_port IS +PORT ( + to_srv : OUT to_srv_typ; + frm_srv : IN STD_LOGIC_VECTOR); +END ENTITY tc_single_port; + +-- -------------------------------------------------- +-- Test Case TC0 +-- This test case is to check two pages of memory +-- Starting at physical address 0x0 , +-- Write a '1' to bit position 0, leaving all other bits 0. +-- Increment the address, +-- Write a '1' to bit position 1, leaving all other bits 0. +-- Increment the address. +-- Write a '1' to bit position 2, leaving all other bits 0. +-- Continue in this fasion, until write a 1 to the MSB. +-- increment the address, +-- Write a '1' to bit position 0, leaving all other bits 0. +-- Continue until the entire page is written to. +-- Read back all addresses in the page, ensuring the +-- correct data is read back. +-- -------------------------------------------------- + + +ARCHITECTURE TC0 OF tc_single_port IS +BEGIN + MAIN : PROCESS + VARIABLE to_srv_v : to_srv_typ; + VARIABLE frm_srv_v : STD_LOGIC_VECTOR(frm_srv'RANGE); + VARIABLE dv : STD_LOGIC_VECTOR(frm_srv'RANGE) := + STD_LOGIC_VECTOR(TO_UNSIGNED(1, frm_srv'length)); + VARIABLE offset_v : INTEGER; + BEGIN + offset_v := 0; + -- Run this write/read test 10 times for benchmark + -- purposes. + FOR i IN 0 to 9 LOOP + FOR index IN 0 to 2*PAGEDEPTH-1 LOOP + -- Specify to testbench server to perform write operation; + to_srv_v.do := write; + to_srv_v.data := TO_INTEGER(SIGNED(dv)); -- specify data to write + dv := To_StdLogicVector(TO_BitVector(dv) ROL 1); -- ROL 1 for next write + -- Specify physical address. + to_srv_v.addr := index+offset_v; + to_srv <= to_srv_v; + WAIT ON frm_srv'TRANSACTION; + END LOOP; + -- Reset data to 1. + dv := STD_LOGIC_VECTOR(TO_UNSIGNED(1,frm_srv'length)); + FOR index IN 0 to 2*PAGEDEPTH-1 LOOP + -- Perform read operation. + to_srv_v.do := read; + -- Specify physical address. + to_srv_v.addr := index+offset_v; + to_srv <= to_srv_v; + WAIT ON frm_srv'TRANSACTION; + -- Compare actual with expected read back data, if the + -- the expected and actual to not compare, print the + -- expected and actual values. + ASSERT frm_srv = dv + REPORT "Expected: " & HexImage(frm_srv) & + " did not equal Actual: " & HexImage(dv) + SEVERITY ERROR; + -- Set expected data for next read. + dv := TO_STDLOGICVECTOR(TO_BITVECTOR(dv) ROL 1); + END LOOP; + END LOOP; + to_srv_v.do := dealloc; -- Deallocate memory + -- + to_srv <= to_srv_v; + -- Tell test bench server process test completed. + to_srv_v.do := end_test; + to_srv <= to_srv_v; + ASSERT FALSE + REPORT "Completed Test TC0" + SEVERITY NOTE; + WAIT; + END PROCESS main; +END TC0; + +-- -------------------------------------------------- +-- Test Case TC1 +-- This test case is to check if the test bench will +-- return 'U' for invalid memory locations for +-- single_port architectures ArrayMem and LinkedList +-- -------------------------------------------------- +ARCHITECTURE TC1 OF tc_single_port IS +BEGIN + MAIN : PROCESS + VARIABLE to_srv_v : to_srv_typ; + VARIABLE frm_srv_v : STD_LOGIC_VECTOR(frm_srv'RANGE); + VARIABLE dv : STD_LOGIC_VECTOR(frm_srv'RANGE) := (OTHERS => 'U'); + BEGIN + -- Perform read operation. + to_srv_v.do := read; + -- Specify physical address. + to_srv_v.addr := 0; + to_srv <= to_srv_v; + WAIT ON frm_srv'TRANSACTION; + -- Compare actual with expected read back data, if the + -- the expected and actual to not compare, print the + -- expected and actual values. + ASSERT frm_srv = dv + REPORT "Expected: " & HexImage(frm_srv) & + " did not equal Actual: " & HexImage(dv) + SEVERITY ERROR; + + -- Write and read back from same address. + + -- Specify to testbench server to perform write operation; + to_srv_v.do := write; + dv := X"a5a5a5a5"; + to_srv_v.data := TO_INTEGER(SIGNED(dv)); -- specify data to write + -- Specify physical address. + to_srv_v.addr := 0; + to_srv <= to_srv_v; + -- Wait until the test bench server finished with the write. + -- WAIT UNTIL frm_srv.event = true; + WAIT ON frm_srv'TRANSACTION; + + to_srv_v.do := read; + -- Specify physical address. + to_srv_v.addr := 0; + to_srv <= to_srv_v; + WAIT ON frm_srv'TRANSACTION; + + -- Compare actual with expected read back data, if the + -- the expected and actual to not compare, print the + -- expected and actual values. + ASSERT frm_srv = dv + REPORT "Expected: " & HexImage(frm_srv) & + " did not equal Actual: " & HexImage(dv) + SEVERITY ERROR; + + to_srv_v.do := dealloc; -- Deallocate memory + -- + to_srv <= to_srv_v; + -- Tell test bench server process test completed. + to_srv_v.do := end_test; + to_srv <= to_srv_v; + + ASSERT FALSE + REPORT "Completed Test TC1" + SEVERITY NOTE; + WAIT; + END PROCESS main; +END TC1; Index: single_port/trunk/VHDL/pkg_image.vhd =================================================================== --- single_port/trunk/VHDL/pkg_image.vhd (nonexistent) +++ single_port/trunk/VHDL/pkg_image.vhd (revision 15) @@ -0,0 +1,307 @@ +-- $Author: rpaley_yid $ +-- $Date: 2003-01-14 21:48:10 $ +-- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/pkg_image.vhd,v 1.1.1.1 2003-01-14 21:48:10 rpaley_yid Exp $ +-- $Locker +-- $Revision: 1.1.1.1 $ +-- $State: Exp $ + +-- Copyright (c) 1997 Ben Cohen. All rights reserved. +-- This model can be used in conjunction with the Kluwer Academic books +-- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0 +-- "VHDL Amswers to Frequently Asked Questions", Kluwer Academic +-- by Ben Cohen. email: vhdlcohen@aol.com +-- +-- This source file for the Image Package +-- may be used and distributed without restriction provided +-- that this copyright statement is not removed from the file +-- and that any derivative work contains this copyright notice. +-- +-- +-- Original Author: Ben Cohen +-- Description: +-- Convert VHDL types to string for printing. This is especially useful when +-- compiling with VHDL-87 + +--------------------------------------------------------------- +LIBRARY IEEE; + USE IEEE.STD_LOGIC_1164.ALL; + USE IEEE.STD_LOGIC_TEXTIO.ALL; + USE IEEE.NUMERIC_STD.ALL; + +LIBRARY STD; + USE STD.TEXTIO.ALL; + +package pkg_image is + function Image(In_Image : Time) return String; + function Image(In_Image : Bit) return String; + function Image(In_Image : Bit_Vector) return String; + function Image(In_Image : Integer) return String; + function Image(In_Image : Real) return String; + function Image(In_Image : Std_uLogic) return String; + function Image(In_Image : Std_uLogic_Vector) return String; + function Image(In_Image : Std_Logic_Vector) return String; + function Image(In_Image : Signed) return String; + function Image(In_Image : UnSigned) return String; + + function HexImage(InStrg : String) return String; + function HexImage(In_Image : Bit_Vector) return String; + function HexImage(In_Image : Std_uLogic_Vector) return String; + function HexImage(In_Image : Std_Logic_Vector) return String; + function HexImage(In_Image : Signed) return String; + function HexImage(In_Image : UnSigned) return String; + + function DecImage(In_Image : Bit_Vector) return String; + function DecImage(In_Image : Std_uLogic_Vector) return String; + function DecImage(In_Image : Std_Logic_Vector) return String; + function DecImage(In_Image : Signed) return String; + function DecImage(In_Image : UnSigned) return String; +end pkg_image; + +package body pkg_image is + function Image(In_Image : Time) return String is + variable L : Line; -- access type + variable W : String(1 to 14) := (others => ' '); + -- Long enough to hold a time string + begin + -- the WRITE procedure creates an object with "NEW". + -- L is passed as an output of the procedure. + Std.TextIO.WRITE(L, in_image); + -- Copy L.all onto W + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Bit) return String is + variable L : Line; -- access type + variable W : String(1 to 3) := (others => ' '); + begin + Std.TextIO.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Bit_Vector) return String is + variable L : Line; -- access type + variable W : String(1 to In_Image'length) := (others => ' '); + begin + Std.TextIO.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Integer) return String is + variable L : Line; -- access type + variable W : String(1 to 32) := (others => ' '); + -- Long enough to hold a time string + begin + Std.TextIO.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Real) return String is + variable L : Line; -- access type + variable W : String(1 to 32) := (others => ' '); + -- Long enough to hold a time string + begin + Std.TextIO.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Std_uLogic) return String is + variable L : Line; -- access type + variable W : String(1 to 3) := (others => ' '); + begin + IEEE.Std_Logic_Textio.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Std_uLogic_Vector) return String is + variable L : Line; -- access type + variable W : String(1 to In_Image'length) := (others => ' '); + begin + IEEE.Std_Logic_Textio.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Std_Logic_Vector) return String is + variable L : Line; -- access type + variable W : String(1 to In_Image'length) := (others => ' '); + begin + IEEE.Std_Logic_TextIO.WRITE(L, In_Image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Signed) return String is + begin + return Image(Std_Logic_Vector(In_Image)); + end Image; + + function Image(In_Image : UnSigned) return String is + begin + return Image(Std_Logic_Vector(In_Image)); + end Image; + + function HexImage(InStrg : String) return String is + subtype Int03_Typ is Integer range 0 to 3; + variable Result : string(1 to ((InStrg'length - 1)/4)+1) := + (others => '0'); + variable StrTo4 : string(1 to Result'length * 4) := + (others => '0'); + variable MTspace : Int03_Typ; -- Empty space to fill in + variable Str4 : String(1 to 4); + variable Group_v : Natural := 0; + begin + MTspace := Result'length * 4 - InStrg'length; + StrTo4(MTspace + 1 to StrTo4'length) := InStrg; -- padded with '0' + Cnvrt_Lbl : for I in Result'range loop + Group_v := Group_v + 4; -- identifies end of bit # in a group of 4 + Str4 := StrTo4(Group_v - 3 to Group_v); -- get next 4 characters + case Str4 is + when "0000" => Result(I) := '0'; + when "0001" => Result(I) := '1'; + when "0010" => Result(I) := '2'; + when "0011" => Result(I) := '3'; + when "0100" => Result(I) := '4'; + when "0101" => Result(I) := '5'; + when "0110" => Result(I) := '6'; + when "0111" => Result(I) := '7'; + when "1000" => Result(I) := '8'; + when "1001" => Result(I) := '9'; + when "1010" => Result(I) := 'A'; + when "1011" => Result(I) := 'B'; + when "1100" => Result(I) := 'C'; + when "1101" => Result(I) := 'D'; + when "1110" => Result(I) := 'E'; + when "1111" => Result(I) := 'F'; + when others => Result(I) := 'X'; + end case; -- Str4 + end loop Cnvrt_Lbl; + + return Result; + end HexImage; + + + function HexImage(In_Image : Bit_Vector) return String is + begin + return HexImage(Image(In_Image)); + end HexImage; + + function HexImage(In_Image : Std_uLogic_Vector) return String is + begin + return HexImage(Image(In_Image)); + end HexImage; + + function HexImage(In_Image : Std_Logic_Vector) return String is + begin + return HexImage(Image(In_Image)); + end HexImage; + + function HexImage(In_Image : Signed) return String is + begin + return HexImage(Image(In_Image)); + end HexImage; + + function HexImage(In_Image : UnSigned) return String is + begin + return HexImage(Image(In_Image)); + end HexImage; + + function DecImage(In_Image : Bit_Vector) return String is + variable In_Image_v : Bit_Vector(In_Image'length downto 1) := In_Image; + begin + if In_Image'length > 31 then + assert False + report "Number too large for Integer, clipping to 31 bits" + severity Warning; + return Image(To_Integer + (Unsigned(To_StdLogicVector + (In_Image_v(31 downto 1))))); + else + return Image(To_Integer(Unsigned(To_StdLogicVector(In_Image)))); + end if; + end DecImage; + + function DecImage(In_Image : Std_uLogic_Vector) return String is + variable In_Image_v : Std_uLogic_Vector(In_Image'length downto 1) + := In_Image; + begin + if In_Image'length > 31 then + assert False + report "Number too large for Integer, clipping to 31 bits" + severity Warning; + return Image(To_Integer(Unsigned(In_Image_v(31 downto 1)))); + else + return Image(To_Integer(Unsigned(In_Image))); + end if; + end DecImage; + + function DecImage(In_Image : Std_Logic_Vector) return String is + variable In_Image_v : Std_Logic_Vector(In_Image'length downto 1) + := In_Image; + begin + if In_Image'length > 31 then + assert False + report "Number too large for Integer, clipping to 31 bits" + severity Warning; + return Image(To_Integer(Unsigned(In_Image_v(31 downto 1)))); + else + return Image(To_Integer(Unsigned(In_Image))); + end if; + end DecImage; + + function DecImage(In_Image : Signed) return String is + variable In_Image_v : Signed(In_Image'length downto 1) := In_Image; + begin + if In_Image'length > 31 then + assert False + report "Number too large for Integer, clipping to 31 bits" + severity Warning; + return Image(To_Integer(In_Image_v(31 downto 1))); + else + return Image(To_Integer(In_Image)); + end if; + end DecImage; + + function DecImage(In_Image : UnSigned) return String is + variable In_Image_v : UnSigned(In_Image'length downto 1) := In_Image; + begin + if In_Image'length > 31 then + assert False + report "Number too large for Integer, clipping to 31 bits" + severity Warning; + return Image(To_Integer(In_Image_v(31 downto 1))); + else + return Image(To_Integer(In_Image)); + end if; + end DecImage; + +end pkg_image; + +-- $Log: not supported by cvs2svn $ +-- Revision 1.1 2003/01/14 17:48:44 Default +-- Initial revision +-- +-- Revision 1.1 2002/12/24 18:07:50 Default +-- Initial revision +-- + + + + + + + + Index: single_port/trunk/VHDL/Makefile =================================================================== --- single_port/trunk/VHDL/Makefile (nonexistent) +++ single_port/trunk/VHDL/Makefile (revision 15) @@ -0,0 +1,161 @@ +# +# Description: Top level make file for single_port test project. +# make com to compile +# make sim to simulate all tests +# make ll_error to run this test only +# make ll_main to run this test only +# make mem_main to run this test only +# make mem_error to run this test only +# make memnoflag_main to run this test +# make memnoflag_error to run this test +# $Author: rpaley_yid $ +# $Date: 2003-01-14 21:48:11 $ +# $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/Makefile,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $ +# $Locker: $ +# $Revision: 1.1.1.1 $ +# $State: Exp $ + +# VCOM , VSIM , and WORK variables are set for Sonata simulator, +# Change appropriately for your simulator. Ex.for Modeltech, +# VCOM = vcom +# VSIM = vsim +# WORK = work + +SHELL = /bin/sh +VCOM = vhdlp +VCOMOPT = -s +VSIM = vhdle +VSIMOPT = +WORK = work.sym +## Need to figure out how to put Bourne shell stuff in Makefile +## will do so to generate log files in +## LOGDIR = ../LOG/ +## For now, log files are in VHDL directory. + + +# List of main compiled objects, does not include configurations, +# which are included in the tb_single_port.vhd file. +# These targets are for the Sonata simulator, adjust accordingly for +# your simulator. + +SINGLE_PORT_PKG_OBJ = $(WORK)/single_port_pkg/prim.var +LINKED_LIST_MEM_OBJ = $(WORK)/linked_list_mem_pkg/prim.var +PKG_IMAGE_OBJ = $(WORK)/pkg_image/prim.var +SINGLE_PORT_OBJ = $(WORK)/single_port/prim.var +TC_SINGLE_PORT_OBJ = $(WORK)/tc_single_port/prim.var +TB_SINGLE_PORT_OBJ = $(WORK)/tb_single_port/prim.var +LL_ERROR_DEP = $(WORK)/ll_error_cfg/prim.var +LL_MAIN_DEP = $(WORK)/ll_main_cfg/prim.var +MEM_MAIN_DEP = $(WORK)/mem_main_cfg/prim.var +MEM_ERROR_DEP = $(WORK)/mem_error_cfg/prim.var +MEMNOFLAG_MAIN_DEP = $(WORK)/memnoflag_main_cfg/prim.var +MEMNOFLAG_ERROR_DEP = $(WORK)/memnoflag_error_cfg/prim.var + +LL_ERROR = $(LOGDIR)ll_error.log +LL_MAIN = ll_main.log +MEM_MAIN = mem_main.log +MEM_ERROR = mem_error.log +MEMNOFLAG_MAIN = memnoflag_main.log +MEMNOFLAG_ERROR = memnoflag_error.log + +OBJS = $(SINGLE_PORT_PKG_OBJ) \ + $(LINKED_LIST_MEM_OBJ) \ + $(PKG_IMAGE_OBJ) \ + $(SINGLE_PORT_OBJ) \ + $(TC_SINGLE_PORT_OBJ) \ + $(TB_SINGLE_PORT_OBJ) + +SIMOBJS = $(LL_ERROR) \ + $(LL_MAIN) \ + $(MEM_MAIN) \ + $(MEM_ERROR) \ + $(MEMNOFLAG_MAIN) \ + $(MEMNOFLAG_ERROR) + +# Compile the project +com: $(OBJS) + +# Clean the library +clean:: $(WORK) + +# Simulate all tests +sim: $(SIMOBJS) + +## Run only ll_error test +ll_error: $(LL_ERROR) + +# Run onle ll_main test +ll_main: $(LL_MAIN) + +# Run only mem_main test +mem_main: $(MEM_MAIN) + +# Run only mem_error test +mem_error: $(MEM_ERROR) + +# Run only memnoflag_main test +memnoflag_main: $(MEMNOFLAG_MAIN) + +# Run only memnoflag_error test +memnoflag_error: $(MEMNOFLAG_ERROR) + +# Target dependency rules to run tests +$(LL_ERROR) : $(LL_ERROR_DEP) + $(VSIM) $(VSIMOPT) ll_error_cfg | tee $@ + +$(LL_MAIN) : $(LL_MAIN_DEP) + $(VSIM) $(VSIMOPT) ll_main_cfg | tee $@ + +$(MEM_MAIN) : $(MEM_MAIN_DEP) + $(VSIM) $(VSIMOPT) mem_main_cfg | tee $@ + +$(MEM_ERROR) : $(MEM_ERROR_DEP) + $(VSIM) $(VSIMOPT) mem_error_cfg | tee $@ + +$(MEMNOFLAG_MAIN) : $(MEMNOFLAG_MAIN_DEP) + $(VSIM) $(VSIMOPT) memnoflag_main_cfg | tee $@ + +$(MEMNOFLAG_ERROR) : $(MEMNOFLAG_ERROR_DEP) + $(VSIM) $(VSIMOPT) memnoflag_error_cfg | tee $@ + +# Target dependency rules to compile tests + +$(SINGLE_PORT_PKG_OBJ) : single_port_pkg.vhd + $(VCOM) $(VCOMOPT) $< + +$(LINKED_LIST_MEM_OBJ) : linked_list_mem_pkg.vhd \ + $(SINGLE_PORT_PKG_OBJ) + $(VCOM) $(VCOMOPT) $< + +$(PKG_IMAGE_OBJ) : pkg_image.vhd + $(VCOM) $(VCOMOPT) $< + +$(SINGLE_PORT_OBJ) : single_port.vhd \ + $(SINGLE_PORT_PKG_OBJ) \ + $(LINKED_LIST_MEM_OBJ) + $(VCOM) $(VCOMOPT) $< + +$(TC_SINGLE_PORT_OBJ) : tc_single_port.vhd \ + $(SINGLE_PORT_PKG_OBJ) \ + $(PKG_IMAGE_OBJ) \ + $(SINGLE_PORT_OBJ) + $(VCOM) $(VCOMOPT) $< + +$(TB_SINGLE_PORT_OBJ) : tb_single_port.vhd \ + $(SINGLE_PORT_PKG_OBJ) \ + $(LINKED_LIST_MEM_OBJ) \ + $(SINGLE_PORT_OBJ) \ + $(TC_SINGLE_PORT_OBJ) + $(VCOM) $(VCOMOPT) $< + +$(WORK) :: + rm -rf $(WORK)/* + + +#################################################################### +# $Log: not supported by cvs2svn $ +# Revision 1.1 2002/12/31 19:21:59 Default +# Initial revision +# +# + Index: single_port/trunk/doc/single_port.html =================================================================== --- single_port/trunk/doc/single_port.html (nonexistent) +++ single_port/trunk/doc/single_port.html (revision 15) @@ -0,0 +1,366 @@ + + + + + + + + + + + + + + + + + + + + + +

+ +

Description + of single_port memory and test environment.

+ +

Abstract:

+ +

A VHDL simulation model for an asynchronous static single + port memory is described. The memory is implemented as three different + architectures, a simple one and 2 ones which are optimized for efficient + use of simulator memory. Data and address buses are unconstrained, so +multiple instances with different address and data bus widths can be implemented +in one single design. A testbench is also provided.
+

+ +

Port Interface:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ + Port Name +	+ + Type +	+ + Description +
+ + rnwtQ +	+ + Time +	+ + Time delay until data or tristate appears on q data bus. +
+ + d +	STD_LOGIC_VECTOR +	+ + Input data bus, unconstrained +
+ + q +	+ + STD_LOGIC_VECTOR + +	+ + Output data bus, unconstrained +
+ + a +	+ + STD_LOGIC_VECTOR + +	+ + Address bus, unconstrained +
+ + nce +	+ + STD_LOGIC +	+ + not chip enable +
nwe +	STD_LOGIC +	not write enable +
noe +	STD_LOGIC +	not output enable +
+ + dealloc_mem +	+ + BOOLEAN +	+ + When set to true, deallocate linked list memory. +

+ +

Functional Description:

+ +

All 3 architectures functionally behave like commercially + available asynchronous SRAMs if you connect d and q to the same bus. If a memory location is read which was not written to during the + current simulation, 'U's are loaded onto the memory bus.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

nce +	nwe +	noe +	d +	q +	Mode +
1 +	don't care +	don't care +	don't care +	high Z +	deselected +
0 +	1 +	1 +	don't care +	high Z +	output disabled +
0 +	0 +	don't care +	input data +	high Z +	write +
0 +	1 +	0 +	don't care +	RAM content +	read +

+ +

Architecture ArrayMemNoFlag

+ +

This architecture implements the memory core as an array + of STD_LOGIC_VECTOR. This is the simplest architecture. It is provided + for comparison with the models below but not recommended for use in your + design.

+ +

Architecture ArrayMem

+ +

This architecture implements the + memory core as an array of BIT_VECTOR. This arrangement allows less workstation + memory to be used than the ArrayMemNoFlag architecture. Use this architecture + if most addresses in the simulated memory are written at least once.
+

+ +

Architecture LinkedList

+ +

+ This architecture implements the memory core as a linked + list of arrays of BIT_VECTOR. Each array in the linked list is a page +of memory whose size is specified with the constant PAGEDEPTH in the package + linked_list_mem_pkg. This arrangement allows less workstation memory +to be used than either the ArrayMemNoFlag or ArrayMem architectures because + memory representing the array data is only allocated if the memory is +actually written to. To de-allocate the memory in the linked list, set +dealloc_mem to true. A short pulse is sufficient. Use this architecture + if a significant portion of your simulated memory (which need not be +contiguous) is never written to. +

Example Timing:

+ +

Clearing both nce and nwe to to '0' immediately causes +a write operation. Changing the address while nce and nwe are asserted causes + a write to the new address, too (But don't do that with real RAMs because + you could destroy more memory locations while the address bus settles). +Every read (and tristate) operation is delayed rnwtQ ns. The below sample + timing diagram illustrates both a read and write operation.

+ +

Timing diagram +
+

+ +

Testbench Description:

+ +

The test bench is arranged as a client server architecture as specified + by Bergeron¹. A diagram illustrating the testbench + is given below.

+ +

Testbench schematic +
+ Two tests are specified in tc_single_port component. The first test + writes data to two logical memory pages, and then reads them back verifying + the correct data. The test case writes an error message to the console +for every miscompare. The second case verifies that the single_port memory +model outputs unknowns to the q bus if a read occurs for an unwritten memory +location. Six configurations are specified in the test bench architecture +tb_single_port, running both tests for each single_port architecture.
+

+ +

Usage:

+ +

A Makefile is used to compile and run all of the tests in a Unix or like + environment, such as Cygwin. The compilation and simulation is targetted + to the SymphonyEDA tool available at www.symphonyeda.com.

+ +

The source files and Makefile are located in {top}/VHDL
+
+ To compile: make com

+ +

To simulate all of the tests: make sim
+

+ +

To clean the compiled library: make clean

+ +

The tests are labeled :

+ +

ll_error
ll_main
mem_main
+
mem_error
+
memnoflag_main
+
memnoflag_error
+

+ +

To simulate any of these tests, type make {testname}

+ +

Please contact Robert Paley at rpaley_yid@opencores.org + or Michael Geng at vhdl@michaelgeng.de + if you have any questions or comments.

+ +

+

1Writing + Testbenches , Functional Verification of HDL Testbenches. Chapter 6 – + ISBN 0-7923-7766-4
+

+

+
+
+
+ + Index: single_port/trunk/doc/copying.txt =================================================================== --- single_port/trunk/doc/copying.txt (nonexistent) +++ single_port/trunk/doc/copying.txt (revision 15) @@ -0,0 +1,504 @@ + GNU LESSER GENERAL PUBLIC LICENSE + Version 2.1, February 1999 + + Copyright (C) 1991, 1999 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + +[This is the first released version of the Lesser GPL. It also counts + as the successor of the GNU Library Public License, version 2, hence + the version number 2.1.] + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +Also add information on how to contact you by electronic and paper mail. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the library, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the + library `Frob' (a library for tweaking knobs) written by James Random Hacker. + + , 1 April 1990 + Ty Coon, President of Vice + +That's all there is to it! + + Index: single_port/trunk/images/timing.dia =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: single_port/trunk/images/timing.dia =================================================================== --- single_port/trunk/images/timing.dia (nonexistent) +++ single_port/trunk/images/timing.dia (revision 15)

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B"H

+

Description +of single_port memory and test environment.

+

Abstract:

+

A single port memory with testbench is described. The memory is +implemented as three different architectures.

+

Port Interface:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+ Port Name +	+ Type +	+ Description +
+ rnwtQ +	+ Time +	+ Time delay from rnw = read until data appears on q data bus. +
+ d +	+ data_inter_typ +	+ Input data bus, type specified in single_port_pkg +
+ q +	+ data_inter_typ +	+ Output data bus, type specified in single_port_pkg +
+ a +	+ addr_inter_typ +	+ Address bus, type specified in single_port_pkg +
+ rnw +	+ STD_LOGIC +	+ Read not write port +
+ dealloc_mem +	+ BOOLEAN +	+ When set to true, deallocate linked list memory. +

+

Functional Description:

+

The single_port memory is implemented as three different +architecures. The first architecture is called ArrayMemNoFlag, and +implements the memory core as an array of STD_LOGIC_VECTOR. The memory +is asynchronous and triggered on rnw'transaction. When rnw = '0', the +data on bus "d" is loaded into the memory at the location specified by +the addres bus "a". When rnw = '1', the data located in memory address +"a" is loaded onto the output data bus "q". If a memory location is read +which was not written to during the current simulation, 'U' are loaded +onto the memory bus.

+

The second architecture is called ArrayMem, and implements the +memory core as an array of BIT_VECTOR. This arrangement allows less +workstation memory to be used than the ArrayMemNoFlag architecture. The +memory is asynchronous and triggered on rnw'transaction. When rnw = '0', +the data on bus "d" is loaded into the memory at the location specified +by the addres bus "a". When rnw = '1', the data located in memory +address "a" is loaded onto the output data bus "q". If a memory location +is read which was not written to during the current simulation, 'U' are +loaded onto the memory bus.

+

The third architecture is called LinkedList, and implements the +memory core as a linked list of arrays of BIT_VECTOR. Each array in the +linked list is a page of memory whose size is specified in +single_port_pkg. This arrangement allows less workstation memory to be +used than either the ArrayMemNoFlag or ArrayMem architectures. The +memory is asynchronous and triggered on rnw'transaction. When rnw = '0', +the data on bus "d" is loaded into the memory at the location specified +by the addres bus "a". When rnw = '1', the data located in memory +address "a" is loaded onto the output data bus "q". If a memory location +is read which was not written to during the current simulation, 'U' are +loaded onto the memory bus. To de-allocate the memory in the linked +list, set dealloc_mem to true.

+

Functional Timing:

+

The single port memory is asynchronous and is triggered on +rnw'transaction. When rnw is cleared to '0', the write occurs at the +same time as rnw'transaction. When a read occurs, with rnw = '1' , data +appears on the Q bus rnwtQ ns after rnw is set to '1'. The below sample +timing diagram illustrates both a read and write operation.

+

Testbench Description:

+

The test bench is arranged as a client server architecture as +specified by Bergeron¹. A diagram illustrating the +testbench is given below.
+
+
+Two tests are specified in tc_single_port component. The first test +writes data to two logical memory pages, and then reads them back +verifying the correct data. The test case writes an error message to the +console for every miscompare. The second case verifies that the +single_port memory model outputs unknowns to the q bus if a read occurs +for an unwritten memory location. Six configurations are specified in +the test bench architecture tb_single_port, running both tests for each +single_port architecture.
+

+

Usage:

+

A Makefile is used to compile and run all of the tests in a Unix or +like environment, such as Cygwin. The compilation and simulation is +targetted to the SymphonyEDA tool available at www.symphonyeda.com .

+

The source files and Makefile are located in {top}/VHDL
+
+To compile: make com

+

To simulate all of the tests: make sim
+

+

To clean the compiled library: make clean

+

The tests are labeled :

+

ll_error
ll_main
mem_main
+
mem_error
+
memnoflag_main
+
memnoflag_error
+

+

To simulate any of these tests, type make {testname}

+

Please contact Robert Paley at rpaley_yid@opencores.org +if you have any questions or comments.

+

1Writing + Testbenches , Functional Verification of HDL Testbenches. Chapter 6 – +ISBN 0-7923-7766-4

+

+ + Index: single_port/tags/REL/images/tbschematic.jpg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: single_port/tags/REL/images/tbschematic.jpg =================================================================== --- single_port/tags/REL/images/tbschematic.jpg (nonexistent) +++ single_port/tags/REL/images/tbschematic.jpg (revision 15)

single_port/tags/REL/images/tbschematic.jpg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: single_port/tags/REL/images/timing.jpg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: single_port/tags/REL/images/timing.jpg =================================================================== --- single_port/tags/REL/images/timing.jpg (nonexistent) +++ single_port/tags/REL/images/timing.jpg (revision 15)

single_port/tags/REL/images/timing.jpg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: single_port/tags/REL/VHDL/linked_list_mem_pkg.vhd =================================================================== --- single_port/tags/REL/VHDL/linked_list_mem_pkg.vhd (nonexistent) +++ single_port/tags/REL/VHDL/linked_list_mem_pkg.vhd (revision 15) @@ -0,0 +1,147 @@ +-- $Author: rpaley_yid $ +-- $Date: 2003-01-14 21:48:10 $ +-- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/linked_list_mem_pkg.vhd,v 1.1.1.1 2003-01-14 21:48:10 rpaley_yid Exp $ +-- $Locker +-- $Revision: 1.1.1.1 $ +-- $State: Exp $ + +-- -------------------------------------------------------------------------- +-- +-- Purpose: This package implements functions to allocate, write, read, and +-- deallocate a linked list based memory. +-- +-- +-- References: +-- 1. The Designer's Guide to VHDL by Peter Ashenden +-- ISBN: 1-55860-270-4 (pbk.) +-- 2. Writing Testbenches - Functional Verification of HDL models by +-- Janick Bergeron | ISBN: 0-7923-7766-4 +-- +-- Notes: +-- +-- -------------------------------------------------------------------------- + +LIBRARY IEEE; +LIBRARY WORK; +USE IEEE.STD_LOGIC_1164.ALL; +USE WORK.single_port_pkg.all; + +PACKAGE linked_list_mem_pkg IS + -- data memory array type definition + TYPE mem_array_typ IS ARRAY (0 TO PAGEDEPTH-1) OF data_typ; + -- Define memory page linked list cell. This cell contains, + -- the mem_array, starting page address, valid data array, and + -- the pointer to the next element in the linked list. + TYPE mem_page_typ; + -- pointer to next item in the linked list. + TYPE mem_page_ptr IS ACCESS mem_page_typ; + TYPE mem_page_typ IS RECORD + mem_array : mem_array_typ; -- data memory + -- This array is a flag which indicates if the corresponding + -- address location inside mem_array contains valid data. + data_valid_array : BIT_VECTOR( 0 TO PAGEDEPTH-1); + page_address : addr_typ; + next_cell : mem_page_ptr; + END RECORD mem_page_typ; + PROCEDURE rw_mem ( + VARIABLE data : INOUT data_inter_typ; + VARIABLE addr : addr_typ; + VARIABLE write_flag : BOOLEAN; + VARIABLE next_cell : INOUT mem_page_ptr + ); + PROCEDURE deallocate_mem ( + VARIABLE next_cell : INOUT mem_page_ptr + ); + +END PACKAGE linked_list_mem_pkg; + +PACKAGE BODY LINKED_LIST_MEM_PKG IS + -- -------------------------------------------------- + -- The purpose of this procedure is to write a memory location from + -- the linked list, if the particular page does not exist, create it. + -- -------------------------------------------------- + PROCEDURE rw_mem ( + VARIABLE data : INOUT data_inter_typ; + VARIABLE addr : addr_typ; + VARIABLE write_flag : BOOLEAN; + VARIABLE next_cell : INOUT mem_page_ptr + ) IS + VARIABLE current_cell_v : mem_page_ptr; -- current page pointer + VARIABLE page_address_v : addr_typ; -- calculated page address + VARIABLE index_v : INTEGER; -- address within the memory page + VARIABLE mem_array_v : mem_array_typ; + VARIABLE data_valid_array_v : BIT_VECTOR(0 TO PAGEDEPTH-1); + BEGIN + -- Copy the top of the linked list pointer to a working pointer + current_cell_v := next_cell; + -- Calculate the index within the page from the given address + index_v := addr MOD PAGEDEPTH; + -- Calculate the page address from the given address + page_address_v := addr - index_v; + -- Search through the memory to determine if the calculated + -- memory page exists. Stop searching when reach the end of + -- the linked list. + WHILE ( current_cell_v /= NULL + AND current_cell_v.page_address /= page_address_v) LOOP + current_cell_v := current_cell_v.next_cell; + END LOOP; + + IF write_flag THEN + IF ( current_cell_v /= NULL AND -- Check if address exists in memory. + current_cell_v.page_address = page_address_v + ) THEN + -- Found the memory page the particular address belongs to + current_cell_v.mem_array(index_v) := TO_BITVECTOR(data); + -- set memory location valid flag + current_cell_v.data_valid_array(index_v) := '1'; + ELSE + -- The memory page the address belongs to was not allocated in memory. + -- Allocate page here and assign data. + mem_array_v(index_v) := TO_BITVECTOR(data); + data_valid_array_v(index_v) := '1'; + next_cell := NEW mem_page_typ'( mem_array => mem_array_v, + data_valid_array => data_valid_array_v, + page_address => page_address_v, + next_cell => next_cell + ); + END IF; + ELSE -- Read memory + IF ( current_cell_v /= NULL AND -- Check if address exists in memory. + current_cell_v.page_address = page_address_v AND + current_cell_v.data_valid_array(index_v) = '1' + ) THEN + -- Found the memory page the particular address belongs to, + -- and the memory location has valid data. + data := TO_STDLOGICVECTOR(current_cell_v.mem_array(index_v)); + ELSE + -- Trying to read from unwritten or unallocated + -- memory location, return 'U'; + data := (OTHERS => 'U'); + END IF; + END IF; + END PROCEDURE rw_mem; + + PROCEDURE deallocate_mem ( + VARIABLE next_cell : INOUT mem_page_ptr + ) IS + VARIABLE delete_cell_v : mem_page_ptr; + BEGIN + -- Deallocate the linked link memory from work station memory. + WHILE next_cell /= NULL LOOP -- while not reached the end of the LL + delete_cell_v := next_cell; -- Copy pointer to record for deleting + next_cell := next_cell.next_cell; -- set pointer to next cell in LL + deallocate(delete_cell_v); -- Deallocate current cell from memory. + END LOOP; + END PROCEDURE deallocate_mem; +END PACKAGE BODY LINKED_LIST_MEM_PKG; + +-- $Log: not supported by cvs2svn $ +-- Revision 1.1 2003/01/14 17:47:32 Default +-- Initial revision +-- +-- Revision 1.1 2002/12/24 18:03:50 Default +-- Initial revision +-- + + + Index: single_port/tags/REL/VHDL/pkg_image.vhd =================================================================== --- single_port/tags/REL/VHDL/pkg_image.vhd (nonexistent) +++ single_port/tags/REL/VHDL/pkg_image.vhd (revision 15) @@ -0,0 +1,307 @@ +-- $Author: rpaley_yid $ +-- $Date: 2003-01-14 21:48:10 $ +-- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/pkg_image.vhd,v 1.1.1.1 2003-01-14 21:48:10 rpaley_yid Exp $ +-- $Locker +-- $Revision: 1.1.1.1 $ +-- $State: Exp $ + +-- Copyright (c) 1997 Ben Cohen. All rights reserved. +-- This model can be used in conjunction with the Kluwer Academic books +-- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0 +-- "VHDL Amswers to Frequently Asked Questions", Kluwer Academic +-- by Ben Cohen. email: vhdlcohen@aol.com +-- +-- This source file for the Image Package +-- may be used and distributed without restriction provided +-- that this copyright statement is not removed from the file +-- and that any derivative work contains this copyright notice. +-- +-- +-- Original Author: Ben Cohen +-- Description: +-- Convert VHDL types to string for printing. This is especially useful when +-- compiling with VHDL-87 + +--------------------------------------------------------------- +LIBRARY IEEE; + USE IEEE.STD_LOGIC_1164.ALL; + USE IEEE.STD_LOGIC_TEXTIO.ALL; + USE IEEE.NUMERIC_STD.ALL; + +LIBRARY STD; + USE STD.TEXTIO.ALL; + +package pkg_image is + function Image(In_Image : Time) return String; + function Image(In_Image : Bit) return String; + function Image(In_Image : Bit_Vector) return String; + function Image(In_Image : Integer) return String; + function Image(In_Image : Real) return String; + function Image(In_Image : Std_uLogic) return String; + function Image(In_Image : Std_uLogic_Vector) return String; + function Image(In_Image : Std_Logic_Vector) return String; + function Image(In_Image : Signed) return String; + function Image(In_Image : UnSigned) return String; + + function HexImage(InStrg : String) return String; + function HexImage(In_Image : Bit_Vector) return String; + function HexImage(In_Image : Std_uLogic_Vector) return String; + function HexImage(In_Image : Std_Logic_Vector) return String; + function HexImage(In_Image : Signed) return String; + function HexImage(In_Image : UnSigned) return String; + + function DecImage(In_Image : Bit_Vector) return String; + function DecImage(In_Image : Std_uLogic_Vector) return String; + function DecImage(In_Image : Std_Logic_Vector) return String; + function DecImage(In_Image : Signed) return String; + function DecImage(In_Image : UnSigned) return String; +end pkg_image; + +package body pkg_image is + function Image(In_Image : Time) return String is + variable L : Line; -- access type + variable W : String(1 to 14) := (others => ' '); + -- Long enough to hold a time string + begin + -- the WRITE procedure creates an object with "NEW". + -- L is passed as an output of the procedure. + Std.TextIO.WRITE(L, in_image); + -- Copy L.all onto W + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Bit) return String is + variable L : Line; -- access type + variable W : String(1 to 3) := (others => ' '); + begin + Std.TextIO.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Bit_Vector) return String is + variable L : Line; -- access type + variable W : String(1 to In_Image'length) := (others => ' '); + begin + Std.TextIO.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Integer) return String is + variable L : Line; -- access type + variable W : String(1 to 32) := (others => ' '); + -- Long enough to hold a time string + begin + Std.TextIO.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Real) return String is + variable L : Line; -- access type + variable W : String(1 to 32) := (others => ' '); + -- Long enough to hold a time string + begin + Std.TextIO.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Std_uLogic) return String is + variable L : Line; -- access type + variable W : String(1 to 3) := (others => ' '); + begin + IEEE.Std_Logic_Textio.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Std_uLogic_Vector) return String is + variable L : Line; -- access type + variable W : String(1 to In_Image'length) := (others => ' '); + begin + IEEE.Std_Logic_Textio.WRITE(L, in_image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Std_Logic_Vector) return String is + variable L : Line; -- access type + variable W : String(1 to In_Image'length) := (others => ' '); + begin + IEEE.Std_Logic_TextIO.WRITE(L, In_Image); + W(L.all'range) := L.all; + Deallocate(L); + return W; + end Image; + + function Image(In_Image : Signed) return String is + begin + return Image(Std_Logic_Vector(In_Image)); + end Image; + + function Image(In_Image : UnSigned) return String is + begin + return Image(Std_Logic_Vector(In_Image)); + end Image; + + function HexImage(InStrg : String) return String is + subtype Int03_Typ is Integer range 0 to 3; + variable Result : string(1 to ((InStrg'length - 1)/4)+1) := + (others => '0'); + variable StrTo4 : string(1 to Result'length * 4) := + (others => '0'); + variable MTspace : Int03_Typ; -- Empty space to fill in + variable Str4 : String(1 to 4); + variable Group_v : Natural := 0; + begin + MTspace := Result'length * 4 - InStrg'length; + StrTo4(MTspace + 1 to StrTo4'length) := InStrg; -- padded with '0' + Cnvrt_Lbl : for I in Result'range loop + Group_v := Group_v + 4; -- identifies end of bit # in a group of 4 + Str4 := StrTo4(Group_v - 3 to Group_v); -- get next 4 characters + case Str4 is + when "0000" => Result(I) := '0'; + when "0001" => Result(I) := '1'; + when "0010" => Result(I) := '2'; + when "0011" => Result(I) := '3'; + when "0100" => Result(I) := '4'; + when "0101" => Result(I) := '5'; + when "0110" => Result(I) := '6'; + when "0111" => Result(I) := '7'; + when "1000" => Result(I) := '8'; + when "1001" => Result(I) := '9'; + when "1010" => Result(I) := 'A'; + when "1011" => Result(I) := 'B'; + when "1100" => Result(I) := 'C'; + when "1101" => Result(I) := 'D'; + when "1110" => Result(I) := 'E'; + when "1111" => Result(I) := 'F'; + when others => Result(I) := 'X'; + end case; -- Str4 + end loop Cnvrt_Lbl; + + return Result; + end HexImage; + + + function HexImage(In_Image : Bit_Vector) return String is + begin + return HexImage(Image(In_Image)); + end HexImage; + + function HexImage(In_Image : Std_uLogic_Vector) return String is + begin + return HexImage(Image(In_Image)); + end HexImage; + + function HexImage(In_Image : Std_Logic_Vector) return String is + begin + return HexImage(Image(In_Image)); + end HexImage; + + function HexImage(In_Image : Signed) return String is + begin + return HexImage(Image(In_Image)); + end HexImage; + + function HexImage(In_Image : UnSigned) return String is + begin + return HexImage(Image(In_Image)); + end HexImage; + + function DecImage(In_Image : Bit_Vector) return String is + variable In_Image_v : Bit_Vector(In_Image'length downto 1) := In_Image; + begin + if In_Image'length > 31 then + assert False + report "Number too large for Integer, clipping to 31 bits" + severity Warning; + return Image(To_Integer + (Unsigned(To_StdLogicVector + (In_Image_v(31 downto 1))))); + else + return Image(To_Integer(Unsigned(To_StdLogicVector(In_Image)))); + end if; + end DecImage; + + function DecImage(In_Image : Std_uLogic_Vector) return String is + variable In_Image_v : Std_uLogic_Vector(In_Image'length downto 1) + := In_Image; + begin + if In_Image'length > 31 then + assert False + report "Number too large for Integer, clipping to 31 bits" + severity Warning; + return Image(To_Integer(Unsigned(In_Image_v(31 downto 1)))); + else + return Image(To_Integer(Unsigned(In_Image))); + end if; + end DecImage; + + function DecImage(In_Image : Std_Logic_Vector) return String is + variable In_Image_v : Std_Logic_Vector(In_Image'length downto 1) + := In_Image; + begin + if In_Image'length > 31 then + assert False + report "Number too large for Integer, clipping to 31 bits" + severity Warning; + return Image(To_Integer(Unsigned(In_Image_v(31 downto 1)))); + else + return Image(To_Integer(Unsigned(In_Image))); + end if; + end DecImage; + + function DecImage(In_Image : Signed) return String is + variable In_Image_v : Signed(In_Image'length downto 1) := In_Image; + begin + if In_Image'length > 31 then + assert False + report "Number too large for Integer, clipping to 31 bits" + severity Warning; + return Image(To_Integer(In_Image_v(31 downto 1))); + else + return Image(To_Integer(In_Image)); + end if; + end DecImage; + + function DecImage(In_Image : UnSigned) return String is + variable In_Image_v : UnSigned(In_Image'length downto 1) := In_Image; + begin + if In_Image'length > 31 then + assert False + report "Number too large for Integer, clipping to 31 bits" + severity Warning; + return Image(To_Integer(In_Image_v(31 downto 1))); + else + return Image(To_Integer(In_Image)); + end if; + end DecImage; + +end pkg_image; + +-- $Log: not supported by cvs2svn $ +-- Revision 1.1 2003/01/14 17:48:44 Default +-- Initial revision +-- +-- Revision 1.1 2002/12/24 18:07:50 Default +-- Initial revision +-- + + + + + + + + Index: single_port/tags/REL/VHDL/single_port.vhd =================================================================== --- single_port/tags/REL/VHDL/single_port.vhd (nonexistent) +++ single_port/tags/REL/VHDL/single_port.vhd (revision 15) @@ -0,0 +1,131 @@ +-- $Author: rpaley_yid $ +-- $Date: 2003-01-14 21:48:11 $ +-- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/single_port.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $ +-- $Locker +-- $Revision: 1.1.1.1 $ +-- $State: Exp $ + +-- -------------------------------------------------------------------------- +-- +-- Purpose: This is a single port asynchronous memory. This files +-- describes three architectures. Two architectures are traditional +-- array based memories. One describes the memory as an array of +-- STD_LOGIC_VECTOR, and the other describes the ARRAY as BIT_VECTOR. +-- The third architecture describes the memory arranged as a linked +-- list in order to conserve computer memory usage. The memory +-- is organized as a linked list of BIT_VECTOR arrays whose size +-- is defined PAGEDEPTH in single_port_pkg.vhd. +-- +-- +-- References: +-- 1. The Designer's Guide to VHDL by Peter Ashenden +-- ISBN: 1-55860-270-4 (pbk.) +-- 2. Writing Testbenches - Functional Verification of HDL models by +-- Janick Bergeron | ISBN: 0-7923-7766-4 +-- +-- Notes: +-- +-- -------------------------------------------------------------------------- +LIBRARY IEEE; +LIBRARY WORK; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE WORK.single_port_pkg.ALL; +USE WORK.linked_list_mem_pkg.ALL; + +ENTITY single_port IS + GENERIC ( + rnwtQ : TIME := 1 NS + ); + PORT ( + d : IN data_inter_typ; + q : OUT data_inter_typ; + a : IN addr_inter_typ; + rnw : IN STD_LOGIC; + dealloc_mem : IN BOOLEAN + ); +END ENTITY single_port; + +ARCHITECTURE ArrayMemNoFlag OF single_port IS +BEGIN + + mem_proc : PROCESS + TYPE mem_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1) OF data_inter_typ; + VARIABLE mem : mem_typ; + BEGIN + WAIT on rnw'transaction; + IF ( rnw = '0') THEN -- Write + mem(TO_INTEGER(unsigned(a))) := d; + ELSE -- Read + q <= mem(TO_INTEGER(unsigned(a))) AFTER rnwtQ; + END IF; + END PROCESS mem_proc; + +END ArrayMemNoFlag; + +ARCHITECTURE ArrayMem OF single_port IS +BEGIN + + mem_proc : PROCESS + TYPE mem_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF data_typ; + TYPE flag_typ IS ARRAY ( 0 TO PAGENUM*PAGEDEPTH-1 ) OF BOOLEAN; + VARIABLE mem : mem_typ; + VARIABLE flag : flag_typ; + BEGIN + WAIT ON rnw'transaction; + IF ( rnw = '0') THEN -- Write + mem(TO_INTEGER(unsigned(a))) := TO_BITVECTOR(d); + flag(TO_INTEGER(unsigned(a))) := true; -- set valid memory location flag + ELSE -- read data, either valid or 'U' + IF ( flag(TO_INTEGER(unsigned(a))) = true ) THEN + q <= TO_STDLOGICVECTOR(mem(TO_INTEGER(unsigned(a)))) AFTER rnwtQ; + ELSE -- reading invalid memory location + q <= (OTHERS => 'U') after rnwtQ; + END IF; + END IF; + END PROCESS mem_proc; +END ArrayMem; + +ARCHITECTURE LinkedList OF single_port IS + BEGIN + + mem_proc : PROCESS + VARIABLE mem_page_v : mem_page_ptr; + VARIABLE d_v : data_inter_typ; + VARIABLE a_v : addr_typ; + VARIABLE WRITE_MEM_v : BOOLEAN := true; + VARIABLE READ_MEM_v : BOOLEAN := false; + BEGIN + WAIT ON dealloc_mem'transaction , rnw'TRANSACTION; + IF NOT dealloc_mem THEN + d_v := d; + a_v := TO_INTEGER(unsigned(a)); + IF ( rnw = '0' ) THEN -- write to linked list memory + rw_mem( data => d_v, + addr => a_v, + write_flag => WRITE_MEM_v, + next_cell => mem_page_v + ); + ELSE -- read from linked list memory + rw_mem( data => d_v, + addr => a_v, + write_flag => READ_MEM_v, + next_cell => mem_page_v + ); + q <= d_v after rnwtQ; + END IF; + ELSE -- Deallocate memory from work station memory. + deallocate_mem(mem_page_v); + END IF; + END PROCESS mem_proc; + +END LinkedList; + +-- $Log: not supported by cvs2svn $ +-- Revision 1.1 2003/01/14 17:48:31 Default +-- Initial revision +-- +-- Revision 1.1 2002/12/24 18:09:05 Default +-- Initial revision +-- + Index: single_port/tags/REL/VHDL/single_port_pkg.vhd =================================================================== --- single_port/tags/REL/VHDL/single_port_pkg.vhd (nonexistent) +++ single_port/tags/REL/VHDL/single_port_pkg.vhd (revision 15) @@ -0,0 +1,70 @@ +-- $Author: rpaley_yid $ +-- $Date: 2003-01-14 21:48:11 $ +-- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/single_port_pkg.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $ +-- $Locker: $ +-- $Revision: 1.1.1.1 $ +-- $State: Exp $ + +-- -------------------------------------------------------------------------- +-- +-- Purpose: Package file for single_port memory and testbench +-- +-- References: +-- 1. The Designer's Guide to VHDL by Peter Ashenden +-- ISBN: 1-55860-270-4 (pbk.) +-- 2. Writing Testbenches - Functional Verification of HDL models by +-- Janick Bergeron | ISBN: 0-7923-7766-4 +-- +-- Notes: +-- +-- -------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +PACKAGE single_port_pkg IS +CONSTANT PAGEDEPTH : INTEGER := 256; -- memory page depth +CONSTANT PAGENUM : INTEGER := 4096; -- number of pages in memory. +CONSTANT DATA_WIDTH : INTEGER := 32; -- memory data bus width +CONSTANT ADDRESS_WIDTH : INTEGER := 16; -- memory address bus width +-- Data bus type for memory interface +SUBTYPE data_inter_typ IS STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0); +-- Data bus type for internal memory +SUBTYPE data_typ IS BIT_VECTOR(DATA_WIDTH-1 DOWNTO 0); +-- Address bus type for memory interface +SUBTYPE addr_inter_typ IS STD_LOGIC_VECTOR(ADDRESS_WIDTH-1 DOWNTO 0); +-- Address bus type for internal memory +SUBTYPE addr_typ IS NATURAL; +-- Operations testbench can do. +TYPE do_typ IS ( init , read , write , dealloc , end_test ); + +TYPE to_srv_typ IS RECORD -- Record passed from test case to test bench + do : do_typ; + addr : addr_inter_typ; + data : data_inter_typ; + event : BOOLEAN; +END RECORD to_srv_typ; + +TYPE frm_srv_typ IS RECORD -- Record passed from test bench to test case + data : data_inter_typ; + event : BOOLEAN; +END RECORD frm_srv_typ; + + +END PACKAGE single_port_pkg; + +PACKAGE BODY single_port_pkg IS + +END PACKAGE BODY single_port_pkg; + +-- $Log: not supported by cvs2svn $ +-- Revision 1.1 2003/01/14 17:48:44 Default +-- Initial revision +-- +-- Revision 1.1 2002/12/24 17:58:49 Default +-- Initial revision +-- + + + Index: single_port/tags/REL/VHDL/tb_single_port.vhd =================================================================== --- single_port/tags/REL/VHDL/tb_single_port.vhd (nonexistent) +++ single_port/tags/REL/VHDL/tb_single_port.vhd (revision 15) @@ -0,0 +1,191 @@ +-- $Author: rpaley_yid $ +-- $Date: 2003-01-14 21:48:11 $ +-- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/tb_single_port.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $ +-- $Locker +-- $Revision: 1.1.1.1 $ +-- $State: Exp $ + +-- -------------------------------------------------------------------------- +-- +-- Purpose: This file specifies test bench harness for the single_port +-- Memory. It also contains the configuration files for all the +-- tests. +-- +-- +-- References: +-- 1. The Designer's Guide to VHDL by Peter Ashenden +-- ISBN: 1-55860-270-4 (pbk.) +-- 2. Writing Testbenches - Functional Verification of HDL models by +-- Janick Bergeron | ISBN: 0-7923-7766-4 +-- +-- Notes: +-- +-- -------------------------------------------------------------------------- +LIBRARY IEEE; +LIBRARY WORK; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE WORK.linked_list_mem_pkg.ALL; +USE WORK.single_port_pkg.all; +USE STD.TEXTIO.ALL; + +ENTITY tb_single_port IS +END ENTITY tb_single_port; + +ARCHITECTURE BHV of tb_single_port IS + +COMPONENT single_port IS + GENERIC ( + rnwtQ : TIME := 1 NS + ); + PORT ( + d : IN data_inter_typ; + q : OUT data_inter_typ; + a : IN addr_inter_typ; + rnw : IN STD_LOGIC; + dealloc_mem : BOOLEAN +); +END COMPONENT single_port; + +COMPONENT tc_single_port IS + PORT ( + to_srv : OUT to_srv_typ; + frm_srv : IN frm_srv_typ +); +END COMPONENT tc_single_port; + +SIGNAL d : data_inter_typ; +SIGNAL q : data_inter_typ; +SIGNAL a : addr_inter_typ; +SIGNAL rnw : STD_LOGIC; +SIGNAL dealloc_mem : BOOLEAN; +SIGNAL to_srv : to_srv_typ; +SIGNAL frm_srv : frm_srv_typ; +SIGNAL tie_vdd : STD_LOGIC := '1'; +BEGIN + dut : single_port + PORT MAP ( + d => d, + a => a, + q => q, + rnw => rnw, + dealloc_mem => dealloc_mem + ); + + tc : tc_single_port + PORT MAP ( + to_srv => to_srv, + frm_srv => frm_srv + ); + + single_port_server : PROCESS + VARIABLE frm_srv_v : frm_srv_typ; + CONSTANT ACCESS_DELAY : TIME := 5 NS; + BEGIN + -- Wait until the test case is finished setting up the next memory access. + WAIT ON to_srv'TRANSACTION; + CASE to_srv.do IS + WHEN init => + ASSERT FALSE + REPORT "initialized" + SEVERITY NOTE; + WHEN read => -- perform memory read + d <= to_srv.data; + a <= to_srv.addr; + rnw <= '1'; + -- Wait for data to appear + WAIT FOR ACCESS_DELAY; + WHEN write => -- perform memory write + d <= to_srv.data; + a <= to_srv.addr; + rnw <= '0'; + WAIT FOR ACCESS_DELAY; + WHEN dealloc => -- deallocate the linked list for the LL architecture + dealloc_mem <= true; + WHEN end_test => -- reached the end of the test case + WAIT; + END CASE; + frm_srv_v.data := q; + -- Send message to test case to continue the test. + frm_srv <= frm_srv_v ; WAIT FOR 0 NS; + END PROCESS single_port_server; +END BHV; + +CONFIGURATION ll_main_cfg OF TB_SINGLE_PORT IS + FOR BHV + FOR dut : single_port + USE ENTITY work.single_port(LinkedList); + END FOR; -- dut + FOR tc : tc_single_port + USE ENTITY work.tc_single_port(TC0); + END FOR; -- tc; + END FOR; -- BHV +END CONFIGURATION ll_main_cfg; + +CONFIGURATION ll_error_cfg OF TB_SINGLE_PORT IS + FOR BHV + FOR dut : single_port + USE ENTITY work.single_port(LinkedList); + END FOR; -- dut + FOR tc : tc_single_port + USE ENTITY work.tc_single_port(TC1); + END FOR; -- tc; + END FOR; -- BHV +END CONFIGURATION ll_error_cfg ; + +CONFIGURATION mem_main_cfg of TB_SINGLE_PORT IS + FOR BHV + FOR dut : single_port + USE ENTITY work.single_port(ArrayMem); + END FOR; -- dut + FOR tc : tc_single_port + USE ENTITY work.tc_single_port(TC0); + END FOR; -- tc; + END FOR; -- BHV +END CONFIGURATION mem_main_cfg; + +CONFIGURATION mem_error_cfg of TB_SINGLE_PORT IS + FOR BHV + FOR dut : single_port + USE ENTITY work.single_port(ArrayMem); + END FOR; -- dut + FOR tc : tc_single_port + USE ENTITY work.tc_single_port(TC1); + END FOR; -- tc; + END FOR; -- BHV +END CONFIGURATION mem_error_cfg; + +CONFIGURATION memnoflag_main_cfg of TB_SINGLE_PORT IS + FOR BHV + FOR dut : single_port + USE ENTITY work.single_port(ArrayMemNoFlag); + END FOR; -- dut + FOR tc : tc_single_port + USE ENTITY work.tc_single_port(TC0); + END FOR; -- tc; + END FOR; -- BHV +END CONFIGURATION memnoflag_main_cfg; + +CONFIGURATION memnoflag_error_cfg of TB_SINGLE_PORT IS + FOR BHV + FOR dut : single_port + USE ENTITY work.single_port(ArrayMemNoFlag); + END FOR; -- dut + FOR tc : tc_single_port + USE ENTITY work.tc_single_port(TC1); + END FOR; -- tc; + END FOR; -- BHV +END CONFIGURATION memnoflag_error_cfg; + +-- $Log: not supported by cvs2svn $ +-- Revision 1.1 2003/01/14 17:49:04 Default +-- Initial revision +-- +-- Revision 1.2 2002/12/31 19:19:43 Default +-- Updated 'transaction statements for fixed simulator. +-- +-- Revision 1.1 2002/12/24 18:10:18 Default +-- Initial revision +-- + + Index: single_port/tags/REL/VHDL/tc_single_port.vhd =================================================================== --- single_port/tags/REL/VHDL/tc_single_port.vhd (nonexistent) +++ single_port/tags/REL/VHDL/tc_single_port.vhd (revision 15) @@ -0,0 +1,194 @@ +-- $Author: rpaley_yid $ +-- $Date: 2003-01-14 21:48:11 $ +-- $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/tc_single_port.vhd,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $ +-- $Locker +-- $Revision: 1.1.1.1 $ +-- $State: Exp $ + +-- -------------------------------------------------------------------------- +-- +-- Purpose: This file specifies test cases for the single_port +-- Memory. +-- +-- +-- References: +-- 1. The Designer's Guide to VHDL by Peter Ashenden +-- ISBN: 1-55860-270-4 (pbk.) +-- 2. Writing Testbenches - Functional Verification of HDL models by +-- Janick Bergeron | ISBN: 0-7923-7766-4 +-- +-- Notes: +-- +-- -------------------------------------------------------------------------- +LIBRARY IEEE; +LIBRARY WORK; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE WORK.SINGLE_PORT_PKG.ALL; +USE WORK.PKG_IMAGE.ALL; + +ENTITY tc_single_port IS +PORT ( + to_srv : OUT to_srv_typ; + frm_srv : IN frm_srv_typ +); +END ENTITY tc_single_port; + +-- -------------------------------------------------- +-- Test Case TC0 +-- This test case is to check two pages of memory +-- Starting at physical address 0x0 , +-- Write a '1' to bit position 0, leaving all other bits 0. +-- Increment the address, +-- Write a '1' to bit position 1, leaving all other bits 0. +-- Increment the address. +-- Write a '1' to bit position 2, leaving all other bits 0. +-- Continue in this fasion, until write a 1 to the MSB. +-- increment the address, +-- Write a '1' to bit position 0, leaving all other bits 0. +-- Continue until the entire page is written to. +-- Read back all addresses in the page, ensuring the +-- correct data is read back. +-- -------------------------------------------------- + + +ARCHITECTURE TC0 OF tc_single_port IS +BEGIN + MAIN : PROCESS + VARIABLE to_srv_v : to_srv_typ; + VARIABLE frm_srv_v : frm_srv_typ; + VARIABLE dv : data_inter_typ := + STD_LOGIC_VECTOR(TO_UNSIGNED(1,data_inter_typ'length)); + VARIABLE offset_v : INTEGER; + BEGIN + offset_v := 0; + -- Run this write/read test 10 times for benchmark + -- purposes. + for i in 0 to 9 loop + for index in 0 to 2*PAGEDEPTH-1 loop + -- Specify to testbench server to perform write operation; + to_srv_v.do := write; + to_srv_v.data := dv; -- specify data to write + dv := To_StdLogicVector(TO_BitVector(dv) rol 1); -- ROL 1 for next write + -- Specify physical address. + to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(index+offset_v, + ADDRESS_WIDTH)); + to_srv <= to_srv_v ; WAIT FOR 0 NS; + WAIT ON frm_srv'TRANSACTION; + end loop; + -- Reset data to 1. + dv := STD_LOGIC_VECTOR(TO_UNSIGNED(1,data_inter_typ'length)); + for index in 0 to 2*PAGEDEPTH-1 loop + -- Perform read operation. + to_srv_v.do := read; + -- Specify physical address. + to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(index+offset_v, + ADDRESS_WIDTH)); + to_srv <= to_srv_v ; WAIT FOR 0 NS; + WAIT ON frm_srv'TRANSACTION; + -- Compare actual with expected read back data, if the + -- the expected and actual to not compare, print the + -- expected and actual values. + ASSERT frm_srv.data = dv + REPORT "Expected: " & HexImage(frm_srv.data) & + " did not equal Actual: " & HexImage(dv) + SEVERITY ERROR; + -- Set expected data for next read. + dv := TO_STDLOGICVECTOR(TO_BITVECTOR(dv) rol 1); + end loop; + end loop; + to_srv_v.do := dealloc; -- Deallocate memory + -- + to_srv <= to_srv_v ; WAIT FOR 0 NS; + -- Tell test bench server process test completed. + to_srv_v.do := end_test; + to_srv <= to_srv_v; + ASSERT FALSE + REPORT "Completed Test TC0" + SEVERITY NOTE; + WAIT; + END PROCESS main; +END TC0; + +-- -------------------------------------------------- +-- Test Case TC1 +-- This test case is to check if the test bench will +-- return 'U' for invalid memory locations for +-- single_port architectures ArrayMEm and LinkedList +-- -------------------------------------------------- +ARCHITECTURE TC1 OF tc_single_port IS +BEGIN + MAIN : PROCESS + VARIABLE to_srv_v : to_srv_typ; + VARIABLE frm_srv_v : frm_srv_typ; + VARIABLE dv : data_inter_typ := (OTHERS => 'U'); + BEGIN + -- Perform read operation. + to_srv_v.do := read; + -- Specify physical address. + to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(0, + ADDRESS_WIDTH)); + to_srv <= to_srv_v; WAIT FOR 0 NS; + WAIT ON frm_srv'TRANSACTION; + -- Compare actual with expected read back data, if the + -- the expected and actual to not compare, print the + -- expected and actual values. + ASSERT frm_srv.data = dv + REPORT "Expected: " & HexImage(frm_srv.data) & + " did not equal Actual: " & HexImage(dv) + SEVERITY ERROR; + + -- Write and read back from same address. + + -- Specify to testbench server to perform write operation; + to_srv_v.do := write; + dv := X"a5a5a5a5"; + to_srv_v.data := dv; -- specify data to write + -- Specify physical address. + to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(0, + ADDRESS_WIDTH)); + to_srv <= to_srv_v; WAIT FOR 0 NS; + -- Wait until the test bench server finished with the write. + -- WAIT UNTIL frm_srv.event = true; + WAIT ON frm_srv'transaction; + + to_srv_v.do := read; + -- Specify physical address. + to_srv_v.addr := STD_LOGIC_VECTOR(TO_UNSIGNED(0, + ADDRESS_WIDTH)); + to_srv <= to_srv_v; WAIT FOR 0 NS; + WAIT ON frm_srv'transaction; + + -- Compare actual with expected read back data, if the + -- the expected and actual to not compare, print the + -- expected and actual values. + ASSERT frm_srv.data = dv + REPORT "Expected: " & HexImage(frm_srv.data) & + " did not equal Actual: " & HexImage(dv) + SEVERITY ERROR; + + to_srv_v.do := dealloc; -- Deallocate memory + -- + to_srv <= to_srv_v; WAIT FOR 0 NS; + -- Tell test bench server process test completed. + to_srv_v.do := end_test; + to_srv <= to_srv_v; WAIT FOR 0 NS; + + ASSERT FALSE + REPORT "Completed Test TC1" + SEVERITY NOTE; + WAIT; + END PROCESS main; +END TC1; + +-- $Log: not supported by cvs2svn $ +-- Revision 1.1 2003/01/14 17:49:04 Default +-- Initial revision +-- +-- Revision 1.2 2002/12/31 19:19:43 Default +-- Updated 'transaction statements for fixed simulator. +-- +-- Revision 1.1 2002/12/24 18:13:50 Default +-- Initial revision +-- + Index: single_port/tags/REL/VHDL/Makefile =================================================================== --- single_port/tags/REL/VHDL/Makefile (nonexistent) +++ single_port/tags/REL/VHDL/Makefile (revision 15) @@ -0,0 +1,161 @@ +# +# Description: Top level make file for single_port test project. +# make com to compile +# make sim to simulate all tests +# make ll_error to run this test only +# make ll_main to run this test only +# make mem_main to run this test only +# make mem_error to run this test only +# make memnoflag_main to run this test +# make memnoflag_error to run this test +# $Author: rpaley_yid $ +# $Date: 2003-01-14 21:48:11 $ +# $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/Makefile,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $ +# $Locker: $ +# $Revision: 1.1.1.1 $ +# $State: Exp $ + +# VCOM , VSIM , and WORK variables are set for Sonata simulator, +# Change appropriately for your simulator. Ex.for Modeltech, +# VCOM = vcom +# VSIM = vsim +# WORK = work + +SHELL = /bin/sh +VCOM = vhdlp +VCOMOPT = -s +VSIM = vhdle +VSIMOPT = +WORK = work.sym +## Need to figure out how to put Bourne shell stuff in Makefile +## will do so to generate log files in +## LOGDIR = ../LOG/ +## For now, log files are in VHDL directory. + + +# List of main compiled objects, does not include configurations, +# which are included in the tb_single_port.vhd file. +# These targets are for the Sonata simulator, adjust accordingly for +# your simulator. + +SINGLE_PORT_PKG_OBJ = $(WORK)/single_port_pkg/prim.var +LINKED_LIST_MEM_OBJ = $(WORK)/linked_list_mem_pkg/prim.var +PKG_IMAGE_OBJ = $(WORK)/pkg_image/prim.var +SINGLE_PORT_OBJ = $(WORK)/single_port/prim.var +TC_SINGLE_PORT_OBJ = $(WORK)/tc_single_port/prim.var +TB_SINGLE_PORT_OBJ = $(WORK)/tb_single_port/prim.var +LL_ERROR_DEP = $(WORK)/ll_error_cfg/prim.var +LL_MAIN_DEP = $(WORK)/ll_main_cfg/prim.var +MEM_MAIN_DEP = $(WORK)/mem_main_cfg/prim.var +MEM_ERROR_DEP = $(WORK)/mem_error_cfg/prim.var +MEMNOFLAG_MAIN_DEP = $(WORK)/memnoflag_main_cfg/prim.var +MEMNOFLAG_ERROR_DEP = $(WORK)/memnoflag_error_cfg/prim.var + +LL_ERROR = $(LOGDIR)ll_error.log +LL_MAIN = ll_main.log +MEM_MAIN = mem_main.log +MEM_ERROR = mem_error.log +MEMNOFLAG_MAIN = memnoflag_main.log +MEMNOFLAG_ERROR = memnoflag_error.log + +OBJS = $(SINGLE_PORT_PKG_OBJ) \ + $(LINKED_LIST_MEM_OBJ) \ + $(PKG_IMAGE_OBJ) \ + $(SINGLE_PORT_OBJ) \ + $(TC_SINGLE_PORT_OBJ) \ + $(TB_SINGLE_PORT_OBJ) + +SIMOBJS = $(LL_ERROR) \ + $(LL_MAIN) \ + $(MEM_MAIN) \ + $(MEM_ERROR) \ + $(MEMNOFLAG_MAIN) \ + $(MEMNOFLAG_ERROR) + +# Compile the project +com: $(OBJS) + +# Clean the library +clean:: $(WORK) + +# Simulate all tests +sim: $(SIMOBJS) + +## Run only ll_error test +ll_error: $(LL_ERROR) + +# Run onle ll_main test +ll_main: $(LL_MAIN) + +# Run only mem_main test +mem_main: $(MEM_MAIN) + +# Run only mem_error test +mem_error: $(MEM_ERROR) + +# Run only memnoflag_main test +memnoflag_main: $(MEMNOFLAG_MAIN) + +# Run only memnoflag_error test +memnoflag_error: $(MEMNOFLAG_ERROR) + +# Target dependency rules to run tests +$(LL_ERROR) : $(LL_ERROR_DEP) + $(VSIM) $(VSIMOPT) ll_error_cfg | tee $@ + +$(LL_MAIN) : $(LL_MAIN_DEP) + $(VSIM) $(VSIMOPT) ll_main_cfg | tee $@ + +$(MEM_MAIN) : $(MEM_MAIN_DEP) + $(VSIM) $(VSIMOPT) mem_main_cfg | tee $@ + +$(MEM_ERROR) : $(MEM_ERROR_DEP) + $(VSIM) $(VSIMOPT) mem_error_cfg | tee $@ + +$(MEMNOFLAG_MAIN) : $(MEMNOFLAG_MAIN_DEP) + $(VSIM) $(VSIMOPT) memnoflag_main_cfg | tee $@ + +$(MEMNOFLAG_ERROR) : $(MEMNOFLAG_ERROR_DEP) + $(VSIM) $(VSIMOPT) memnoflag_error_cfg | tee $@ + +# Target dependency rules to compile tests + +$(SINGLE_PORT_PKG_OBJ) : single_port_pkg.vhd + $(VCOM) $(VCOMOPT) $< + +$(LINKED_LIST_MEM_OBJ) : linked_list_mem_pkg.vhd \ + $(SINGLE_PORT_PKG_OBJ) + $(VCOM) $(VCOMOPT) $< + +$(PKG_IMAGE_OBJ) : pkg_image.vhd + $(VCOM) $(VCOMOPT) $< + +$(SINGLE_PORT_OBJ) : single_port.vhd \ + $(SINGLE_PORT_PKG_OBJ) \ + $(LINKED_LIST_MEM_OBJ) + $(VCOM) $(VCOMOPT) $< + +$(TC_SINGLE_PORT_OBJ) : tc_single_port.vhd \ + $(SINGLE_PORT_PKG_OBJ) \ + $(PKG_IMAGE_OBJ) \ + $(SINGLE_PORT_OBJ) + $(VCOM) $(VCOMOPT) $< + +$(TB_SINGLE_PORT_OBJ) : tb_single_port.vhd \ + $(SINGLE_PORT_PKG_OBJ) \ + $(LINKED_LIST_MEM_OBJ) \ + $(SINGLE_PORT_OBJ) \ + $(TC_SINGLE_PORT_OBJ) + $(VCOM) $(VCOMOPT) $< + +$(WORK) :: + rm -rf $(WORK)/* + + +#################################################################### +# $Log: not supported by cvs2svn $ +# Revision 1.1 2002/12/31 19:21:59 Default +# Initial revision +# +# + Index: single_port/tags =================================================================== --- single_port/tags (nonexistent) +++ single_port/tags (revision 15)

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