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URL https://opencores.org/ocsvn/socwire/socwire/trunk

Subversion Repositories socwire

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Rev 14 → Rev 15

/socwire/trunk/CODEC/dp_ram.vhd
0,0 → 1,150
 
---====================== Start Copyright Notice ========================---
--== ==--
--== Filename ..... dp_ram.vhd ==--
--== Download ..... http://www.ida.ing.tu-bs.de ==--
--== Company ...... IDA TU Braunschweig, Prof. Dr.-Ing. Harald Michalik ==--
 
 
--== Copyright .... Copyright (c) 2008 IDA ==--
--== Project ...... SoCWire CODEC ==--
--== Version ...... 1.00 ==--
--== Conception ... 11 November 2008 ==--
--== Modified ..... N/A ==--
--== ==--
---======================= End Copyright Notice =========================---
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
 
LIBRARY UNISIM;
USE UNISIM.ALL;
 
 
ENTITY dp_ram IS
GENERIC( datawidth : NATURAL RANGE 8 TO 8192);
PORT(
--== General Interface ==--
 
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
 
--== Write Interface ==--
 
wr_en : IN STD_LOGIC;
wr_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_din : IN STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
--== Read Interface ==--
 
rd_en : IN STD_LOGIC;
rd_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_dout : OUT STD_LOGIC_VECTOR(datawidth DOWNTO 0)
);
END dp_ram;
 
 
ARCHITECTURE rtl OF dp_ram IS
 
---==========================---
--== Component Declarations ==--
---==========================---
 
COMPONENT RAMB16_S18_S18
port (
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0);
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
CLKA : in STD_LOGIC;
CLKB : in STD_LOGIC;
DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in STD_LOGIC;
ENB : in STD_LOGIC;
SSRA : in STD_LOGIC;
SSRB : in STD_LOGIC;
WEA : in STD_LOGIC;
WEB : in STD_LOGIC
);
END COMPONENT;
 
---=======================---
--== Signal Declarations ==--
---=======================---
 
SIGNAL logic_0 : STD_LOGIC;
SIGNAL logic_1 : STD_LOGIC;
SIGNAL logic_0_bus : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL addra_i : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL addrb_i : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL logic_00 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL ramin : STD_LOGIC_VECTOR(((datawidth / 16) + 1)*16-1 DOWNTO 0) := (others => '0');
SIGNAL ramout : STD_LOGIC_VECTOR(((datawidth / 16) + 1)*16-1 DOWNTO 0) := (others => '0');
SIGNAL ENA : STD_LOGIC;
SIGNAL ENB : STD_LOGIC;
SIGNAL rst_buf : STD_LOGIC;
BEGIN
 
---===================---
--== Tie-Off Signals ==--
---===================---
 
logic_0 <= '0';
logic_1 <= '1';
logic_0_bus <= (OTHERS => '0');
logic_00 <= (OTHERS => '0');
 
---=================---
--== Dual Port RAM ==--
---=================---
 
addra_i <= wr_addr;
addrb_i <= rd_addr;
ena <= wr_en;
enb <= rd_en OR rst;
 
 
G0 : FOR a IN 0 TO (datawidth) GENERATE
ramin(a) <= wr_din(a);
END GENERATE G0;
G1 : FOR b IN 0 TO (datawidth) GENERATE
rd_dout(b) <= ramout(b);
END GENERATE G1;
G2 : FOR i IN 0 TO (datawidth / 16) GENERATE
U0 : RAMB16_S18_S18
port map(
DOA => OPEN, -- Port A 16-bit Data Output
DOB => ramout((i+1)*16-1 DOWNTO i*16), -- Port B 16-bit Data Output
DOPA => OPEN, -- Port A 2-bit Parity Output
DOPB => OPEN, -- Port B 2-bit Parity Output
ADDRA => addra_i, -- Port A 10-bit Address Input
ADDRB => addrb_i, -- Port B 10-bit Address Input
CLKA => clk, -- Port A Clock
CLKB => clk, -- Port B Clock
DIA => ramin((i+1)*16-1 DOWNTO i*16), -- Port A 16-bit Data Input
DIB => logic_0_bus, -- Port B 16-bit Data Input
DIPA => logic_00, -- Port A 2-bit parity Input
DIPB => logic_00, -- Port-B 2-bit parity Input
ENA => ena, -- Port A RAM Enable Input
ENB => enb, -- PortB RAM Enable Input
SSRA => rst, -- Port A Synchronous Set/Reset Input
SSRB => rst, -- Port B Synchronous Set/Reset Input
WEA => logic_1, -- Port A Write Enable Input
WEB => logic_0 -- Port B Write Enable Input
);
 
END GENERATE G2;
 
END rtl;
 
 
 
 
/socwire/trunk/CODEC/receiver.vhd
0,0 → 1,312
---====================== Start Software License ========================---
--== ==--
--== This license governs the use of this software, and your use of ==--
--== this software constitutes acceptance of this license. Agreement ==--
--== with all points is required to use this software. ==--
--== ==--
--== 1. This source file may be used and distributed without ==--
--== restriction provided that this software license statement is not ==--
--== removed from the file and that any derivative work contains the ==--
--== original software license notice and the associated disclaimer. ==--
--== ==--
--== 2. This source file is free software; you can redistribute it ==--
--== and/or modify it under the restriction that UNDER NO CIRCUMTANCES ==--
--== this Software is to be used to CONSTRUCT a SPACEWIRE INTERFACE ==--
--== This implies modification and/or derivative work of this Software. ==--
--== ==--
--== 3. This source is distributed in the hope that it will be useful, ==--
--== but WITHOUT ANY WARRANTY; without even the implied warranty of ==--
--== MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ==--
--== ==--
--== Your rights under this license are terminated immediately if you ==--
--== breach it in any way. ==--
--== ==--
---======================= End Software License =========================---
 
 
---====================== Start Copyright Notice ========================---
--== ==--
--== Filename ..... receiver.vhd ==--
--== Download ..... http://www.ida.ing.tu-bs.de ==--
--== Company ...... IDA TU Braunschweig, Prof. Dr.-Ing. Harald Michalik ==--
 
 
--== Copyright .... Copyright (c) 2008 IDA ==--
--== Project ...... SoCWire CODEC ==--
--== Version ...... 1.00 ==--
--== Conception ... 11 November 2008 ==--
--== Modified ..... N/A ==--
--== ==--
---======================= End Copyright Notice =========================---
 
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.ALL;
 
 
ENTITY receiver IS
GENERIC(
 
datawidth : NATURAL RANGE 8 TO 8192;
speed : NATURAL RANGE 1 TO 100;
disconnect_detection : NATURAL RANGE 1 TO 850
);
PORT(
--== General Interface (Sync Rst, 50MHz Clock) ==--
 
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
 
--== SoCWire Interface ==--
 
state : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
 
--== External Receive Interface ==--
 
rx : IN STD_LOGIC_VECTOR(datawidth+1 DOWNTO 0);
rx_valid : IN STD_LOGIC;
 
--== Character Interface ==--
 
got_null : OUT STD_LOGIC;
got_fct : OUT STD_LOGIC;
got_nchar : OUT STD_LOGIC;
 
--== Error Interface ==--
 
err_par : OUT STD_LOGIC;
err_esc : OUT STD_LOGIC;
err_dsc : OUT STD_LOGIC;
err_fct : OUT STD_LOGIC;
err_nchar : OUT STD_LOGIC;
 
--== Data Output Interface ==--
 
dat_nread : IN STD_LOGIC;
dat_empty : OUT STD_LOGIC;
dat_dout : OUT STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
--== FCT Output Interface ==--
 
fct_nread : IN STD_LOGIC;
fct_empty : OUT STD_LOGIC
);
END receiver;
 
 
ARCHITECTURE rtl OF receiver IS
 
---==========================---
--== Constants Declarations ==--
---==========================---
 
CONSTANT st_error_reset : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
CONSTANT st_error_wait : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
CONSTANT st_ready : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010";
CONSTANT st_started : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011";
CONSTANT st_connecting : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100";
CONSTANT st_run : STD_LOGIC_VECTOR(2 DOWNTO 0) := "101";
CONSTANT st_unknown_1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "110";
CONSTANT st_unknown_2 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "111";
CONSTANT zeros : STD_LOGIC_VECTOR(datawidth+1 downto 9) := (others => '0');
 
 
---=======================---
--== Signal Declarations ==--
---=======================---
 
SIGNAL rx_rst : STD_LOGIC;
SIGNAL dsc_count_d : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL dsc_count : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL bit_array : STD_LOGIC_VECTOR(datawidth+1 DOWNTO 0);
SIGNAL got_char : STD_LOGIC;
SIGNAL got_null_d : STD_LOGIC;
SIGNAL got_fct_d : STD_LOGIC;
SIGNAL got_eop_d : STD_LOGIC;
SIGNAL got_esc_d : STD_LOGIC;
SIGNAL got_data_d : STD_LOGIC;
SIGNAL got_nchar_d : STD_LOGIC;
SIGNAL err_par_d : STD_LOGIC;
SIGNAL err_esc_d : STD_LOGIC;
SIGNAL par_ok : STD_LOGIC;
SIGNAL got_null_i : STD_LOGIC;
SIGNAL got_esc_dd : STD_LOGIC;
SIGNAL got_esc : STD_LOGIC;
SIGNAL dat_empty_d : STD_LOGIC;
SIGNAL dat_empty_i : STD_LOGIC;
SIGNAL fct_empty_d : STD_LOGIC;
SIGNAL fct_empty_i : STD_LOGIC;
SIGNAL err_dsc_d : STD_LOGIC;
SIGNAL dat_dout_d : STD_LOGIC_VECTOR(datawidth DOWNTO 0);
SIGNAL x : STD_LOGIC;
 
 
 
BEGIN
 
---======================================================---
--== Generate Tx Reset Signal to hold Receiver in Reset ==--
---======================================================---
 
rx_rst <= '1' WHEN (rst = '1') OR (state = st_error_reset) ELSE '0';
 
---=====================---
--== Synchronous Logic ==--
---=====================---
 
PROCESS (clk)
VARIABLE par_temp : STD_LOGIC;
BEGIN
IF RISING_EDGE(clk) THEN
IF rx_rst = '0' THEN
par_temp := '0';
FOR i IN 2 TO datawidth+1 LOOP
par_temp := par_temp XOR bit_array(i);
END LOOP;
par_ok <= rx(0) XOR rx(1) XOR par_temp;
err_dsc <= err_dsc_d;
dsc_count <= dsc_count_d;
bit_array <= rx;
dat_dout <= dat_dout_d;
dat_empty_i <= dat_empty_d;
fct_empty_i <= fct_empty_d;
got_esc <= got_esc_dd;
err_par <= err_par_d;
err_esc <= err_esc_d;
got_fct <= got_fct_d;
got_nchar <= got_nchar_d;
ELSE
par_ok <= '0';
par_temp := '0';
err_dsc <= '0';
dsc_count <= (others => '0');
bit_array <= zeros & "000000001";
dat_dout <= (others => '0');
fct_empty_i <= '1';
dat_empty_i <= '1';
got_esc <= '0';
err_par <= '0';
err_esc <= '0';
got_fct <= '0';
got_nchar <= '0';
END IF;
END IF;
END PROCESS;
---===========================---
--== Rx Disconnect Detection ==--
---===========================---
 
err_dsc_d <= '1' WHEN (dsc_count = disconnect_detection / speed) ELSE '0';
PROCESS(rx_valid, dsc_count)
BEGIN
IF (rx_valid = '1') THEN
dsc_count_d <= "0000000001";
ELSIF (dsc_count /= "0000000000") THEN
dsc_count_d <= dsc_count + 1;
ELSE
dsc_count_d <= dsc_count; -- could be all 0's, if so add it to reset!!
END IF;
END PROCESS;
 
---===============================---
--== Rx Character Identification ==--
---===============================---
 
got_char <= '1' WHEN (rx_valid = '1') AND (rx /= zeros & "000101110")
AND (got_null_i = '1') ELSE '0';
 
got_null_d <= '1' WHEN (rx_valid = '1') AND (rx(9 downto 1) = "000010111") AND (rx(datawidth+1 downto 9) = zeros)
AND (par_ok = '1') ELSE '0';
 
got_fct_d <= '1' WHEN (got_char = '1') AND
(got_esc = '0') AND
(rx(9 downto 1) = "000000001") AND (rx(datawidth+1 downto 9) = zeros)
AND (par_ok = '1') ELSE '0';
 
got_eop_d <= '1' WHEN (got_char = '1') AND (rx(datawidth+1 downto 9) = zeros) AND
(got_esc = '0') AND
((rx(9 downto 1) = "000000011") OR
(rx(9 downto 1) = "000000101")) AND
(par_ok = '1') ELSE '0';
 
got_esc_d <= '1' WHEN (got_char = '1') AND (rx(datawidth+1 downto 9) = zeros) AND
(rx(9 downto 1) = "000000111") AND
(par_ok = '1') ELSE '0';
 
got_data_d <= '1' WHEN (got_char = '1') AND
(rx(1) = '0') AND
(got_esc = '0') AND
(par_ok = '1') ELSE '0';
 
err_esc_d <= got_esc AND got_char AND ((rx(3) OR rx(2)) AND rx(1));
 
err_par_d <= NOT par_ok AND rx_valid;
 
got_nchar_d <= got_eop_d OR got_data_d;
got_nchar_d <= got_eop_d OR got_data_d;
x <= got_null_d NOR got_null_i;
got_null_i <= rx_rst NOR x;
PROCESS(rx_valid, got_esc_d, got_char, got_esc)
BEGIN
IF (rx_valid = '1') AND (got_esc_d = '1') THEN
got_esc_dd <= '1';
ELSIF (got_char = '1') THEN
got_esc_dd <= '0';
ELSE
got_esc_dd <= got_esc;
END IF;
END PROCESS;
 
fct_empty_d <= NOT(got_fct_d);
dat_empty_d <= NOT(got_nchar_d);
 
PROCESS(rx, got_eop_d)
BEGIN
IF(got_eop_d = '1') THEN
dat_dout_d(datawidth) <= '1';
dat_dout_d(datawidth-1 downto 1) <= (others => '0');
dat_dout_d(0) <= rx(2);
ELSE
dat_dout_d(datawidth) <= '0';
FOR i IN 0 TO datawidth-1 LOOP
dat_dout_d(i) <= rx(i+2);
END LOOP;
END IF;
END PROCESS;
 
 
---===============================================---
--== Generate error for too much data comming in ==--
---===============================================---
 
err_nchar <= NOT(dat_empty_i) AND dat_nread;
 
 
---================================================---
--== Generate error for too many FCT's comming in ==--
---================================================---
 
err_fct <= NOT(fct_empty_i) AND fct_nread;
 
 
---======================================---
--== Shared Internal & External Signals ==--
---======================================---
 
got_null <= got_null_i;
dat_empty <= dat_empty_i;
fct_empty <= fct_empty_i;
 
END rtl;
/socwire/trunk/CODEC/state_machine.vhd
0,0 → 1,259
---====================== Start Software License ========================---
--== ==--
--== This license governs the use of this software, and your use of ==--
--== this software constitutes acceptance of this license. Agreement ==--
--== with all points is required to use this software. ==--
--== ==--
--== 1. This source file may be used and distributed without ==--
--== restriction provided that this software license statement is not ==--
--== removed from the file and that any derivative work contains the ==--
--== original software license notice and the associated disclaimer. ==--
--== ==--
--== 2. This source file is free software; you can redistribute it ==--
--== and/or modify it under the restriction that UNDER NO CIRCUMTANCES ==--
--== this Software is to be used to CONSTRUCT a SPACEWIRE INTERFACE ==--
--== This implies modification and/or derivative work of this Software. ==--
--== ==--
--== 3. This source is distributed in the hope that it will be useful, ==--
--== but WITHOUT ANY WARRANTY; without even the implied warranty of ==--
--== MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ==--
--== ==--
--== Your rights under this license are terminated immediately if you ==--
--== breach it in any way. ==--
--== ==--
---======================= End Software License =========================---
 
 
---====================== Start Copyright Notice ========================---
--== ==--
--== Filename ..... state_machine.vhd ==--
--== Download ..... http://www.ida.ing.tu-bs.de ==--
--== Company ...... IDA TU Braunschweig, Prof. Dr.-Ing. Harald Michalik ==--
 
 
--== Copyright .... Copyright (c) 2008 IDA ==--
--== Project ...... SoCWire CODEC ==--
--== Version ...... 1.00 ==--
--== Conception ... 11 November 2008 ==--
--== Modified ..... N/A ==--
--== ==--
---======================= End Copyright Notice =========================---
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.ALL;
 
 
ENTITY state_machine IS
GENERIC(
speed : NATURAL RANGE 1 TO 100;
after64 : NATURAL RANGE 1 TO 6400;
after128 : NATURAL RANGE 1 TO 12800
);
PORT(
--== General Interface (Sync Rst, 50MHz Clock) ==--
 
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
 
--== Link Enable Interface ==--
 
socw_en : IN STD_LOGIC;
socw_dis : IN STD_LOGIC;
 
--== SoCWire Interface ==--
 
state : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
 
--== Character Interface ==--
 
got_null : IN STD_LOGIC;
got_fct : IN STD_LOGIC;
got_nchar : IN STD_LOGIC;
 
--== Error Interface ==--
 
err_par : IN STD_LOGIC;
err_esc : IN STD_LOGIC;
err_dsc : IN STD_LOGIC;
err_fct : IN STD_LOGIC;
err_nchar : IN STD_LOGIC;
 
--== Active Interface ==--
 
active : OUT STD_LOGIC
);
END state_machine;
 
 
ARCHITECTURE rtl OF state_machine IS
 
---==========================---
--== Constants Declarations ==--
---==========================---
 
CONSTANT st_error_reset : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
CONSTANT st_error_wait : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
CONSTANT st_ready : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010";
CONSTANT st_started : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011";
CONSTANT st_connecting : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100";
CONSTANT st_run : STD_LOGIC_VECTOR(2 DOWNTO 0) := "101";
CONSTANT st_unknown_1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "110";
CONSTANT st_unknown_2 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "111";
 
---=======================---
--== Signal Declarations ==--
---=======================---
 
SIGNAL state_i : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL state_d : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL watchdog_r : STD_LOGIC;
SIGNAL watchdog_d : STD_LOGIC_VECTOR(13 DOWNTO 0);
SIGNAL watchdog : STD_LOGIC_VECTOR(13 DOWNTO 0);
 
 
BEGIN
 
---=====================---
--== Synchronous Logic ==--
---=====================---
 
PROCESS (clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst = '0' THEN
state_i <= state_d;
watchdog <= watchdog_d;
ELSE
state_i <= (others => '0');
watchdog <= (others => '0');
END IF;
END IF;
END PROCESS;
---===========================---
--== SoCWire State Machine ==--
---===========================---
 
PROCESS(state_i, watchdog, got_fct, got_nchar, err_par, err_esc, err_dsc, err_fct, err_nchar, socw_en, got_null, socw_dis)
BEGIN
CASE state_i IS
 
WHEN st_error_reset =>
 
IF (watchdog = after64 / speed - 1) THEN -- 6.4us Passed
state_d <= st_error_wait;
watchdog_r <= '1';
ELSE
state_d <= st_error_reset;
watchdog_r <= '0';
END IF;
 
WHEN st_error_wait =>
 
IF (got_fct = '1') OR (got_nchar = '1') OR
(err_par = '1') OR (err_esc = '1') OR (err_dsc = '1') THEN
state_d <= st_error_reset;
watchdog_r <= '1';
ELSIF (watchdog = after128 / speed - 1) THEN -- 12.8us Passed
state_d <= st_ready;
watchdog_r <= '0';
ELSE
state_d <= st_error_wait;
watchdog_r <= '0';
END IF;
 
WHEN st_ready =>
 
IF (got_fct = '1') OR (got_nchar = '1') OR
(err_par = '1') OR (err_esc = '1') OR (err_dsc = '1') THEN
state_d <= st_error_reset;
watchdog_r <= '1';
ELSIF (socw_en = '1') THEN
state_d <= st_started;
watchdog_r <= '1';
ELSE
state_d <= st_ready;
watchdog_r <= '0';
END IF;
 
WHEN st_started =>
 
IF (got_nchar = '1') OR
(err_par = '1') OR (err_esc = '1') OR (err_dsc = '1') THEN
state_d <= st_error_reset;
watchdog_r <= '1';
ELSIF (watchdog = after128 / speed - 1) THEN -- 12.8us Passed
state_d <= st_error_reset;
watchdog_r <= '1';
ELSIF (got_null = '1') THEN
state_d <= st_connecting;
watchdog_r <= '1';
ELSE
state_d <= st_started;
watchdog_r <= '0';
END IF;
 
WHEN st_connecting =>
 
IF (got_nchar = '1') OR
(err_par = '1') OR (err_esc = '1') OR (err_dsc = '1') THEN
state_d <= st_error_reset;
watchdog_r <= '1';
ELSIF (watchdog = after128 / speed - 1) THEN -- 12.8us Passed
state_d <= st_error_reset;
watchdog_r <= '1';
ELSIF (got_fct = '1') THEN
state_d <= st_run;
watchdog_r <= '1';
ELSE
state_d <= st_connecting;
watchdog_r <= '0';
END IF;
 
WHEN st_run =>
 
IF (err_fct = '1') OR (err_nchar = '1') OR
(err_par = '1') OR (err_esc = '1') OR
(err_dsc = '1') OR (socw_dis = '1') THEN
state_d <= st_error_reset;
watchdog_r <= '1';
ELSE
state_d <= st_run;
watchdog_r <= '0';
END IF;
 
WHEN OTHERS =>
state_d <= st_error_reset;
watchdog_r <= '1';
 
END CASE;
 
END PROCESS;
 
 
---====================---
--== Watchdog Counter ==--
---====================---
 
PROCESS(watchdog_r, watchdog, state_i)
BEGIN
IF (watchdog_r = '1') OR (state_i = st_run) OR (state_i = st_ready) THEN
watchdog_d <= (others => '0');
ELSE
watchdog_d <= watchdog + 1;
END IF;
END PROCESS;
 
 
---======================================---
--== Shared Internal & External Signals ==--
---======================================---
 
state <= state_i;
 
active <= '1' WHEN (state_i = st_Run) ELSE '0';
 
END rtl;
/socwire/trunk/CODEC/transmit_fifo.vhd
0,0 → 1,326
---====================== Start Software License ========================---
--== ==--
--== This license governs the use of this software, and your use of ==--
--== this software constitutes acceptance of this license. Agreement ==--
--== with all points is required to use this software. ==--
--== ==--
--== 1. This source file may be used and distributed without ==--
--== restriction provided that this software license statement is not ==--
--== removed from the file and that any derivative work contains the ==--
--== original software license notice and the associated disclaimer. ==--
--== ==--
--== 2. This source file is free software; you can redistribute it ==--
--== and/or modify it under the restriction that UNDER NO CIRCUMTANCES ==--
--== this Software is to be used to CONSTRUCT a SPACEWIRE INTERFACE ==--
--== This implies modification and/or derivative work of this Software. ==--
--== ==--
--== 3. This source is distributed in the hope that it will be useful, ==--
--== but WITHOUT ANY WARRANTY; without even the implied warranty of ==--
--== MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ==--
--== ==--
--== Your rights under this license are terminated immediately if you ==--
--== breach it in any way. ==--
--== ==--
---======================= End Software License =========================---
 
 
---====================== Start Copyright Notice ========================---
--== ==--
--== Filename ..... transmit_fifo.vhd ==--
--== Download ..... http://www.ida.ing.tu-bs.de ==--
--== Company ...... IDA TU Braunschweig, Prof. Dr.-Ing. Harald Michalik ==--
 
 
--== Copyright .... Copyright (c) 2008 IDA ==--
--== Project ...... SoCWire CODEC ==--
--== Version ...... 1.00 ==--
--== Conception ... 11 November 2008 ==--
--== Modified ..... N/A ==--
--== ==--
---======================= End Copyright Notice =========================---
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.ALL;
 
 
ENTITY transmit_fifo IS
GENERIC(
 
datawidth : NATURAL RANGE 8 TO 8192
);
PORT(
--== General Interface (Sync Rst, 50MHz Clock) ==--
 
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
 
--== SoCWire Interface ==--
 
state : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
 
--== Data Input Interface ==--
 
dat_full : OUT STD_LOGIC;
dat_nwrite : IN STD_LOGIC;
dat_din : IN STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
--== Data Output Interface ==--
 
dat_nread : IN STD_LOGIC;
dat_empty : OUT STD_LOGIC;
dat_dout : OUT STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
--== FCT Input Interface ==--
 
fct_full : OUT STD_LOGIC;
fct_nwrite : IN STD_LOGIC
);
END transmit_fifo;
 
 
 
ARCHITECTURE rtl OF transmit_fifo IS
 
---==========================---
--== Constants Declarations ==--
---==========================---
 
CONSTANT st_error_reset : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
CONSTANT st_error_wait : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
CONSTANT st_ready : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010";
CONSTANT st_started : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011";
CONSTANT st_connecting : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100";
CONSTANT st_run : STD_LOGIC_VECTOR(2 DOWNTO 0) := "101";
CONSTANT st_unknown_1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "110";
CONSTANT st_unknown_2 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "111";
 
---=======================---
--== Signal Declarations ==--
---=======================---
 
SIGNAL rst_fct : STD_LOGIC;
SIGNAL fct_full_d : STD_LOGIC;
SIGNAL fct_full_i : STD_LOGIC;
SIGNAL fct_en : STD_LOGIC;
SIGNAL dat_en : STD_LOGIC;
SIGNAL dat2_en : STD_LOGIC;
SIGNAL credit : STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
SIGNAL credit_d : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL credit_e : STD_LOGIC;
SIGNAL dat_full_d : STD_LOGIC;
SIGNAL dat_full_i : STD_LOGIC;
SIGNAL dat_empty_d : STD_LOGIC;
SIGNAL dat_empty_i : STD_LOGIC;
SIGNAL store_e : STD_LOGIC;
SIGNAL store : STD_LOGIC_VECTOR(datawidth DOWNTO 0);
SIGNAL got_eop : STD_LOGIC;
SIGNAL swallow_d : STD_LOGIC;
SIGNAL swallow : STD_LOGIC;
SIGNAL dat_dout_e : STD_LOGIC;
SIGNAL dat_dout_d : STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
 
BEGIN
 
---============================================---
--== Reset for non-Connecting & non-Run logic ==--
---============================================---
 
rst_fct <= '1' WHEN (rst = '1') OR NOT((state = st_connecting) OR (state = st_run)) ELSE '0';
 
---=====================---
--== Synchronous Logic ==--
---=====================---
 
PROCESS (clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_fct = '0' THEN
fct_full_i <= fct_full_d;
IF credit_e = '1' THEN
credit <= credit_d;
END IF;
ELSE
credit <= (others => '0');
fct_full_i <= '1';
END IF;
IF rst = '0' THEN
swallow <= swallow_d;
dat_full_i <= dat_full_d;
dat_empty_i <= dat_empty_d;
IF dat2_en = '1' THEN
got_eop <= dat_din(datawidth);
END IF;
IF store_e = '1' THEN
store <= dat_din;
END IF;
IF dat_dout_e = '1' THEN
dat_dout <= dat_dout_d;
END IF;
ELSE
got_eop <= '1';
swallow <= '1';
dat_full_i <= '1';
dat_empty_i <= '1';
store <= (others => '0');
dat_dout <= (others => '0');
END IF;
END IF;
END PROCESS;
 
---====================---
--== FCT Write Enable ==--
---====================---
 
fct_en <= NOT(fct_full_i) AND NOT(fct_nwrite);
 
 
---========================---
--== Data Out Read Enable ==--
---========================---
 
dat_en <= NOT(dat_empty_i) AND NOT(dat_nread);
 
 
---========================---
--== Data In Write Enable ==--
---========================---
 
dat2_en <= NOT(dat_full_i) AND NOT(dat_nwrite);
 
 
---===========================---
--== Transmit Credit Counter ==--
---===========================---
 
PROCESS(fct_en, dat_en, credit)
VARIABLE tmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
tmp := fct_en & dat_en;
CASE tmp IS
WHEN "11" => credit_d <= credit + 7;
WHEN "10" => credit_d <= credit + 8;
WHEN "01" => credit_d <= credit - 1;
WHEN OTHERS => credit_d <= credit;
END CASE;
END PROCESS;
 
credit_e <= fct_en OR dat_en;
 
---=======================---
--== FCT Handshake Logic ==--
---=======================---
 
PROCESS(credit, fct_en)
BEGIN
IF (credit <= '1' & NOT(fct_en) & fct_en & "000") THEN
fct_full_d <= '0';
ELSE
fct_full_d <= '1';
END IF;
END PROCESS;
 
 
---========================---
--== Packet swallow logic ==--
---========================---
 
PROCESS(state, swallow, dat_full_i, dat_nwrite, dat_din, got_eop)
BEGIN
IF (state /= st_Run) THEN
swallow_d <= '1';
ELSE
IF (swallow = '1') THEN
IF ((dat_full_i = '0') AND (dat_nwrite = '0') AND (dat_din(datawidth) = '1')) OR (got_eop = '1') THEN
swallow_d <= '0';
ELSE
swallow_d <= '1';
END IF;
ELSE
swallow_d <= '0';
END IF;
END IF;
END PROCESS;
 
 
---========================---
--== FIFO full flag logic ==--
---========================---
 
PROCESS(state, swallow, got_eop, dat_full_i, dat_nwrite, dat_din, credit, dat_en, dat_empty_i, dat_nread)
BEGIN
IF (state /= st_Run) THEN
dat_full_d <= '0';
ELSE
IF (swallow = '1') THEN
IF (got_eop = '1') AND (dat_full_i = '0') AND (dat_nwrite = '0') AND (dat_din(datawidth) = '0') THEN
dat_full_d <= '1';
ELSE
dat_full_d <= '0';
END IF;
ELSE
IF (credit(5 DOWNTO 1) = "000000") AND ((credit(0) = '0') OR (dat_en = '1')) THEN
dat_full_d <= dat_full_i OR NOT(dat_nwrite);
ELSE
dat_full_d <= NOT(dat_empty_i) AND dat_nread AND (dat_full_i OR NOT(dat_nwrite));
END IF;
END IF;
END IF;
END PROCESS;
 
 
---=========================---
--== FIFO empty flag logic ==--
---=========================---
 
PROCESS(state, swallow, credit, dat_en, dat_full_i, dat_nwrite, dat_empty_i, dat_nread)
BEGIN
IF (state /= st_Run) OR (swallow = '1') THEN
dat_empty_d <= '1';
ELSE
IF (credit(5 DOWNTO 1) = "000000") AND ((credit(0) = '0') OR (dat_en = '1')) THEN
dat_empty_d <= '1';
ELSE
dat_empty_d <= NOT(dat_full_i) AND dat_nwrite AND (dat_empty_i OR NOT(dat_nread));
END IF;
END IF;
END PROCESS;
 
 
---===============---
--== FIFO memory ==--
---===============---
 
store_e <= NOT(dat_full_i);
 
 
---=======================---
--== FIFO data out logic ==--
---=======================---
 
PROCESS(dat_full_i, dat_din, store)
BEGIN
CASE dat_full_i IS
WHEN '0' => dat_dout_d <= dat_din;
WHEN '1' => dat_dout_d <= store;
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
 
dat_dout_e <= '1' WHEN (dat_empty_i = '1') OR (dat_nread = '0') ELSE '0';
 
---======================================---
--== Shared Internal & External Signals ==--
---======================================---
 
dat_full <= dat_full_i;
fct_full <= fct_full_i;
dat_empty <= dat_empty_i;
 
END rtl;
/socwire/trunk/CODEC/receive_fifo.vhd
0,0 → 1,395
---====================== Start Software License ========================---
--== ==--
--== This license governs the use of this software, and your use of ==--
--== this software constitutes acceptance of this license. Agreement ==--
--== with all points is required to use this software. ==--
--== ==--
--== 1. This source file may be used and distributed without ==--
--== restriction provided that this software license statement is not ==--
--== removed from the file and that any derivative work contains the ==--
--== original software license notice and the associated disclaimer. ==--
--== ==--
--== 2. This source file is free software; you can redistribute it ==--
--== and/or modify it under the restriction that UNDER NO CIRCUMTANCES ==--
--== this Software is to be used to CONSTRUCT a SPACEWIRE INTERFACE ==--
--== This implies modification and/or derivative work of this Software. ==--
--== ==--
--== 3. This source is distributed in the hope that it will be useful, ==--
--== but WITHOUT ANY WARRANTY; without even the implied warranty of ==--
--== MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ==--
--== ==--
--== Your rights under this license are terminated immediately if you ==--
--== breach it in any way. ==--
--== ==--
---======================= End Software License =========================---
 
 
---====================== Start Copyright Notice ========================---
--== ==--
--== Filename ..... receive_fifo.vhd ==--
--== Download ..... http://www.ida.ing.tu-bs.de ==--
--== Company ...... IDA TU Braunschweig, Prof. Dr.-Ing. Harald Michalik ==--
 
 
--== Copyright .... Copyright (c) 2008 IDA ==--
--== Project ...... SoCWire CODEC ==--
--== Version ...... 1.00 ==--
--== Conception ... 11 November 2008 ==--
--== Modified ..... N/A ==--
--== ==--
---======================= End Copyright Notice =========================---
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.ALL;
 
 
ENTITY receive_fifo IS
GENERIC(
datawidth : NATURAL RANGE 8 TO 8192
);
PORT(
--== General Interface (Sync Rst, 50MHz Clock) ==--
 
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
 
--== SoCWire Interface ==--
 
state : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
 
--== Data Input Interface ==--
 
dat_full : OUT STD_LOGIC;
dat_nwrite : IN STD_LOGIC;
dat_din : IN STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
--== Data Output Interface ==--
 
dat_nread : IN STD_LOGIC;
dat_empty : OUT STD_LOGIC;
dat_dout : OUT STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
--== FCT Output Interface ==--
 
fct_nread : IN STD_LOGIC;
fct_empty : OUT STD_LOGIC
);
END receive_fifo;
 
 
ARCHITECTURE rtl OF receive_fifo IS
 
---==========================---
--== Constants Declarations ==--
---==========================---
 
CONSTANT st_error_reset : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
CONSTANT st_error_wait : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
CONSTANT st_ready : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010";
CONSTANT st_started : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011";
CONSTANT st_connecting : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100";
CONSTANT st_run : STD_LOGIC_VECTOR(2 DOWNTO 0) := "101";
CONSTANT st_unknown_1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "110";
CONSTANT st_unknown_2 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "111";
CONSTANT zeros : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 1) := (OTHERS => '0');
 
---=======================---
--== Signal Declarations ==--
---=======================---
 
SIGNAL rd_en : STD_LOGIC;
SIGNAL rd_addr : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_empty_d : STD_LOGIC;
SIGNAL rd_empty : STD_LOGIC;
SIGNAL rd_addr_d : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL wr_en : STD_LOGIC;
SIGNAL wr_addr : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL wr_full_d : STD_LOGIC;
SIGNAL wr_full : STD_LOGIC;
SIGNAL wr_din : STD_LOGIC_VECTOR(datawidth DOWNTO 0);
SIGNAL wr_addr_d : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL empty_i : STD_LOGIC;
SIGNAL fct_empty_i_d : STD_LOGIC;
SIGNAL fct_empty_i : STD_LOGIC;
SIGNAL fct_en : STD_LOGIC;
SIGNAL credit : STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
SIGNAL credit_d : STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
SIGNAL credit_e : STD_LOGIC;
SIGNAL vfullness : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL vfullness_d : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL vfullness_e : STD_LOGIC;
SIGNAL fullness : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL fullness_d : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL fullness_e : STD_LOGIC;
SIGNAL got_eop : STD_LOGIC;
SIGNAL empty_i_d : STD_LOGIC;
SIGNAL rst_fct : STD_LOGIC;
SIGNAL wr_en_ext : STD_LOGIC;
 
 
 
---=============================================---
--== Component Instantiations for leaf modules ==--
---=============================================---
 
COMPONENT dp_ram
GENERIC(
datawidth : NATURAL RANGE 8 TO 8192
);
PORT(
--== General Interface ==--
 
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
 
--== Write Interface ==--
 
wr_en : IN STD_LOGIC;
wr_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_din : IN STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
--== Read Interface ==--
 
rd_en : IN STD_LOGIC;
rd_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_dout : OUT STD_LOGIC_VECTOR(datawidth DOWNTO 0)
);
END COMPONENT dp_ram;
 
 
BEGIN
 
---============================================---
--== Reset for non-Connecting & non-Run logic ==--
---============================================---
 
rst_fct <= '1' WHEN (rst = '1') OR NOT((state = st_connecting) OR (state = st_run)) ELSE '0';
 
 
---=====================---
--== Synchronous Logic ==--
---=====================---
 
PROCESS (clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst_fct = '0' THEN
fct_empty_i <= fct_empty_i_d;
IF credit_e = '1' THEN
credit <= credit_d;
END IF;
ELSE
credit <= (others => '0');
fct_empty_i <= '1';
END IF;
IF rst = '0' THEN
wr_full <= wr_full_d;
rd_empty <= rd_empty_d;
empty_i <= empty_i_d;
 
IF wr_en = '1' THEN
got_eop <= wr_din(datawidth);
wr_addr <= wr_addr_d;
END IF;
IF rd_en = '1' THEN
rd_addr <= rd_addr_d;
END IF;
IF fullness_e = '1' THEN
fullness <= fullness_d;
END IF;
IF vfullness_e = '1' THEN
vfullness <= vfullness_d;
END IF;
ELSE
got_eop <= '1';
wr_addr <= (others => '0');
rd_addr <= (others => '0');
wr_full <= '1';
rd_empty <= '1';
fullness <= (others => '0');
empty_i <= '1';
vfullness <= (others => '0');
 
END IF;
END IF;
END PROCESS;
 
---=================---
--== EEP Generator ==--
---=================---
 
wr_din <= dat_din WHEN (dat_nwrite = '0') AND (wr_full = '0') ELSE '1' & zeros & '1';
 
 
---===========================================---
--== FIFO Write Enable & EEP Insertion Logic ==--
---===========================================---
 
wr_en <= '1' WHEN ((dat_nwrite = '0') AND (wr_full = '0')) OR ((got_eop = '0') AND (state /= st_connecting) AND (state /= st_run)) ELSE '0';
 
 
---======================---
--== FIFO Write Address ==--
---======================---
 
wr_addr_d <= wr_addr + 1;
 
 
---==================---
--== FIFO Full Flag ==--
---==================---
 
wr_full_d <= '1' WHEN ((credit(5 DOWNTO 1) = 0) AND ((credit(0) = '0') OR (wr_en_ext = '1')) AND
(fct_en = '0')) OR (state /= st_run) ELSE '0';
 
 
---===========================---
--== FIFO (Auto) Read Enable ==--
---===========================---
 
rd_en <= NOT(rd_empty) AND (empty_i OR NOT(dat_nread));
 
 
---=====================---
--== FIFO Read Address ==--
---=====================---
 
rd_addr_d <= rd_addr + 1;
 
 
---===================---
--== FIFO Empty Flag ==--
---===================---
 
rd_empty_d <= '1' WHEN (fullness(9 DOWNTO 1) = 0) AND (wr_en = '0') AND
((fullness(0) = '0') OR (rd_en = '1')) ELSE '0';
 
 
---==================================---
--== FIFO (Actual) Fullness Counter ==--
---==================================---
 
PROCESS(wr_en, rd_en, fullness)
BEGIN
IF (wr_en = '1') THEN
fullness_d <= fullness + 1;
ELSIF (rd_en = '1') THEN
fullness_d <= fullness - 1;
ELSE
fullness_d <= fullness;
END IF;
END PROCESS;
 
fullness_e <= rd_en XOR wr_en;
 
 
---===============================---
--== Data Output Handshake Logic ==--
---===============================---
 
empty_i_d <= rd_empty AND (empty_i OR NOT(dat_nread));
 
 
---===================================---
--== FIFO (Virtual) Fullness Counter ==--
---===================================---
 
PROCESS(vfullness, fct_en, rd_en, fullness_d)
VARIABLE tmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
tmp := fct_en & rd_en;
CASE tmp IS
WHEN "00" => vfullness_d <= fullness_d;
WHEN "01" => vfullness_d <= vfullness - 1;
WHEN "10" => vfullness_d <= vfullness + 8;
WHEN "11" => vfullness_d <= vfullness + 7;
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
 
vfullness_e <= (fct_en OR rd_en) WHEN (state = st_connecting) OR (state = st_run) ELSE '1';
 
---===================---
--== FCT Read Enable ==--
---===================---
 
fct_en <= NOT(fct_nread) AND NOT(fct_empty_i);
 
 
---==========================---
--== Receive Credit Counter ==--
---==========================---
 
wr_en_ext <= '1' WHEN ((dat_nwrite = '0') AND (wr_full = '0')) ELSE '0';
 
PROCESS(credit, fct_en, wr_en_ext)
VARIABLE tmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
tmp := fct_en & wr_en_ext;
CASE tmp IS
WHEN "11" => credit_d <= credit + 7;
WHEN "10" => credit_d <= credit + 8;
WHEN OTHERS => credit_d <= credit - 1;
END CASE;
END PROCESS;
 
credit_e <= fct_en OR wr_en_ext;
 
---=======================---
--== FCT Handshake Logic ==--
---=======================---
 
PROCESS(fct_empty_i, fct_nread, credit, vfullness)
BEGIN
CASE fct_empty_i IS
WHEN '0' => IF (fct_nread = '0') THEN
fct_empty_i_d <= '1';
ELSE
fct_empty_i_d <= '0';
END IF;
WHEN '1' => IF (credit <= 48) AND (vfullness <= 1014) THEN
fct_empty_i_d <= '0';
ELSE
fct_empty_i_d <= '1';
END IF;
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
 
 
---=================---
--== Dual Port RAM ==--
---=================---
 
dp_ram0 : dp_ram
GENERIC MAP
( datawidth => datawidth )
PORT MAP
(--== General Interface ==--
rst => rst,
clk => clk,
--== Write Interface ==--
wr_en => wr_en,
wr_addr => wr_addr,
wr_din => wr_din,
--== Read Interface ==--
rd_en => rd_en,
rd_addr => rd_addr,
rd_dout => dat_dout
);
 
 
---======================================---
--== Shared Internal & External Signals ==--
---======================================---
 
fct_empty <= fct_empty_i;
dat_empty <= empty_i;
dat_full <= wr_full;
END rtl;
/socwire/trunk/CODEC/socwire_codec.vhd
0,0 → 1,547
---====================== Start Software License ========================---
--== ==--
--== This license governs the use of this software, and your use of ==--
--== this software constitutes acceptance of this license. Agreement ==--
--== with all points is required to use this software. ==--
--== ==--
--== 1. This source file may be used and distributed without ==--
--== restriction provided that this software license statement is not ==--
--== removed from the file and that any derivative work contains the ==--
--== original software license notice and the associated disclaimer. ==--
--== ==--
--== 2. This source file is free software; you can redistribute it ==--
--== and/or modify it under the restriction that UNDER NO CIRCUMTANCES ==--
--== this Software is to be used to CONSTRUCT a SPACEWIRE INTERFACE ==--
--== This implies modification and/or derivative work of this Software. ==--
--== ==--
--== 3. This source is distributed in the hope that it will be useful, ==--
--== but WITHOUT ANY WARRANTY; without even the implied warranty of ==--
--== MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ==--
--== ==--
--== Your rights under this license are terminated immediately if you ==--
--== breach it in any way. ==--
--== ==--
---======================= End Software License =========================---
 
 
---====================== Start Copyright Notice ========================---
--== ==--
--== Filename ..... socwire_codec.vhd ==--
--== Download ..... http://www.ida.ing.tu-bs.de ==--
--== Company ...... IDA TU Braunschweig, Prof. Dr.-Ing. Harald Michalik ==--
 
 
--== Copyright .... Copyright (c) 2008 IDA ==--
--== Project ...... SoCWire CODEC ==--
--== Version ...... 1.00 ==--
--== Conception ... 11 November 2008 ==--
--== Modified ..... N/A ==--
--== ==--
---======================= End Copyright Notice =========================---
 
 
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.ALL;
 
 
ENTITY socwire_codec IS
GENERIC(
--== USE GEREIC MAPPING FROM TOPLEVEL!!! ==--
datawidth : NATURAL RANGE 8 TO 8192:=8;
speed : NATURAL RANGE 1 TO 100:=10; -- Set CODEC speed to system clock in nanoseconds !
after64 : NATURAL RANGE 1 TO 6400:=64; -- Spacewire Standard 6400 = 6.4 us
after128 : NATURAL RANGE 1 TO 12800:=128; -- Spacewire Standard 12800 = 12.8 us
disconnect_detection : NATURAL RANGE 1 TO 850:=85 -- Spacewire Standard 850 = 850 ns
);
PORT(
--== General Interface (Sync Rst, 50MHz Clock) ==--
 
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
 
--== Link Enable Interface ==--
 
socw_en : IN STD_LOGIC;
socw_dis : IN STD_LOGIC;
 
--== Serial Receive Interface ==--
 
rx : IN STD_LOGIC_VECTOR(datawidth+1 DOWNTO 0);
rx_valid : IN STD_LOGIC;
 
--== Serial Transmit Interface ==--
 
tx : OUT STD_LOGIC_VECTOR(datawidth+1 DOWNTO 0);
tx_valid : OUT STD_LOGIC;
 
--== Data Input Interface ==--
 
dat_full : OUT STD_LOGIC;
dat_nwrite : IN STD_LOGIC;
dat_din : IN STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
--== Data Output Interface ==--
 
dat_nread : IN STD_LOGIC;
dat_empty : OUT STD_LOGIC;
dat_dout : OUT STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
--== Active Interface ==--
 
active : OUT STD_LOGIC
);
END socwire_codec;
 
 
ARCHITECTURE rtl OF socwire_codec IS
 
---==========================---
--== Constants Declarations ==--
---==========================---
 
CONSTANT st_error_reset : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
CONSTANT st_error_wait : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
CONSTANT st_ready : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010";
CONSTANT st_started : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011";
CONSTANT st_connecting : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100";
CONSTANT st_run : STD_LOGIC_VECTOR(2 DOWNTO 0) := "101";
CONSTANT st_unknown_1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "110";
CONSTANT st_unknown_2 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "111";
 
---===================================---
--== Signal Declarations (SM to All) ==--
---===================================---
 
SIGNAL state : STD_LOGIC_VECTOR(2 DOWNTO 0);
 
---==================================---
--== Signal Declarations (Rx to SM) ==--
---==================================---
 
SIGNAL got_null : STD_LOGIC;
SIGNAL got_fct : STD_LOGIC;
SIGNAL got_nchar : STD_LOGIC;
SIGNAL err_par : STD_LOGIC;
SIGNAL err_esc : STD_LOGIC;
SIGNAL err_dsc : STD_LOGIC;
SIGNAL err_fct : STD_LOGIC;
SIGNAL err_nchar : STD_LOGIC;
 
---=======================================---
--== Signal Declarations (Rx to Rx FIFO) ==--
---=======================================---
 
SIGNAL dat_full_i : STD_LOGIC;
SIGNAL dat_nwrite_i : STD_LOGIC;
SIGNAL dat_din_i : STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
---=======================================---
--== Signal Declarations (Rx FIFO to Tx) ==--
---=======================================---
 
SIGNAL fct_nread_i : STD_LOGIC;
SIGNAL fct_empty_i : STD_LOGIC;
 
---=======================================---
--== Signal Declarations (Rx to Tx FIFO) ==--
---=======================================---
 
SIGNAL fct_full_i : STD_LOGIC;
SIGNAL fct_nwrite_i : STD_LOGIC;
 
---=======================================---
--== Signal Declarations (Tx FIFO to Tx) ==--
---=======================================---
 
SIGNAL dat_nread_i : STD_LOGIC;
SIGNAL dat_empty_i : STD_LOGIC;
SIGNAL dat_dout_i : STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
---=============================================---
--== TESTBENCH : Type Declarations : TESTBENCH ==--
---=============================================---
 
TYPE ss IS
(
error_reset,
error_wait,
ready,
started,
connecting,
run,
unknown_1,
unknown_2,
baffled
);
 
---===============================================---
--== TESTBENCH : Signal Declarations : TESTBENCH ==--
---===============================================---
 
SIGNAL codec_state : ss;
 
 
---=============================================---
--== Component Instantiations for leaf modules ==--
---=============================================---
 
COMPONENT receiver
GENERIC(
datawidth : NATURAL RANGE 8 TO 8192;
speed : NATURAL RANGE 1 TO 100;
disconnect_detection : NATURAL RANGE 1 TO 850
);
PORT(
--== General Interface (Sync Rst, 50MHz Clock) ==--
 
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
 
--== SoCWire Interface ==--
 
state : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
 
--== External Receive Interface ==--
 
rx : IN STD_LOGIC_VECTOR(datawidth+1 DOWNTO 0);
rx_valid : IN STD_LOGIC;
 
--== Character Interface ==--
 
got_null : OUT STD_LOGIC;
got_fct : OUT STD_LOGIC;
got_nchar : OUT STD_LOGIC;
 
--== Error Interface ==--
 
err_par : OUT STD_LOGIC;
err_esc : OUT STD_LOGIC;
err_dsc : OUT STD_LOGIC;
err_fct : OUT STD_LOGIC;
err_nchar : OUT STD_LOGIC;
 
--== Data Output Interface ==--
 
dat_nread : IN STD_LOGIC;
dat_empty : OUT STD_LOGIC;
dat_dout : OUT STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
--== FCT Output Interface ==--
 
fct_nread : IN STD_LOGIC;
fct_empty : OUT STD_LOGIC
);
END COMPONENT;
 
COMPONENT receive_fifo
 
GENERIC(
datawidth : NATURAL RANGE 8 TO 8192
);
 
PORT(
--== General Interface (Sync Rst, 50MHz Clock) ==--
 
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
 
--== SoCWire Interface ==--
 
state : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
 
--== Data Input Interface ==--
 
dat_full : OUT STD_LOGIC;
dat_nwrite : IN STD_LOGIC;
dat_din : IN STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
--== Data Output Interface ==--
 
dat_nread : IN STD_LOGIC;
dat_empty : OUT STD_LOGIC;
dat_dout : OUT STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
--== FCT Output Interface ==--
 
fct_nread : IN STD_LOGIC;
fct_empty : OUT STD_LOGIC
);
END COMPONENT receive_fifo;
 
COMPONENT state_machine
GENERIC(
speed : NATURAL RANGE 1 TO 100;
after64 : NATURAL RANGE 1 TO 6400;
after128 : NATURAL RANGE 1 TO 12800
);
PORT(
--== General Interface (Sync Rst, 50MHz Clock) ==--
 
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
 
--== Link Enable Interface ==--
 
socw_en : IN STD_LOGIC;
socw_dis : IN STD_LOGIC;
 
--== SoCWire Interface ==--
 
state : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
 
--== Character Interface ==--
 
got_null : IN STD_LOGIC;
got_fct : IN STD_LOGIC;
got_nchar : IN STD_LOGIC;
 
--== Error Interface ==--
 
err_par : IN STD_LOGIC;
err_esc : IN STD_LOGIC;
err_dsc : IN STD_LOGIC;
err_fct : IN STD_LOGIC;
err_nchar : IN STD_LOGIC;
 
--== Active Interface ==--
 
active : OUT STD_LOGIC
);
END COMPONENT state_machine;
 
COMPONENT transmitter
GENERIC(
datawidth : NATURAL RANGE 8 TO 8192
);
PORT(
 
--== General Interface (Sync Rst, 50MHz Clock) ==--
 
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
 
--== SoCWire Interface ==--
 
state : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
 
--== External Transmit Interface ==--
 
tx : OUT STD_LOGIC_VECTOR(datawidth+1 DOWNTO 0);
tx_valid : OUT STD_LOGIC;
 
--== Data Input Interface ==--
 
dat_full : OUT STD_LOGIC;
dat_nwrite : IN STD_LOGIC;
dat_din : IN STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
--== FCT Input Interface ==--
 
fct_full : OUT STD_LOGIC;
fct_nwrite : IN STD_LOGIC
);
END COMPONENT transmitter;
 
COMPONENT transmit_fifo
GENERIC(
datawidth : NATURAL RANGE 8 TO 8192
);
PORT(
--== General Interface (Sync Rst, 50MHz Clock) ==--
 
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
 
--== SoCWire Interface ==--
 
state : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
 
--== Data Input Interface ==--
 
dat_full : OUT STD_LOGIC;
dat_nwrite : IN STD_LOGIC;
dat_din : IN STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
--== Data Output Interface ==--
 
dat_nread : IN STD_LOGIC;
dat_empty : OUT STD_LOGIC;
dat_dout : OUT STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
--== FCT Input Interface ==--
 
fct_full : OUT STD_LOGIC;
fct_nwrite : IN STD_LOGIC
);
END COMPONENT transmit_fifo;
 
BEGIN
 
---===================================================---
--== TESTBENCH : Show State more clearly : TESTBENCH ==--
---===================================================---
 
codec_state <= error_reset WHEN (state = st_error_reset) ELSE
error_wait WHEN (state = st_error_wait) ELSE
ready WHEN (state = st_ready) ELSE
started WHEN (state = st_started) ELSE
connecting WHEN (state = st_connecting) ELSE
run WHEN (state = st_run) ELSE
unknown_1 WHEN (state = st_unknown_1) ELSE
unknown_2 WHEN (state = st_unknown_2) ELSE
baffled;
 
 
---======================---
--== SoCWire Receiver ==--
---======================---
 
rx0 : receiver
GENERIC MAP
( speed => speed,
datawidth => datawidth,
disconnect_detection=>disconnect_detection)
PORT MAP
(--== General Interface (Sync Rst) ==--
rst => rst,
clk => clk,
--== SoCWire Interface ==--
state => state,
--== External Receive Interface ==--
rx => rx,
rx_valid => rx_valid,
--== Character Interface ==--
got_null => got_null,
got_fct => got_fct,
got_nchar => got_nchar,
--== Error Interface ==--
err_par => err_par,
err_esc => err_esc,
err_dsc => err_dsc,
err_fct => err_fct,
err_nchar => err_nchar,
--== Data Output Interface ==--
dat_nread => dat_full_i,
dat_empty => dat_nwrite_i,
dat_dout => dat_din_i,
--== FCT Output Interface ==--
fct_nread => fct_full_i,
fct_empty => fct_nwrite_i
);
 
 
---================---
--== Receive FIFO ==--
---================---
 
rx_fifo : receive_fifo
GENERIC MAP
( datawidth => datawidth )
PORT MAP
(--== General Interface (Sync Rst) ==--
rst => rst,
clk => clk,
--== SoCWire Interface ==--
state => state,
--== Data Input Interface ==--
dat_full => dat_full_i,
dat_nwrite => dat_nwrite_i,
dat_din => dat_din_i,
--== Data Output Interface ==--
dat_nread => dat_nread,
dat_empty => dat_empty,
dat_dout => dat_dout,
--== FCT Output Interface ==--
fct_nread => fct_nread_i,
fct_empty => fct_empty_i
);
 
 
---===========================---
--== SoCWire State Machine ==--
---===========================---
 
statem : state_machine
GENERIC MAP
( speed => speed,
after64 =>after64,
after128=>after128)
PORT MAP
(--== General Interface (Sync Rst, 50MHz Clock) ==--
rst => rst,
clk => clk,
--== Link Enable Interface ==--
socw_en => socw_en,
socw_dis => socw_dis,
--== SoCWire Interface ==--
state => state,
--== Character Interface ==--
got_null => got_null,
got_fct => got_fct,
got_nchar => got_nchar,
--== Error Interface ==--
err_par => err_par,
err_esc => err_esc,
err_dsc => err_dsc,
err_fct => err_fct,
err_nchar => err_nchar,
--== Active Interface ==--
active => active
);
 
 
---=========================---
--== SoCWire Transmitter ==--
---=========================---
 
tx0 : transmitter
GENERIC MAP
( datawidth => datawidth )
PORT MAP
(--== General Interface (Sync Rst, 50MHz Clock) ==--
rst => rst,
clk => clk,
--== SoCWire Interface ==--
state => state,
--== External Transmit Interface ==--
tx => tx,
tx_valid => tx_valid,
--== Data Input Interface ==--
dat_full => dat_nread_i,
dat_nwrite => dat_empty_i,
dat_din => dat_dout_i,
--== FCT Input Interface ==--
fct_full => fct_nread_i,
fct_nwrite => fct_empty_i
);
 
 
---====================---
--== Transmitter FIFO ==--
---====================---
 
tx_fifo : transmit_fifo
GENERIC MAP
( datawidth => datawidth )
PORT MAP
(--== General Interface (Sync Rst, 50MHz Clock) ==--
rst => rst,
clk => clk,
--== SoCWire Interface ==--
state => state,
--== Data Input Interface ==--
dat_full => dat_full,
dat_nwrite => dat_nwrite,
dat_din => dat_din,
--== Data Output Interface ==--
dat_nread => dat_nread_i,
dat_empty => dat_empty_i,
dat_dout => dat_dout_i,
--== FCT Input Interface ==--
fct_full => fct_full_i,
fct_nwrite => fct_nwrite_i
);
END rtl;
/socwire/trunk/CODEC/transmitter.vhd
0,0 → 1,235
---====================== Start Software License ========================---
--== ==--
--== This license governs the use of this software, and your use of ==--
--== this software constitutes acceptance of this license. Agreement ==--
--== with all points is required to use this software. ==--
--== ==--
--== 1. This source file may be used and distributed without ==--
--== restriction provided that this software license statement is not ==--
--== removed from the file and that any derivative work contains the ==--
--== original software license notice and the associated disclaimer. ==--
--== ==--
--== 2. This source file is free software; you can redistribute it ==--
--== and/or modify it under the restriction that UNDER NO CIRCUMTANCES ==--
--== this Software is to be used to CONSTRUCT a SPACEWIRE INTERFACE ==--
--== This implies modification and/or derivative work of this Software. ==--
--== ==--
--== 3. This source is distributed in the hope that it will be useful, ==--
--== but WITHOUT ANY WARRANTY; without even the implied warranty of ==--
--== MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ==--
--== ==--
--== Your rights under this license are terminated immediately if you ==--
--== breach it in any way. ==--
--== ==--
---======================= End Software License =========================---
 
 
---====================== Start Copyright Notice ========================---
--== ==--
--== Filename ..... transmitter.vhd ==--
--== Download ..... http://www.ida.ing.tu-bs.de ==--
--== Company ...... IDA TU Braunschweig, Prof. Dr.-Ing. Harald Michalik ==--
 
 
--== Copyright .... Copyright (c) 2008 IDA ==--
--== Project ...... SoCWire CODEC ==--
--== Version ...... 1.00 ==--
--== Conception ... 11 November 2008 ==--
--== Modified ..... N/A ==--
--== ==--
---======================= End Copyright Notice =========================---
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.ALL;
 
 
ENTITY transmitter IS
GENERIC(
 
datawidth : NATURAL RANGE 8 TO 8192
);
PORT(
--== General Interface (Sync Rst, 50MHz Clock) ==--
 
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
 
--== SoCWire Interface ==--
 
state : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
 
--== External Transmit Interface ==--
 
tx : OUT STD_LOGIC_VECTOR(datawidth+1 DOWNTO 0);
tx_valid : OUT STD_LOGIC;
 
--== Data Input Interface ==--
 
dat_full : OUT STD_LOGIC;
dat_nwrite : IN STD_LOGIC;
dat_din : IN STD_LOGIC_VECTOR(datawidth DOWNTO 0);
 
--== FCT Input Interface ==--
 
fct_full : OUT STD_LOGIC;
fct_nwrite : IN STD_LOGIC
);
END transmitter;
 
 
ARCHITECTURE rtl OF transmitter IS
 
---==========================---
--== Constants Declarations ==--
---==========================---
 
CONSTANT st_error_reset : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
CONSTANT st_error_wait : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
CONSTANT st_ready : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010";
CONSTANT st_started : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011";
CONSTANT st_connecting : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100";
CONSTANT st_run : STD_LOGIC_VECTOR(2 DOWNTO 0) := "101";
CONSTANT st_unknown_1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "110";
CONSTANT st_unknown_2 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "111";
CONSTANT zeros : STD_LOGIC_VECTOR(datawidth DOWNTO 5) := (others => '0');
 
---=======================---
--== Signal Declarations ==--
---=======================---
 
SIGNAL tx_rst : STD_LOGIC;
SIGNAL clk_en : STD_LOGIC;
SIGNAL load_d : STD_LOGIC;
SIGNAL load : STD_LOGIC;
SIGNAL bit_array_d : STD_LOGIC_VECTOR(datawidth DOWNTO 0);
SIGNAL bit_array : STD_LOGIC_VECTOR(datawidth DOWNTO 0);
SIGNAL parity_d : STD_LOGIC;
SIGNAL parity : STD_LOGIC;
SIGNAL fct_en : STD_LOGIC;
SIGNAL dat_en : STD_LOGIC;
SIGNAL fct_full_i : STD_LOGIC;
SIGNAL dat_full_i : STD_LOGIC;
 
 
 
BEGIN
 
 
---=========================================================---
--== Generate Tx Reset Signal to hold Transmitter in Reset ==--
---=========================================================---
 
tx_rst <= '1' WHEN ((state /= st_Started) AND (state /= st_connecting) AND
(state /= st_run)) OR (rst = '1') ELSE '0';
 
 
---=====================---
--== Synchronous Logic ==--
---=====================---
 
PROCESS (clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF tx_rst = '0' THEN
clk_en <= NOT clk_en;
load <= load_d;
IF load = '1' THEN
parity <= parity_d;
bit_array <= bit_array_d;
END IF;
ELSE
clk_en <= '0';
load <= '0';
parity <= '1';
bit_array <= (others => '0');
END IF;
END IF;
END PROCESS;
 
---===========================================================---
--== Generate pulse for cycle where shift register is loaded ==--
---===========================================================---
 
load_d <= NOT tx_rst;
 
---===========================================================---
--== FCT & NChar Input Interfaces (pre-sniff then handshake) ==--
---===========================================================---
 
PROCESS(load_d, state, fct_nwrite, dat_nwrite)
BEGIN
IF (load_d = '1') THEN
IF ((state = st_connecting) OR (state = st_run)) AND (fct_nwrite = '0') THEN
fct_full_i <= '0';
dat_full_i <= '1';
ELSIF (state = st_run) AND (dat_nwrite = '0') THEN
fct_full_i <= '1';
dat_full_i <= '0';
ELSE
fct_full_i <= '1';
dat_full_i <= '1';
END IF;
ELSE
fct_full_i <= '1';
dat_full_i <= '1';
END IF;
END PROCESS;
 
fct_en <= NOT(fct_full_i) AND NOT(fct_nwrite);
dat_en <= NOT(dat_full_i) AND NOT(dat_nwrite);
 
 
---==================================---
--== Character Priority Multiplexor ==--
---==================================---
 
PROCESS(load, bit_array, fct_en, dat_en, parity, dat_din)
BEGIN
IF (load = '1') THEN
IF (fct_en = '1') THEN
bit_array_d <= zeros & "00001";
ELSIF (dat_en = '1') THEN
IF (dat_din(datawidth) = '1') THEN
bit_array_d <= zeros & "00" & NOT(dat_din(0)) & dat_din(0) & '1';
ELSE
bit_array_d <= dat_din(datawidth-1 DOWNTO 0) & '0';
END IF;
ELSE
bit_array_d <= zeros & "10111";
END IF;
ELSE
bit_array_d <= (others => '0');
END IF;
END PROCESS;
PROCESS(bit_array_d, bit_array)
VARIABLE temp : STD_LOGIC;
BEGIN
temp := '0' XOR bit_array_d(0);
FOR i IN 1 TO datawidth LOOP
temp := temp XOR bit_array(i);
END LOOP;
parity_d <= NOT temp;
END PROCESS;
 
---===================================---
--== Drive Tx Data Output (NONE-TMR) ==--
---===================================---
 
tx <= bit_array & parity;
tx_valid <= load;
 
---======================================---
--== Shared Internal & External Signals ==--
---======================================---
 
fct_full <= fct_full_i;
dat_full <= dat_full_i;
 
END rtl;
/socwire/branches/CODEC/transmitter.vhd File deleted
/socwire/branches/CODEC/dp_ram.vhd File deleted
/socwire/branches/CODEC/receiver.vhd File deleted
/socwire/branches/CODEC/state_machine.vhd File deleted
/socwire/branches/CODEC/transmit_fifo.vhd File deleted
/socwire/branches/CODEC/receive_fifo.vhd File deleted
/socwire/branches/CODEC/socwire_codec.vhd File deleted

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