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URL https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk

Subversion Repositories versatile_fifo

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Rev 14 → Rev 15

/versatile_fifo/trunk/rtl/verilog/gray_counter_defines.v
0,0 → 1,37
// module name
`define CNT_MODULE_NAME gray_counter
 
// counter type = [BINARY, GRAY, LFSR]
//`define CNT_TYPE_BINARY
`define CNT_TYPE_GRAY
//`define CNT_TYPE_LFSR
 
// q as output
`define CNT_Q
 
// number of CNT bins
`define CNT_LENGTH 6
 
// clear
//`define CNT_CLEAR
 
// set
//`define CNT_SET
`define CNT_SET_VALUE `CNT_LENGTH'h9
 
// wrap around creates shorter cycle than maximum length
//`define CNT_WRAP
`define CNT_WRAP_VALUE `CNT_LENGTH'h9
 
// clock enable
`define CNT_CE
 
// q_next as an output
//`define CNT_QNEXT
 
// q=0 as an output
//`define CNT_Z
 
// q_next=0 as a registered output
//`define CNT_ZQ
 
/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_dw.v
25,22 → 25,14
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] ;
always @ (posedge clk)
begin
q_a <= ram[adr_a];
if (we_a)
begin
ram[adr_a] <= d_a;
q_a <= d_a;
end
else
q_a <= ram[adr_a];
end
always @ (posedge clk)
begin
q_b <= ram[adr_b];
if (we_b)
begin
ram[adr_b] <= d_b;
q_b <= d_b;
end
else
q_b <= ram[adr_b];
ram[adr_b] <= d_b;
end
endmodule
/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v
60,13 → 60,9
`endif
`ifdef DW
begin // Port A
q_a <= ram[adr_a];
if (we_a)
begin
ram[adr_a] <= d_a;
q_a <= d_a;
end
else
q_a <= ram[adr_a];
end
`else
if (we_a)
80,13 → 76,9
`endif
`ifdef DW
begin // Port b
q_b <= ram[adr_b];
if (we_b)
begin
ram[adr_b] <= d_b;
q_b <= d_b;
end
else
q_b <= ram[adr_b];
ram[adr_b] <= d_b;
end
`else // !`ifdef DW
adr_b_reg <= adr_b;
/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
26,22 → 26,14
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] ;
always @ (posedge clk_a)
begin
q_a <= ram[adr_a];
if (we_a)
begin
ram[adr_a] <= d_a;
q_a <= d_a;
end
else
q_a <= ram[adr_a];
end
always @ (posedge clk_b)
begin
q_b <= ram[adr_b];
if (we_b)
begin
ram[adr_b] <= d_b;
q_b <= d_b;
end
else
q_b <= ram[adr_b];
ram[adr_b] <= d_b;
end
endmodule
/versatile_fifo/trunk/doc/src/versatile_fifo.odt Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/versatile_fifo/trunk/doc/versatile_fifo.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

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