URL
https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk
Subversion Repositories dbg_interface
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 147 to Rev 148
- ↔ Reverse comparison
Rev 147 → Rev 148
/tags/rel_23/rtl/verilog/dbg_cpu_defines.v
0,0 → 1,108
////////////////////////////////////////////////////////////////////// |
//// //// |
//// dbg_cpu_defines.v //// |
//// //// |
//// //// |
//// This file is part of the SoC Debug Interface. //// |
//// http://www.opencores.org/projects/DebugInterface/ //// |
//// //// |
//// Author(s): //// |
//// Igor Mohor (igorm@opencores.org) //// |
//// //// |
//// //// |
//// All additional information is avaliable in the README.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 - 2004 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2004/03/31 14:34:09 igorm |
// data_cnt_lim length changed to reduce number of warnings. |
// |
// Revision 1.4 2004/03/28 20:27:02 igorm |
// New release of the debug interface (3rd. release). |
// |
// Revision 1.3 2004/03/22 16:35:46 igorm |
// Temp version before changing dbg interface. |
// |
// Revision 1.2 2004/01/17 17:01:14 mohor |
// Almost finished. |
// |
// Revision 1.1 2004/01/16 14:53:33 mohor |
// *** empty log message *** |
// |
// |
// |
|
|
|
// Defining length of the command |
`define DBG_CPU_CMD_LEN 3'd4 |
`define DBG_CPU_CMD_CNT_WIDTH 3 |
|
// Defining length of the access_type field |
`define DBG_CPU_ACC_TYPE_LEN 3'd4 |
|
// Defining length of the address |
`define DBG_CPU_ADR_LEN 6'd32 |
|
// Defining length of the length register |
`define DBG_CPU_LEN_LEN 5'd16 |
|
// Defining total length of the DR needed |
`define DBG_CPU_DR_LEN (`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN) |
|
// Defining length of the CRC |
`define DBG_CPU_CRC_LEN 6'd32 |
`define DBG_CPU_CRC_CNT_WIDTH 6 |
|
// Defining length of status |
`define DBG_CPU_STATUS_LEN 3'd4 |
`define DBG_CPU_STATUS_CNT_WIDTH 3 |
|
// Defining length of the data |
`define DBG_CPU_DATA_CNT_WIDTH (`DBG_CPU_LEN_LEN + 3) |
`define DBG_CPU_DATA_CNT_LIM_WIDTH `DBG_CPU_LEN_LEN |
|
// Defining length of the control register |
`define DBG_CPU_CTRL_LEN 2 |
|
//Defining commands |
`define DBG_CPU_GO 4'h0 |
`define DBG_CPU_RD_COMM 4'h1 |
`define DBG_CPU_WR_COMM 4'h2 |
`define DBG_CPU_RD_CTRL 4'h3 |
`define DBG_CPU_WR_CTRL 4'h4 |
|
// Defining access types for wishbone |
`define DBG_CPU_WRITE 4'h2 |
`define DBG_CPU_READ 4'h6 |
|
|
tags/rel_23/rtl/verilog/dbg_cpu_defines.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_23/rtl/verilog/dbg_wb.v
===================================================================
--- tags/rel_23/rtl/verilog/dbg_wb.v (nonexistent)
+++ tags/rel_23/rtl/verilog/dbg_wb.v (revision 148)
@@ -0,0 +1,1175 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbg_wb.v ////
+//// ////
+//// ////
+//// This file is part of the SoC Debug Interface. ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2004 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.22 2004/04/01 11:56:59 igorm
+// Port names and defines for the supported CPUs changed.
+//
+// Revision 1.21 2004/03/31 14:34:09 igorm
+// data_cnt_lim length changed to reduce number of warnings.
+//
+// Revision 1.20 2004/03/28 20:27:02 igorm
+// New release of the debug interface (3rd. release).
+//
+// Revision 1.19 2004/03/22 16:35:46 igorm
+// Temp version before changing dbg interface.
+//
+// Revision 1.18 2004/01/25 14:04:18 mohor
+// All flipflops are reset.
+//
+// Revision 1.17 2004/01/22 13:58:53 mohor
+// Port signals are all set to zero after reset.
+//
+// Revision 1.16 2004/01/19 07:32:41 simons
+// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
+//
+// Revision 1.15 2004/01/17 18:01:24 mohor
+// New version.
+//
+// Revision 1.14 2004/01/16 14:51:33 mohor
+// cpu registers added.
+//
+// Revision 1.13 2004/01/15 12:09:43 mohor
+// Working.
+//
+// Revision 1.12 2004/01/14 22:59:18 mohor
+// Temp version.
+//
+// Revision 1.11 2004/01/14 12:29:40 mohor
+// temp version. Resets will be changed in next version.
+//
+// Revision 1.10 2004/01/13 11:28:14 mohor
+// tmp version.
+//
+// Revision 1.9 2004/01/10 07:50:24 mohor
+// temp version.
+//
+// Revision 1.8 2004/01/09 12:48:44 mohor
+// tmp version.
+//
+// Revision 1.7 2004/01/08 17:53:36 mohor
+// tmp version.
+//
+// Revision 1.6 2004/01/07 11:58:56 mohor
+// temp4 version.
+//
+// Revision 1.5 2004/01/06 17:15:19 mohor
+// temp3 version.
+//
+// Revision 1.4 2004/01/05 12:16:00 mohor
+// tmp2 version.
+//
+// Revision 1.3 2003/12/23 16:22:46 mohor
+// Tmp version.
+//
+// Revision 1.2 2003/12/23 15:26:26 mohor
+// Small fix.
+//
+// Revision 1.1 2003/12/23 15:09:04 mohor
+// New directory structure. New version of the debug interface.
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "dbg_wb_defines.v"
+
+// Top module
+module dbg_wb(
+ // JTAG signals
+ tck_i,
+ tdi_i,
+ tdo_o,
+
+ // TAP states
+ shift_dr_i,
+ pause_dr_i,
+ update_dr_i,
+
+ wishbone_ce_i,
+ crc_match_i,
+ crc_en_o,
+ shift_crc_o,
+ rst_i,
+
+ // WISHBONE common signals
+ wb_clk_i,
+
+ // WISHBONE master interface
+ wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
+ wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o
+
+ );
+
+// JTAG signals
+input tck_i;
+input tdi_i;
+output tdo_o;
+
+// TAP states
+input shift_dr_i;
+input pause_dr_i;
+input update_dr_i;
+
+input wishbone_ce_i;
+input crc_match_i;
+output crc_en_o;
+output shift_crc_o;
+input rst_i;
+// WISHBONE common signals
+input wb_clk_i;
+
+// WISHBONE master interface
+output [31:0] wb_adr_o;
+output [31:0] wb_dat_o;
+input [31:0] wb_dat_i;
+output wb_cyc_o;
+output wb_stb_o;
+output [3:0] wb_sel_o;
+output wb_we_o;
+input wb_ack_i;
+output wb_cab_o;
+input wb_err_i;
+output [2:0] wb_cti_o;
+output [1:0] wb_bte_o;
+
+reg wb_cyc_o;
+
+reg tdo_o;
+
+reg [31:0] wb_dat_tmp, wb_dat_dsff;
+reg [31:0] wb_adr_dsff;
+reg [3:0] wb_sel_dsff;
+reg wb_we_dsff;
+reg [`DBG_WB_DR_LEN -1 :0] dr;
+wire enable;
+wire cmd_cnt_en;
+reg [`DBG_WB_CMD_CNT_WIDTH -1:0] cmd_cnt;
+wire cmd_cnt_end;
+reg cmd_cnt_end_q;
+reg addr_len_cnt_en;
+reg [5:0] addr_len_cnt;
+wire addr_len_cnt_end;
+reg addr_len_cnt_end_q;
+reg crc_cnt_en;
+reg [`DBG_WB_CRC_CNT_WIDTH -1:0] crc_cnt;
+wire crc_cnt_end;
+reg crc_cnt_end_q;
+reg data_cnt_en;
+reg [`DBG_WB_DATA_CNT_WIDTH:0] data_cnt;
+reg [`DBG_WB_DATA_CNT_LIM_WIDTH:0] data_cnt_limit;
+wire data_cnt_end;
+reg data_cnt_end_q;
+
+reg crc_match_reg;
+
+reg [`DBG_WB_ACC_TYPE_LEN -1:0] acc_type;
+reg [`DBG_WB_ADR_LEN -1:0] adr;
+reg [`DBG_WB_LEN_LEN -1:0] len;
+reg [`DBG_WB_LEN_LEN:0] len_var;
+reg start_rd_tck;
+reg rd_tck_started;
+reg start_rd_csff;
+reg start_wb_rd;
+reg start_wb_rd_q;
+reg start_wr_tck;
+reg start_wr_csff;
+reg start_wb_wr;
+reg start_wb_wr_q;
+
+reg status_cnt_en;
+wire status_cnt_end;
+
+wire byte, half, long;
+reg byte_q, half_q, long_q;
+
+reg [`DBG_WB_STATUS_CNT_WIDTH -1:0] status_cnt;
+
+reg [`DBG_WB_STATUS_LEN -1:0] status;
+
+reg wb_error, wb_error_csff, wb_error_tck;
+reg wb_overrun, wb_overrun_csff, wb_overrun_tck;
+reg underrun_tck;
+
+reg busy_wb;
+reg busy_tck;
+reg wb_end;
+reg wb_end_rst;
+reg wb_end_rst_csff;
+reg wb_end_csff;
+reg wb_end_tck, wb_end_tck_q;
+reg busy_csff;
+reg latch_data;
+reg update_dr_csff, update_dr_wb;
+
+reg set_addr, set_addr_csff, set_addr_wb, set_addr_wb_q;
+wire [31:0] input_data;
+
+wire len_eq_0;
+wire crc_cnt_31;
+
+reg [1:0] ptr;
+reg [2:0] fifo_cnt;
+wire fifo_full;
+wire fifo_empty;
+reg [7:0] mem [0:3];
+reg [2:0] mem_ptr_dsff;
+reg wishbone_ce_csff;
+reg mem_ptr_init;
+reg [`DBG_WB_CMD_LEN -1: 0] curr_cmd;
+wire curr_cmd_go;
+reg curr_cmd_go_q;
+wire curr_cmd_wr_comm;
+wire curr_cmd_rd_comm;
+wire acc_type_read;
+wire acc_type_write;
+wire acc_type_8bit;
+wire acc_type_16bit;
+wire acc_type_32bit;
+
+
+assign enable = wishbone_ce_i & shift_dr_i;
+assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
+assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC
+
+assign curr_cmd_go = (curr_cmd == `DBG_WB_GO) && cmd_cnt_end;
+assign curr_cmd_wr_comm = (curr_cmd == `DBG_WB_WR_COMM) && cmd_cnt_end;
+assign curr_cmd_rd_comm = (curr_cmd == `DBG_WB_RD_COMM) && cmd_cnt_end;
+
+assign acc_type_read = (acc_type == `DBG_WB_READ8 || acc_type == `DBG_WB_READ16 || acc_type == `DBG_WB_READ32);
+assign acc_type_write = (acc_type == `DBG_WB_WRITE8 || acc_type == `DBG_WB_WRITE16 || acc_type == `DBG_WB_WRITE32);
+
+assign acc_type_8bit = (acc_type == `DBG_WB_READ8 || acc_type == `DBG_WB_WRITE8);
+assign acc_type_16bit = (acc_type == `DBG_WB_READ16 || acc_type == `DBG_WB_WRITE16);
+assign acc_type_32bit = (acc_type == `DBG_WB_READ32 || acc_type == `DBG_WB_WRITE32);
+
+
+// Selecting where to take the data from
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ ptr <= #1 2'h0;
+ else if (update_dr_i)
+ ptr <= #1 2'h0;
+ else if (curr_cmd_go && acc_type_read && crc_cnt_31) // first latch
+ ptr <= #1 ptr + 1'b1;
+ else if (curr_cmd_go && acc_type_read && byte && (!byte_q))
+ ptr <= ptr + 1'd1;
+end
+
+
+// Shift register for shifting in and out the data
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ latch_data <= #1 1'b0;
+ dr <= #1 {`DBG_WB_DR_LEN{1'b0}};
+ end
+ else if (curr_cmd_rd_comm && crc_cnt_31) // Latching data (from iternal regs)
+ begin
+ dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1:0] <= #1 {acc_type, adr, len};
+ end
+ else if (acc_type_read && curr_cmd_go && crc_cnt_31) // Latchind first data (from WB)
+ begin
+ dr[31:0] <= #1 input_data[31:0];
+ latch_data <= #1 1'b1;
+ end
+ else if (acc_type_read && curr_cmd_go && crc_cnt_end) // Latching data (from WB)
+ begin
+ if (acc_type == `DBG_WB_READ8)
+ begin
+ if(byte & (~byte_q))
+ begin
+ case (ptr) // synthesis parallel_case
+ 2'b00 : dr[31:24] <= #1 input_data[31:24];
+ 2'b01 : dr[31:24] <= #1 input_data[23:16];
+ 2'b10 : dr[31:24] <= #1 input_data[15:8];
+ 2'b11 : dr[31:24] <= #1 input_data[7:0];
+ endcase
+ latch_data <= #1 1'b1;
+ end
+ else
+ begin
+ dr[31:24] <= #1 {dr[30:24], 1'b0};
+ latch_data <= #1 1'b0;
+ end
+ end
+ else if (acc_type == `DBG_WB_READ16)
+ begin
+ if(half & (~half_q))
+ begin
+ if (ptr[1])
+ dr[31:16] <= #1 input_data[15:0];
+ else
+ dr[31:16] <= #1 input_data[31:16];
+ latch_data <= #1 1'b1;
+ end
+ else
+ begin
+ dr[31:16] <= #1 {dr[30:16], 1'b0};
+ latch_data <= #1 1'b0;
+ end
+ end
+ else if (acc_type == `DBG_WB_READ32)
+ begin
+ if(long & (~long_q))
+ begin
+ dr[31:0] <= #1 input_data[31:0];
+ latch_data <= #1 1'b1;
+ end
+ else
+ begin
+ dr[31:0] <= #1 {dr[30:0], 1'b0};
+ latch_data <= #1 1'b0;
+ end
+ end
+ end
+ else if (enable && (!addr_len_cnt_end))
+ begin
+ dr <= #1 {dr[`DBG_WB_DR_LEN -2:0], tdi_i};
+ end
+end
+
+
+
+assign cmd_cnt_en = enable & (~cmd_cnt_end);
+
+
+// Command counter
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ cmd_cnt <= #1 {`DBG_WB_CMD_CNT_WIDTH{1'b0}};
+ else if (update_dr_i)
+ cmd_cnt <= #1 {`DBG_WB_CMD_CNT_WIDTH{1'b0}};
+ else if (cmd_cnt_en)
+ cmd_cnt <= #1 cmd_cnt + 1'b1;
+end
+
+
+// Assigning current command
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ curr_cmd <= #1 {`DBG_WB_CMD_LEN{1'b0}};
+ else if (update_dr_i)
+ curr_cmd <= #1 {`DBG_WB_CMD_LEN{1'b0}};
+ else if (cmd_cnt == (`DBG_WB_CMD_LEN -1))
+ curr_cmd <= #1 {dr[`DBG_WB_CMD_LEN-2 :0], tdi_i};
+end
+
+
+// Assigning current command
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ curr_cmd_go_q <= #1 1'b0;
+ else
+ curr_cmd_go_q <= #1 curr_cmd_go;
+end
+
+
+always @ (enable or cmd_cnt_end or addr_len_cnt_end or curr_cmd_wr_comm or curr_cmd_rd_comm or crc_cnt_end)
+begin
+ if (enable && (!addr_len_cnt_end))
+ begin
+ if (cmd_cnt_end && curr_cmd_wr_comm)
+ addr_len_cnt_en = 1'b1;
+ else if (crc_cnt_end && curr_cmd_rd_comm)
+ addr_len_cnt_en = 1'b1;
+ else
+ addr_len_cnt_en = 1'b0;
+ end
+ else
+ addr_len_cnt_en = 1'b0;
+end
+
+
+// Address/length counter
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ addr_len_cnt <= #1 6'h0;
+ else if (update_dr_i)
+ addr_len_cnt <= #1 6'h0;
+ else if (addr_len_cnt_en)
+ addr_len_cnt <= #1 addr_len_cnt + 1'b1;
+end
+
+
+always @ (enable or data_cnt_end or cmd_cnt_end or curr_cmd_go or acc_type_write or acc_type_read or crc_cnt_end)
+begin
+ if (enable && (!data_cnt_end))
+ begin
+ if (cmd_cnt_end && curr_cmd_go && acc_type_write)
+ data_cnt_en = 1'b1;
+ else if (crc_cnt_end && curr_cmd_go && acc_type_read)
+ data_cnt_en = 1'b1;
+ else
+ data_cnt_en = 1'b0;
+ end
+ else
+ data_cnt_en = 1'b0;
+end
+
+
+// Data counter
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ data_cnt <= #1 {`DBG_WB_DATA_CNT_WIDTH{1'b0}};
+ else if (update_dr_i)
+ data_cnt <= #1 {`DBG_WB_DATA_CNT_WIDTH{1'b0}};
+ else if (data_cnt_en)
+ data_cnt <= #1 data_cnt + 1'b1;
+end
+
+
+
+// Upper limit. Data counter counts until this value is reached.
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ data_cnt_limit <= #1 {`DBG_WB_DATA_CNT_LIM_WIDTH{1'b0}};
+ else if (update_dr_i)
+ data_cnt_limit <= #1 len + 1'b1;
+end
+
+
+always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_wr_comm or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
+begin
+ if (enable && (!crc_cnt_end) && cmd_cnt_end)
+ begin
+ if (addr_len_cnt_end && curr_cmd_wr_comm)
+ crc_cnt_en = 1'b1;
+ else if (data_cnt_end && curr_cmd_go && acc_type_write)
+ crc_cnt_en = 1'b1;
+ else if (cmd_cnt_end && (curr_cmd_go && acc_type_read || curr_cmd_rd_comm))
+ crc_cnt_en = 1'b1;
+ else
+ crc_cnt_en = 1'b0;
+ end
+ else
+ crc_cnt_en = 1'b0;
+end
+
+
+// crc counter
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ crc_cnt <= #1 {`DBG_WB_CRC_CNT_WIDTH{1'b0}};
+ else if(crc_cnt_en)
+ crc_cnt <= #1 crc_cnt + 1'b1;
+ else if (update_dr_i)
+ crc_cnt <= #1 {`DBG_WB_CRC_CNT_WIDTH{1'b0}};
+end
+
+assign cmd_cnt_end = cmd_cnt == `DBG_WB_CMD_LEN;
+assign addr_len_cnt_end = addr_len_cnt == `DBG_WB_DR_LEN;
+assign crc_cnt_end = crc_cnt == `DBG_WB_CRC_CNT_WIDTH'd32;
+assign crc_cnt_31 = crc_cnt == `DBG_WB_CRC_CNT_WIDTH'd31;
+assign data_cnt_end = (data_cnt == {data_cnt_limit, 3'b000});
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ crc_cnt_end_q <= #1 1'b0;
+ cmd_cnt_end_q <= #1 1'b0;
+ data_cnt_end_q <= #1 1'b0;
+ addr_len_cnt_end_q <= #1 1'b0;
+ end
+ else
+ begin
+ crc_cnt_end_q <= #1 crc_cnt_end;
+ cmd_cnt_end_q <= #1 cmd_cnt_end;
+ data_cnt_end_q <= #1 data_cnt_end;
+ addr_len_cnt_end_q <= #1 addr_len_cnt_end;
+ end
+end
+
+
+// Status counter is made of 4 serialy connected registers
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ status_cnt <= #1 {`DBG_WB_STATUS_CNT_WIDTH{1'b0}};
+ else if (update_dr_i)
+ status_cnt <= #1 {`DBG_WB_STATUS_CNT_WIDTH{1'b0}};
+ else if (status_cnt_en)
+ status_cnt <= #1 status_cnt + 1'b1;
+end
+
+
+always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_wr_comm or curr_cmd_go or acc_type_write or acc_type_read or data_cnt_end or addr_len_cnt_end)
+begin
+ if (enable && (!status_cnt_end))
+ begin
+ if (crc_cnt_end && curr_cmd_wr_comm)
+ status_cnt_en = 1'b1;
+ else if (crc_cnt_end && curr_cmd_go && acc_type_write)
+ status_cnt_en = 1'b1;
+ else if (data_cnt_end && curr_cmd_go && acc_type_read)
+ status_cnt_en = 1'b1;
+ else if (addr_len_cnt_end && curr_cmd_rd_comm)
+ status_cnt_en = 1'b1;
+ else
+ status_cnt_en = 1'b0;
+ end
+ else
+ status_cnt_en = 1'b0;
+end
+
+
+assign status_cnt_end = status_cnt == `DBG_WB_STATUS_LEN;
+
+
+// Latching acc_type, address and length
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ acc_type <= #1 {`DBG_WB_ACC_TYPE_LEN{1'b0}};
+ adr <= #1 {`DBG_WB_ADR_LEN{1'b0}};
+ len <= #1 {`DBG_WB_LEN_LEN{1'b0}};
+ set_addr <= #1 1'b0;
+ end
+ else if(crc_cnt_end && (!crc_cnt_end_q) && crc_match_i && curr_cmd_wr_comm)
+ begin
+ acc_type <= #1 dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1 : `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN];
+ adr <= #1 dr[`DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1 : `DBG_WB_LEN_LEN];
+ len <= #1 dr[`DBG_WB_LEN_LEN -1:0];
+ set_addr <= #1 1'b1;
+ end
+ else if(wb_end_tck) // Writing back the address
+ begin
+ adr <= #1 wb_adr_dsff;
+ end
+ else
+ set_addr <= #1 1'b0;
+end
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ crc_match_reg <= #1 1'b0;
+ else if(crc_cnt_end & (~crc_cnt_end_q))
+ crc_match_reg <= #1 crc_match_i;
+end
+
+
+// Length counter
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ len_var <= #1 {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
+ else if(update_dr_i)
+ len_var <= #1 len + 1'b1;
+ else if (start_rd_tck)
+ begin
+ case (acc_type) // synthesis parallel_case
+ `DBG_WB_READ8 :
+ if (len_var > 'd1)
+ len_var <= #1 len_var - 1'd1;
+ else
+ len_var <= #1 {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
+ `DBG_WB_READ16:
+ if (len_var > 'd2)
+ len_var <= #1 len_var - 2'd2;
+ else
+ len_var <= #1 {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
+ `DBG_WB_READ32:
+ if (len_var > 'd4)
+ len_var <= #1 len_var - 3'd4;
+ else
+ len_var <= #1 {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
+ default: len_var <= #1 {1'bx, {`DBG_WB_LEN_LEN{1'bx}}};
+ endcase
+ end
+end
+
+
+assign len_eq_0 = len_var == 'h0;
+
+
+assign byte = data_cnt[2:0] == 3'd7;
+assign half = data_cnt[3:0] == 4'd15;
+assign long = data_cnt[4:0] == 5'd31;
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ byte_q <= #1 1'b0;
+ half_q <= #1 1'b0;
+ long_q <= #1 1'b0;
+ end
+ else
+ begin
+ byte_q <= #1 byte;
+ half_q <= #1 half;
+ long_q <= #1 long;
+ end
+end
+
+
+// Start wishbone write cycle
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ start_wr_tck <= #1 1'b0;
+ wb_dat_tmp <= #1 32'h0;
+ end
+ else if (curr_cmd_go && acc_type_write)
+ begin
+ case (acc_type) // synthesis parallel_case full_case
+ `DBG_WB_WRITE8 : begin
+ if (byte_q)
+ begin
+ start_wr_tck <= #1 1'b1;
+ wb_dat_tmp <= #1 {4{dr[7:0]}};
+ end
+ else
+ begin
+ start_wr_tck <= #1 1'b0;
+ end
+ end
+ `DBG_WB_WRITE16 : begin
+ if (half_q)
+ begin
+ start_wr_tck <= #1 1'b1;
+ wb_dat_tmp <= #1 {2{dr[15:0]}};
+ end
+ else
+ begin
+ start_wr_tck <= #1 1'b0;
+ end
+ end
+ `DBG_WB_WRITE32 : begin
+ if (long_q)
+ begin
+ start_wr_tck <= #1 1'b1;
+ wb_dat_tmp <= #1 dr[31:0];
+ end
+ else
+ begin
+ start_wr_tck <= #1 1'b0;
+ end
+ end
+ endcase
+ end
+ else
+ start_wr_tck <= #1 1'b0;
+end
+
+
+// wb_dat_o in WB clk domain
+always @ (posedge wb_clk_i)
+begin
+ wb_dat_dsff <= #1 wb_dat_tmp;
+end
+
+assign wb_dat_o = wb_dat_dsff;
+
+
+// Start wishbone read cycle
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ start_rd_tck <= #1 1'b0;
+ else if (curr_cmd_go && (!curr_cmd_go_q) && acc_type_read) // First read after cmd is entered
+ start_rd_tck <= #1 1'b1;
+ else if ((!start_rd_tck) && curr_cmd_go && acc_type_read && (!len_eq_0) && (!fifo_full) && (!rd_tck_started))
+ start_rd_tck <= #1 1'b1;
+ else
+ start_rd_tck <= #1 1'b0;
+end
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ rd_tck_started <= #1 1'b0;
+ else if (update_dr_i || wb_end_tck && (!wb_end_tck_q))
+ rd_tck_started <= #1 1'b0;
+ else if (start_rd_tck)
+ rd_tck_started <= #1 1'b1;
+end
+
+
+
+always @ (posedge wb_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ start_rd_csff <= #1 1'b0;
+ start_wb_rd <= #1 1'b0;
+ start_wb_rd_q <= #1 1'b0;
+
+ start_wr_csff <= #1 1'b0;
+ start_wb_wr <= #1 1'b0;
+ start_wb_wr_q <= #1 1'b0;
+
+ set_addr_csff <= #1 1'b0;
+ set_addr_wb <= #1 1'b0;
+ set_addr_wb_q <= #1 1'b0;
+ end
+ else
+ begin
+ start_rd_csff <= #1 start_rd_tck;
+ start_wb_rd <= #1 start_rd_csff;
+ start_wb_rd_q <= #1 start_wb_rd;
+
+ start_wr_csff <= #1 start_wr_tck;
+ start_wb_wr <= #1 start_wr_csff;
+ start_wb_wr_q <= #1 start_wb_wr;
+
+ set_addr_csff <= #1 set_addr;
+ set_addr_wb <= #1 set_addr_csff;
+ set_addr_wb_q <= #1 set_addr_wb;
+ end
+end
+
+
+// wb_cyc_o
+always @ (posedge wb_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ wb_cyc_o <= #1 1'b0;
+ else if ((start_wb_wr && (!start_wb_wr_q)) || (start_wb_rd && (!start_wb_rd_q)))
+ wb_cyc_o <= #1 1'b1;
+ else if (wb_ack_i || wb_err_i)
+ wb_cyc_o <= #1 1'b0;
+end
+
+
+// wb_adr_o logic
+always @ (posedge wb_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ wb_adr_dsff <= #1 32'h0;
+ else if (set_addr_wb && (!set_addr_wb_q)) // Setting starting address
+ wb_adr_dsff <= #1 adr;
+ else if (wb_ack_i)
+ begin
+ if ((acc_type == `DBG_WB_WRITE8) || (acc_type == `DBG_WB_READ8))
+ wb_adr_dsff <= #1 wb_adr_dsff + 1'd1;
+ else if ((acc_type == `DBG_WB_WRITE16) || (acc_type == `DBG_WB_READ16))
+ wb_adr_dsff <= #1 wb_adr_dsff + 2'd2;
+ else
+ wb_adr_dsff <= #1 wb_adr_dsff + 3'd4;
+ end
+end
+
+
+assign wb_adr_o = wb_adr_dsff;
+
+
+// adr byte | short | long
+// 0 1000 1100 1111
+// 1 0100 err err
+// 2 0010 0011 err
+// 3 0001 err err
+// wb_sel_o logic
+
+always @ (posedge wb_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ wb_sel_dsff[3:0] <= #1 4'h0;
+ else
+ begin
+ case ({wb_adr_dsff[1:0], acc_type_8bit, acc_type_16bit, acc_type_32bit}) // synthesis parallel_case
+ {2'd0, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h8;
+ {2'd0, 3'b010} : wb_sel_dsff[3:0] <= #1 4'hC;
+ {2'd0, 3'b001} : wb_sel_dsff[3:0] <= #1 4'hF;
+ {2'd1, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h4;
+ {2'd2, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h2;
+ {2'd2, 3'b010} : wb_sel_dsff[3:0] <= #1 4'h3;
+ {2'd3, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h1;
+ default: wb_sel_dsff[3:0] <= #1 4'hx;
+ endcase
+ end
+end
+
+
+assign wb_sel_o = wb_sel_dsff;
+
+
+always @ (posedge wb_clk_i)
+begin
+ wb_we_dsff <= #1 curr_cmd_go && acc_type_write;
+end
+
+
+assign wb_we_o = wb_we_dsff;
+assign wb_cab_o = 1'b0;
+assign wb_stb_o = wb_cyc_o;
+assign wb_cti_o = 3'h0; // always performing single access
+assign wb_bte_o = 2'h0; // always performing single access
+
+
+
+// Logic for detecting end of transaction
+always @ (posedge wb_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ wb_end <= #1 1'b0;
+ else if (wb_ack_i || wb_err_i)
+ wb_end <= #1 1'b1;
+ else if (wb_end_rst)
+ wb_end <= #1 1'b0;
+end
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ wb_end_csff <= #1 1'b0;
+ wb_end_tck <= #1 1'b0;
+ wb_end_tck_q <= #1 1'b0;
+ end
+ else
+ begin
+ wb_end_csff <= #1 wb_end;
+ wb_end_tck <= #1 wb_end_csff;
+ wb_end_tck_q <= #1 wb_end_tck;
+ end
+end
+
+
+always @ (posedge wb_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ wb_end_rst_csff <= #1 1'b0;
+ wb_end_rst <= #1 1'b0;
+ end
+ else
+ begin
+ wb_end_rst_csff <= #1 wb_end_tck;
+ wb_end_rst <= #1 wb_end_rst_csff;
+ end
+end
+
+
+always @ (posedge wb_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ busy_wb <= #1 1'b0;
+ else if (wb_end_rst)
+ busy_wb <= #1 1'b0;
+ else if (wb_cyc_o)
+ busy_wb <= #1 1'b1;
+end
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ busy_csff <= #1 1'b0;
+ busy_tck <= #1 1'b0;
+
+ update_dr_csff <= #1 1'b0;
+ update_dr_wb <= #1 1'b0;
+ end
+ else
+ begin
+ busy_csff <= #1 busy_wb;
+ busy_tck <= #1 busy_csff;
+
+ update_dr_csff <= #1 update_dr_i;
+ update_dr_wb <= #1 update_dr_csff;
+ end
+end
+
+
+// Detecting WB error
+always @ (posedge wb_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ wb_error <= #1 1'b0;
+ else if(wb_err_i)
+ wb_error <= #1 1'b1;
+ else if(update_dr_wb) // error remains active until update_dr arrives
+ wb_error <= #1 1'b0;
+end
+
+
+// Detecting overrun when write operation.
+always @ (posedge wb_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ wb_overrun <= #1 1'b0;
+ else if(start_wb_wr && (!start_wb_wr_q) && wb_cyc_o)
+ wb_overrun <= #1 1'b1;
+ else if(update_dr_wb) // error remains active until update_dr arrives
+ wb_overrun <= #1 1'b0;
+end
+
+
+// Detecting underrun when read operation
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ underrun_tck <= #1 1'b0;
+ else if(latch_data && fifo_empty && (!data_cnt_end))
+ underrun_tck <= #1 1'b1;
+ else if(update_dr_i) // error remains active until update_dr arrives
+ underrun_tck <= #1 1'b0;
+end
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ wb_error_csff <= #1 1'b0;
+ wb_error_tck <= #1 1'b0;
+
+ wb_overrun_csff <= #1 1'b0;
+ wb_overrun_tck <= #1 1'b0;
+ end
+ else
+ begin
+ wb_error_csff <= #1 wb_error;
+ wb_error_tck <= #1 wb_error_csff;
+
+ wb_overrun_csff <= #1 wb_overrun;
+ wb_overrun_tck <= #1 wb_overrun_csff;
+ end
+end
+
+
+
+always @ (posedge wb_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ wishbone_ce_csff <= #1 1'b0;
+ mem_ptr_init <= #1 1'b0;
+ end
+ else
+ begin
+ wishbone_ce_csff <= #1 wishbone_ce_i;
+ mem_ptr_init <= #1 ~wishbone_ce_csff;
+ end
+end
+
+
+// Logic for latching data that is read from wishbone
+always @ (posedge wb_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ mem_ptr_dsff <= #1 3'h0;
+ else if(mem_ptr_init)
+ mem_ptr_dsff <= #1 3'h0;
+ else if (wb_ack_i)
+ begin
+ if (acc_type == `DBG_WB_READ8)
+ mem_ptr_dsff <= #1 mem_ptr_dsff + 1'd1;
+ else if (acc_type == `DBG_WB_READ16)
+ mem_ptr_dsff <= #1 mem_ptr_dsff + 2'd2;
+ end
+end
+
+
+// Logic for latching data that is read from wishbone
+always @ (posedge wb_clk_i)
+begin
+ if (wb_ack_i)
+ begin
+ case (wb_sel_dsff) // synthesis parallel_case
+ 4'b1000 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[31:24]; // byte
+ 4'b0100 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[23:16]; // byte
+ 4'b0010 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[15:08]; // byte
+ 4'b0001 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[07:00]; // byte
+
+ 4'b1100 : // half
+ begin
+ mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[31:24];
+ mem[mem_ptr_dsff[1:0]+1'b1] <= #1 wb_dat_i[23:16];
+ end
+ 4'b0011 : // half
+ begin
+ mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[15:08];
+ mem[mem_ptr_dsff[1:0]+1'b1] <= #1 wb_dat_i[07:00];
+ end
+ 4'b1111 : // long
+ begin
+ mem[0] <= #1 wb_dat_i[31:24];
+ mem[1] <= #1 wb_dat_i[23:16];
+ mem[2] <= #1 wb_dat_i[15:08];
+ mem[3] <= #1 wb_dat_i[07:00];
+ end
+ default : // long
+ begin
+ mem[0] <= #1 8'hxx;
+ mem[1] <= #1 8'hxx;
+ mem[2] <= #1 8'hxx;
+ mem[3] <= #1 8'hxx;
+ end
+ endcase
+ end
+end
+
+
+
+assign input_data = {mem[0], mem[1], mem[2], mem[3]};
+
+
+// Fifo counter and empty/full detection
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ fifo_cnt <= #1 3'h0;
+ else if (update_dr_i)
+ fifo_cnt <= #1 3'h0;
+ else if (wb_end_tck && (!wb_end_tck_q) && (!latch_data) && (!fifo_full)) // incrementing
+ begin
+ case (acc_type) // synthesis parallel_case
+ `DBG_WB_READ8 : fifo_cnt <= #1 fifo_cnt + 1'd1;
+ `DBG_WB_READ16: fifo_cnt <= #1 fifo_cnt + 2'd2;
+ `DBG_WB_READ32: fifo_cnt <= #1 fifo_cnt + 3'd4;
+ default: fifo_cnt <= #1 3'bxxx;
+ endcase
+ end
+ else if (!(wb_end_tck && (!wb_end_tck_q)) && latch_data && (!fifo_empty)) // decrementing
+ begin
+ case (acc_type) // synthesis parallel_case
+ `DBG_WB_READ8 : fifo_cnt <= #1 fifo_cnt - 1'd1;
+ `DBG_WB_READ16: fifo_cnt <= #1 fifo_cnt - 2'd2;
+ `DBG_WB_READ32: fifo_cnt <= #1 fifo_cnt - 3'd4;
+ default: fifo_cnt <= #1 3'bxxx;
+ endcase
+ end
+end
+
+
+assign fifo_full = fifo_cnt == 3'h4;
+assign fifo_empty = fifo_cnt == 3'h0;
+
+
+// TDO multiplexer
+always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or curr_cmd_wr_comm or
+ curr_cmd_rd_comm or curr_cmd_go or acc_type_write or acc_type_read or crc_match_i
+ or data_cnt_end or dr or data_cnt_end_q or crc_match_reg or status_cnt_en or status
+ or addr_len_cnt_end or addr_len_cnt_end_q)
+begin
+ if (pause_dr_i)
+ begin
+ tdo_o = busy_tck;
+ end
+ else if (crc_cnt_end && (!crc_cnt_end_q) && (curr_cmd_wr_comm || curr_cmd_go && acc_type_write ))
+ begin
+ tdo_o = ~crc_match_i;
+ end
+ else if (curr_cmd_go && acc_type_read && crc_cnt_end && (!data_cnt_end))
+ begin
+ tdo_o = dr[31];
+ end
+ else if (curr_cmd_go && acc_type_read && data_cnt_end && (!data_cnt_end_q))
+ begin
+ tdo_o = ~crc_match_reg;
+ end
+ else if (curr_cmd_rd_comm && addr_len_cnt_end && (!addr_len_cnt_end_q))
+ begin
+ tdo_o = ~crc_match_reg;
+ end
+ else if (curr_cmd_rd_comm && crc_cnt_end && (!addr_len_cnt_end))
+ begin
+ tdo_o = dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1];
+ end
+ else if (status_cnt_en)
+ begin
+ tdo_o = status[3];
+ end
+ else
+ begin
+ tdo_o = 1'b0;
+ end
+end
+
+// Status register
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ status <= #1 {`DBG_WB_STATUS_LEN{1'b0}};
+ end
+ else if(crc_cnt_end && (!crc_cnt_end_q) && (!(curr_cmd_go && acc_type_read)))
+ begin
+ status <= #1 {1'b0, wb_error_tck, wb_overrun_tck, crc_match_i};
+ end
+ else if (data_cnt_end && (!data_cnt_end_q) && curr_cmd_go && acc_type_read)
+ begin
+ status <= #1 {1'b0, wb_error_tck, underrun_tck, crc_match_reg};
+ end
+ else if (addr_len_cnt_end && (!addr_len_cnt_end) && curr_cmd_rd_comm)
+ begin
+ status <= #1 {1'b0, 1'b0, 1'b0, crc_match_reg};
+ end
+ else if (shift_dr_i && (!status_cnt_end))
+ begin
+ status <= #1 {status[`DBG_WB_STATUS_LEN -2:0], status[`DBG_WB_STATUS_LEN -1]};
+ end
+end
+// Following status is shifted out (MSB first):
+// 3. bit: 1 if crc is OK, else 0
+// 2. bit: 1'b0
+// 1. bit: 1 if WB error occured, else 0
+// 0. bit: 1 if overrun occured during write (data couldn't be written fast enough)
+// or underrun occured during read (data couldn't be read fast enough)
+
+
+endmodule
+
tags/rel_23/rtl/verilog/dbg_wb.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_23/rtl/verilog/dbg_top.v
===================================================================
--- tags/rel_23/rtl/verilog/dbg_top.v (nonexistent)
+++ tags/rel_23/rtl/verilog/dbg_top.v (revision 148)
@@ -0,0 +1,798 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbg_top.v ////
+//// ////
+//// ////
+//// This file is part of the SoC Debug Interface. ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2004 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.44 2004/03/28 20:27:02 igorm
+// New release of the debug interface (3rd. release).
+//
+// Revision 1.43 2004/03/22 16:35:46 igorm
+// Temp version before changing dbg interface.
+//
+// Revision 1.42 2004/01/30 10:24:31 mohor
+// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
+// turned on.
+//
+// Revision 1.41 2004/01/25 14:04:18 mohor
+// All flipflops are reset.
+//
+// Revision 1.40 2004/01/20 14:23:47 mohor
+// Define name changed.
+//
+// Revision 1.39 2004/01/19 07:32:41 simons
+// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
+//
+// Revision 1.38 2004/01/18 09:22:47 simons
+// Sensitivity list updated.
+//
+// Revision 1.37 2004/01/17 17:01:14 mohor
+// Almost finished.
+//
+// Revision 1.36 2004/01/16 14:51:33 mohor
+// cpu registers added.
+//
+// Revision 1.35 2004/01/14 22:59:16 mohor
+// Temp version.
+//
+// Revision 1.34 2003/12/23 15:07:34 mohor
+// New directory structure. New version of the debug interface.
+// Files that are not needed removed.
+//
+// Revision 1.33 2003/10/23 16:17:01 mohor
+// CRC logic changed.
+//
+// Revision 1.32 2003/09/18 14:00:47 simons
+// Lower two address lines must be always zero.
+//
+// Revision 1.31 2003/09/17 14:38:57 simons
+// WB_CNTL register added, some syncronization fixes.
+//
+// Revision 1.30 2003/08/28 13:55:22 simons
+// Three more chains added for cpu debug access.
+//
+// Revision 1.29 2003/07/31 12:19:49 simons
+// Multiple cpu support added.
+//
+// Revision 1.28 2002/11/06 14:22:41 mohor
+// Trst signal is not inverted here any more. Inverted on higher layer !!!.
+//
+// Revision 1.27 2002/10/10 02:42:55 mohor
+// WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added).
+// Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value,
+// wb_cyc_o is negated.
+//
+// Revision 1.26 2002/05/07 14:43:59 mohor
+// mon_cntl_o signals that controls monitor mux added.
+//
+// Revision 1.25 2002/04/22 12:54:11 mohor
+// Signal names changed to lower case.
+//
+// Revision 1.24 2002/04/17 13:17:01 mohor
+// Intentional error removed.
+//
+// Revision 1.23 2002/04/17 11:16:33 mohor
+// A block for checking possible simulation/synthesis missmatch added.
+//
+// Revision 1.22 2002/03/12 10:31:53 mohor
+// tap_top and dbg_top modules are put into two separate modules. tap_top
+// contains only tap state machine and related logic. dbg_top contains all
+// logic necessery for debugging.
+//
+// Revision 1.21 2002/03/08 15:28:16 mohor
+// Structure changed. Hooks for jtag chain added.
+//
+// Revision 1.20 2002/02/06 12:23:09 mohor
+// latched_jtag_ir used when muxing TDO instead of JTAG_IR.
+//
+// Revision 1.19 2002/02/05 13:34:51 mohor
+// Stupid bug that was entered by previous update fixed.
+//
+// Revision 1.18 2002/02/05 12:41:01 mohor
+// trst synchronization is not needed and was removed.
+//
+// Revision 1.17 2002/01/25 07:58:35 mohor
+// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
+// not filled-in. Tested in hw.
+//
+// Revision 1.16 2001/12/20 11:17:26 mohor
+// TDO and TDO Enable signal are separated into two signals.
+//
+// Revision 1.15 2001/12/05 13:28:21 mohor
+// trst signal is synchronized to wb_clk_i.
+//
+// Revision 1.14 2001/11/28 09:36:15 mohor
+// Register length fixed.
+//
+// Revision 1.13 2001/11/27 13:37:43 mohor
+// CRC is returned when chain selection data is transmitted.
+//
+// Revision 1.12 2001/11/26 10:47:09 mohor
+// Crc generation is different for read or write commands. Small synthesys fixes.
+//
+// Revision 1.11 2001/11/14 10:10:41 mohor
+// Wishbone data latched on wb_clk_i instead of risc_clk.
+//
+// Revision 1.10 2001/11/12 01:11:27 mohor
+// Reset signals are not combined any more.
+//
+// Revision 1.9 2001/10/19 11:40:01 mohor
+// dbg_timescale.v changed to timescale.v This is done for the simulation of
+// few different cores in a single project.
+//
+// Revision 1.8 2001/10/17 10:39:03 mohor
+// bs_chain_o added.
+//
+// Revision 1.7 2001/10/16 10:09:56 mohor
+// Signal names changed to lowercase.
+//
+//
+// Revision 1.6 2001/10/15 09:55:47 mohor
+// Wishbone interface added, few fixes for better performance,
+// hooks for boundary scan testing added.
+//
+// Revision 1.5 2001/09/24 14:06:42 mohor
+// Changes connected to the OpenRISC access (SPR read, SPR write).
+//
+// Revision 1.4 2001/09/20 10:11:25 mohor
+// Working version. Few bugs fixed, comments added.
+//
+// Revision 1.3 2001/09/19 11:55:13 mohor
+// Asynchronous set/reset not used in trace any more.
+//
+// Revision 1.2 2001/09/18 14:13:47 mohor
+// Trace fixed. Some registers changed, trace simplified.
+//
+// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
+// Initial official release.
+//
+// Revision 1.3 2001/06/01 22:22:35 mohor
+// This is a backup. It is not a fully working version. Not for use, yet.
+//
+// Revision 1.2 2001/05/18 13:10:00 mohor
+// Headers changed. All additional information is now avaliable in the README.txt file.
+//
+// Revision 1.1.1.1 2001/05/18 06:35:02 mohor
+// Initial release
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "dbg_defines.v"
+`include "dbg_cpu_defines.v"
+
+// Top module
+module dbg_top(
+ // JTAG signals
+ tck_i,
+ tdi_i,
+ tdo_o,
+ rst_i,
+
+ // TAP states
+ shift_dr_i,
+ pause_dr_i,
+ update_dr_i,
+
+ // Instructions
+ debug_select_i
+
+
+ `ifdef DBG_WISHBONE_SUPPORTED
+ // WISHBONE common signals
+ ,
+ wb_clk_i,
+
+ // WISHBONE master interface
+ wb_adr_o,
+ wb_dat_o,
+ wb_dat_i,
+ wb_cyc_o,
+ wb_stb_o,
+ wb_sel_o,
+ wb_we_o,
+ wb_ack_i,
+ wb_cab_o,
+ wb_err_i,
+ wb_cti_o,
+ wb_bte_o
+ `endif
+
+ `ifdef DBG_CPU0_SUPPORTED
+ // CPU signals
+ ,
+ cpu0_clk_i,
+ cpu0_addr_o,
+ cpu0_data_i,
+ cpu0_data_o,
+ cpu0_bp_i,
+ cpu0_stall_o,
+ cpu0_stb_o,
+ cpu0_we_o,
+ cpu0_ack_i,
+ cpu0_rst_o
+ `endif
+
+ `ifdef DBG_CPU1_SUPPORTED
+ // CPU signals
+ ,
+ cpu1_clk_i,
+ cpu1_addr_o,
+ cpu1_data_i,
+ cpu1_data_o,
+ cpu1_bp_i,
+ cpu1_stall_o,
+ cpu1_stb_o,
+ cpu1_we_o,
+ cpu1_ack_i,
+ cpu1_rst_o
+ `endif
+
+ );
+
+
+// JTAG signals
+input tck_i;
+input tdi_i;
+output tdo_o;
+input rst_i;
+
+// TAP states
+input shift_dr_i;
+input pause_dr_i;
+input update_dr_i;
+
+// Instructions
+input debug_select_i;
+
+`ifdef DBG_WISHBONE_SUPPORTED
+input wb_clk_i;
+output [31:0] wb_adr_o;
+output [31:0] wb_dat_o;
+input [31:0] wb_dat_i;
+output wb_cyc_o;
+output wb_stb_o;
+output [3:0] wb_sel_o;
+output wb_we_o;
+input wb_ack_i;
+output wb_cab_o;
+input wb_err_i;
+output [2:0] wb_cti_o;
+output [1:0] wb_bte_o;
+
+reg wishbone_module;
+reg wishbone_ce;
+wire tdi_wb;
+wire tdo_wb;
+wire crc_en_wb;
+wire shift_crc_wb;
+`else
+wire crc_en_wb = 1'b0;
+wire shift_crc_wb = 1'b0;
+`endif
+
+`ifdef DBG_CPU0_SUPPORTED
+// CPU signals
+input cpu0_clk_i;
+output [31:0] cpu0_addr_o;
+input [31:0] cpu0_data_i;
+output [31:0] cpu0_data_o;
+input cpu0_bp_i;
+output cpu0_stall_o;
+output cpu0_stb_o;
+output cpu0_we_o;
+input cpu0_ack_i;
+output cpu0_rst_o;
+
+reg cpu0_debug_module;
+reg cpu0_ce;
+wire cpu0_tdi;
+wire cpu0_tdo;
+wire cpu0_crc_en;
+wire cpu0_shift_crc;
+`else
+wire cpu0_crc_en = 1'b0;
+wire cpu0_shift_crc = 1'b0;
+`endif
+
+`ifdef DBG_CPU1_SUPPORTED
+input cpu1_clk_i;
+output [31:0] cpu1_addr_o;
+input [31:0] cpu1_data_i;
+output [31:0] cpu1_data_o;
+input cpu1_bp_i;
+output cpu1_stall_o;
+output cpu1_stb_o;
+output cpu1_we_o;
+input cpu1_ack_i;
+output cpu1_rst_o;
+
+reg cpu1_debug_module;
+reg cpu1_ce;
+wire cpu1_tdi;
+wire cpu1_tdo;
+wire cpu1_crc_en;
+wire cpu1_shift_crc;
+`else
+wire cpu1_crc_en = 1'b0;
+wire cpu1_shift_crc = 1'b0;
+`endif
+
+
+reg [`DBG_TOP_DATA_CNT -1:0] data_cnt;
+reg [`DBG_TOP_CRC_CNT -1:0] crc_cnt;
+reg [`DBG_TOP_STATUS_CNT_WIDTH -1:0] status_cnt;
+reg [`DBG_TOP_MODULE_DATA_LEN -1:0] module_dr;
+reg [`DBG_TOP_MODULE_ID_LENGTH -1:0] module_id;
+
+wire module_latch_en;
+wire data_cnt_end;
+wire crc_cnt_end;
+wire status_cnt_end;
+reg crc_cnt_end_q;
+reg module_select;
+reg module_select_error;
+wire crc_out;
+wire crc_match;
+
+wire data_shift_en;
+wire selecting_command;
+
+reg tdo_o;
+
+
+
+
+wire shift_crc;
+
+// data counter
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ data_cnt <= #1 {`DBG_TOP_DATA_CNT{1'b0}};
+ else if(shift_dr_i & (~data_cnt_end))
+ data_cnt <= #1 data_cnt + 1'b1;
+ else if (update_dr_i)
+ data_cnt <= #1 {`DBG_TOP_DATA_CNT{1'b0}};
+end
+
+
+assign data_cnt_end = data_cnt == `DBG_TOP_MODULE_DATA_LEN;
+
+
+// crc counter
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ crc_cnt <= #1 {`DBG_TOP_CRC_CNT{1'b0}};
+ else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & module_select)
+ crc_cnt <= #1 crc_cnt + 1'b1;
+ else if (update_dr_i)
+ crc_cnt <= #1 {`DBG_TOP_CRC_CNT{1'b0}};
+end
+
+assign crc_cnt_end = crc_cnt == `DBG_TOP_CRC_LEN;
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ crc_cnt_end_q <= #1 1'b0;
+ else
+ crc_cnt_end_q <= #1 crc_cnt_end;
+end
+
+
+// status counter
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ status_cnt <= #1 {`DBG_TOP_STATUS_CNT_WIDTH{1'b0}};
+ else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
+ status_cnt <= #1 status_cnt + 1'b1;
+ else if (update_dr_i)
+ status_cnt <= #1 {`DBG_TOP_STATUS_CNT_WIDTH{1'b0}};
+end
+
+assign status_cnt_end = status_cnt == `DBG_TOP_STATUS_LEN;
+
+
+assign selecting_command = shift_dr_i & (data_cnt == `DBG_TOP_DATA_CNT'h0) & debug_select_i;
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ module_select <= #1 1'b0;
+ else if(selecting_command & tdi_i) // Chain select
+ module_select <= #1 1'b1;
+ else if (update_dr_i)
+ module_select <= #1 1'b0;
+end
+
+
+always @ (module_id)
+begin
+ `ifdef DBG_CPU0_SUPPORTED
+ cpu0_debug_module <= #1 1'b0;
+ `endif
+ `ifdef DBG_CPU1_SUPPORTED
+ cpu1_debug_module <= #1 1'b0;
+ `endif
+ `ifdef DBG_WISHBONE_SUPPORTED
+ wishbone_module <= #1 1'b0;
+ `endif
+ module_select_error <= #1 1'b0;
+
+ case (module_id) /* synthesis parallel_case */
+ `ifdef DBG_CPU0_SUPPORTED
+ `DBG_TOP_CPU0_DEBUG_MODULE : cpu0_debug_module <= #1 1'b1;
+ `endif
+ `ifdef DBG_CPU1_SUPPORTED
+ `DBG_TOP_CPU1_DEBUG_MODULE : cpu1_debug_module <= #1 1'b1;
+ `endif
+ `ifdef DBG_WISHBONE_SUPPORTED
+ `DBG_TOP_WISHBONE_DEBUG_MODULE : wishbone_module <= #1 1'b1;
+ `endif
+ default : module_select_error <= #1 1'b1;
+ endcase
+end
+
+
+assign module_latch_en = module_select & crc_cnt_end & (~crc_cnt_end_q);
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ module_id <= {`DBG_TOP_MODULE_ID_LENGTH{1'b1}};
+ else if(module_latch_en & crc_match)
+ module_id <= #1 module_dr[`DBG_TOP_MODULE_DATA_LEN -2:0];
+end
+
+
+assign data_shift_en = shift_dr_i & (~data_cnt_end);
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ module_dr <= #1 `DBG_TOP_MODULE_DATA_LEN'h0;
+ else if (data_shift_en)
+ module_dr[`DBG_TOP_MODULE_DATA_LEN -1:0] <= #1 {module_dr[`DBG_TOP_MODULE_DATA_LEN -2:0], tdi_i};
+end
+
+
+// Calculating crc for input data
+dbg_crc32_d1 i_dbg_crc32_d1_in
+ (
+ .data (tdi_i),
+ .enable (shift_dr_i),
+ .shift (1'b0),
+ .rst (rst_i),
+ .sync_rst (update_dr_i),
+ .crc_out (),
+ .clk (tck_i),
+ .crc_match (crc_match)
+ );
+
+
+reg tdo_module_select;
+wire crc_en;
+wire crc_en_dbg;
+reg crc_started;
+
+assign crc_en = crc_en_dbg | crc_en_wb | cpu1_crc_en | cpu0_crc_en;
+
+assign crc_en_dbg = shift_dr_i & crc_cnt_end & (~status_cnt_end);
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ crc_started <= #1 1'b0;
+ else if (crc_en)
+ crc_started <= #1 1'b1;
+ else if (update_dr_i)
+ crc_started <= #1 1'b0;
+end
+
+
+reg tdo_tmp;
+
+
+// Calculating crc for input data
+dbg_crc32_d1 i_dbg_crc32_d1_out
+ (
+ .data (tdo_tmp),
+ .enable (crc_en), // enable has priority
+// .shift (1'b0),
+ .shift (shift_dr_i & crc_started & (~crc_en)),
+ .rst (rst_i),
+ .sync_rst (update_dr_i),
+ .crc_out (crc_out),
+ .clk (tck_i),
+ .crc_match ()
+ );
+
+// Following status is shifted out:
+// 1. bit: 0 if crc is OK, else 1
+// 2. bit: 0 if existing module_id is selected, 1 if non-existing module_id is selected
+// 3. bit: 0 (always)
+// 4. bit: 0 (always)
+
+
+always @ (status_cnt or crc_match or module_select_error or crc_out)
+begin
+ case (status_cnt) /* synthesis full_case parallel_case */
+ `DBG_TOP_STATUS_CNT_WIDTH'd0 : begin
+ tdo_module_select = ~crc_match;
+ end
+ `DBG_TOP_STATUS_CNT_WIDTH'd1 : begin
+ tdo_module_select = module_select_error;
+ end
+ `DBG_TOP_STATUS_CNT_WIDTH'd2 : begin
+ tdo_module_select = 1'b0;
+ end
+ `DBG_TOP_STATUS_CNT_WIDTH'd3 : begin
+ tdo_module_select = 1'b0;
+ end
+ `DBG_TOP_STATUS_CNT_WIDTH'd4 : begin
+ tdo_module_select = crc_out;
+ end
+ endcase
+end
+
+
+
+
+assign shift_crc = shift_crc_wb | cpu1_shift_crc | cpu0_shift_crc;
+
+always @ (shift_crc or crc_out or tdo_module_select
+`ifdef DBG_WISHBONE_SUPPORTED
+ or wishbone_ce or tdo_wb
+`endif
+`ifdef DBG_CPU0_SUPPORTED
+ or cpu0_ce or cpu0_tdo
+`endif
+`ifdef DBG_CPU1_SUPPORTED
+ or cpu1_ce or cpu1_tdo
+`endif
+ )
+begin
+ if (shift_crc) // shifting crc
+ tdo_tmp = crc_out;
+ `ifdef DBG_WISHBONE_SUPPORTED
+ else if (wishbone_ce) // shifting data from wb
+ tdo_tmp = tdo_wb;
+ `endif
+ `ifdef DBG_CPU0_SUPPORTED
+ else if (cpu0_ce) // shifting data from cpu
+ tdo_tmp = cpu0_tdo;
+ `endif
+ `ifdef DBG_CPU1_SUPPORTED
+ else if (cpu1_ce) // shifting data from cpu
+ tdo_tmp = cpu1_tdo;
+ `endif
+ else
+ tdo_tmp = tdo_module_select;
+end
+
+
+always @ (negedge tck_i)
+begin
+ tdo_o <= #1 tdo_tmp;
+end
+
+
+
+
+// Signals for WISHBONE module
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ `ifdef DBG_WISHBONE_SUPPORTED
+ wishbone_ce <= #1 1'b0;
+ `endif
+ `ifdef DBG_CPU0_SUPPORTED
+ cpu0_ce <= #1 1'b0;
+ `endif
+ `ifdef DBG_CPU1_SUPPORTED
+ cpu1_ce <= #1 1'b0;
+ `endif
+ end
+ else if(selecting_command & (~tdi_i))
+ begin
+ `ifdef DBG_WISHBONE_SUPPORTED
+ if (wishbone_module) // wishbone CE
+ wishbone_ce <= #1 1'b1;
+ `endif
+ `ifdef DBG_CPU0_SUPPORTED
+ if (cpu0_debug_module) // CPU CE
+ cpu0_ce <= #1 1'b1;
+ `endif
+ `ifdef DBG_CPU1_SUPPORTED
+ if (cpu1_debug_module) // CPU CE
+ cpu1_ce <= #1 1'b1;
+ `endif
+ end
+ else if (update_dr_i)
+ begin
+ `ifdef DBG_WISHBONE_SUPPORTED
+ wishbone_ce <= #1 1'b0;
+ `endif
+ `ifdef DBG_CPU0_SUPPORTED
+ cpu0_ce <= #1 1'b0;
+ `endif
+ `ifdef DBG_CPU1_SUPPORTED
+ cpu1_ce <= #1 1'b0;
+ `endif
+ end
+end
+
+
+`ifdef DBG_WISHBONE_SUPPORTED
+assign tdi_wb = wishbone_ce & tdi_i;
+`endif
+
+`ifdef DBG_CPU0_SUPPORTED
+assign cpu0_tdi = cpu0_ce & tdi_i;
+`endif
+`ifdef DBG_CPU1_SUPPORTED
+assign cpu1_tdi = cpu1_ce & tdi_i;
+`endif
+
+
+`ifdef DBG_WISHBONE_SUPPORTED
+// Connecting wishbone module
+dbg_wb i_dbg_wb (
+ // JTAG signals
+ .tck_i (tck_i),
+ .tdi_i (tdi_wb),
+ .tdo_o (tdo_wb),
+
+ // TAP states
+ .shift_dr_i (shift_dr_i),
+ .pause_dr_i (pause_dr_i),
+ .update_dr_i (update_dr_i),
+
+ .wishbone_ce_i (wishbone_ce),
+ .crc_match_i (crc_match),
+ .crc_en_o (crc_en_wb),
+ .shift_crc_o (shift_crc_wb),
+ .rst_i (rst_i),
+
+ // WISHBONE common signals
+ .wb_clk_i (wb_clk_i),
+
+ // WISHBONE master interface
+ .wb_adr_o (wb_adr_o),
+ .wb_dat_o (wb_dat_o),
+ .wb_dat_i (wb_dat_i),
+ .wb_cyc_o (wb_cyc_o),
+ .wb_stb_o (wb_stb_o),
+ .wb_sel_o (wb_sel_o),
+ .wb_we_o (wb_we_o),
+ .wb_ack_i (wb_ack_i),
+ .wb_cab_o (wb_cab_o),
+ .wb_err_i (wb_err_i),
+ .wb_cti_o (wb_cti_o),
+ .wb_bte_o (wb_bte_o)
+ );
+`endif
+
+
+
+`ifdef DBG_CPU0_SUPPORTED
+dbg_cpu i_dbg_cpu_or1k (
+ // JTAG signals
+ .tck_i (tck_i),
+ .tdi_i (cpu0_tdi),
+ .tdo_o (cpu0_tdo),
+
+ // TAP states
+ .shift_dr_i (shift_dr_i),
+ .pause_dr_i (pause_dr_i),
+ .update_dr_i (update_dr_i),
+
+ .cpu_ce_i (cpu0_ce),
+ .crc_match_i (crc_match),
+ .crc_en_o (cpu0_crc_en),
+ .shift_crc_o (cpu0_shift_crc),
+ .rst_i (rst_i),
+
+ // CPU signals
+ .cpu_clk_i (cpu0_clk_i),
+ .cpu_addr_o (cpu0_addr_o),
+ .cpu_data_i (cpu0_data_i),
+ .cpu_data_o (cpu0_data_o),
+ .cpu_bp_i (cpu0_bp_i),
+ .cpu_stall_o (cpu0_stall_o),
+ .cpu_stb_o (cpu0_stb_o),
+ .cpu_we_o (cpu0_we_o),
+ .cpu_ack_i (cpu0_ack_i),
+ .cpu_rst_o (cpu0_rst_o)
+ );
+
+`endif // DBG_CPU0_SUPPORTED
+
+
+
+`ifdef DBG_CPU1_SUPPORTED
+// Connecting cpu module
+dbg_cpu i_dbg_cpu_8051 (
+ // JTAG signals
+ .tck_i (tck_i),
+ .tdi_i (cpu1_tdi),
+ .tdo_o (cpu1_tdo),
+
+ // TAP states
+ .shift_dr_i (shift_dr_i),
+ .pause_dr_i (pause_dr_i),
+ .update_dr_i (update_dr_i),
+
+ .cpu_ce_i (cpu1_ce),
+ .crc_match_i (crc_match),
+ .crc_en_o (cpu1_crc_en),
+ .shift_crc_o (cpu1_shift_crc),
+ .rst_i (rst_i),
+
+ // CPU signals
+ .cpu_clk_i (cpu1_clk_i),
+ .cpu_addr_o (cpu1_addr_o),
+ .cpu_data_i (cpu1_data_i),
+ .cpu_data_o (cpu1_data_o),
+ .cpu_bp_i (cpu1_bp_i),
+ .cpu_stall_o (cpu1_stall_o),
+ .cpu_stb_o (cpu1_stb_o),
+ .cpu_we_o (cpu1_we_o),
+ .cpu_ack_i (cpu1_ack_i),
+ .cpu_rst_o (cpu1_rst_o)
+ );
+`endif
+
+
+endmodule
Index: tags/rel_23/rtl/verilog/dbg_defines.v
===================================================================
--- tags/rel_23/rtl/verilog/dbg_defines.v (nonexistent)
+++ tags/rel_23/rtl/verilog/dbg_defines.v (revision 148)
@@ -0,0 +1,150 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbg_defines.v ////
+//// ////
+//// ////
+//// This file is part of the SoC Debug Interface. ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2004 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.19 2004/03/28 20:27:02 igorm
+// New release of the debug interface (3rd. release).
+//
+// Revision 1.18 2004/03/22 16:35:46 igorm
+// Temp version before changing dbg interface.
+//
+// Revision 1.17 2004/01/30 10:24:30 mohor
+// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
+// turned on.
+//
+// Revision 1.16 2004/01/20 14:23:45 mohor
+// Define name changed.
+//
+// Revision 1.15 2003/12/23 15:07:34 mohor
+// New directory structure. New version of the debug interface.
+// Files that are not needed removed.
+//
+// Revision 1.14 2003/10/23 16:17:00 mohor
+// CRC logic changed.
+//
+// Revision 1.13 2003/10/21 09:48:31 simons
+// Mbist support added.
+//
+// Revision 1.12 2003/09/17 14:38:57 simons
+// WB_CNTL register added, some syncronization fixes.
+//
+// Revision 1.11 2003/08/28 13:55:21 simons
+// Three more chains added for cpu debug access.
+//
+// Revision 1.10 2003/07/31 12:19:49 simons
+// Multiple cpu support added.
+//
+// Revision 1.9 2002/05/07 14:43:59 mohor
+// mon_cntl_o signals that controls monitor mux added.
+//
+// Revision 1.8 2002/01/25 07:58:34 mohor
+// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
+// not filled-in. Tested in hw.
+//
+// Revision 1.7 2001/12/06 10:08:06 mohor
+// Warnings from synthesys tools fixed.
+//
+// Revision 1.6 2001/11/28 09:38:30 mohor
+// Trace disabled by default.
+//
+// Revision 1.5 2001/10/15 09:55:47 mohor
+// Wishbone interface added, few fixes for better performance,
+// hooks for boundary scan testing added.
+//
+// Revision 1.4 2001/09/24 14:06:42 mohor
+// Changes connected to the OpenRISC access (SPR read, SPR write).
+//
+// Revision 1.3 2001/09/20 10:11:25 mohor
+// Working version. Few bugs fixed, comments added.
+//
+// Revision 1.2 2001/09/18 14:13:47 mohor
+// Trace fixed. Some registers changed, trace simplified.
+//
+// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
+// Initial official release.
+//
+// Revision 1.3 2001/06/01 22:22:35 mohor
+// This is a backup. It is not a fully working version. Not for use, yet.
+//
+// Revision 1.2 2001/05/18 13:10:00 mohor
+// Headers changed. All additional information is now avaliable in the README.txt file.
+//
+// Revision 1.1.1.1 2001/05/18 06:35:08 mohor
+// Initial release
+//
+//
+
+
+// Length of the MODULE ID register
+`define DBG_TOP_MODULE_ID_LENGTH 4
+
+// Length of data
+`define DBG_TOP_MODULE_DATA_LEN `DBG_TOP_MODULE_ID_LENGTH + 1
+`define DBG_TOP_DATA_CNT 3
+
+// Length of status
+`define DBG_TOP_STATUS_LEN 3'd4
+`define DBG_TOP_STATUS_CNT_WIDTH 3
+
+// Length of the CRC
+`define DBG_TOP_CRC_LEN 32
+`define DBG_TOP_CRC_CNT 6
+
+// Chains
+`define DBG_TOP_WISHBONE_DEBUG_MODULE 4'h0
+`define DBG_TOP_CPU0_DEBUG_MODULE 4'h1
+`define DBG_TOP_CPU1_DEBUG_MODULE 4'h2
+
+// If WISHBONE sub-module is supported uncomment the folowing line
+`define DBG_WISHBONE_SUPPORTED
+
+// If CPU_0 sub-module is supported uncomment the folowing line
+`define DBG_CPU0_SUPPORTED
+
+// If CPU_1 sub-module is supported uncomment the folowing line
+`define DBG_CPU1_SUPPORTED
+
+// If more debug info is needed, uncomment the follofing line
+//`define DBG_MORE_INFO
+
Index: tags/rel_23/rtl/verilog/dbg_cpu.v
===================================================================
--- tags/rel_23/rtl/verilog/dbg_cpu.v (nonexistent)
+++ tags/rel_23/rtl/verilog/dbg_cpu.v (revision 148)
@@ -0,0 +1,956 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbg_cpu.v ////
+//// ////
+//// ////
+//// This file is part of the SoC Debug Interface. ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2004 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.9 2004/03/31 14:34:09 igorm
+// data_cnt_lim length changed to reduce number of warnings.
+//
+// Revision 1.8 2004/03/28 20:27:01 igorm
+// New release of the debug interface (3rd. release).
+//
+// Revision 1.7 2004/01/25 14:04:18 mohor
+// All flipflops are reset.
+//
+// Revision 1.6 2004/01/22 13:58:53 mohor
+// Port signals are all set to zero after reset.
+//
+// Revision 1.5 2004/01/19 07:32:41 simons
+// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
+//
+// Revision 1.4 2004/01/17 18:38:11 mohor
+// cpu_tall_o is set with cpu_stb_o or register.
+//
+// Revision 1.3 2004/01/17 18:01:24 mohor
+// New version.
+//
+// Revision 1.2 2004/01/17 17:01:14 mohor
+// Almost finished.
+//
+// Revision 1.1 2004/01/16 14:53:31 mohor
+// *** empty log message ***
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "dbg_cpu_defines.v"
+
+// Top module
+module dbg_cpu(
+ // JTAG signals
+ tck_i,
+ tdi_i,
+ tdo_o,
+
+ // TAP states
+ shift_dr_i,
+ pause_dr_i,
+ update_dr_i,
+
+ cpu_ce_i,
+ crc_match_i,
+ crc_en_o,
+ shift_crc_o,
+ rst_i,
+
+ // CPU
+ cpu_clk_i,
+ cpu_addr_o, cpu_data_i, cpu_data_o, cpu_bp_i, cpu_stall_o,
+ cpu_stb_o,
+ cpu_we_o, cpu_ack_i, cpu_rst_o
+
+ );
+
+// JTAG signals
+input tck_i;
+input tdi_i;
+output tdo_o;
+
+// TAP states
+input shift_dr_i;
+input pause_dr_i;
+input update_dr_i;
+
+input cpu_ce_i;
+input crc_match_i;
+output crc_en_o;
+output shift_crc_o;
+input rst_i;
+
+// CPU
+input cpu_clk_i;
+output [31:0] cpu_addr_o;
+output [31:0] cpu_data_o;
+input cpu_bp_i;
+output cpu_stall_o;
+input [31:0] cpu_data_i;
+output cpu_stb_o;
+output cpu_we_o;
+input cpu_ack_i;
+output cpu_rst_o;
+
+reg cpu_stb_o;
+wire cpu_reg_stall;
+reg tdo_o;
+reg cpu_ack_q;
+reg cpu_ack_csff;
+reg cpu_ack_tck;
+
+reg [31:0] cpu_dat_tmp, cpu_data_dsff;
+reg [31:0] cpu_addr_dsff;
+reg cpu_we_dsff;
+reg [`DBG_CPU_DR_LEN -1 :0] dr;
+wire enable;
+wire cmd_cnt_en;
+reg [`DBG_CPU_CMD_CNT_WIDTH -1:0] cmd_cnt;
+wire cmd_cnt_end;
+reg cmd_cnt_end_q;
+reg addr_len_cnt_en;
+reg [5:0] addr_len_cnt;
+wire addr_len_cnt_end;
+reg addr_len_cnt_end_q;
+reg crc_cnt_en;
+reg [`DBG_CPU_CRC_CNT_WIDTH -1:0] crc_cnt;
+wire crc_cnt_end;
+reg crc_cnt_end_q;
+reg data_cnt_en;
+reg [`DBG_CPU_DATA_CNT_WIDTH:0] data_cnt;
+reg [`DBG_CPU_DATA_CNT_LIM_WIDTH:0] data_cnt_limit;
+wire data_cnt_end;
+reg data_cnt_end_q;
+reg crc_match_reg;
+
+reg [`DBG_CPU_ACC_TYPE_LEN -1:0] acc_type;
+reg [`DBG_CPU_ADR_LEN -1:0] adr;
+reg [`DBG_CPU_LEN_LEN -1:0] len;
+reg [`DBG_CPU_LEN_LEN:0] len_var;
+wire [`DBG_CPU_CTRL_LEN -1:0]ctrl_reg;
+reg start_rd_tck;
+reg rd_tck_started;
+reg start_rd_csff;
+reg start_cpu_rd;
+reg start_cpu_rd_q;
+reg start_wr_tck;
+reg start_wr_csff;
+reg start_cpu_wr;
+reg start_cpu_wr_q;
+
+reg status_cnt_en;
+wire status_cnt_end;
+
+wire half, long;
+reg half_q, long_q;
+
+reg [`DBG_CPU_STATUS_CNT_WIDTH -1:0] status_cnt;
+
+reg [`DBG_CPU_STATUS_LEN -1:0] status;
+
+reg cpu_overrun, cpu_overrun_csff, cpu_overrun_tck;
+reg underrun_tck;
+
+reg busy_cpu;
+reg busy_tck;
+reg cpu_end;
+reg cpu_end_rst;
+reg cpu_end_rst_csff;
+reg cpu_end_csff;
+reg cpu_end_tck, cpu_end_tck_q;
+reg busy_csff;
+reg latch_data;
+reg update_dr_csff, update_dr_cpu;
+wire [`DBG_CPU_CTRL_LEN -1:0] cpu_reg_data_i;
+wire cpu_reg_we;
+
+reg set_addr, set_addr_csff, set_addr_cpu, set_addr_cpu_q;
+wire [31:0] input_data;
+
+wire len_eq_0;
+wire crc_cnt_31;
+
+reg fifo_full;
+reg [7:0] mem [0:3];
+reg cpu_ce_csff;
+reg mem_ptr_init;
+reg [`DBG_CPU_CMD_LEN -1: 0] curr_cmd;
+wire curr_cmd_go;
+reg curr_cmd_go_q;
+wire curr_cmd_wr_comm;
+wire curr_cmd_wr_ctrl;
+wire curr_cmd_rd_comm;
+wire curr_cmd_rd_ctrl;
+wire acc_type_read;
+wire acc_type_write;
+
+
+assign enable = cpu_ce_i & shift_dr_i;
+assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
+assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC
+
+assign curr_cmd_go = (curr_cmd == `DBG_CPU_GO) && cmd_cnt_end;
+assign curr_cmd_wr_comm = (curr_cmd == `DBG_CPU_WR_COMM) && cmd_cnt_end;
+assign curr_cmd_wr_ctrl = (curr_cmd == `DBG_CPU_WR_CTRL) && cmd_cnt_end;
+assign curr_cmd_rd_comm = (curr_cmd == `DBG_CPU_RD_COMM) && cmd_cnt_end;
+assign curr_cmd_rd_ctrl = (curr_cmd == `DBG_CPU_RD_CTRL) && cmd_cnt_end;
+
+assign acc_type_read = (acc_type == `DBG_CPU_READ);
+assign acc_type_write = (acc_type == `DBG_CPU_WRITE);
+
+
+
+// Shift register for shifting in and out the data
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ latch_data <= #1 1'b0;
+ dr <= #1 {`DBG_CPU_DR_LEN{1'b0}};
+ end
+ else if (curr_cmd_rd_comm && crc_cnt_31) // Latching data (from internal regs)
+ begin
+ dr[`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1:0] <= #1 {acc_type, adr, len};
+ end
+ else if (curr_cmd_rd_ctrl && crc_cnt_31) // Latching data (from control regs)
+ begin
+ dr[`DBG_CPU_DR_LEN -1:`DBG_CPU_DR_LEN -`DBG_CPU_CTRL_LEN] <= #1 ctrl_reg;
+ end
+ else if (acc_type_read && curr_cmd_go && crc_cnt_31) // Latchind first data (from WB)
+ begin
+ dr[31:0] <= #1 input_data[31:0];
+ latch_data <= #1 1'b1;
+ end
+ else if (acc_type_read && curr_cmd_go && crc_cnt_end) // Latching data (from WB)
+ begin
+ case (acc_type) // synthesis parallel_case full_case
+ `DBG_CPU_READ: begin
+ if(long & (~long_q))
+ begin
+ dr[31:0] <= #1 input_data[31:0];
+ latch_data <= #1 1'b1;
+ end
+ else
+ begin
+ dr[31:0] <= #1 {dr[30:0], 1'b0};
+ latch_data <= #1 1'b0;
+ end
+ end
+ endcase
+ end
+ else if (enable && (!addr_len_cnt_end))
+ begin
+ dr <= #1 {dr[`DBG_CPU_DR_LEN -2:0], tdi_i};
+ end
+end
+
+
+
+assign cmd_cnt_en = enable & (~cmd_cnt_end);
+
+
+// Command counter
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ cmd_cnt <= #1 {`DBG_CPU_CMD_CNT_WIDTH{1'b0}};
+ else if (update_dr_i)
+ cmd_cnt <= #1 {`DBG_CPU_CMD_CNT_WIDTH{1'b0}};
+ else if (cmd_cnt_en)
+ cmd_cnt <= #1 cmd_cnt + 1'b1;
+end
+
+
+// Assigning current command
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ curr_cmd <= #1 {`DBG_CPU_CMD_LEN{1'b0}};
+ else if (update_dr_i)
+ curr_cmd <= #1 {`DBG_CPU_CMD_LEN{1'b0}};
+ else if (cmd_cnt == (`DBG_CPU_CMD_LEN -1))
+ curr_cmd <= #1 {dr[`DBG_CPU_CMD_LEN-2 :0], tdi_i};
+end
+
+
+// Assigning current command
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ curr_cmd_go_q <= #1 1'b0;
+ else
+ curr_cmd_go_q <= #1 curr_cmd_go;
+end
+
+
+always @ (enable or cmd_cnt_end or addr_len_cnt_end or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_rd_comm or curr_cmd_rd_ctrl or crc_cnt_end)
+begin
+ if (enable && (!addr_len_cnt_end))
+ begin
+ if (cmd_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
+ addr_len_cnt_en = 1'b1;
+ else if (crc_cnt_end && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
+ addr_len_cnt_en = 1'b1;
+ else
+ addr_len_cnt_en = 1'b0;
+ end
+ else
+ addr_len_cnt_en = 1'b0;
+end
+
+
+// Address/length counter
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ addr_len_cnt <= #1 6'h0;
+ else if (update_dr_i)
+ addr_len_cnt <= #1 6'h0;
+ else if (addr_len_cnt_en)
+ addr_len_cnt <= #1 addr_len_cnt + 1'b1;
+end
+
+
+always @ (enable or data_cnt_end or cmd_cnt_end or curr_cmd_go or acc_type_write or acc_type_read or crc_cnt_end)
+begin
+ if (enable && (!data_cnt_end))
+ begin
+ if (cmd_cnt_end && curr_cmd_go && acc_type_write)
+ data_cnt_en = 1'b1;
+ else if (crc_cnt_end && curr_cmd_go && acc_type_read)
+ data_cnt_en = 1'b1;
+ else
+ data_cnt_en = 1'b0;
+ end
+ else
+ data_cnt_en = 1'b0;
+end
+
+
+// Data counter
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ data_cnt <= #1 {`DBG_CPU_DATA_CNT_WIDTH{1'b0}};
+ else if (update_dr_i)
+ data_cnt <= #1 {`DBG_CPU_DATA_CNT_WIDTH{1'b0}};
+ else if (data_cnt_en)
+ data_cnt <= #1 data_cnt + 1'b1;
+end
+
+
+
+// Upper limit. Data counter counts until this value is reached.
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ data_cnt_limit <= #1 {`DBG_CPU_DATA_CNT_LIM_WIDTH{1'b0}};
+ else if (update_dr_i)
+ data_cnt_limit <= #1 len + 1'b1;
+end
+
+
+always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
+begin
+ if (enable && (!crc_cnt_end) && cmd_cnt_end)
+ begin
+ if (addr_len_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
+ crc_cnt_en = 1'b1;
+ else if (data_cnt_end && curr_cmd_go && acc_type_write)
+ crc_cnt_en = 1'b1;
+ else if (cmd_cnt_end && (curr_cmd_go && acc_type_read || curr_cmd_rd_comm || curr_cmd_rd_ctrl))
+ crc_cnt_en = 1'b1;
+ else
+ crc_cnt_en = 1'b0;
+ end
+ else
+ crc_cnt_en = 1'b0;
+end
+
+
+// crc counter
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ crc_cnt <= #1 {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
+ else if(crc_cnt_en)
+ crc_cnt <= #1 crc_cnt + 1'b1;
+ else if (update_dr_i)
+ crc_cnt <= #1 {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
+end
+
+assign cmd_cnt_end = cmd_cnt == `DBG_CPU_CMD_LEN;
+assign addr_len_cnt_end = addr_len_cnt == `DBG_CPU_DR_LEN;
+assign crc_cnt_end = crc_cnt == `DBG_CPU_CRC_CNT_WIDTH'd32;
+assign crc_cnt_31 = crc_cnt == `DBG_CPU_CRC_CNT_WIDTH'd31;
+assign data_cnt_end = (data_cnt == {data_cnt_limit, 3'b000});
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ crc_cnt_end_q <= #1 1'b0;
+ cmd_cnt_end_q <= #1 1'b0;
+ data_cnt_end_q <= #1 1'b0;
+ addr_len_cnt_end_q <= #1 1'b0;
+ end
+ else
+ begin
+ crc_cnt_end_q <= #1 crc_cnt_end;
+ cmd_cnt_end_q <= #1 cmd_cnt_end;
+ data_cnt_end_q <= #1 data_cnt_end;
+ addr_len_cnt_end_q <= #1 addr_len_cnt_end;
+ end
+end
+
+
+// Status counter is made of 4 serialy connected registers
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ status_cnt <= #1 {`DBG_CPU_STATUS_CNT_WIDTH{1'b0}};
+ else if (update_dr_i)
+ status_cnt <= #1 {`DBG_CPU_STATUS_CNT_WIDTH{1'b0}};
+ else if (status_cnt_en)
+ status_cnt <= #1 status_cnt + 1'b1;
+end
+
+
+always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or
+ curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or
+ acc_type_read or data_cnt_end or addr_len_cnt_end)
+begin
+ if (enable && (!status_cnt_end))
+ begin
+ if (crc_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
+ status_cnt_en = 1'b1;
+ else if (crc_cnt_end && curr_cmd_go && acc_type_write)
+ status_cnt_en = 1'b1;
+ else if (data_cnt_end && curr_cmd_go && acc_type_read)
+ status_cnt_en = 1'b1;
+ else if (addr_len_cnt_end && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
+ status_cnt_en = 1'b1;
+ else
+ status_cnt_en = 1'b0;
+ end
+ else
+ status_cnt_en = 1'b0;
+end
+
+
+assign status_cnt_end = status_cnt == `DBG_CPU_STATUS_LEN;
+
+
+// Latching acc_type, address and length
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ acc_type <= #1 {`DBG_CPU_ACC_TYPE_LEN{1'b0}};
+ adr <= #1 {`DBG_CPU_ADR_LEN{1'b0}};
+ len <= #1 {`DBG_CPU_LEN_LEN{1'b0}};
+ set_addr <= #1 1'b0;
+ end
+ else if(crc_cnt_end && (!crc_cnt_end_q) && crc_match_i && curr_cmd_wr_comm)
+ begin
+ acc_type <= #1 dr[`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1 : `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN];
+ adr <= #1 dr[`DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1 : `DBG_CPU_LEN_LEN];
+ len <= #1 dr[`DBG_CPU_LEN_LEN -1:0];
+ set_addr <= #1 1'b1;
+ end
+ else if(cpu_end_tck) // Writing back the address
+ begin
+ adr <= #1 cpu_addr_dsff;
+ end
+ else
+ set_addr <= #1 1'b0;
+end
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ crc_match_reg <= #1 1'b0;
+ else if(crc_cnt_end & (~crc_cnt_end_q))
+ crc_match_reg <= #1 crc_match_i;
+end
+
+
+// Length counter
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ len_var <= #1 {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
+ else if(update_dr_i)
+ len_var <= #1 len + 1'b1;
+ else if (start_rd_tck)
+ begin
+ if (len_var > 'd4)
+ len_var <= #1 len_var - 3'd4;
+ else
+ len_var <= #1 {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
+ end
+end
+
+
+assign len_eq_0 = len_var == 'h0;
+
+
+assign half = data_cnt[3:0] == 4'd15;
+assign long = data_cnt[4:0] == 5'd31;
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ half_q <= #1 1'b0;
+ long_q <= #1 1'b0;
+ end
+ else
+ begin
+ half_q <= #1 half;
+ long_q <= #1 long;
+ end
+end
+
+
+// Start cpu write cycle
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ start_wr_tck <= #1 1'b0;
+ cpu_dat_tmp <= #1 32'h0;
+ end
+ else if (curr_cmd_go && acc_type_write)
+ begin
+ if (long_q)
+ begin
+ start_wr_tck <= #1 1'b1;
+ cpu_dat_tmp <= #1 dr[31:0];
+ end
+ else
+ begin
+ start_wr_tck <= #1 1'b0;
+ end
+ end
+ else
+ start_wr_tck <= #1 1'b0;
+end
+
+
+// cpu_data_o in WB clk domain
+always @ (posedge cpu_clk_i)
+begin
+ cpu_data_dsff <= #1 cpu_dat_tmp;
+end
+
+assign cpu_data_o = cpu_data_dsff;
+
+
+// Start cpu read cycle
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ start_rd_tck <= #1 1'b0;
+ else if (curr_cmd_go && (!curr_cmd_go_q) && acc_type_read) // First read after cmd is entered
+ start_rd_tck <= #1 1'b1;
+ else if ((!start_rd_tck) && curr_cmd_go && acc_type_read && (!len_eq_0) && (!fifo_full) && (!rd_tck_started) && (!cpu_ack_tck))
+ start_rd_tck <= #1 1'b1;
+ else
+ start_rd_tck <= #1 1'b0;
+end
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ rd_tck_started <= #1 1'b0;
+ else if (update_dr_i || cpu_end_tck && (!cpu_end_tck_q))
+ rd_tck_started <= #1 1'b0;
+ else if (start_rd_tck)
+ rd_tck_started <= #1 1'b1;
+end
+
+
+
+always @ (posedge cpu_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ start_rd_csff <= #1 1'b0;
+ start_cpu_rd <= #1 1'b0;
+ start_cpu_rd_q <= #1 1'b0;
+
+ start_wr_csff <= #1 1'b0;
+ start_cpu_wr <= #1 1'b0;
+ start_cpu_wr_q <= #1 1'b0;
+
+ set_addr_csff <= #1 1'b0;
+ set_addr_cpu <= #1 1'b0;
+ set_addr_cpu_q <= #1 1'b0;
+
+ cpu_ack_q <= #1 1'b0;
+ end
+ else
+ begin
+ start_rd_csff <= #1 start_rd_tck;
+ start_cpu_rd <= #1 start_rd_csff;
+ start_cpu_rd_q <= #1 start_cpu_rd;
+
+ start_wr_csff <= #1 start_wr_tck;
+ start_cpu_wr <= #1 start_wr_csff;
+ start_cpu_wr_q <= #1 start_cpu_wr;
+
+ set_addr_csff <= #1 set_addr;
+ set_addr_cpu <= #1 set_addr_csff;
+ set_addr_cpu_q <= #1 set_addr_cpu;
+
+ cpu_ack_q <= #1 cpu_ack_i;
+ end
+end
+
+
+// cpu_stb_o
+always @ (posedge cpu_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ cpu_stb_o <= #1 1'b0;
+ else if (cpu_ack_i)
+ cpu_stb_o <= #1 1'b0;
+ else if ((start_cpu_wr && (!start_cpu_wr_q)) || (start_cpu_rd && (!start_cpu_rd_q)))
+ cpu_stb_o <= #1 1'b1;
+end
+
+
+assign cpu_stall_o = cpu_stb_o | cpu_reg_stall;
+
+
+// cpu_addr_o logic
+always @ (posedge cpu_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ cpu_addr_dsff <= #1 32'h0;
+ else if (set_addr_cpu && (!set_addr_cpu_q)) // Setting starting address
+ cpu_addr_dsff <= #1 adr;
+ else if (cpu_ack_i && (!cpu_ack_q))
+ cpu_addr_dsff <= #1 cpu_addr_dsff + 3'd4;
+end
+
+
+assign cpu_addr_o = cpu_addr_dsff;
+
+
+always @ (posedge cpu_clk_i)
+begin
+ cpu_we_dsff <= #1 curr_cmd_go && acc_type_write;
+end
+
+
+assign cpu_we_o = cpu_we_dsff;
+
+
+
+// Logic for detecting end of transaction
+always @ (posedge cpu_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ cpu_end <= #1 1'b0;
+ else if (cpu_ack_i && (!cpu_ack_q))
+ cpu_end <= #1 1'b1;
+ else if (cpu_end_rst)
+ cpu_end <= #1 1'b0;
+end
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ cpu_end_csff <= #1 1'b0;
+ cpu_end_tck <= #1 1'b0;
+ cpu_end_tck_q <= #1 1'b0;
+ end
+ else
+ begin
+ cpu_end_csff <= #1 cpu_end;
+ cpu_end_tck <= #1 cpu_end_csff;
+ cpu_end_tck_q <= #1 cpu_end_tck;
+ end
+end
+
+
+always @ (posedge cpu_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ cpu_end_rst_csff <= #1 1'b0;
+ cpu_end_rst <= #1 1'b0;
+ end
+ else
+ begin
+ cpu_end_rst_csff <= #1 cpu_end_tck;
+ cpu_end_rst <= #1 cpu_end_rst_csff;
+ end
+end
+
+
+always @ (posedge cpu_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ busy_cpu <= #1 1'b0;
+ else if (cpu_end_rst)
+ busy_cpu <= #1 1'b0;
+ else if (cpu_stb_o)
+ busy_cpu <= #1 1'b1;
+end
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ busy_csff <= #1 1'b0;
+ busy_tck <= #1 1'b0;
+
+ update_dr_csff <= #1 1'b0;
+ update_dr_cpu <= #1 1'b0;
+ end
+ else
+ begin
+ busy_csff <= #1 busy_cpu;
+ busy_tck <= #1 busy_csff;
+
+ update_dr_csff <= #1 update_dr_i;
+ update_dr_cpu <= #1 update_dr_csff;
+ end
+end
+
+
+// Detecting overrun when write operation.
+always @ (posedge cpu_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ cpu_overrun <= #1 1'b0;
+ else if(start_cpu_wr && (!start_cpu_wr_q) && cpu_ack_i)
+ cpu_overrun <= #1 1'b1;
+ else if(update_dr_cpu) // error remains active until update_dr arrives
+ cpu_overrun <= #1 1'b0;
+end
+
+
+// Detecting underrun when read operation
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ underrun_tck <= #1 1'b0;
+ else if(latch_data && (!fifo_full) && (!data_cnt_end))
+ underrun_tck <= #1 1'b1;
+ else if(update_dr_i) // error remains active until update_dr arrives
+ underrun_tck <= #1 1'b0;
+end
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ cpu_overrun_csff <= #1 1'b0;
+ cpu_overrun_tck <= #1 1'b0;
+
+ cpu_ack_csff <= #1 1'b0;
+ cpu_ack_tck <= #1 1'b0;
+ end
+ else
+ begin
+ cpu_overrun_csff <= #1 cpu_overrun;
+ cpu_overrun_tck <= #1 cpu_overrun_csff;
+
+ cpu_ack_csff <= #1 cpu_ack_i;
+ cpu_ack_tck <= #1 cpu_ack_csff;
+ end
+end
+
+
+
+always @ (posedge cpu_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ cpu_ce_csff <= #1 1'b0;
+ mem_ptr_init <= #1 1'b0;
+ end
+ else
+ begin
+ cpu_ce_csff <= #1 cpu_ce_i;
+ mem_ptr_init <= #1 ~cpu_ce_csff;
+ end
+end
+
+
+// Logic for latching data that is read from cpu
+always @ (posedge cpu_clk_i)
+begin
+ if (cpu_ack_i && (!cpu_ack_q))
+ begin
+ mem[0] <= #1 cpu_data_i[31:24];
+ mem[1] <= #1 cpu_data_i[23:16];
+ mem[2] <= #1 cpu_data_i[15:08];
+ mem[3] <= #1 cpu_data_i[07:00];
+ end
+end
+
+
+assign input_data = {mem[0], mem[1], mem[2], mem[3]};
+
+
+// Fifo counter and empty/full detection
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ fifo_full <= #1 1'h0;
+ else if (update_dr_i)
+ fifo_full <= #1 1'h0;
+ else if (cpu_end_tck && (!cpu_end_tck_q) && (!latch_data) && (!fifo_full)) // incrementing
+ fifo_full <= #1 1'b1;
+ else if (!(cpu_end_tck && (!cpu_end_tck_q)) && latch_data && (fifo_full)) // decrementing
+ fifo_full <= #1 1'h0;
+end
+
+
+
+// TDO multiplexer
+always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or acc_type_read or crc_match_i or data_cnt_end or dr or data_cnt_end_q or crc_match_reg or status_cnt_en or status or addr_len_cnt_end or addr_len_cnt_end_q or curr_cmd_rd_comm or curr_cmd_rd_ctrl)
+begin
+ if (pause_dr_i)
+ begin
+ tdo_o = busy_tck;
+ end
+ else if (crc_cnt_end && (!crc_cnt_end_q) && (curr_cmd_wr_comm || curr_cmd_wr_ctrl || curr_cmd_go && acc_type_write ))
+ begin
+ tdo_o = ~crc_match_i;
+ end
+ else if (curr_cmd_go && acc_type_read && crc_cnt_end && (!data_cnt_end))
+ begin
+ tdo_o = dr[31];
+ end
+ else if (curr_cmd_go && acc_type_read && data_cnt_end && (!data_cnt_end_q))
+ begin
+ tdo_o = ~crc_match_reg;
+ end
+ else if ((curr_cmd_rd_comm || curr_cmd_rd_ctrl) && addr_len_cnt_end && (!addr_len_cnt_end_q))
+ begin
+ tdo_o = ~crc_match_reg;
+ end
+ else if ((curr_cmd_rd_comm || curr_cmd_rd_ctrl) && crc_cnt_end && (!addr_len_cnt_end))
+ begin
+ tdo_o = dr[`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1];
+ end
+ else if (status_cnt_en)
+ begin
+ tdo_o = status[3];
+ end
+ else
+ begin
+ tdo_o = 1'b0;
+ end
+end
+
+
+// Status register
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ status <= #1 {`DBG_CPU_STATUS_LEN{1'b0}};
+ end
+ else if(crc_cnt_end && (!crc_cnt_end_q) && (!(curr_cmd_go && acc_type_read)))
+ begin
+ status <= #1 {1'b0, 1'b0, cpu_overrun_tck, crc_match_i};
+ end
+ else if (data_cnt_end && (!data_cnt_end_q) && curr_cmd_go && acc_type_read)
+ begin
+ status <= #1 {1'b0, 1'b0, underrun_tck, crc_match_reg};
+ end
+ else if (addr_len_cnt_end && (!addr_len_cnt_end) && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
+ begin
+ status <= #1 {1'b0, 1'b0, 1'b0, crc_match_reg};
+ end
+ else if (shift_dr_i && (!status_cnt_end))
+ begin
+ status <= #1 {status[`DBG_CPU_STATUS_LEN -2:0], status[`DBG_CPU_STATUS_LEN -1]};
+ end
+end
+// Following status is shifted out (MSB first):
+// 3. bit: 1 if crc is OK, else 0
+// 2. bit: 1'b0
+// 1. bit: 0
+// 0. bit: 1 if overrun occured during write (data couldn't be written fast enough)
+// or underrun occured during read (data couldn't be read fast enough)
+
+
+
+// Connecting cpu registers
+assign cpu_reg_we = crc_cnt_end && (!crc_cnt_end_q) && crc_match_i && curr_cmd_wr_ctrl;
+assign cpu_reg_data_i = dr[`DBG_CPU_DR_LEN -1:`DBG_CPU_DR_LEN -`DBG_CPU_CTRL_LEN];
+
+dbg_cpu_registers i_dbg_cpu_registers
+ (
+ .data_i (cpu_reg_data_i),
+ .we_i (cpu_reg_we),
+ .tck_i (tck_i),
+ .bp_i (cpu_bp_i),
+ .rst_i (rst_i),
+ .cpu_clk_i (cpu_clk_i),
+ .ctrl_reg_o (ctrl_reg),
+ .cpu_stall_o (cpu_reg_stall),
+ .cpu_rst_o (cpu_rst_o)
+ );
+
+
+
+
+
+endmodule
+
tags/rel_23/rtl/verilog/dbg_cpu.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_23/rtl/verilog/dbg_wb_defines.v
===================================================================
--- tags/rel_23/rtl/verilog/dbg_wb_defines.v (nonexistent)
+++ tags/rel_23/rtl/verilog/dbg_wb_defines.v (revision 148)
@@ -0,0 +1,108 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbg_wb_defines.v ////
+//// ////
+//// ////
+//// This file is part of the SoC Debug Interface. ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2004 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.6 2004/03/28 20:27:02 igorm
+// New release of the debug interface (3rd. release).
+//
+// Revision 1.5 2004/03/22 16:35:46 igorm
+// Temp version before changing dbg interface.
+//
+// Revision 1.4 2004/01/16 14:51:33 mohor
+// cpu registers added.
+//
+// Revision 1.3 2004/01/08 17:53:36 mohor
+// tmp version.
+//
+// Revision 1.2 2004/01/06 17:15:19 mohor
+// temp3 version.
+//
+// Revision 1.1 2003/12/23 15:09:04 mohor
+// New directory structure. New version of the debug interface.
+//
+//
+//
+
+// Defining length of the command
+`define DBG_WB_CMD_LEN 3'd4
+`define DBG_WB_CMD_CNT_WIDTH 3
+
+// Defining length of the access_type field
+`define DBG_WB_ACC_TYPE_LEN 3'd4
+
+// Defining length of the address
+`define DBG_WB_ADR_LEN 6'd32
+
+// Defining length of the length register
+`define DBG_WB_LEN_LEN 5'd16
+
+// Defining total length of the DR needed
+`define DBG_WB_DR_LEN (`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN)
+
+// Defining length of the CRC
+`define DBG_WB_CRC_LEN 6'd32
+`define DBG_WB_CRC_CNT_WIDTH 6
+
+// Defining length of status
+`define DBG_WB_STATUS_LEN 3'd4
+`define DBG_WB_STATUS_CNT_WIDTH 3
+
+// Defining length of the data
+`define DBG_WB_DATA_CNT_WIDTH (`DBG_WB_LEN_LEN + 3)
+`define DBG_WB_DATA_CNT_LIM_WIDTH `DBG_WB_LEN_LEN
+
+//Defining commands
+`define DBG_WB_GO 4'h0
+`define DBG_WB_RD_COMM 4'h1
+`define DBG_WB_WR_COMM 4'h2
+
+// Defining access types for wishbone
+`define DBG_WB_WRITE8 4'h0
+`define DBG_WB_WRITE16 4'h1
+`define DBG_WB_WRITE32 4'h2
+`define DBG_WB_READ8 4'h4
+`define DBG_WB_READ16 4'h5
+`define DBG_WB_READ32 4'h6
+
+
tags/rel_23/rtl/verilog/dbg_wb_defines.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_23/rtl/verilog/dbg_crc32_d1.v
===================================================================
--- tags/rel_23/rtl/verilog/dbg_crc32_d1.v (nonexistent)
+++ tags/rel_23/rtl/verilog/dbg_crc32_d1.v (revision 148)
@@ -0,0 +1,148 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbg_crc32_d1.v ////
+//// ////
+//// ////
+//// This file is part of the SoC Debug Interface. ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2004 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+// File: CRC32_D1.v
+// Date: Thu Nov 27 13:56:49 2003
+//
+// Copyright (C) 1999-2003 Easics NV.
+// This source file may be used and distributed without restriction
+// provided that this copyright statement is not removed from the file
+// and that any derivative work contains the original copyright notice
+// and the associated disclaimer.
+//
+// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
+// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+// Purpose: Verilog module containing a synthesizable CRC function
+// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
+// * data width: 1
+//
+// Info: janz@easics.be (Jan Zegers)
+// http://www.easics.com
+///////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.2 2003/12/23 15:26:26 mohor
+// Small fix.
+//
+// Revision 1.1 2003/12/23 15:09:04 mohor
+// New directory structure. New version of the debug interface.
+//
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+
+module dbg_crc32_d1 (data, enable, shift, rst, sync_rst, crc_out, clk, crc_match);
+
+input data;
+input enable;
+input shift;
+input rst;
+input sync_rst;
+input clk;
+
+
+output crc_out;
+output crc_match;
+
+reg [31:0] crc;
+
+wire [31:0] new_crc;
+
+
+assign new_crc[0] = data ^ crc[31];
+assign new_crc[1] = data ^ crc[0] ^ crc[31];
+assign new_crc[2] = data ^ crc[1] ^ crc[31];
+assign new_crc[3] = crc[2];
+assign new_crc[4] = data ^ crc[3] ^ crc[31];
+assign new_crc[5] = data ^ crc[4] ^ crc[31];
+assign new_crc[6] = crc[5];
+assign new_crc[7] = data ^ crc[6] ^ crc[31];
+assign new_crc[8] = data ^ crc[7] ^ crc[31];
+assign new_crc[9] = crc[8];
+assign new_crc[10] = data ^ crc[9] ^ crc[31];
+assign new_crc[11] = data ^ crc[10] ^ crc[31];
+assign new_crc[12] = data ^ crc[11] ^ crc[31];
+assign new_crc[13] = crc[12];
+assign new_crc[14] = crc[13];
+assign new_crc[15] = crc[14];
+assign new_crc[16] = data ^ crc[15] ^ crc[31];
+assign new_crc[17] = crc[16];
+assign new_crc[18] = crc[17];
+assign new_crc[19] = crc[18];
+assign new_crc[20] = crc[19];
+assign new_crc[21] = crc[20];
+assign new_crc[22] = data ^ crc[21] ^ crc[31];
+assign new_crc[23] = data ^ crc[22] ^ crc[31];
+assign new_crc[24] = crc[23];
+assign new_crc[25] = crc[24];
+assign new_crc[26] = data ^ crc[25] ^ crc[31];
+assign new_crc[27] = crc[26];
+assign new_crc[28] = crc[27];
+assign new_crc[29] = crc[28];
+assign new_crc[30] = crc[29];
+assign new_crc[31] = crc[30];
+
+
+always @ (posedge clk or posedge rst)
+begin
+ if(rst)
+ crc[31:0] <= #1 32'hffffffff;
+ else if(sync_rst)
+ crc[31:0] <= #1 32'hffffffff;
+ else if(enable)
+ crc[31:0] <= #1 new_crc;
+ else if (shift)
+ crc[31:0] <= #1 {crc[30:0], 1'b0};
+end
+
+
+assign crc_match = (crc == 32'h0);
+assign crc_out = crc[31];
+
+endmodule
tags/rel_23/rtl/verilog/dbg_crc32_d1.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_23/rtl/verilog/dbg_register.v
===================================================================
--- tags/rel_23/rtl/verilog/dbg_register.v (nonexistent)
+++ tags/rel_23/rtl/verilog/dbg_register.v (revision 148)
@@ -0,0 +1,92 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbg_register.v ////
+//// ////
+//// ////
+//// This file is part of the SoC Debug Interface. ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2004 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.9 2004/01/25 14:04:18 mohor
+// All flipflops are reset.
+//
+// Revision 1.8 2004/01/16 14:53:33 mohor
+// *** empty log message ***
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+
+module dbg_register (
+ data_in,
+ data_out,
+ write,
+ clk,
+ reset
+ );
+
+
+parameter WIDTH = 8; // default parameter of the register width
+parameter RESET_VALUE = 0;
+
+
+input [WIDTH-1:0] data_in;
+input write;
+input clk;
+input reset;
+
+output [WIDTH-1:0] data_out;
+reg [WIDTH-1:0] data_out;
+
+
+
+always @ (posedge clk or posedge reset)
+begin
+ if(reset)
+ data_out[WIDTH-1:0] <= #1 RESET_VALUE;
+ else if(write)
+ data_out[WIDTH-1:0] <= #1 data_in[WIDTH-1:0];
+end
+
+
+endmodule // Register
+
Index: tags/rel_23/rtl/verilog/dbg_cpu_registers.v
===================================================================
--- tags/rel_23/rtl/verilog/dbg_cpu_registers.v (nonexistent)
+++ tags/rel_23/rtl/verilog/dbg_cpu_registers.v (revision 148)
@@ -0,0 +1,193 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbg_cpu_registers.v ////
+//// ////
+//// ////
+//// This file is part of the SoC Debug Interface. ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2004 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.5 2004/03/22 16:35:46 igorm
+// Temp version before changing dbg interface.
+//
+// Revision 1.4 2004/01/25 14:04:18 mohor
+// All flipflops are reset.
+//
+// Revision 1.3 2004/01/22 10:16:08 mohor
+// cpu_stall_o activated as soon as bp occurs.
+//
+// Revision 1.2 2004/01/17 17:01:14 mohor
+// Almost finished.
+//
+// Revision 1.1 2004/01/16 14:53:33 mohor
+// *** empty log message ***
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "dbg_cpu_defines.v"
+
+module dbg_cpu_registers (
+ data_i,
+ we_i,
+ tck_i,
+ bp_i,
+ rst_i,
+ cpu_clk_i,
+ ctrl_reg_o,
+ cpu_stall_o,
+ cpu_rst_o
+ );
+
+
+input [`DBG_CPU_CTRL_LEN -1:0] data_i;
+input we_i;
+input tck_i;
+input bp_i;
+input rst_i;
+input cpu_clk_i;
+
+output [`DBG_CPU_CTRL_LEN -1:0]ctrl_reg_o;
+output cpu_stall_o;
+output cpu_rst_o;
+
+reg cpu_reset;
+wire [2:1] cpu_op_out;
+
+reg stall_bp, stall_bp_csff, stall_bp_tck;
+reg stall_reg, stall_reg_csff, stall_reg_cpu;
+reg cpu_reset_csff;
+reg cpu_rst_o;
+
+
+
+// Breakpoint is latched and synchronized. Stall is set and latched.
+always @ (posedge cpu_clk_i or posedge rst_i)
+begin
+ if(rst_i)
+ stall_bp <= #1 1'b0;
+ else if(bp_i)
+ stall_bp <= #1 1'b1;
+ else if(stall_reg_cpu)
+ stall_bp <= #1 1'b0;
+end
+
+
+// Synchronizing
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ stall_bp_csff <= #1 1'b0;
+ stall_bp_tck <= #1 1'b0;
+ end
+ else
+ begin
+ stall_bp_csff <= #1 stall_bp;
+ stall_bp_tck <= #1 stall_bp_csff;
+ end
+end
+
+
+always @ (posedge cpu_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ stall_reg_csff <= #1 1'b0;
+ stall_reg_cpu <= #1 1'b0;
+ end
+ else
+ begin
+ stall_reg_csff <= #1 stall_reg;
+ stall_reg_cpu <= #1 stall_reg_csff;
+ end
+end
+
+
+assign cpu_stall_o = bp_i | stall_bp | stall_reg_cpu;
+
+
+// Writing data to the control registers (stall)
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ stall_reg <= #1 1'b0;
+ else if (stall_bp_tck)
+ stall_reg <= #1 1'b1;
+ else if (we_i)
+ stall_reg <= #1 data_i[0];
+end
+
+
+// Writing data to the control registers (reset)
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ cpu_reset <= #1 1'b0;
+ else if(we_i)
+ cpu_reset <= #1 data_i[1];
+end
+
+
+// Synchronizing signals from registers
+always @ (posedge cpu_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ cpu_reset_csff <= #1 1'b0;
+ cpu_rst_o <= #1 1'b0;
+ end
+ else
+ begin
+ cpu_reset_csff <= #1 cpu_reset;
+ cpu_rst_o <= #1 cpu_reset_csff;
+ end
+end
+
+
+
+// Value for read back
+assign ctrl_reg_o = {cpu_reset, stall_reg};
+
+
+endmodule
+
Index: tags/rel_23/rtl/README.txt
===================================================================
--- tags/rel_23/rtl/README.txt (nonexistent)
+++ tags/rel_23/rtl/README.txt (revision 148)
@@ -0,0 +1,114 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// README.txt ////
+//// ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/cores/DebugInterface/ ////
+//// ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor ////
+//// igorm@opencores.org ////
+//// ////
+//// ////
+//// All additional information is avaliable in this README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000,2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
+// Initial official release.
+//
+// Revision 1.2 2001/06/01 22:22:35 mohor
+// This is a backup. It is not a fully working version. Not for use, yet.
+//
+// Revision 1.1 2001/05/18 13:12:09 mohor
+// Header changed. All additional information is now avaliable in this README.txt file.
+//
+//
+
+
+
+PROJECT:
+SoC/OpenRISC Development (debug) Interface
+
+
+PROJECT AND DOCUMENTATION ON THE WEB:
+
+The project that this files are part of is avaliable on the opencores
+web page:
+
+http://www.opencores.org/cores/DebugInterface/
+
+Documentation can also be found there. For direct download of the
+documentation go to:
+
+http://www.opencores.org/cgi-bin/cvsget.cgi/dbg_interface/doc/DbgSupp.pdf
+
+
+
+
+OVERVIEW (main Features):
+
+Development Interface is used for development purposes
+(Boundary Scan testing and debugging). It is an interface
+between the RISC, peripheral cores and any commercial
+debugger/emulator or BS testing device. The external
+debugger or BS tester connects to the core via JTAG port.
+The Development Port also contains a trace and support for
+tracing the program flow, execution coverage and profiling
+the code.
+
+dbg_tb.v is a testbench file.
+file_communication.v is used for simulating the whole design together with the
+ debugger through two files that make a JTAG interface
+dbg_top.v is top level module of the development interface design
+
+
+
+COMPATIBILITY:
+
+- WISHBONE rev B.1
+- IEEE 1149.1 (JTAG)
+
+
+
+KNOWN PROBLEMS (limits):
+- RISC changes Watchpoints and breakpoints on rising edge of the
+Mclk clock signal. Simulation should do the same.
+
+
+
+TO DO:
+- Add a WISHBONE master support if needed
+- Add support for boundary scan (This is already done, but not yet incorporated in the design)
+
Index: tags/rel_23/bench/verilog/dbg_tb.v
===================================================================
--- tags/rel_23/bench/verilog/dbg_tb.v (nonexistent)
+++ tags/rel_23/bench/verilog/dbg_tb.v (revision 148)
@@ -0,0 +1,2163 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbg_tb.v ////
+//// ////
+//// ////
+//// This file is part of the SoC Debug Interface. ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2004 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.44 2004/04/01 09:33:26 igorm
+// Typo fixed.
+//
+// Revision 1.43 2004/03/31 14:34:13 igorm
+// data_cnt_lim length changed to reduce number of warnings.
+//
+// Revision 1.42 2004/03/30 23:10:39 igorm
+// CRC checking of incoming CRC added to all tasks.
+//
+// Revision 1.41 2004/03/28 20:27:40 igorm
+// New release of the debug interface (3rd. release).
+//
+// Revision 1.40 2004/03/22 16:36:06 igorm
+// Temp version before changing dbg interface.
+//
+// Revision 1.39 2004/03/15 16:17:07 igorm
+// 'hz changed to 1'hz because Icarus complains.
+//
+// Revision 1.38 2004/01/30 10:24:02 mohor
+// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
+// turned on.
+//
+// Revision 1.37 2004/01/25 14:10:25 mohor
+// Display for VATS added.
+//
+// Revision 1.36 2004/01/22 13:58:51 mohor
+// Port signals are all set to zero after reset.
+//
+// Revision 1.35 2004/01/22 11:07:28 mohor
+// test stall_test added.
+//
+// Revision 1.34 2004/01/20 14:24:08 mohor
+// Define name changed.
+//
+// Revision 1.33 2004/01/20 14:05:26 mohor
+// Data latching changed when testing WB.
+//
+// Revision 1.32 2004/01/20 10:23:21 mohor
+// More debug data added.
+//
+// Revision 1.31 2004/01/20 09:07:44 mohor
+// CRC generation iand verification in bench changed.
+//
+// Revision 1.30 2004/01/20 08:03:35 mohor
+// IDCODE test improved.
+//
+// Revision 1.29 2004/01/19 13:13:18 mohor
+// Define tap_defines.v added to test bench.
+//
+// Revision 1.28 2004/01/19 12:38:10 mohor
+// Waiting for "ready" improved.
+//
+// Revision 1.27 2004/01/17 18:01:31 mohor
+// New version.
+//
+// Revision 1.26 2004/01/17 17:01:25 mohor
+// Almost finished.
+//
+// Revision 1.25 2004/01/16 14:51:24 mohor
+// cpu registers added.
+//
+// Revision 1.24 2004/01/15 10:47:13 mohor
+// Working.
+//
+// Revision 1.23 2004/01/14 22:59:01 mohor
+// Temp version.
+//
+// Revision 1.22 2004/01/13 11:28:30 mohor
+// tmp version.
+//
+// Revision 1.21 2004/01/10 07:50:41 mohor
+// temp version.
+//
+// Revision 1.20 2004/01/09 12:49:23 mohor
+// tmp version.
+//
+// Revision 1.19 2004/01/08 17:53:12 mohor
+// tmp version.
+//
+// Revision 1.18 2004/01/07 11:59:48 mohor
+// temp4 version.
+//
+// Revision 1.17 2004/01/06 17:14:59 mohor
+// temp3 version.
+//
+// Revision 1.16 2004/01/05 12:16:50 mohor
+// tmp2 version.
+//
+// Revision 1.15 2003/12/23 14:26:01 mohor
+// New version of the debug interface. Not finished, yet.
+//
+// Revision 1.14 2003/10/23 16:16:30 mohor
+// CRC logic changed.
+//
+// Revision 1.13 2003/08/28 13:54:33 simons
+// Three more chains added for cpu debug access.
+//
+// Revision 1.12 2002/05/07 14:44:52 mohor
+// mon_cntl_o signals that controls monitor mux added.
+//
+// Revision 1.11 2002/03/12 14:32:26 mohor
+// Few outputs for boundary scan chain added.
+//
+// Revision 1.10 2002/03/08 15:27:08 mohor
+// Structure changed. Hooks for jtag chain added.
+//
+// Revision 1.9 2001/10/19 11:39:20 mohor
+// dbg_timescale.v changed to timescale.v This is done for the simulation of
+// few different cores in a single project.
+//
+// Revision 1.8 2001/10/17 10:39:17 mohor
+// bs_chain_o added.
+//
+// Revision 1.7 2001/10/16 10:10:18 mohor
+// Signal names changed to lowercase.
+//
+// Revision 1.6 2001/10/15 09:52:50 mohor
+// Wishbone interface added, few fixes for better performance,
+// hooks for boundary scan testing added.
+//
+// Revision 1.5 2001/09/24 14:06:12 mohor
+// Changes connected to the OpenRISC access (SPR read, SPR write).
+//
+// Revision 1.4 2001/09/20 10:10:29 mohor
+// Working version. Few bugs fixed, comments added.
+//
+// Revision 1.3 2001/09/19 11:54:03 mohor
+// Minor changes for simulation.
+//
+// Revision 1.2 2001/09/18 14:12:43 mohor
+// Trace fixed. Some registers changed, trace simplified.
+//
+// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
+// Initial official release.
+//
+// Revision 1.3 2001/06/01 22:23:40 mohor
+// This is a backup. It is not a fully working version. Not for use, yet.
+//
+// Revision 1.2 2001/05/18 13:10:05 mohor
+// Headers changed. All additional information is now avaliable in the README.txt file.
+//
+// Revision 1.1.1.1 2001/05/18 06:35:15 mohor
+// Initial release
+//
+//
+
+
+`include "timescale.v"
+`include "tap_defines.v"
+`include "dbg_defines.v"
+`include "dbg_wb_defines.v"
+`include "dbg_cpu_defines.v"
+
+`define DBG_TEXT(TEXT) $display("%0s", TEXT);
+// `DBG_TEXT("Bla bla bla")
+// $sformat(dbg_text, "\n\nbla 0x%0x 0x%0x\n\n", 32'h12345678, 16'h543);
+// `DBG_TEXT(dbg_text)
+
+// For common cpu routines
+`ifdef DBG_CPU0_SUPPORTED
+ `define DBG_CPU_SUPPORTED
+`else
+ `ifdef DBG_CPU1_SUPPORTED
+ `define DBG_CPU_SUPPORTED
+ `endif
+`endif
+
+// Test bench
+module dbg_tb;
+
+parameter TCLK = 50; // Clock half period (Clok period = 100 ns => 10 MHz)
+
+reg [999:0] dbg_text;
+reg tms_pad_i;
+reg tck_pad_i;
+reg trst_pad_i;
+reg tdi_pad_i;
+wire tdo_pad_o;
+wire tdo_padoe_o;
+
+wire shift_dr_o;
+wire pause_dr_o;
+wire update_dr_o;
+wire capture_dr_o;
+
+wire extest_select_o;
+wire sample_preload_select_o;
+wire mbist_select_o;
+wire debug_select_o;
+
+reg rst_i;
+
+`ifdef DBG_WISHBONE_SUPPORTED
+// WISHBONE common signals
+reg wb_clk_i;
+
+// WISHBONE master interface
+wire [31:0] wb_adr_o;
+wire [31:0] wb_dat_o;
+wire [31:0] wb_dat_i;
+wire wb_cyc_o;
+wire wb_stb_o;
+wire [3:0] wb_sel_o;
+wire wb_we_o;
+wire wb_ack_i;
+wire wb_cab_o;
+wire wb_err_i;
+wire [2:0] wb_cti_o;
+wire [1:0] wb_bte_o;
+`endif
+
+`ifdef DBG_CPU0_SUPPORTED
+// CPU signals
+wire cpu0_clk_i;
+wire [31:0] cpu0_addr_o;
+wire [31:0] cpu0_data_i;
+wire [31:0] cpu0_data_o;
+wire cpu0_bp_i;
+wire cpu0_stall_o;
+wire cpu0_stb_o;
+wire cpu0_we_o;
+wire cpu0_ack_i;
+wire cpu0_rst_o;
+`endif
+
+`ifdef DBG_CPU1_SUPPORTED
+// CPU signals
+wire cpu1_clk_i;
+wire [31:0] cpu1_addr_o;
+wire [31:0] cpu1_data_i;
+wire [31:0] cpu1_data_o;
+wire cpu1_bp_i;
+wire cpu1_stall_o;
+wire cpu1_stb_o;
+wire cpu1_we_o;
+wire cpu1_ack_i;
+wire cpu1_rst_o;
+`endif
+
+// Text used for easier debugging
+reg [199:0] test_text;
+reg [`DBG_WB_CMD_LEN -1:0] last_wb_cmd;
+reg [`DBG_CPU_CMD_LEN -1:0] last_cpu_cmd;
+reg [199:0] last_wb_cmd_text;
+reg [199:0] last_cpu_cmd_text;
+
+reg [31:0] wb_data [0:4095]; // Data that is written to (read from) wishbone is stored here.
+
+
+
+wire tdo_o;
+
+wire debug_tdi_i;
+wire bs_chain_tdi_i;
+wire mbist_tdi_i;
+
+reg test_enabled;
+
+reg [31:0] result;
+reg [31:0] in_data_le, in_data_be;
+reg [31:0] id;
+
+wire crc_match_in;
+reg [31:0] crc_in;
+reg [31:0] crc_out;
+reg [`DBG_TOP_STATUS_LEN -1:0] status;
+reg [`DBG_WB_STATUS_LEN -1:0] status_wb;
+reg [`DBG_CPU_STATUS_LEN -1:0] status_cpu;
+
+reg [`DBG_WB_ACC_TYPE_LEN -1:0] read_acc_type;
+reg [`DBG_WB_ADR_LEN -1:0] read_addr;
+reg [`DBG_WB_LEN_LEN -1:0] read_length;
+reg [`DBG_CPU_CTRL_LEN -1:0] read_ctrl_reg;
+
+integer length_global;
+wire tdo;
+
+assign tdo = tdo_padoe_o? tdo_pad_o : 1'hz;
+
+
+
+// Connecting TAP module
+tap_top i_tap_top (
+ .tms_pad_i (tms_pad_i),
+ .tck_pad_i (tck_pad_i),
+ .trst_pad_i (!trst_pad_i),
+ .tdi_pad_i (tdi_pad_i),
+ .tdo_pad_o (tdo_pad_o),
+ .tdo_padoe_o (tdo_padoe_o),
+
+ // TAP states
+ .shift_dr_o (shift_dr_o),
+ .pause_dr_o (pause_dr_o),
+ .update_dr_o (update_dr_o),
+ .capture_dr_o (capture_dr_o),
+
+ // Select signals for boundary scan or mbist
+ .extest_select_o (extest_select_o),
+ .sample_preload_select_o(sample_preload_select_o),
+ .mbist_select_o (mbist_select_o),
+ .debug_select_o (debug_select_o),
+
+ // TDO signal that is connected to TDI of sub-modules.
+ .tdo_o (tdo_o),
+
+ // TDI signals from sub-modules
+ .debug_tdi_i (debug_tdi_i), // from debug module
+ .bs_chain_tdi_i (bs_chain_tdi_i), // from Boundary Scan Chain
+ .mbist_tdi_i (mbist_tdi_i) // from Mbist Chain
+
+ );
+
+
+// Connecting debug top module
+dbg_top i_dbg_top (
+ .tck_i (tck_pad_i),
+ .tdi_i (tdo_o),
+ .tdo_o (debug_tdi_i),
+ .rst_i (rst_i),
+
+ // TAP states
+ .shift_dr_i (shift_dr_o),
+ .pause_dr_i (pause_dr_o),
+ .update_dr_i (update_dr_o),
+
+ // Instructions
+ .debug_select_i (debug_select_o)
+
+ `ifdef DBG_WISHBONE_SUPPORTED
+ // WISHBONE common signals
+ ,
+ .wb_clk_i (wb_clk_i),
+
+ // WISHBONE master interface
+ .wb_adr_o (wb_adr_o),
+ .wb_dat_o (wb_dat_o),
+ .wb_dat_i (wb_dat_i),
+ .wb_cyc_o (wb_cyc_o),
+ .wb_stb_o (wb_stb_o),
+ .wb_sel_o (wb_sel_o),
+ .wb_we_o (wb_we_o),
+ .wb_ack_i (wb_ack_i),
+ .wb_cab_o (wb_cab_o),
+ .wb_err_i (wb_err_i),
+ .wb_cti_o (wb_cti_o),
+ .wb_bte_o (wb_bte_o)
+ `endif
+
+ `ifdef DBG_CPU0_SUPPORTED
+ // CPU signals
+ ,
+ .cpu0_clk_i (cpu0_clk_i),
+ .cpu0_addr_o (cpu0_addr_o),
+ .cpu0_data_i (cpu0_data_i),
+ .cpu0_data_o (cpu0_data_o),
+ .cpu0_bp_i (cpu0_bp_i),
+ .cpu0_stall_o (cpu0_stall_o),
+ .cpu0_stb_o (cpu0_stb_o),
+ .cpu0_we_o (cpu0_we_o),
+ .cpu0_ack_i (cpu0_ack_i),
+ .cpu0_rst_o (cpu0_rst_o)
+ `endif
+
+ `ifdef DBG_CPU1_SUPPORTED
+ // CPU signals
+ ,
+ .cpu1_clk_i (cpu1_clk_i),
+ .cpu1_addr_o (cpu1_addr_o),
+ .cpu1_data_i (cpu1_data_i),
+ .cpu1_data_o (cpu1_data_o),
+ .cpu1_bp_i (cpu1_bp_i),
+ .cpu1_stall_o (cpu1_stall_o),
+ .cpu1_stb_o (cpu1_stb_o),
+ .cpu1_we_o (cpu1_we_o),
+ .cpu1_ack_i (cpu1_ack_i),
+ .cpu1_rst_o (cpu1_rst_o)
+ `endif
+
+
+
+ );
+
+
+`ifdef DBG_WISHBONE_SUPPORTED
+wb_slave_behavioral wb_slave
+ (
+ .CLK_I (wb_clk_i),
+ .RST_I (rst_i),
+ .ACK_O (wb_ack_i),
+ .ADR_I (wb_adr_o),
+ .CYC_I (wb_cyc_o),
+ .DAT_O (wb_dat_i),
+ .DAT_I (wb_dat_o),
+ .ERR_O (wb_err_i),
+ .RTY_O (), // NOT USED for now!
+ .SEL_I (wb_sel_o),
+ .STB_I (wb_stb_o),
+ .WE_I (wb_we_o),
+ .CAB_I (1'b0)
+ );
+`endif
+
+
+`ifdef DBG_CPU0_SUPPORTED
+cpu_behavioral i_cpu0_behavioral
+ (
+ // CPU signals
+ .cpu_rst_i (rst_i),
+ .cpu_clk_o (cpu0_clk_i),
+ .cpu_addr_i (cpu0_addr_o),
+ .cpu_data_o (cpu0_data_i),
+ .cpu_data_i (cpu0_data_o),
+ .cpu_bp_o (cpu0_bp_i),
+ .cpu_stall_i (cpu0_stall_o),
+ .cpu_stb_i (cpu0_stb_o),
+ .cpu_we_i (cpu0_we_o),
+ .cpu_ack_o (cpu0_ack_i),
+ .cpu_rst_o (cpu0_rst_o)
+ );
+`endif
+
+
+
+`ifdef DBG_CPU1_SUPPORTED
+cpu_behavioral i_cpu1_behavioral
+ (
+ // CPU signals
+ .cpu_rst_i (rst_i),
+ .cpu_clk_o (cpu1_clk_i),
+ .cpu_addr_i (cpu1_addr_o),
+ .cpu_data_o (cpu1_data_i),
+ .cpu_data_i (cpu1_data_o),
+ .cpu_bp_o (cpu1_bp_i),
+ .cpu_stall_i (cpu1_stall_o),
+ .cpu_stb_i (cpu1_stb_o),
+ .cpu_we_i (cpu1_we_o),
+ .cpu_ack_o (cpu1_ack_i),
+ .cpu_rst_o (cpu1_rst_o)
+ );
+`endif
+
+
+
+// Initial values
+initial
+begin
+ trst_pad_i = 1'b1;
+ tms_pad_i = 1'hz;
+ tck_pad_i = 1'hz;
+ tdi_pad_i = 1'hz;
+
+ #100;
+ trst_pad_i = 1'b0;
+ #100;
+ trst_pad_i = 1'b1;
+end
+
+initial
+begin
+ test_enabled = 1'b0;
+ rst_i = 1'b0;
+ #1000;
+ rst_i = 1'b1;
+ #1000;
+ rst_i = 1'b0;
+
+ // Initial values for wishbone slave model
+ `ifdef DBG_WISHBONE_SUPPORTED
+// wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
+ wb_slave.cycle_response(`ACK_RESPONSE, 9'h35, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
+ `endif
+ #1 test_enabled<=#1 1'b1;
+end
+
+`ifdef DBG_WISHBONE_SUPPORTED
+initial
+begin
+ wb_clk_i = 1'b0;
+ forever #5 wb_clk_i = ~wb_clk_i;
+end
+`endif
+
+always @ (posedge test_enabled)
+begin
+ $display("//////////////////////////////////////////////////////////////////");
+ $display("// //");
+ $display("// (%0t) dbg_tb starting //", $time);
+ $display("// //");
+ $display("//////////////////////////////////////////////////////////////////");
+
+ $display("TEST: DBG_TEST");
+
+
+ initialize_memory(32'h12340000, 32'h00100000); // Initialize 0x100000 bytes starting from address 0x12340000
+
+ reset_tap;
+
+ #500;
+ goto_run_test_idle;
+
+// `ifdef DBG_CPU0_SUPPORTED
+// // Test stall signal
+// stall_test_cpu0;
+// `endif
+
+ // Testing read and write to internal registers
+ #10000;
+
+ id_test;
+
+ set_instruction(`DEBUG);
+ #10000;
+
+
+
+
+
+
+
+
+
+ #100000;
+ `ifdef DBG_WISHBONE_SUPPORTED
+ module_select(`DBG_TOP_WISHBONE_DEBUG_MODULE, 1'b0); // {module_id, gen_crc_err}
+
+ #10000;
+ debug_wishbone(`DBG_WB_READ32, 1'b0, 32'h12345678, 16'h3, 1'b0, "read32 1"); // {command, ready, addr, length, gen_crc_err, text}
+// debug_wishbone(`DBG_WB_WRITE8, 1'b0, 32'h23456788, 16'h7, 1'b0, "write32 1"); // {command, ready, addr, length, gen_crc_err, text}
+ debug_wishbone(`DBG_WB_WRITE32, 1'b0, 32'h23456788, 16'h7, 1'b0, "write32 1"); // {command, ready, addr, length, gen_crc_err, text}
+
+ #10000;
+ test_text = "debug_wishbone_rd_comm";
+ debug_wishbone_rd_comm(read_acc_type, read_addr, read_length);
+ $display("debug_wishbone_rd_comm returns: acc_type = 0x%0x, addr = 0x%0x, length = 0x%0x", read_acc_type, read_addr, read_length);
+ debug_wishbone_go(1'b0, 1'b0);
+ debug_wishbone_rd_comm(read_acc_type, read_addr, read_length);
+ $display("debug_wishbone_rd_comm returns: acc_type = 0x%0x, addr = 0x%0x, length = 0x%0x", read_acc_type, read_addr, read_length);
+
+ debug_wishbone_go(1'b0, 1'b0);
+
+ #100000;
+// debug_wishbone(`DBG_WB_READ32, 1'b0, 32'h12345224, 16'h7, 1'b0, "read32 1"); // {command, ready, addr, length, gen_crc_err, text}
+ debug_wishbone(`DBG_WB_READ8, 1'b0, 32'h12345223, 16'h8, 1'b0, "read8 1"); // {command, ready, addr, length, gen_crc_err, text}
+ #100000;
+ debug_wishbone_go(1'b0, 1'b0);
+
+
+/*
+// debug_wishbone(`DBG_WB_READ8, 1'b0, 32'h12345678, 16'h4, 1'b0, "abc 1"); // {command, ready, addr, length, gen_crc_err, text}
+// debug_wishbone(`DBG_WB_READ8, 1'b0, 32'h12345679, 16'h4, 1'b0, "abc 2"); // {command, ready, addr, length, gen_crc_err, text}
+// debug_wishbone(`DBG_WB_READ8, 1'b0, 32'h1234567a, 16'h4, 1'b0, "abc 3"); // {command, ready, addr, length, gen_crc_err, text}
+//
+// debug_wishbone(`DBG_WB_READ16, 1'b0, 32'h12345678, 16'h4, 1'b0, "abc 4"); // {command, ready, addr, length, gen_crc_err, text}
+// debug_wishbone(`DBG_WB_READ16, 1'b0, 32'h1234567a, 16'h4, 1'b0, "abc 5"); // {command, ready, addr, length, gen_crc_err, text}
+//
+ debug_wishbone(`DBG_WB_READ32, 1'b0, 32'h12345678, 16'h4, 1'b0, "read32 1"); // {command, ready, addr, length, gen_crc_err, text}
+//
+// debug_wishbone(`DBG_WB_READ16, 1'b0, 32'h12345679, 16'h4, 1'b0, "abc 6"); // {command, ready, addr, length, gen_crc_err, text}
+
+ #10000;
+
+ debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12345678, 16'h4, 1'b0, "read32 2"); // {command, ready, addr, length, gen_crc_err, text}
+
+ #10000;
+ wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
+ debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12346668, 16'h4, 1'b0, "read32 3"); // {command, ready, addr, length, gen_crc_err, text}
+
+ #10000;
+ wb_slave.cycle_response(`ERR_RESPONSE, 9'h03, 8'h2); // (`ERR_RESPONSE, wbs_waits, wbs_retries);
+ debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12346668, 16'h4, 1'b0, "read32 4"); // {command, ready, addr, length, gen_crc_err, text}
+
+ #10000;
+ debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 1'b0, "status 1"); // {command, ready, addr, length, gen_crc_err, text}
+
+ #10000;
+ debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 1'b0, "status 2"); // {command, ready, addr, length, gen_crc_err, text}
+
+ #10000;
+ wb_slave.cycle_response(`ACK_RESPONSE, 9'h012, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
+ debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12347778, 16'hc, 1'b0, "read32 5"); // {command, ready, addr, length, gen_crc_err, text}
+
+ #10000;
+ debug_wishbone(`DBG_WB_WRITE32, 1'b0, 32'h12346668, 16'h8, 1'b0, "wr32 len8"); // {command, ready, addr, length, gen_crc_err, text}
+
+ #10000;
+ debug_wishbone(`DBG_WB_WRITE16, 1'b0, 32'h12344446, 16'h8, 1'b0, "wr16 len8"); // {command, ready, addr, length, gen_crc_err, text}
+
+ #10000;
+ debug_wishbone(`DBG_WB_WRITE8, 1'b0, 32'h1234010e, 16'h8, 1'b0, "wr8 len8"); // {command, ready, addr, length, gen_crc_err, text}
+
+ #10000;
+ debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, "go 1"); // {command, ready, addr, length, gen_crc_err, text}
+
+ #10000;
+ debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12340100, 16'hc, 1'b0, "read32 6"); // {command, ready, addr, length, gen_crc_err, text}
+// debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12340100, 16'hfffc, 1'b0, "read32 6"); // {command, ready, addr, length, gen_crc_err, text}
+
+ #10000;
+// debug_wishbone(`DBG_WB_READ16, 1'b1, 32'h12340102, 16'he, 1'b0, "read16 7"); // {command, ready, addr, length, gen_crc_err, text}
+// debug_wishbone(`DBG_WB_READ16, 1'b1, 32'h12340102, 16'hfffe, 1'b0, "read16 7"); // {command, ready, addr, length, gen_crc_err, text}
+
+ #10000;
+// debug_wishbone(`DBG_WB_READ8, 1'b1, 32'h12348804, 16'h6, 1'b0, "read8 8"); // {command, ready, addr, length, gen_crc_err, text}
+// debug_wishbone(`DBG_WB_READ8, 1'b1, 32'h12348804, 16'hfffc, 1'b0, "read8 8"); // {command, ready, addr, length, gen_crc_err, text}
+
+ #10000;
+ debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, "go 2"); // {command, ready, addr, length, gen_crc_err, text}
+*/
+ `endif // DBG_WISHBONE_SUPPORTED
+
+ `ifdef DBG_CPU0_SUPPORTED
+ #10000;
+ module_select(`DBG_TOP_CPU0_DEBUG_MODULE, 1'b0); // {module_id, gen_crc_err}
+
+
+
+
+ // Select cpu0
+
+ #10000;
+ debug_cpu(`DBG_CPU_WRITE, 1'b0, 32'h23456788, 16'h3, 1'b0, "cpu write 1"); // {command, ready, addr, length, gen_crc_err, text}
+
+ #10000;
+ debug_cpu(`DBG_CPU_READ, 1'b0, 32'h23456788, 16'h3, 1'b0, "cpu read 1"); // {command, ready, addr, length, gen_crc_err, text}
+ // Read register
+ #10000;
+
+ debug_cpu(`DBG_CPU_WRITE, 1'b0, 32'h32323232, 16'h3, 1'b0, "cpu write 1"); // {command, ready, addr, length, gen_crc_err, text}
+
+ #10000;
+ debug_cpu(`DBG_CPU_READ, 1'b0, 32'h77665544, 16'h3, 1'b0, "cpu read 1"); // {command, ready, addr, length, gen_crc_err, text}
+ // Read register
+ #10000;
+
+ // Reset cpu on
+ debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b10, "rst cpu on"); // {data, text}
+ #10000;
+
+ // Reset cpu off
+ debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b00, "rst cpu off"); // {data, text}
+ #10000;
+
+ // Stall cpu
+ debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b01, "stall on"); // {data, text}
+ #10000;
+
+ debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b00, "stall off"); // {data, text}
+ #10000;
+
+ // Stall cpu0
+ debug_cpu_rd_ctrl(read_ctrl_reg, "read ctrl");
+ $display("debug_cpu_rd_ctrl returns: read_ctrl_reg = 0x%0x", read_ctrl_reg);
+ #10000;
+
+ debug_cpu(`DBG_CPU_READ, 1'b0, 32'h23456788, 16'h3, 1'b0, "cpu read 2"); // {command, ready, addr, length, gen_crc_err, text}
+ // write to cpu 32-bit
+ #10000;
+
+ debug_cpu(`DBG_CPU_WRITE, 1'b0, 32'h32323232, 16'hf, 1'b0, "cpu write 2"); // {command, ready, addr, length, gen_crc_err, text}
+
+ #10000;
+
+ // read from cpu 32-bit
+ #10000;
+
+ #10000;
+
+ `endif // DBG_CPU0_SUPPORTED
+
+
+ `ifdef DBG_CPU1_SUPPORTED
+ #10000;
+ module_select(`DBG_TOP_CPU1_DEBUG_MODULE, 1'b0); // {module_id, gen_crc_err}
+
+
+
+
+ // Select cpu1
+
+ #10000;
+ debug_cpu(`DBG_CPU_WRITE, 1'b0, 32'h23456788, 16'h3, 1'b0, "cpu write 1"); // {command, ready, addr, length, gen_crc_err, text}
+
+ #10000;
+ debug_cpu(`DBG_CPU_READ, 1'b0, 32'h23456788, 16'h3, 1'b0, "cpu read 1"); // {command, ready, addr, length, gen_crc_err, text}
+ // Read register
+ #10000;
+
+ debug_cpu(`DBG_CPU_WRITE, 1'b0, 32'h32323232, 16'h3, 1'b0, "cpu write 1"); // {command, ready, addr, length, gen_crc_err, text}
+
+ #10000;
+ debug_cpu(`DBG_CPU_READ, 1'b0, 32'h77665544, 16'h3, 1'b0, "cpu read 1"); // {command, ready, addr, length, gen_crc_err, text}
+ // Read register
+ #10000;
+
+ // Reset cpu on
+ debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b10, "rst cpu on"); // {data, text}
+ #10000;
+
+ // Reset cpu off
+ debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b00, "rst cpu off"); // {data, text}
+ #10000;
+
+ // Stall cpu
+ debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b01, "stall on"); // {data, text}
+ #10000;
+
+ debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b00, "stall off"); // {data, text}
+ #10000;
+
+ // Stall cpu1
+ debug_cpu_rd_ctrl(read_ctrl_reg, "read ctrl");
+ $display("debug_cpu_rd_ctrl returns: read_ctrl_reg = 0x%0x", read_ctrl_reg);
+ #10000;
+
+ debug_cpu(`DBG_CPU_READ, 1'b0, 32'h23456788, 16'h3, 1'b0, "cpu read 2"); // {command, ready, addr, length, gen_crc_err, text}
+ // write to cpu 32-bit
+ #10000;
+
+ debug_cpu(`DBG_CPU_WRITE, 1'b0, 32'h32323232, 16'hf, 1'b0, "cpu write 2"); // {command, ready, addr, length, gen_crc_err, text}
+
+ #10000;
+
+ // read from cpu 32-bit
+ #10000;
+
+ #10000;
+
+ `endif // DBG_CPU1_SUPPORTED
+
+
+
+
+
+
+
+
+
+ #5000 gen_clk(1); // One extra TCLK for debugging purposes
+ $display("STATUS: passed");
+ $display("\n\nSimulation end.");
+ #1000 $stop;
+
+end
+
+
+`ifdef DBG_CPU0_SUPPORTED
+task stall_test_cpu0;
+ integer i;
+
+ begin
+ test_text = "stall_test_cpu0";
+ $display("\n\n(%0t) stall_test_cpu0 started", $time);
+
+ // Set bp_i active for 1 clock cycle and check is stall is set or not
+ check_stall_cpu0(0); // Should not be set at the beginning
+ @ (posedge cpu0_clk_i);
+ #1 dbg_tb.i_cpu0_behavioral.cpu_bp_o = 1'b1;
+ #1 check_stall_cpu0(1); // set?
+ @ (posedge cpu0_clk_i);
+ #1 dbg_tb.i_cpu0_behavioral.cpu_bp_o = 1'b0;
+ #1 check_stall_cpu0(1); // set?
+
+ gen_clk(1);
+ #1 check_stall_cpu0(1); // set?
+
+ // Unstall with register
+ set_instruction(`DEBUG);
+ module_select(`DBG_TOP_CPU0_DEBUG_MODULE, 1'b0); // {module_id, gen_crc_err}
+ #1 check_stall_cpu0(1); // set?
+// igor !!! debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr unstall"); // {command, addr, data, gen_crc_err, result, text}
+ #1 check_stall_cpu0(1); // set?
+ debug_cpu(`DBG_CPU_WR_COMM, 32'h0, 32'h0, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
+ #1 check_stall_cpu0(0); // reset?
+
+ // Set stall with register
+// igor !!! debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr stall"); // {command, addr, data, gen_crc_err, result, text}
+ #1 check_stall_cpu0(0); // reset?
+ debug_cpu(`DBG_CPU_WR_COMM, 32'h0, 32'h1, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
+ #1 check_stall_cpu0(1); // set?
+
+ // Unstall with register
+// igor !!! debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr unstall"); // {command, addr, data, gen_crc_err, result, text}
+ #1 check_stall_cpu0(1); // set?
+ debug_cpu(`DBG_CPU_WR_COMM, 32'h0, 32'h0, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
+ #1 check_stall_cpu0(0); // reset?
+
+ $display("\n\n(%0t) stall_test_cpu0 passed\n\n", $time);
+ end
+endtask // stall_test_cpu0
+
+
+task check_stall_cpu0;
+ input should_be_set;
+ begin
+ if (should_be_set && (!cpu0_stall_o))
+ begin
+ $display ("\t\t(%0t) ERROR: cpu0_stall_o is not set but should be.", $time);
+ $stop;
+ end
+ if ((!should_be_set) && cpu0_stall_o)
+ begin
+ $display ("\t\t(%0t) ERROR: cpu0_stall_o set but shouldn't be.", $time);
+ $stop;
+ end
+ end
+endtask // check_stall_cpu0
+`endif // DBG_CPU0_SUPPORTED
+
+
+task initialize_memory;
+ input [31:0] start_addr;
+ input [31:0] length;
+ integer i;
+ reg [31:0] addr;
+ begin
+ for (i=0; i=0; i=i-1) // Shifting module ID
+ begin
+ tdi_pad_i<=#1 data[i];
+ calculate_crc(data[i]);
+ gen_clk(1);
+ end
+
+ for(i=`DBG_TOP_CRC_LEN -1; i>=0; i=i-1)
+ begin
+ if (gen_crc_err & (i==0)) // Generate crc error at last crc bit
+ tdi_pad_i<=#1 ~crc_out[i]; // error crc
+ else
+ tdi_pad_i<=#1 crc_out[i]; // ok crc
+
+ gen_clk(1);
+ end
+
+ tdi_pad_i<=#1 1'hz; // tri-state
+
+ crc_in = {`DBG_TOP_CRC_LEN{1'b1}}; // Initialize incoming CRC to all ff
+
+ for(i=`DBG_TOP_STATUS_LEN -1; i>=0; i=i-1)
+ begin
+ gen_clk(1); // Generating 1 clock to read out a status bit.
+ status[i] = tdo;
+ end
+
+ for(i=0; i<`DBG_TOP_CRC_LEN -1; i=i+1)
+ gen_clk(1);
+
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1); // to exit1_dr
+
+ if (~crc_match_in)
+ begin
+ $display("(%0t) Incoming CRC failed !!!", $time);
+ $stop;
+ end
+
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1); // to update_dr
+ tms_pad_i<=#1 1'b0;
+ gen_clk(1); // to run_test_idle
+
+ if (|status)
+ begin
+ $write("(*E) (%0t) Module select error: ", $time);
+ casex (status)
+ 4'b1xxx : $display("CRC error !!!\n\n", $time);
+ 4'bx1xx : $display("Non-existing module selected !!!\n\n", $time);
+ 4'bxx1x : $display("Status[1] should be 1'b0 !!!\n\n", $time);
+ 4'bxxx1 : $display("Status[0] should be 1'b0 !!!\n\n", $time);
+ endcase
+ $stop;
+ end
+ end
+endtask // module_select
+
+
+
+
+`ifdef DBG_WISHBONE_SUPPORTED
+task debug_wishbone;
+ input [`DBG_WB_CMD_LEN -1:0] command;
+ input ready;
+ input [`DBG_WB_ADR_LEN -1:0] addr;
+ input [`DBG_WB_LEN_LEN -1:0] length;
+ input gen_crc_err;
+ input [99:0] text;
+ integer i;
+
+ begin
+ $write("(%0t) Task debug_wishbone: ", $time);
+
+ test_text = text;
+
+ case (command)
+ `DBG_WB_READ8 :
+ begin
+ $display("wb_read8 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
+ debug_wishbone_wr_comm(`DBG_WB_READ8, addr, length, gen_crc_err);
+ last_wb_cmd = `DBG_WB_READ8; last_wb_cmd_text = "DBG_WB_READ8";
+#10000;
+ length_global = length + 1;
+ debug_wishbone_go(ready, gen_crc_err);
+ end
+ `DBG_WB_READ16 :
+ begin
+ $display("wb_read16 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
+ debug_wishbone_wr_comm(`DBG_WB_READ16, addr, length, gen_crc_err);
+ last_wb_cmd = `DBG_WB_READ16; last_wb_cmd_text = "DBG_WB_READ16";
+#10000;
+ length_global = length + 1;
+ debug_wishbone_go(ready, gen_crc_err);
+ end
+ `DBG_WB_READ32 :
+ begin
+ $display("wb_read32 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
+ debug_wishbone_wr_comm(`DBG_WB_READ32, addr, length, gen_crc_err);
+ last_wb_cmd = `DBG_WB_READ32; last_wb_cmd_text = "DBG_WB_READ32";
+#10000;
+ length_global = length + 1;
+ debug_wishbone_go(ready, gen_crc_err);
+ end
+ `DBG_WB_WRITE8 :
+ begin
+ $display("wb_write8 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
+ debug_wishbone_wr_comm(`DBG_WB_WRITE8, addr, length, gen_crc_err);
+ last_wb_cmd = `DBG_WB_WRITE8; last_wb_cmd_text = "DBG_WB_WRITE8";
+#10000;
+ length_global = length + 1;
+ debug_wishbone_go(ready, gen_crc_err);
+ end
+ `DBG_WB_WRITE16 :
+ begin
+ $display("wb_write16 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
+ debug_wishbone_wr_comm(`DBG_WB_WRITE16, addr, length, gen_crc_err);
+ last_wb_cmd = `DBG_WB_WRITE16; last_wb_cmd_text = "DBG_WB_WRITE16";
+#10000;
+ length_global = length + 1;
+ debug_wishbone_go(ready, gen_crc_err);
+ end
+ `DBG_WB_WRITE32 :
+ begin
+ $display("wb_write32 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
+ debug_wishbone_wr_comm(`DBG_WB_WRITE32, addr, length, gen_crc_err);
+ last_wb_cmd = `DBG_WB_WRITE32; last_wb_cmd_text = "DBG_WB_WRITE32";
+#10000;
+ length_global = length + 1;
+ debug_wishbone_go(ready, gen_crc_err);
+ end
+ default:
+ begin
+ $display("(*E) debug_wishbone : Unsupported instruction !!!");
+ $stop;
+ end
+ endcase
+ end
+endtask // debug_wishbone
+
+
+
+
+
+
+task debug_wishbone_wr_comm;
+ input [`DBG_WB_ACC_TYPE_LEN -1:0] acc_type;
+ input [`DBG_WB_ADR_LEN -1:0] addr;
+ input [`DBG_WB_LEN_LEN -1:0] length;
+ input gen_crc_err;
+ integer i;
+ reg [`DBG_WB_CMD_LEN -1:0] command;
+
+ begin
+ $display("(%0t) Task debug_wishbone_wr_comm: ", $time);
+
+ command = `DBG_WB_WR_COMM;
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1);
+ tms_pad_i<=#1 1'b0;
+ gen_clk(2); // we are in shiftDR
+
+ crc_out = {`DBG_WB_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
+
+ tdi_pad_i<=#1 1'b0; // module_select bit = 0
+ calculate_crc(1'b0);
+ gen_clk(1);
+
+ for(i=`DBG_WB_CMD_LEN -1; i>=0; i=i-1)
+ begin
+ tdi_pad_i<=#1 command[i]; // command
+ calculate_crc(command[i]);
+ gen_clk(1);
+ end
+
+ for(i=`DBG_WB_ACC_TYPE_LEN -1; i>=0; i=i-1)
+ begin
+ tdi_pad_i<=#1 acc_type[i]; // command
+ calculate_crc(acc_type[i]);
+ gen_clk(1);
+ end
+
+ for(i=`DBG_WB_ADR_LEN -1; i>=0; i=i-1) // address
+ begin
+ tdi_pad_i<=#1 addr[i];
+ calculate_crc(addr[i]);
+ gen_clk(1);
+ end
+
+ for(i=`DBG_WB_LEN_LEN -1; i>=0; i=i-1) // length
+ begin
+ tdi_pad_i<=#1 length[i];
+ calculate_crc(length[i]);
+ gen_clk(1);
+ end
+
+ for(i=`DBG_WB_CRC_LEN -1; i>=0; i=i-1)
+ begin
+ if (gen_crc_err & (i==0)) // Generate crc error at last crc bit
+ tdi_pad_i<=#1 ~crc_out[i]; // error crc
+ else
+ tdi_pad_i<=#1 crc_out[i]; // ok crc
+
+ gen_clk(1);
+ end
+
+ tdi_pad_i<=#1 1'hz;
+
+ crc_in = {`DBG_WB_CRC_LEN{1'b1}}; // Initialize incoming CRC to all ff
+
+ for(i=`DBG_WB_STATUS_LEN -1; i>=0; i=i-1)
+ begin
+ gen_clk(1); // Generating clock to read out a status bit.
+ status_wb[i] = tdo;
+ end
+
+ if (|status_wb)
+ begin
+ $write("(*E) (%0t) debug_wishbone_wr_comm error: ", $time);
+ casex (status_wb)
+ 4'b1xxx : $display("CRC error !!!\n\n", $time);
+ 4'bx1xx : $display("Unknown command !!!\n\n", $time);
+ 4'bxx1x : $display("WISHBONE error !!!\n\n", $time);
+ 4'bxxx1 : $display("Overrun/Underrun !!!\n\n", $time);
+ endcase
+ $stop;
+ end
+
+
+ for(i=0; i<`DBG_WB_CRC_LEN -1; i=i+1) // Getting in the CRC
+ begin
+ gen_clk(1);
+ end
+
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1); // to exit1_dr
+
+ if (~crc_match_in)
+ begin
+ $display("(%0t) Incoming CRC failed !!!", $time);
+ $stop;
+ end
+
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1); // to update_dr
+ tms_pad_i<=#1 1'b0;
+ gen_clk(1); // to run_test_idle
+ end
+endtask // debug_wishbone_wr_comm
+
+
+
+
+
+task debug_wishbone_rd_comm;
+ output [`DBG_WB_ACC_TYPE_LEN -1:0] acc_type;
+ output [`DBG_WB_ADR_LEN -1:0] addr;
+ output [`DBG_WB_LEN_LEN -1:0] length;
+ integer i;
+ reg [`DBG_WB_CMD_LEN -1:0] command;
+
+ begin
+ $display("(%0t) Task debug_wishbone_rd_comm: ", $time);
+
+ command = `DBG_WB_RD_COMM;
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1);
+ tms_pad_i<=#1 1'b0;
+ gen_clk(2); // we are in shiftDR
+
+ crc_out = {`DBG_WB_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
+
+ tdi_pad_i<=#1 1'b0; // module_select bit = 0
+ calculate_crc(1'b0);
+ gen_clk(1);
+
+ for(i=`DBG_WB_CMD_LEN -1; i>=0; i=i-1)
+ begin
+ tdi_pad_i<=#1 command[i]; // command
+ calculate_crc(command[i]);
+ gen_clk(1);
+ end
+
+ for(i=`DBG_WB_CRC_LEN -1; i>=0; i=i-1)
+ begin
+ tdi_pad_i<=#1 crc_out[i];
+ gen_clk(1);
+ end
+
+ tdi_pad_i<=#1 1'hz;
+
+ crc_in = {`DBG_WB_CRC_LEN{1'b1}}; // Initialize incoming CRC to all ff
+
+ for(i=`DBG_WB_ACC_TYPE_LEN -1; i>=0; i=i-1)
+ begin
+ gen_clk(1);
+ acc_type[i] = tdo;
+ end
+
+ for(i=`DBG_WB_ADR_LEN -1; i>=0; i=i-1) // address
+ begin
+ gen_clk(1);
+ addr[i] = tdo;
+ end
+
+ for(i=`DBG_WB_LEN_LEN -1; i>=0; i=i-1) // length
+ begin
+ gen_clk(1);
+ length[i] = tdo;
+ end
+
+ for(i=`DBG_WB_STATUS_LEN -1; i>=0; i=i-1)
+ begin
+ gen_clk(1); // Generating clock to read out a status bit.
+ status_wb[i] = tdo;
+ end
+
+ if (|status_wb)
+ begin
+ $write("(*E) (%0t) debug_wishbone_rd_comm: ", $time);
+ casex (status_wb)
+ 4'b1xxx : $display("CRC error !!!\n\n", $time);
+ 4'bx1xx : $display("Unknown command !!!\n\n", $time);
+ 4'bxx1x : $display("Unknown command !!!\n\n", $time);
+ 4'bxxx1 : $display("Unknown command !!!\n\n", $time);
+ endcase
+ $stop;
+ end
+
+
+ for(i=0; i<`DBG_WB_CRC_LEN -1; i=i+1) // Getting in the CRC
+ begin
+ gen_clk(1);
+ end
+
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1); // to exit1_dr
+
+ if (~crc_match_in)
+ begin
+ $display("(%0t) Incoming CRC failed !!!", $time);
+ $stop;
+ end
+
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1); // to update_dr
+ tms_pad_i<=#1 1'b0;
+ gen_clk(1); // to run_test_idle
+ end
+endtask // debug_wishbone_rd_comm
+
+
+
+
+
+task debug_wishbone_go;
+ input wait_for_wb_ready;
+ input gen_crc_err;
+ integer i;
+ reg [4:0] bit_pointer;
+ integer word_pointer;
+ reg [31:0] tmp_data;
+ reg [`DBG_WB_CMD_LEN -1:0] command;
+
+
+ begin
+ $display("(%0t) Task debug_wishbone_go (previous command was %0s): ", $time, last_wb_cmd_text);
+ command = `DBG_WB_GO;
+ word_pointer = 0;
+
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1);
+ tms_pad_i<=#1 1'b0;
+ gen_clk(2); // we are in shiftDR
+
+ crc_out = {`DBG_WB_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
+
+ tdi_pad_i<=#1 1'b0; // module_select bit = 0
+ calculate_crc(1'b0);
+ gen_clk(1);
+
+ for(i=`DBG_WB_CMD_LEN -1; i>=0; i=i-1)
+ begin
+ tdi_pad_i<=#1 command[i]; // command
+ calculate_crc(command[i]);
+ gen_clk(1);
+ end
+
+
+ if ((last_wb_cmd == `DBG_WB_WRITE8) | (last_wb_cmd == `DBG_WB_WRITE16) | (last_wb_cmd == `DBG_WB_WRITE32)) // When WB_WRITEx was previously activated, data needs to be shifted.
+ begin
+ for (i=0; i<((length_global) << 3); i=i+1)
+ begin
+ tmp_data = wb_data[word_pointer];
+ if ((!(i%32)) && (i>0))
+ begin
+ word_pointer = word_pointer + 1;
+ end
+ bit_pointer = 31-i[4:0];
+ tdi_pad_i<=#1 tmp_data[bit_pointer];
+ calculate_crc(tmp_data[bit_pointer]);
+ gen_clk(1);
+
+ end
+ end
+
+ for(i=`DBG_WB_CRC_LEN -1; i>=1; i=i-1)
+ begin
+ tdi_pad_i<=#1 crc_out[i];
+ gen_clk(1);
+ end
+
+ if (gen_crc_err) // Generate crc error at last crc bit
+ tdi_pad_i<=#1 ~crc_out[0]; // error crc
+ else
+ tdi_pad_i<=#1 crc_out[0]; // ok crc
+
+ if (wait_for_wb_ready)
+ begin
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1); // to exit1_dr. Last CRC is shifted on this clk
+ tms_pad_i<=#1 1'b0;
+ gen_clk(1); // to pause_dr
+
+ #2; // wait a bit for tdo to activate
+ while (tdo) // waiting for wb to send "ready"
+ begin
+ gen_clk(1); // staying in pause_dr
+ end
+
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1); // to exit2_dr
+ tms_pad_i<=#1 1'b0;
+ gen_clk(1); // to shift_dr
+ end
+ else
+ begin
+ gen_clk(1); // Last CRC is shifted on this clk
+ end
+
+
+ tdi_pad_i<=#1 1'hz;
+ crc_in = {`DBG_WB_CRC_LEN{1'b1}}; // Initialize incoming CRC to all ff
+
+ if ((last_wb_cmd == `DBG_WB_READ8) | (last_wb_cmd == `DBG_WB_READ16) | (last_wb_cmd == `DBG_WB_READ32)) // When WB_READx was previously activated, data needs to be shifted.
+ begin
+ $display("\t\tGenerating %0d clocks to read %0d data bytes.", length_global<<3, length_global);
+ word_pointer = 0; // Reset pointer
+ for (i=0; i<(length_global<<3); i=i+1)
+ begin
+ gen_clk(1);
+ if (i[4:0] == 31) // Latching data
+ begin
+ wb_data[word_pointer] = in_data_be;
+ $display("\t\tin_data_be = 0x%x", in_data_be);
+ word_pointer = word_pointer + 1;
+ end
+ end
+ end
+
+
+ for(i=`DBG_WB_STATUS_LEN -1; i>=0; i=i-1)
+ begin
+ gen_clk(1); // Generating clock to read out a status bit.
+ status_wb[i] = tdo;
+ end
+
+ if (|status_wb)
+ begin
+ $write("(*E) (%0t) debug_wishbone_go error: ", $time);
+ casex (status_wb)
+ 4'b1xxx : $display("CRC error !!!\n\n", $time);
+ 4'bx1xx : $display("Unknown command !!!\n\n", $time);
+ 4'bxx1x : $display("WISHBONE error !!!\n\n", $time);
+ 4'bxxx1 : $display("Overrun/Underrun !!!\n\n", $time);
+ endcase
+ $stop;
+ end
+
+
+ for(i=0; i<`DBG_WB_CRC_LEN -1; i=i+1) // Getting in the CRC
+ begin
+ gen_clk(1);
+ end
+
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1); // to exit1_dr
+
+ if (~crc_match_in)
+ begin
+ $display("(%0t) Incoming CRC failed !!!", $time);
+ $stop;
+ end
+
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1); // to update_dr
+ tms_pad_i<=#1 1'b0;
+ gen_clk(1); // to run_test_idle
+ end
+endtask // debug_wishbone_go
+
+
+`endif // DBG_WISHBONE_SUPPORTED
+
+
+`ifdef DBG_CPU_SUPPORTED
+task debug_cpu;
+ input [`DBG_CPU_CMD_LEN -1:0] command;
+ input ready;
+ input [`DBG_CPU_ADR_LEN -1:0] addr;
+ input [`DBG_CPU_LEN_LEN -1:0] length;
+ input gen_crc_err;
+ input [99:0] text;
+ integer i;
+
+ begin
+ $write("(%0t) Task debug_cpu: ", $time);
+
+ test_text = text;
+
+ case (command)
+ `DBG_CPU_READ :
+ begin
+ $display("cpu_read (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
+ debug_cpu_wr_comm(`DBG_CPU_READ, addr, length, gen_crc_err);
+ last_cpu_cmd = `DBG_CPU_READ; last_cpu_cmd_text = "DBG_CPU_READ";
+ length_global = length + 1;
+#10000;
+ debug_cpu_go(ready, gen_crc_err);
+ end
+ `DBG_CPU_WRITE :
+ begin
+ $display("cpu_write (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
+ debug_cpu_wr_comm(`DBG_CPU_WRITE, addr, length, gen_crc_err);
+ last_cpu_cmd = `DBG_CPU_WRITE; last_cpu_cmd_text = "DBG_CPU_WRITE";
+#10000;
+ length_global = length + 1;
+ debug_cpu_go(ready, gen_crc_err);
+ end
+ default:
+ begin
+ $display("(*E) debug_cpu : Unsupported instruction !!!");
+ $stop;
+ end
+ endcase
+ end
+endtask // debug_cpu
+
+
+
+task debug_cpu_wr_comm;
+ input [`DBG_CPU_ACC_TYPE_LEN -1:0] acc_type;
+ input [`DBG_CPU_ADR_LEN -1:0] addr;
+ input [`DBG_CPU_LEN_LEN -1:0] length;
+ input gen_crc_err;
+ integer i;
+ reg [`DBG_CPU_CMD_LEN -1:0] command;
+
+ begin
+ $display("(%0t) Task debug_cpu_wr_comm: ", $time);
+
+ command = `DBG_CPU_WR_COMM;
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1);
+ tms_pad_i<=#1 1'b0;
+ gen_clk(2); // we are in shiftDR
+
+ crc_out = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
+
+ tdi_pad_i<=#1 1'b0; // module_select bit = 0
+ calculate_crc(1'b0);
+ gen_clk(1);
+
+ for(i=`DBG_CPU_CMD_LEN -1; i>=0; i=i-1)
+ begin
+ tdi_pad_i<=#1 command[i]; // command
+ calculate_crc(command[i]);
+ gen_clk(1);
+ end
+
+ for(i=`DBG_CPU_ACC_TYPE_LEN -1; i>=0; i=i-1)
+ begin
+ tdi_pad_i<=#1 acc_type[i]; // command
+ calculate_crc(acc_type[i]);
+ gen_clk(1);
+ end
+
+ for(i=`DBG_CPU_ADR_LEN -1; i>=0; i=i-1) // address
+ begin
+ tdi_pad_i<=#1 addr[i];
+ calculate_crc(addr[i]);
+ gen_clk(1);
+ end
+
+ for(i=`DBG_CPU_LEN_LEN -1; i>=0; i=i-1) // length
+ begin
+ tdi_pad_i<=#1 length[i];
+ calculate_crc(length[i]);
+ gen_clk(1);
+ end
+
+ for(i=`DBG_CPU_CRC_LEN -1; i>=0; i=i-1)
+ begin
+ if (gen_crc_err & (i==0)) // Generate crc error at last crc bit
+ tdi_pad_i<=#1 ~crc_out[i]; // error crc
+ else
+ tdi_pad_i<=#1 crc_out[i]; // ok crc
+
+ gen_clk(1);
+ end
+
+ tdi_pad_i<=#1 1'hz;
+
+ crc_in = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize incoming CRC to all ff
+
+ for(i=`DBG_CPU_STATUS_LEN -1; i>=0; i=i-1)
+ begin
+ gen_clk(1); // Generating clock to read out a status bit.
+ status_cpu[i] = tdo;
+ end
+
+ if (|status_cpu)
+ begin
+ $write("(*E) (%0t) debug_cpu_wr_comm error: ", $time);
+ casex (status_cpu)
+ 4'b1xxx : $display("CRC error !!!\n\n", $time);
+ 4'bx1xx : $display("Unknown command !!!\n\n", $time);
+ 4'bxx1x : $display("??? error !!!\n\n", $time);
+ 4'bxxx1 : $display("Overrun/Underrun !!!\n\n", $time);
+ endcase
+ $stop;
+ end
+
+
+ for(i=0; i<`DBG_CPU_CRC_LEN -1; i=i+1) // Getting in the CRC
+ begin
+ gen_clk(1);
+ end
+
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1); // to exit1_dr
+
+ if (~crc_match_in)
+ begin
+ $display("(%0t) Incoming CRC failed !!!", $time);
+ $stop;
+ end
+
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1); // to update_dr
+ tms_pad_i<=#1 1'b0;
+ gen_clk(1); // to run_test_idle
+ end
+endtask // debug_cpu_wr_comm
+
+
+
+task debug_cpu_wr_ctrl;
+ input [`DBG_CPU_CTRL_LEN -1:0] data;
+ input [99:0] text;
+ integer i;
+ reg [`DBG_CPU_CMD_LEN -1:0] command;
+
+ begin
+ test_text = text;
+
+ $display("(%0t) Task debug_cpu_wr_ctrl (data=0x%0x (%0s))", $time, data, text);
+
+ command = `DBG_CPU_WR_CTRL;
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1);
+ tms_pad_i<=#1 1'b0;
+ gen_clk(2); // we are in shiftDR
+
+ crc_out = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
+
+ tdi_pad_i<=#1 1'b0; // module_select bit = 0
+ calculate_crc(1'b0);
+ gen_clk(1);
+
+ for(i=`DBG_CPU_CMD_LEN -1; i>=0; i=i-1)
+ begin
+ tdi_pad_i<=#1 command[i]; // command
+ calculate_crc(command[i]);
+ gen_clk(1);
+ end
+
+ for(i=`DBG_CPU_CTRL_LEN -1; i>=0; i=i-1)
+ begin
+ tdi_pad_i<=#1 data[i]; // data (used cotrol bits
+ calculate_crc(data[i]);
+ gen_clk(1);
+ end
+
+ for(i=`DBG_CPU_DR_LEN - `DBG_CPU_CTRL_LEN -1; i>=0; i=i-1) // unused control bits
+ begin
+ tdi_pad_i<=#1 1'b0;
+ calculate_crc(1'b0);
+ gen_clk(1);
+ end
+
+ for(i=`DBG_CPU_CRC_LEN -1; i>=0; i=i-1)
+ begin
+ tdi_pad_i<=#1 crc_out[i]; // ok crc
+ gen_clk(1);
+ end
+
+ tdi_pad_i<=#1 1'hz;
+
+ crc_in = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize incoming CRC to all ff
+
+ for(i=`DBG_CPU_STATUS_LEN -1; i>=0; i=i-1)
+ begin
+ gen_clk(1); // Generating clock to read out a status bit.
+ status_cpu[i] = tdo;
+ end
+
+ if (|status_cpu)
+ begin
+ $write("(*E) (%0t) debug_cpu_wr_ctrl error: ", $time);
+ casex (status_cpu)
+ 4'b1xxx : $display("CRC error !!!\n\n", $time);
+ 4'bx1xx : $display("??? error !!!\n\n", $time);
+ 4'bxx1x : $display("??? error !!!\n\n", $time);
+ 4'bxxx1 : $display("??? error !!!\n\n", $time);
+ endcase
+ $stop;
+ end
+
+
+ for(i=0; i<`DBG_CPU_CRC_LEN -1; i=i+1) // Getting in the CRC
+ begin
+ gen_clk(1);
+ end
+
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1); // to exit1_dr
+
+ if (~crc_match_in)
+ begin
+ $display("(%0t) Incoming CRC failed !!!", $time);
+ $stop;
+ end
+
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1); // to update_dr
+ tms_pad_i<=#1 1'b0;
+ gen_clk(1); // to run_test_idle
+ end
+endtask // debug_cpu_wr_ctrl
+
+
+
+task debug_cpu_rd_ctrl;
+ output [`DBG_CPU_CTRL_LEN -1:0] data;
+ input [99:0] text;
+ integer i;
+ reg [`DBG_CPU_CMD_LEN -1:0] command;
+
+ begin
+ test_text = text;
+ $display("(%0t) Task debug_cpu_rd_ctrl: ", $time);
+
+ command = `DBG_CPU_RD_CTRL;
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1);
+ tms_pad_i<=#1 1'b0;
+ gen_clk(2); // we are in shiftDR
+
+ crc_out = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
+
+ tdi_pad_i<=#1 1'b0; // module_select bit = 0
+ calculate_crc(1'b0);
+ gen_clk(1);
+
+ for(i=`DBG_CPU_CMD_LEN -1; i>=0; i=i-1)
+ begin
+ tdi_pad_i<=#1 command[i]; // command
+ calculate_crc(command[i]);
+ gen_clk(1);
+ end
+
+ for(i=`DBG_CPU_CRC_LEN -1; i>=0; i=i-1)
+ begin
+ tdi_pad_i<=#1 crc_out[i];
+ gen_clk(1);
+ end
+
+ tdi_pad_i<=#1 1'hz;
+
+ crc_in = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize incoming CRC to all ff
+
+ for(i=`DBG_CPU_CTRL_LEN -1; i>=0; i=i-1) // data (used control bits)
+ begin
+ gen_clk(1);
+ data[i] = tdo;
+ end
+
+ for(i=`DBG_CPU_DR_LEN - `DBG_CPU_CTRL_LEN -1; i>=0; i=i-1) // unused control bits
+ begin
+ gen_clk(1);
+ end
+
+ for(i=`DBG_CPU_STATUS_LEN -1; i>=0; i=i-1)
+ begin
+ gen_clk(1); // Generating clock to read out a status bit.
+ status_cpu[i] = tdo;
+ end
+
+ if (|status_cpu)
+ begin
+ $write("(*E) (%0t) debug_cpu_rd_ctrl: ", $time);
+ casex (status_cpu)
+ 4'b1xxx : $display("CRC error !!!\n\n", $time);
+ 4'bx1xx : $display("Unknown command !!!\n\n", $time);
+ 4'bxx1x : $display("Unknown command !!!\n\n", $time);
+ 4'bxxx1 : $display("Unknown command !!!\n\n", $time);
+ endcase
+ $stop;
+ end
+
+
+ for(i=0; i<`DBG_CPU_CRC_LEN -1; i=i+1) // Getting in the CRC
+ begin
+ gen_clk(1);
+ end
+
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1); // to exit1_dr
+
+ if (~crc_match_in)
+ begin
+ $display("(%0t) Incoming CRC failed !!!", $time);
+ $stop;
+ end
+
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1); // to update_dr
+ tms_pad_i<=#1 1'b0;
+ gen_clk(1); // to run_test_idle
+ end
+endtask // debug_cpu_rd_ctrl
+
+
+
+task debug_cpu_go;
+ input wait_for_cpu_ready;
+ input gen_crc_err;
+ integer i;
+ reg [4:0] bit_pointer;
+ integer word_pointer;
+ reg [31:0] tmp_data;
+ reg [`DBG_CPU_CMD_LEN -1:0] command;
+
+
+ begin
+ $display("(%0t) Task debug_cpu_go (previous command was %0s): ", $time, last_cpu_cmd_text);
+ command = `DBG_CPU_GO;
+ word_pointer = 0;
+
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1);
+ tms_pad_i<=#1 1'b0;
+ gen_clk(2); // we are in shiftDR
+
+ crc_out = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
+
+ tdi_pad_i<=#1 1'b0; // module_select bit = 0
+ calculate_crc(1'b0);
+ gen_clk(1);
+
+ for(i=`DBG_CPU_CMD_LEN -1; i>=0; i=i-1)
+ begin
+ tdi_pad_i<=#1 command[i]; // command
+ calculate_crc(command[i]);
+ gen_clk(1);
+ end
+
+
+ if (last_cpu_cmd == `DBG_CPU_WRITE) // When DBG_CPU_WRITE was previously activated, data needs to be shifted.
+ begin
+ for (i=0; i<((length_global) << 3); i=i+1)
+ begin
+ tmp_data = wb_data[word_pointer];
+ if ((!(i%32)) && (i>0))
+ begin
+ word_pointer = word_pointer + 1;
+ end
+ bit_pointer = 31-i[4:0];
+ tdi_pad_i<=#1 tmp_data[bit_pointer];
+ calculate_crc(tmp_data[bit_pointer]);
+ gen_clk(1);
+
+ end
+ end
+
+ for(i=`DBG_CPU_CRC_LEN -1; i>=1; i=i-1)
+ begin
+ tdi_pad_i<=#1 crc_out[i];
+ gen_clk(1);
+ end
+
+ if (gen_crc_err) // Generate crc error at last crc bit
+ tdi_pad_i<=#1 ~crc_out[0]; // error crc
+ else
+ tdi_pad_i<=#1 crc_out[0]; // ok crc
+
+ if (wait_for_cpu_ready)
+ begin
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1); // to exit1_dr. Last CRC is shifted on this clk
+ tms_pad_i<=#1 1'b0;
+ gen_clk(1); // to pause_dr
+
+ #2; // wait a bit for tdo to activate
+ while (tdo) // waiting for wb to send "ready"
+ begin
+ gen_clk(1); // staying in pause_dr
+ end
+
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1); // to exit2_dr
+ tms_pad_i<=#1 1'b0;
+ gen_clk(1); // to shift_dr
+ end
+ else
+ begin
+ gen_clk(1); // Last CRC is shifted on this clk
+ end
+
+
+ tdi_pad_i<=#1 1'hz;
+ crc_in = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize incoming CRC to all ff
+
+ if (last_cpu_cmd == `DBG_CPU_READ) // When DBG_CPU_READ was previously activated, data needs to be shifted.
+ begin
+ $display("\t\tGenerating %0d clocks to read %0d data bytes.", length_global<<3, length_global);
+ word_pointer = 0; // Reset pointer
+ for (i=0; i<(length_global<<3); i=i+1)
+ begin
+ gen_clk(1);
+ if (i[4:0] == 31) // Latching data
+ begin
+ wb_data[word_pointer] = in_data_be;
+ $display("\t\tin_data_be = 0x%x", in_data_be);
+ word_pointer = word_pointer + 1;
+ end
+ end
+ end
+
+
+ for(i=`DBG_CPU_STATUS_LEN -1; i>=0; i=i-1)
+ begin
+ gen_clk(1); // Generating clock to read out a status bit.
+ status_cpu[i] = tdo;
+ end
+
+ if (|status_cpu)
+ begin
+ $write("(*E) (%0t) debug_cpu_go error: ", $time);
+ casex (status_cpu)
+ 4'b1xxx : $display("CRC error !!!\n\n", $time);
+ 4'bx1xx : $display("Unknown command !!!\n\n", $time);
+ 4'bxx1x : $display("??? error !!!\n\n", $time);
+ 4'bxxx1 : $display("Overrun/Underrun !!!\n\n", $time);
+ endcase
+ $stop;
+ end
+
+
+ for(i=0; i<`DBG_CPU_CRC_LEN -1; i=i+1) // Getting in the CRC
+ begin
+ gen_clk(1);
+ end
+
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1); // to exit1_dr
+
+ if (~crc_match_in)
+ begin
+ $display("(%0t) Incoming CRC failed !!!", $time);
+ $stop;
+ end
+
+ tms_pad_i<=#1 1'b1;
+ gen_clk(1); // to update_dr
+ tms_pad_i<=#1 1'b0;
+ gen_clk(1); // to run_test_idle
+ end
+endtask // debug_cpu_go
+`endif // DBG_CPU_SUPPORTED
+
+
+
+always @ (posedge tck_pad_i)
+begin
+ in_data_be[31:1] <= #1 in_data_be[30:0];
+ in_data_be[0] <= #1 tdo;
+
+ in_data_le[31] <= #1 tdo;
+ in_data_le[30:0] <= #1 in_data_le[31:1];
+end
+
+
+
+// Calculating outgoing CRC
+task calculate_crc;
+ input data;
+
+ begin
+ crc_out[0] <= #1 data ^ crc_out[31];
+ crc_out[1] <= #1 data ^ crc_out[0] ^ crc_out[31];
+ crc_out[2] <= #1 data ^ crc_out[1] ^ crc_out[31];
+ crc_out[3] <= #1 crc_out[2];
+ crc_out[4] <= #1 data ^ crc_out[3] ^ crc_out[31];
+ crc_out[5] <= #1 data ^ crc_out[4] ^ crc_out[31];
+ crc_out[6] <= #1 crc_out[5];
+ crc_out[7] <= #1 data ^ crc_out[6] ^ crc_out[31];
+ crc_out[8] <= #1 data ^ crc_out[7] ^ crc_out[31];
+ crc_out[9] <= #1 crc_out[8];
+ crc_out[10] <= #1 data ^ crc_out[9] ^ crc_out[31];
+ crc_out[11] <= #1 data ^ crc_out[10] ^ crc_out[31];
+ crc_out[12] <= #1 data ^ crc_out[11] ^ crc_out[31];
+ crc_out[13] <= #1 crc_out[12];
+ crc_out[14] <= #1 crc_out[13];
+ crc_out[15] <= #1 crc_out[14];
+ crc_out[16] <= #1 data ^ crc_out[15] ^ crc_out[31];
+ crc_out[17] <= #1 crc_out[16];
+ crc_out[18] <= #1 crc_out[17];
+ crc_out[19] <= #1 crc_out[18];
+ crc_out[20] <= #1 crc_out[19];
+ crc_out[21] <= #1 crc_out[20];
+ crc_out[22] <= #1 data ^ crc_out[21] ^ crc_out[31];
+ crc_out[23] <= #1 data ^ crc_out[22] ^ crc_out[31];
+ crc_out[24] <= #1 crc_out[23];
+ crc_out[25] <= #1 crc_out[24];
+ crc_out[26] <= #1 data ^ crc_out[25] ^ crc_out[31];
+ crc_out[27] <= #1 crc_out[26];
+ crc_out[28] <= #1 crc_out[27];
+ crc_out[29] <= #1 crc_out[28];
+ crc_out[30] <= #1 crc_out[29];
+ crc_out[31] <= #1 crc_out[30];
+ end
+endtask // calculate_crc
+
+
+// Calculating and checking input CRC
+always @(posedge tck_pad_i)
+begin
+ crc_in[0] <= #1 tdo ^ crc_in[31];
+ crc_in[1] <= #1 tdo ^ crc_in[0] ^ crc_in[31];
+ crc_in[2] <= #1 tdo ^ crc_in[1] ^ crc_in[31];
+ crc_in[3] <= #1 crc_in[2];
+ crc_in[4] <= #1 tdo ^ crc_in[3] ^ crc_in[31];
+ crc_in[5] <= #1 tdo ^ crc_in[4] ^ crc_in[31];
+ crc_in[6] <= #1 crc_in[5];
+ crc_in[7] <= #1 tdo ^ crc_in[6] ^ crc_in[31];
+ crc_in[8] <= #1 tdo ^ crc_in[7] ^ crc_in[31];
+ crc_in[9] <= #1 crc_in[8];
+ crc_in[10] <= #1 tdo ^ crc_in[9] ^ crc_in[31];
+ crc_in[11] <= #1 tdo ^ crc_in[10] ^ crc_in[31];
+ crc_in[12] <= #1 tdo ^ crc_in[11] ^ crc_in[31];
+ crc_in[13] <= #1 crc_in[12];
+ crc_in[14] <= #1 crc_in[13];
+ crc_in[15] <= #1 crc_in[14];
+ crc_in[16] <= #1 tdo ^ crc_in[15] ^ crc_in[31];
+ crc_in[17] <= #1 crc_in[16];
+ crc_in[18] <= #1 crc_in[17];
+ crc_in[19] <= #1 crc_in[18];
+ crc_in[20] <= #1 crc_in[19];
+ crc_in[21] <= #1 crc_in[20];
+ crc_in[22] <= #1 tdo ^ crc_in[21] ^ crc_in[31];
+ crc_in[23] <= #1 tdo ^ crc_in[22] ^ crc_in[31];
+ crc_in[24] <= #1 crc_in[23];
+ crc_in[25] <= #1 crc_in[24];
+ crc_in[26] <= #1 tdo ^ crc_in[25] ^ crc_in[31];
+ crc_in[27] <= #1 crc_in[26];
+ crc_in[28] <= #1 crc_in[27];
+ crc_in[29] <= #1 crc_in[28];
+ crc_in[30] <= #1 crc_in[29];
+ crc_in[31] <= #1 crc_in[30];
+end
+
+assign crc_match_in = crc_in == 32'h0;
+
+
+
+/**********************************************************************************
+* *
+* Printing the information to the screen *
+* *
+**********************************************************************************/
+
+`ifdef DBG_MORE_INFO
+always @ (posedge tck_pad_i)
+begin
+ if(dbg_tb.i_tap_top.update_ir)
+ case(dbg_tb.i_tap_top.jtag_ir[`IR_LENGTH-1:0])
+ `EXTEST : $display("\tInstruction EXTEST entered");
+ `SAMPLE_PRELOAD : $display("\tInstruction SAMPLE_PRELOAD entered");
+ `IDCODE : $display("\tInstruction IDCODE entered");
+ `MBIST : $display("\tInstruction MBIST entered");
+ `DEBUG : $display("\tInstruction DEBUG entered");
+ `BYPASS : $display("\tInstruction BYPASS entered");
+ default : $display("\n\tInstruction not valid. Instruction BYPASS activated !!!");
+ endcase
+end
+`endif
+
+
+// We never use following states: exit2_ir, exit2_dr, pause_ir or pause_dr
+always @ (posedge tck_pad_i)
+begin
+ if(dbg_tb.i_tap_top.pause_ir | dbg_tb.i_tap_top.exit2_ir)
+ begin
+ $display("\n(%0t) ERROR: State pause_ir or exit2_ir detected.", $time);
+ $display("(%0t) Simulation stopped !!!", $time);
+ $stop;
+ end
+end
+
+
+
+
+endmodule // dbg_tb
+
+
Index: tags/rel_23/bench/verilog/wb_slave_behavioral.v
===================================================================
--- tags/rel_23/bench/verilog/wb_slave_behavioral.v (nonexistent)
+++ tags/rel_23/bench/verilog/wb_slave_behavioral.v (revision 148)
@@ -0,0 +1,410 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// wb_slave_behavioral.v ////
+//// ////
+//// ////
+//// This file is part of the SoC Debug Interface. ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// Author(s): ////
+//// Tadej Markovic, tadej@opencores.org ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2004 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.2 2004/01/15 10:47:13 mohor
+// Working.
+//
+// Revision 1.1 2003/12/23 14:26:01 mohor
+// New version of the debug interface. Not finished, yet.
+//
+//
+//
+//
+
+`include "timescale.v"
+`include "wb_model_defines.v"
+module wb_slave_behavioral
+(
+ CLK_I,
+ RST_I,
+ ACK_O,
+ ADR_I,
+ CYC_I,
+ DAT_O,
+ DAT_I,
+ ERR_O,
+ RTY_O,
+ SEL_I,
+ STB_I,
+ WE_I,
+ CAB_I
+);
+
+/*------------------------------------------------------------------------------------------------------
+WISHBONE signals
+------------------------------------------------------------------------------------------------------*/
+input CLK_I;
+input RST_I;
+output ACK_O;
+input `WB_ADDR_TYPE ADR_I;
+input CYC_I;
+output `WB_DATA_TYPE DAT_O;
+input `WB_DATA_TYPE DAT_I;
+output ERR_O;
+output RTY_O;
+input `WB_SEL_TYPE SEL_I;
+input STB_I;
+input WE_I;
+input CAB_I;
+
+reg `WB_DATA_TYPE DAT_O;
+
+/*------------------------------------------------------------------------------------------------------
+Asynchronous dual-port RAM signals for storing and fetching the data
+------------------------------------------------------------------------------------------------------*/
+//reg `WB_DATA_TYPE wb_memory [0:16777215]; // WB memory - 24 addresses connected - 2 LSB not used
+reg `WB_DATA_TYPE wb_memory [0:1048575]; // WB memory - 20 addresses connected - 2 LSB not used
+reg `WB_DATA_TYPE mem_wr_data_out;
+reg `WB_DATA_TYPE mem_rd_data_in;
+
+/*------------------------------------------------------------------------------------------------------
+Maximum values for WAIT and RETRY counters and which response !!!
+------------------------------------------------------------------------------------------------------*/
+reg [2:0] a_e_r_resp; // tells with which cycle_termination_signal must wb_slave respond !
+reg [8:0] wait_cyc;
+reg [7:0] max_retry;
+
+// assign registers to default state while in reset
+// always@(RST_I)
+// begin
+// if (RST_I)
+// begin
+// a_e_r_resp <= 3'b000; // do not respond
+// wait_cyc <= 8'b0; // no wait cycles
+// max_retry <= 8'h0; // no retries
+// end
+// end //reset
+
+task cycle_response;
+ input [2:0] ack_err_rty_resp; // acknowledge, error or retry response input flags
+ input [8:0] wait_cycles; // if wait cycles before each data termination cycle (ack, err or rty)
+ input [7:0] retry_cycles; // noumber of retry cycles before acknowledge cycle
+begin
+ // assign values
+ a_e_r_resp <= #1 ack_err_rty_resp;
+ wait_cyc <= #1 wait_cycles;
+ max_retry <= #1 retry_cycles;
+end
+endtask // cycle_response
+
+/*------------------------------------------------------------------------------------------------------
+Tasks for writing and reading to and from memory !!!
+------------------------------------------------------------------------------------------------------*/
+reg `WB_ADDR_TYPE task_wr_adr_i;
+reg `WB_ADDR_TYPE task_rd_adr_i;
+reg `WB_DATA_TYPE task_dat_i;
+reg `WB_DATA_TYPE task_dat_o;
+reg `WB_SEL_TYPE task_sel_i;
+reg task_wr_data;
+reg task_data_written;
+reg `WB_DATA_TYPE task_mem_wr_data;
+
+// write to memory
+task wr_mem;
+ input `WB_ADDR_TYPE adr_i;
+ input `WB_DATA_TYPE dat_i;
+ input `WB_SEL_TYPE sel_i;
+begin
+ task_data_written = 0;
+ task_wr_adr_i = adr_i;
+ task_dat_i = dat_i;
+ task_sel_i = sel_i;
+ task_wr_data = 1;
+ wait(task_data_written);
+ task_wr_data = 0;
+end
+endtask
+
+// read from memory
+task rd_mem;
+ input `WB_ADDR_TYPE adr_i;
+ output `WB_DATA_TYPE dat_o;
+ input `WB_SEL_TYPE sel_i;
+begin
+ task_rd_adr_i = adr_i;
+ task_sel_i = sel_i;
+ #1;
+ dat_o = task_dat_o;
+end
+endtask
+
+/*------------------------------------------------------------------------------------------------------
+Internal signals and logic
+------------------------------------------------------------------------------------------------------*/
+reg calc_ack;
+reg calc_err;
+reg calc_rty;
+
+reg [7:0] retry_cnt;
+reg [7:0] retry_num;
+reg retry_expired;
+
+// Retry counter
+always@(posedge RST_I or posedge CLK_I)
+begin
+ if (RST_I)
+ retry_cnt <= #1 8'h00;
+ else
+ begin
+ if (calc_ack || calc_err)
+ retry_cnt <= #1 8'h00;
+ else if (calc_rty)
+ retry_cnt <= #1 retry_num;
+ end
+end
+
+always@(retry_cnt or max_retry)
+begin
+ if (retry_cnt < max_retry)
+ begin
+ retry_num = retry_cnt + 1'b1;
+ retry_expired = 1'b0;
+ end
+ else
+ begin
+ retry_num = retry_cnt;
+ retry_expired = 1'b1;
+ end
+end
+
+reg [8:0] wait_cnt;
+reg [8:0] wait_num;
+reg wait_expired;
+
+// Wait counter
+always@(posedge RST_I or posedge CLK_I)
+begin
+ if (RST_I)
+ wait_cnt <= #1 9'h0;
+ else
+ begin
+ if (wait_expired || ~STB_I)
+ wait_cnt <= #1 9'h0;
+ else
+ wait_cnt <= #1 wait_num;
+ end
+end
+
+always@(wait_cnt or wait_cyc or STB_I or a_e_r_resp or retry_expired)
+begin
+ if ((wait_cyc > 0) && (STB_I))
+ begin
+ if (wait_cnt < wait_cyc)
+ begin
+ wait_num = wait_cnt + 1'b1;
+ wait_expired = 1'b0;
+ calc_ack = 1'b0;
+ calc_err = 1'b0;
+ calc_rty = 1'b0;
+ end
+ else
+ begin
+ wait_num = wait_cnt;
+ wait_expired = 1'b1;
+ if (a_e_r_resp == 3'b100)
+ begin
+ calc_ack = 1'b1;
+ calc_err = 1'b0;
+ calc_rty = 1'b0;
+ end
+ else
+ if (a_e_r_resp == 3'b010)
+ begin
+ calc_ack = 1'b0;
+ calc_err = 1'b1;
+ calc_rty = 1'b0;
+ end
+ else
+ if (a_e_r_resp == 3'b001)
+ begin
+ calc_err = 1'b0;
+ if (retry_expired)
+ begin
+ calc_ack = 1'b1;
+ calc_rty = 1'b0;
+ end
+ else
+ begin
+ calc_ack = 1'b0;
+ calc_rty = 1'b1;
+ end
+ end
+ else
+ begin
+ calc_ack = 1'b0;
+ calc_err = 1'b0;
+ calc_rty = 1'b0;
+ end
+ end
+ end
+ else
+ if ((wait_cyc == 0) && (STB_I))
+ begin
+ wait_num = 9'h0;
+ wait_expired = 1'b1;
+ if (a_e_r_resp == 3'b100)
+ begin
+ calc_ack = 1'b1;
+ calc_err = 1'b0;
+ calc_rty = 1'b0;
+ end
+ else if (a_e_r_resp == 3'b010)
+ begin
+ calc_ack = 1'b0;
+ calc_err = 1'b1;
+ calc_rty = 1'b0;
+ end
+ else if (a_e_r_resp == 3'b001)
+ begin
+ calc_err = 1'b0;
+ if (retry_expired)
+ begin
+ calc_ack = 1'b1;
+ calc_rty = 1'b0;
+ end
+ else
+ begin
+ calc_ack = 1'b0;
+ calc_rty = 1'b1;
+ end
+ end
+ else
+ begin
+ calc_ack = 1'b0;
+ calc_err = 1'b0;
+ calc_rty = 1'b0;
+ end
+ end
+ else
+ begin
+ wait_num = 9'h0;
+ wait_expired = 1'b0;
+ calc_ack = 1'b0;
+ calc_err = 1'b0;
+ calc_rty = 1'b0;
+ end
+end
+
+wire rd_sel = (CYC_I && STB_I && ~WE_I);
+wire wr_sel = (CYC_I && STB_I && WE_I);
+
+// Generate cycle termination signals
+assign ACK_O = calc_ack && STB_I;
+assign ERR_O = calc_err && STB_I;
+assign RTY_O = calc_rty && STB_I;
+
+// Assign address to asynchronous memory
+always@(RST_I or ADR_I)
+begin
+ if (RST_I) // this is added because at start of test bench we need address change in order to get data!
+ begin
+ #1 mem_rd_data_in = `WB_DATA_WIDTH'hxxxx_xxxx;
+ end
+ else
+ begin
+// #1 mem_rd_data_in = wb_memory[ADR_I[25:2]];
+ #1 mem_rd_data_in = wb_memory[ADR_I[21:2]];
+ end
+end
+
+// Data input/output interface
+always@(rd_sel or mem_rd_data_in or RST_I)
+begin
+ if (RST_I)
+ DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx; // assign outputs to unknown state while in reset
+ else if (rd_sel)
+ DAT_O <=#1 mem_rd_data_in;
+ else
+ DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx;
+end
+
+
+always@(RST_I or task_rd_adr_i)
+begin
+ if (RST_I)
+ task_dat_o = `WB_DATA_WIDTH'hxxxx_xxxx;
+ else
+ task_dat_o = wb_memory[task_rd_adr_i[21:2]];
+end
+always@(CLK_I or wr_sel or task_wr_data or ADR_I or task_wr_adr_i or
+ mem_wr_data_out or DAT_I or task_mem_wr_data or task_dat_i or
+ SEL_I or task_sel_i)
+begin
+ if (task_wr_data)
+ begin
+ task_mem_wr_data = wb_memory[task_wr_adr_i[21:2]];
+
+ if (task_sel_i[3])
+ task_mem_wr_data[31:24] = task_dat_i[31:24];
+ if (task_sel_i[2])
+ task_mem_wr_data[23:16] = task_dat_i[23:16];
+ if (task_sel_i[1])
+ task_mem_wr_data[15: 8] = task_dat_i[15: 8];
+ if (task_sel_i[0])
+ task_mem_wr_data[ 7: 0] = task_dat_i[ 7: 0];
+
+ wb_memory[task_wr_adr_i[21:2]] = task_mem_wr_data; // write data
+ task_data_written = 1;
+ end
+ else if (wr_sel && CLK_I)
+ begin
+// mem_wr_data_out = wb_memory[ADR_I[25:2]]; // if no SEL_I is active, old value will be written
+ mem_wr_data_out = wb_memory[ADR_I[21:2]]; // if no SEL_I is active, old value will be written
+
+ if (SEL_I[3])
+ mem_wr_data_out[31:24] = DAT_I[31:24];
+ if (SEL_I[2])
+ mem_wr_data_out[23:16] = DAT_I[23:16];
+ if (SEL_I[1])
+ mem_wr_data_out[15: 8] = DAT_I[15: 8];
+ if (SEL_I[0])
+ mem_wr_data_out[ 7: 0] = DAT_I[ 7: 0];
+
+// wb_memory[ADR_I[25:2]] <= mem_wr_data_out; // write data
+ wb_memory[ADR_I[21:2]] = mem_wr_data_out; // write data
+ end
+end
+
+endmodule
Index: tags/rel_23/bench/verilog/cpu_behavioral.v
===================================================================
--- tags/rel_23/bench/verilog/cpu_behavioral.v (nonexistent)
+++ tags/rel_23/bench/verilog/cpu_behavioral.v (revision 148)
@@ -0,0 +1,142 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// cpu_behavioral.v ////
+//// ////
+//// ////
+//// This file is part of the SoC Debug Interface. ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2004 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.3 2004/01/22 11:07:28 mohor
+// test stall_test added.
+//
+// Revision 1.2 2004/01/17 18:01:31 mohor
+// New version.
+//
+// Revision 1.1 2004/01/17 17:01:25 mohor
+// Almost finished.
+//
+//
+//
+//
+//
+`include "timescale.v"
+`include "dbg_cpu_defines.v"
+
+
+
+module cpu_behavioral
+ (
+ // CPU signals
+ cpu_rst_i,
+ cpu_clk_o,
+ cpu_addr_i,
+ cpu_data_o,
+ cpu_data_i,
+ cpu_bp_o,
+ cpu_stall_i,
+ cpu_stb_i,
+ cpu_we_i,
+ cpu_ack_o,
+ cpu_rst_o
+ );
+
+
+// CPU signals
+input cpu_rst_i;
+output cpu_clk_o;
+input [31:0] cpu_addr_i;
+output [31:0] cpu_data_o;
+input [31:0] cpu_data_i;
+output cpu_bp_o;
+input cpu_stall_i;
+input cpu_stb_i;
+input cpu_we_i;
+output cpu_ack_o;
+output cpu_rst_o;
+
+reg cpu_clk_o;
+reg [31:0] cpu_data_o;
+reg cpu_bp_o;
+reg cpu_ack_o;
+reg cpu_ack_q;
+wire cpu_ack;
+initial
+begin
+ cpu_clk_o = 1'b0;
+ forever #5 cpu_clk_o = ~cpu_clk_o;
+end
+
+
+initial
+begin
+ cpu_bp_o = 1'b0;
+end
+
+assign #200 cpu_ack = cpu_stall_i & cpu_stb_i;
+
+
+
+always @ (posedge cpu_clk_o or posedge cpu_rst_i)
+begin
+ if (cpu_rst_i)
+ begin
+ cpu_ack_o <= #1 1'b0;
+ cpu_ack_q <= #1 1'b0;
+ end
+ else
+ begin
+ cpu_ack_o <= #1 cpu_ack;
+ cpu_ack_q <= #1 cpu_ack_o;
+ end
+end
+
+always @ (posedge cpu_clk_o or posedge cpu_rst_i)
+begin
+ if (cpu_rst_i)
+ cpu_data_o <= #1 32'h12345678;
+ else if (cpu_ack_o && (!cpu_ack_q))
+ cpu_data_o <= #1 cpu_data_o + 32'h11111111;
+end
+
+
+
+
+endmodule
+
Index: tags/rel_23/bench/verilog/wb_model_defines.v
===================================================================
--- tags/rel_23/bench/verilog/wb_model_defines.v (nonexistent)
+++ tags/rel_23/bench/verilog/wb_model_defines.v (revision 148)
@@ -0,0 +1,151 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// wb_model_defines.v ////
+//// ////
+//// ////
+//// This file is part of the SoC Debug Interface. ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// Author(s): ////
+//// - Miha Dolenc (mihad@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2004 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1 2003/12/23 14:26:01 mohor
+// New version of the debug interface. Not finished, yet.
+//
+//
+//
+
+// WISHBONE frequency in GHz
+`define WB_FREQ 0.100
+
+// memory frequency in GHz
+`define MEM_FREQ 0.100
+
+// setup and hold time definitions for WISHBONE - used in BFMs for signal generation
+`define Tsetup 4
+`define Thold 1
+
+// how many clock cycles should model wait for design's response - integer 32 bit value
+`define WAIT_FOR_RESPONSE 1023
+
+// maximum number of transactions allowed in single call to block or cab transfer routines
+`define MAX_BLK_SIZE 1024
+
+// maximum retry terminations allowed for WISHBONE master to repeat an access
+`define WB_TB_MAX_RTY 0
+
+
+// some common types and defines
+`define WB_ADDR_WIDTH 32
+`define WB_DATA_WIDTH 32
+`define WB_SEL_WIDTH `WB_DATA_WIDTH/8
+`define WB_TAG_WIDTH 5
+`define WB_ADDR_TYPE [(`WB_ADDR_WIDTH - 1):0]
+`define WB_DATA_TYPE [(`WB_DATA_WIDTH - 1):0]
+`define WB_SEL_TYPE [(`WB_SEL_WIDTH - 1):0]
+`define WB_TAG_TYPE [(`WB_TAG_WIDTH - 1):0]
+
+// read cycle stimulus - consists of:
+// - address field - which address read will be performed from
+// - sel field - what byte select value should be
+// - tag field - what tag values should be put on the bus
+`define READ_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
+`define READ_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
+`define READ_ADDRESS [(`WB_ADDR_WIDTH - 1):0]
+`define READ_SEL [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH - 1):`WB_ADDR_WIDTH]
+`define READ_TAG_STIM [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_SEL_WIDTH)]
+
+// read cycle return type consists of:
+// - read data field
+// - tag field received from WISHBONE
+// - wishbone slave response fields - ACK, ERR and RTY
+// - test bench error indicator (when testcase has not used wb master model properly)
+// - how much data was actually transfered
+`define READ_RETURN_TYPE [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):0]
+`define READ_DATA [(32 + `WB_DATA_WIDTH + 4 - 1):32 + 4]
+`define READ_TAG_RET [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):(`WB_DATA_WIDTH + 32 + 4)]
+`define READ_RETURN_LENGTH (32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1)
+
+// write cycle stimulus type consists of
+// - address field
+// - data field
+// - sel field
+// - tag field
+`define WRITE_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0]
+`define WRITE_ADDRESS [(`WB_ADDR_WIDTH - 1):0]
+`define WRITE_DATA [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH - 1):`WB_ADDR_WIDTH]
+`define WRITE_SEL [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH)]
+`define WRITE_TAG_STIM [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH)]
+
+// length of WRITE_STIMULUS
+`define WRITE_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH)
+
+// write cycle return type consists of:
+// - test bench error indicator (when testcase has not used wb master model properly)
+// - wishbone slave response fields - ACK, ERR and RTY
+// - tag field received from WISHBONE
+// - how much data was actually transfered
+`define WRITE_RETURN_TYPE [(32 + 4 + `WB_TAG_WIDTH - 1):0]
+`define WRITE_TAG_RET [(32 + 4 + `WB_TAG_WIDTH - 1):32 + 4]
+
+// this four fields are common to both read and write routines return values
+`define TB_ERROR_BIT [0]
+`define CYC_ACK [1]
+`define CYC_RTY [2]
+`define CYC_ERR [3]
+`define CYC_RESPONSE [3:1]
+`define CYC_ACTUAL_TRANSFER [35:4]
+
+// block transfer flags
+`define WB_TRANSFER_FLAGS [41:0]
+// consists of:
+// - number of transfer cycles to perform
+// - flag that enables retry termination handling - if disabled, block transfer routines will return on any termination other than acknowledge
+// - flag indicating CAB transfer is to be performed - ignored by all single transfer routines
+// - number of initial wait states to insert
+// - number of subsequent wait states to insert
+`define WB_TRANSFER_SIZE [41:10]
+`define WB_TRANSFER_AUTO_RTY [8]
+`define WB_TRANSFER_CAB [9]
+`define INIT_WAITS [3:0]
+`define SUBSEQ_WAITS [7:4]
+
+// wb slave response
+`define ACK_RESPONSE 3'b100
+`define ERR_RESPONSE 3'b010
+`define RTY_RESPONSE 3'b001
+`define NO_RESPONSE 3'b000
Index: tags/rel_23/bench/verilog/timescale.v
===================================================================
--- tags/rel_23/bench/verilog/timescale.v (nonexistent)
+++ tags/rel_23/bench/verilog/timescale.v (revision 148)
@@ -0,0 +1,56 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// timescale.v ////
+//// ////
+//// ////
+//// This file is part of the SoC Debug Interface. ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2004 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.3 2004/01/17 17:01:25 mohor
+// Almost finished.
+//
+// Revision 1.2 2003/12/23 14:26:01 mohor
+// New version of the debug interface. Not finished, yet.
+//
+//
+//
+//
+`timescale 1ns/10ps
+
tags/rel_23/bench/verilog/timescale.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_23/sim/rtl_sim/run/wave.do
===================================================================
--- tags/rel_23/sim/rtl_sim/run/wave.do (nonexistent)
+++ tags/rel_23/sim/rtl_sim/run/wave.do (revision 148)
@@ -0,0 +1,396 @@
+// Signalscan Version 6.7p1
+
+
+define noactivityindicator
+define analog waveform lines
+define add variable default overlay off
+define waveform window analogheight 1
+define terminal automatic
+define buttons control \
+ 1 opensimmulationfile \
+ 2 executedofile \
+ 3 designbrowser \
+ 4 waveform \
+ 5 source \
+ 6 breakpoints \
+ 7 definesourcessearchpath \
+ 8 exit \
+ 9 createbreakpoint \
+ 10 creategroup \
+ 11 createmarker \
+ 12 closesimmulationfile \
+ 13 renamesimmulationfile \
+ 14 replacesimulationfiledata \
+ 15 listopensimmulationfiles \
+ 16 savedofile
+define buttons waveform \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 zoomin \
+ 7 zoomout \
+ 8 zoomoutfull \
+ 9 expand \
+ 10 createmarker \
+ 11 designbrowser:1 \
+ 12 variableradixbinary \
+ 13 variableradixoctal \
+ 14 variableradixdecimal \
+ 15 variableradixhexadecimal \
+ 16 variableradixascii
+define buttons designbrowser \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 cdupscope \
+ 7 getallvariables \
+ 8 getdeepallvariables \
+ 9 addvariables \
+ 10 addvarsandclosewindow \
+ 11 closewindow \
+ 12 scopefiltermodule \
+ 13 scopefiltertask \
+ 14 scopefilterfunction \
+ 15 scopefilterblock \
+ 16 scopefilterprimitive
+define buttons event \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 move \
+ 7 closewindow \
+ 8 duplicate \
+ 9 defineasrisingedge \
+ 10 defineasfallingedge \
+ 11 defineasanyedge \
+ 12 variableradixbinary \
+ 13 variableradixoctal \
+ 14 variableradixdecimal \
+ 15 variableradixhexadecimal \
+ 16 variableradixascii
+define buttons source \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 createbreakpoint \
+ 7 creategroup \
+ 8 createmarker \
+ 9 createevent \
+ 10 createregisterpage \
+ 11 closewindow \
+ 12 opensimmulationfile \
+ 13 closesimmulationfile \
+ 14 renamesimmulationfile \
+ 15 replacesimulationfiledata \
+ 16 listopensimmulationfiles
+define buttons register \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 createregisterpage \
+ 7 closewindow \
+ 8 continuefor \
+ 9 continueuntil \
+ 10 continueforever \
+ 11 stop \
+ 12 previous \
+ 13 next \
+ 14 variableradixbinary \
+ 15 variableradixhexadecimal \
+ 16 variableradixascii
+define show related transactions
+define exit prompt
+define event search direction forward
+define variable nofullhierarchy
+define variable nofilenames
+define variable nofullpathfilenames
+include bookmark with filenames
+include scope history without filenames
+define waveform window listpane 5.97
+define waveform window namepane 14.99
+define multivalueindication
+define pattern curpos dot
+define pattern cursor1 dot
+define pattern cursor2 dot
+define pattern marker dot
+define print designer "Igor Mohor"
+define print border
+define print color blackonwhite
+define print command "/usr/ucb/lpr -P%P"
+define print printer lp
+define print range visible
+define print variable visible
+define rise fall time low threshold percentage 10
+define rise fall time high threshold percentage 90
+define rise fall time low value 0
+define rise fall time high value 3.3
+define sendmail command "/usr/lib/sendmail"
+define sequence time width 30.00
+define snap
+
+define source noprompt
+define time units default
+define userdefinedbussymbol
+define user guide directory "/usr/local/designacc/signalscan-6.7p1/doc/html"
+define waveform window grid off
+define waveform window waveheight 14
+define waveform window wavespace 6
+define web browser command netscape
+define zoom outfull on initial add off
+add group \
+ tap_top \
+ dbg_tb.i_tap_top.tck_pad_i \
+ dbg_tb.i_tap_top.tms_pad_i \
+ dbg_tb.i_tap_top.tdi_pad_i \
+ dbg_tb.i_tap_top.tms_reset \
+ dbg_tb.i_tap_top.tdo_pad_o \
+ dbg_tb.i_tap_top.tdo_padoe_o \
+ dbg_tb.i_tap_top.idcode_tdo \
+ dbg_tb.i_tap_top.test_logic_reset \
+ dbg_tb.i_tap_top.run_test_idle \
+ dbg_tb.i_tap_top.select_dr_scan \
+ dbg_tb.i_tap_top.capture_dr \
+ dbg_tb.i_tap_top.tck_pad_i \
+ dbg_tb.i_tap_top.tms_pad_i \
+ dbg_tb.i_tap_top.tdi_pad_i \
+ dbg_tb.i_tap_top.tms_reset \
+ dbg_tb.i_tap_top.tdo_pad_o \
+ dbg_tb.i_tap_top.tdo_padoe_o \
+ dbg_tb.i_tap_top.idcode_tdo \
+ dbg_tb.i_tap_top.test_logic_reset \
+ dbg_tb.i_tap_top.run_test_idle \
+ dbg_tb.i_tap_top.select_dr_scan \
+ dbg_tb.i_tap_top.capture_dr \
+ dbg_tb.i_tap_top.shift_dr \
+ dbg_tb.i_tap_top.exit1_dr \
+ dbg_tb.i_tap_top.pause_dr \
+ dbg_tb.i_tap_top.exit2_dr \
+ dbg_tb.i_tap_top.update_dr \
+ dbg_tb.i_tap_top.select_ir_scan \
+ dbg_tb.i_tap_top.capture_ir \
+ dbg_tb.i_tap_top.shift_ir \
+ dbg_tb.i_tap_top.exit1_ir \
+ dbg_tb.i_tap_top.pause_ir \
+ dbg_tb.i_tap_top.exit2_ir \
+ dbg_tb.i_tap_top.update_ir \
+ dbg_tb.i_tap_top.bypass_reg \
+ dbg_tb.i_tap_top.bypass_select \
+ dbg_tb.i_tap_top.bypassed_tdo \
+ dbg_tb.i_tap_top.debug_select \
+ dbg_tb.i_tap_top.extest_select \
+ dbg_tb.i_tap_top.idcode_reg[31:0]'h \
+ dbg_tb.i_tap_top.idcode_select \
+ dbg_tb.i_tap_top.idcode_tdo \
+ dbg_tb.i_tap_top.instruction_tdo \
+ dbg_tb.i_tap_top.jtag_ir[3:0]'h \
+ dbg_tb.i_tap_top.latched_jtag_ir[3:0]'h \
+ dbg_tb.i_tap_top.mbist_select \
+ dbg_tb.i_tap_top.sample_preload_select \
+ dbg_tb.i_tap_top.trst_pad_i \
+ dbg_tb.i_tap_top.tck_pad_i \
+ dbg_tb.i_tap_top.shift_dr \
+ dbg_tb.i_tap_top.exit1_dr \
+ dbg_tb.i_tap_top.pause_dr \
+ dbg_tb.i_tap_top.exit2_dr \
+ dbg_tb.i_tap_top.update_dr \
+ dbg_tb.i_tap_top.select_ir_scan \
+ dbg_tb.i_tap_top.capture_ir \
+ dbg_tb.i_tap_top.shift_ir \
+ dbg_tb.i_tap_top.exit1_ir \
+ dbg_tb.i_tap_top.pause_ir \
+ dbg_tb.i_tap_top.exit2_ir \
+ dbg_tb.i_tap_top.update_ir \
+ dbg_tb.i_tap_top.bypass_reg \
+ dbg_tb.i_tap_top.bypass_select \
+ dbg_tb.i_tap_top.bypassed_tdo \
+ dbg_tb.i_tap_top.debug_select \
+ dbg_tb.i_tap_top.extest_select \
+ dbg_tb.i_tap_top.idcode_reg[31:0]'h \
+ dbg_tb.i_tap_top.idcode_select \
+ dbg_tb.i_tap_top.idcode_tdo \
+ dbg_tb.i_tap_top.instruction_tdo \
+ dbg_tb.i_tap_top.jtag_ir[3:0]'h \
+ dbg_tb.i_tap_top.latched_jtag_ir[3:0]'h \
+ dbg_tb.i_tap_top.mbist_select \
+ dbg_tb.i_tap_top.sample_preload_select \
+ dbg_tb.i_tap_top.trst_pad_i \
+ dbg_tb.i_tap_top.tck_pad_i \
+
+add group \
+ dbg_top \
+ dbg_tb.test_text[199:0]'a \
+ dbg_tb.i_dbg_top.crc_cnt_end \
+ dbg_tb.i_dbg_top.crc_cnt_end_q \
+ dbg_tb.i_dbg_top.data_cnt[2:0]'h \
+ dbg_tb.i_dbg_top.data_cnt_end \
+ dbg_tb.i_dbg_top.crc_cnt[5:0]'h \
+ dbg_tb.i_dbg_top.crc_cnt_end \
+ dbg_tb.i_dbg_top.crc_match \
+ dbg_tb.i_dbg_top.debug_select_i \
+ dbg_tb.i_dbg_top.module_select \
+ dbg_tb.i_dbg_top.cpu_debug_module \
+ dbg_tb.i_dbg_top.shift_dr_i \
+ dbg_tb.i_dbg_top.status_cnt[2:0]'h \
+ dbg_tb.i_dbg_top.status_cnt_end \
+ dbg_tb.i_dbg_top.tck_i \
+ dbg_tb.i_dbg_top.tdi_i \
+ dbg_tb.i_dbg_top.tdo_o \
+ dbg_tb.i_dbg_top.tdo_module_select \
+ dbg_tb.i_dbg_top.update_dr_i \
+ dbg_tb.i_dbg_top.crc_en \
+ dbg_tb.i_dbg_top.crc_en_dbg \
+ dbg_tb.i_dbg_top.crc_en_wb \
+ dbg_tb.status[3:0]'h \
+ dbg_tb.crc_match_in \
+ dbg_tb.test_text[199:0]'a \
+ dbg_tb.i_dbg_top.crc_cnt_end \
+ dbg_tb.i_dbg_top.crc_cnt_end_q \
+ dbg_tb.i_dbg_top.data_cnt[2:0]'h \
+ dbg_tb.i_dbg_top.data_cnt_end \
+ dbg_tb.i_dbg_top.crc_cnt[5:0]'h \
+ dbg_tb.i_dbg_top.crc_cnt_end \
+ dbg_tb.i_dbg_top.crc_match \
+ dbg_tb.i_dbg_top.debug_select_i \
+ dbg_tb.i_dbg_top.module_select \
+ dbg_tb.i_dbg_top.cpu_debug_module \
+ dbg_tb.i_dbg_top.shift_dr_i \
+ dbg_tb.i_dbg_top.status_cnt[2:0]'h \
+ dbg_tb.i_dbg_top.status_cnt_end \
+ dbg_tb.i_dbg_top.tck_i \
+ dbg_tb.i_dbg_top.tdi_i \
+ dbg_tb.i_dbg_top.tdo_o \
+ dbg_tb.i_dbg_top.tdo_module_select \
+ dbg_tb.i_dbg_top.update_dr_i \
+ dbg_tb.i_dbg_top.crc_en \
+ dbg_tb.i_dbg_top.crc_en_dbg \
+ dbg_tb.i_dbg_top.crc_en_wb \
+ dbg_tb.status[3:0]'h \
+ dbg_tb.crc_match_in \
+
+add group \
+ crc_out \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.clk \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.crc[31:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.crc_match \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.crc_out \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.data \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.enable \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.shift \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.new_crc[31:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.rst \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.sync_rst \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.clk \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.crc[31:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.crc_match \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.crc_out \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.data \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.enable \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.shift \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.new_crc[31:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.rst \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_out.sync_rst \
+
+add group \
+ crc_in \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.clk \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.crc_match \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.data \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.enable \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.new_crc[31:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.rst \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.shift \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.sync_rst \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.crc[31:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.clk \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.crc_match \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.data \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.enable \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.new_crc[31:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.rst \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.shift \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.sync_rst \
+ dbg_tb.i_dbg_top.i_dbg_crc32_d1_in.crc[31:0]'h \
+
+add group \
+ cpu_module \
+ dbg_tb.test_text[199:0]'a \
+ dbg_tb.i_dbg_top.i_dbg_cpu.cpu_ce_i \
+ dbg_tb.i_dbg_top.i_dbg_cpu.curr_cmd[3:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_cpu.curr_cmd_go \
+ dbg_tb.i_dbg_top.i_dbg_cpu.cmd_cnt[2:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_cpu.addr_len_cnt[5:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_cpu.data_cnt_en \
+ dbg_tb.i_dbg_top.i_dbg_cpu.data_cnt[19:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_cpu.crc_cnt[5:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_cpu.status_cnt[2:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_cpu.adr[31:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_cpu.acc_type[3:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_cpu.len[15:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_cpu.start_rd_tck \
+ dbg_tb.i_dbg_top.i_dbg_cpu.start_wr_tck \
+ dbg_tb.i_dbg_top.i_dbg_cpu.long_q \
+ dbg_tb.i_dbg_top.i_dbg_cpu.acc_type[3:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_cpu.long \
+ dbg_tb.i_dbg_top.i_dbg_cpu.data_cnt[19:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_cpu.cpu_stb_o \
+ dbg_tb.i_dbg_top.i_dbg_cpu.i_dbg_cpu_registers.cpu_rst_o \
+ dbg_tb.i_dbg_top.i_dbg_cpu.cpu_stall_o \
+ dbg_tb.i_dbg_top.i_dbg_cpu.cpu_reg_stall \
+ dbg_tb.i_dbg_top.i_dbg_cpu.fifo_full \
+ dbg_tb.i_dbg_top.i_dbg_cpu.latch_data \
+ dbg_tb.i_dbg_top.i_dbg_cpu.cpu_overrun \
+ dbg_tb.i_dbg_top.i_dbg_cpu.cpu_overrun_tck \
+ dbg_tb.i_dbg_top.i_dbg_cpu.underrun_tck \
+ dbg_tb.i_dbg_top.i_dbg_cpu.cpu_reg_stall \
+ dbg_tb.test_text[199:0]'a \
+ dbg_tb.i_dbg_top.i_dbg_cpu.cpu_ce_i \
+ dbg_tb.i_dbg_top.i_dbg_cpu.curr_cmd[3:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_cpu.curr_cmd_go \
+ dbg_tb.i_dbg_top.i_dbg_cpu.cmd_cnt[2:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_cpu.addr_len_cnt[5:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_cpu.data_cnt[19:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_cpu.crc_cnt[5:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_cpu.status_cnt[2:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_cpu.adr[31:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_cpu.acc_type[3:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_cpu.len[15:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_cpu.start_wr_tck \
+ dbg_tb.i_dbg_top.i_dbg_cpu.long_q \
+ dbg_tb.i_dbg_top.i_dbg_cpu.acc_type[3:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_cpu.long \
+ dbg_tb.i_dbg_top.i_dbg_cpu.data_cnt[19:0]'h \
+ dbg_tb.i_dbg_top.i_dbg_cpu.cpu_stall_o \
+ dbg_tb.i_dbg_top.i_dbg_cpu.cpu_stb_o \
+ dbg_tb.i_dbg_top.i_dbg_cpu.i_dbg_cpu_registers.cpu_rst_o \
+ dbg_tb.i_dbg_top.i_dbg_cpu.i_dbg_cpu_registers.cpu_stall_o \
+ dbg_tb.i_dbg_top.i_dbg_cpu.cpu_overrun \
+ dbg_tb.i_dbg_top.i_dbg_cpu.underrun_tck \
+
+add group \
+ cpu_behavioural \
+ dbg_tb.i_cpu_behavioral.cpu_ack_o \
+ dbg_tb.i_cpu_behavioral.cpu_addr_i[31:0]'h \
+ dbg_tb.i_cpu_behavioral.cpu_bp_o \
+ dbg_tb.i_cpu_behavioral.cpu_clk_o \
+ dbg_tb.i_cpu_behavioral.cpu_data_i[31:0]'h \
+ dbg_tb.i_cpu_behavioral.cpu_data_o[31:0]'h \
+ dbg_tb.i_cpu_behavioral.cpu_rst_i \
+ dbg_tb.i_cpu_behavioral.cpu_rst_o \
+ dbg_tb.i_cpu_behavioral.cpu_stall_i \
+ dbg_tb.i_cpu_behavioral.cpu_stb_i \
+ dbg_tb.i_cpu_behavioral.cpu_we_i \
+
+
+deselect all
+open window waveform 1 geometry 10 60 1592 1139
+zoom at 914057.1(0)ns 0.00038020 0.00000000
tags/rel_23/sim/rtl_sim/run/wave.do
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_23/sim/rtl_sim/run/run_sim
===================================================================
--- tags/rel_23/sim/rtl_sim/run/run_sim (nonexistent)
+++ tags/rel_23/sim/rtl_sim/run/run_sim (revision 148)
@@ -0,0 +1,92 @@
+#!/bin/csh -f
+
+if ( $# < 1 ) then
+ echo "Top level module name is dbg_tb"
+ set SIM_TOP = dbg_tb
+# exit
+else
+ set SIM_TOP = $1
+endif
+
+set current_par = 1
+set output_waveform = 0
+while ( $current_par < $# )
+ @ current_par = $current_par + 1
+ case wave:
+ @ output_waveform = 1
+ breaksw
+ default:
+ echo 'Unknown option "'$argv[$current_par]'"!'
+ exit
+ breaksw
+ endsw
+end
+
+echo "-CDSLIB ../bin/cds.lib" > ncvlog.args
+echo "-HDLVAR ../bin/hdl.var" >> ncvlog.args
+echo "-MESSAGES" >> ncvlog.args
+echo "-INCDIR ../../../bench/verilog" >> ncvlog.args
+echo "-INCDIR ../../../rtl/verilog" >> ncvlog.args
+echo "-INCDIR ../../../../jtag/tap/rtl/verilog" >> ncvlog.args
+echo "-NOCOPYRIGHT" >> ncvlog.args
+echo "-LOGFILE ../log/ncvlog.log" >> ncvlog.args
+
+
+#foreach filename ( `cat ../bin/rtl_file_list` )
+# echo "../../../rtl/verilog/"$filename >> ncvlog.args
+#end
+#
+#foreach filename ( `cat ../bin/sim_file_list` )
+# echo "../../../bench/verilog/"$filename >> ncvlog.args
+#end
+
+
+# RTL files
+echo "../../../rtl/verilog/dbg_crc32_d1.v" >> ncvlog.args
+echo "../../../rtl/verilog/dbg_wb.v" >> ncvlog.args
+echo "../../../rtl/verilog/dbg_register.v" >> ncvlog.args
+echo "../../../rtl/verilog/dbg_cpu_registers.v" >> ncvlog.args
+echo "../../../rtl/verilog/dbg_cpu.v" >> ncvlog.args
+echo "../../../rtl/verilog/dbg_top.v" >> ncvlog.args
+echo "../../../../jtag/tap/rtl/verilog/tap_top.v" >> ncvlog.args
+
+
+# Simulation files
+echo "../../../bench/verilog/timescale.v" >> ncvlog.args
+echo "../../../bench/verilog/wb_slave_behavioral.v" >> ncvlog.args
+echo "../../../bench/verilog/cpu_behavioral.v" >> ncvlog.args
+echo "../../../bench/verilog/dbg_tb.v" >> ncvlog.args
+
+ncvlog -f ncvlog.args
+
+echo "-MESSAGES" > ncelab.args
+echo "-NOCOPYRIGHT" >> ncelab.args
+echo "-CDSLIB ../bin/cds.lib" >> ncelab.args
+echo "-HDLVAR ../bin/hdl.var" >> ncelab.args
+echo "-LOGFILE ../log/ncelab.log" >> ncelab.args
+echo "-SNAPSHOT worklib.bench:rtl" >> ncelab.args
+echo "-NO_TCHK_MSG" >> ncelab.args
+echo "-ACCESS +RWC" >> ncelab.args
+echo worklib.$SIM_TOP >> ncelab.args
+
+ncelab -f ncelab.args
+
+echo "-MESSAGES" > ncsim.args
+echo "-NOCOPYRIGHT" >> ncsim.args
+echo "-CDSLIB ../bin/cds.lib" >> ncsim.args
+echo "-HDLVAR ../bin/hdl.var" >> ncsim.args
+echo "-INPUT ncsim.tcl" >> ncsim.args
+echo "-LOGFILE ../log/ncsim.log" >> ncsim.args
+echo "worklib.bench:rtl" >> ncsim.args
+
+if ( $output_waveform ) then
+ echo "database -open waves -shm -into ../out/waves.shm" > ./ncsim.tcl
+ echo "probe -create -database waves $SIM_TOP -shm -all -depth all" >> ./ncsim.tcl
+ echo "run" >> ./ncsim.tcl
+else
+ echo "run" > ./ncsim.tcl
+endif
+
+echo "quit" >> ncsim.tcl
+
+ncsim -LICQUEUE -f ./ncsim.args
tags/rel_23/sim/rtl_sim/run/run_sim
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_23/sim/rtl_sim/run/clean
===================================================================
--- tags/rel_23/sim/rtl_sim/run/clean (nonexistent)
+++ tags/rel_23/sim/rtl_sim/run/clean (revision 148)
@@ -0,0 +1,4 @@
+rm ../bin/INCA_libs/worklib/*
+rm ../bin/INCA_libs/worklib/.*
+rm ../log/*.log
+rm -rf ../out/*.shm
tags/rel_23/sim/rtl_sim/run/clean
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_23/sim/rtl_sim/bin/INCA_libs/worklib/dir_keeper
===================================================================
Index: tags/rel_23/sim/rtl_sim/bin/cds.lib
===================================================================
--- tags/rel_23/sim/rtl_sim/bin/cds.lib (nonexistent)
+++ tags/rel_23/sim/rtl_sim/bin/cds.lib (revision 148)
@@ -0,0 +1,6 @@
+#
+# cds.lib: Defines the locations of compiled libraries.
+# Created by ncprep on Tue Jul 3 11:40:44 2001
+#
+
+define worklib ./INCA_libs/worklib
tags/rel_23/sim/rtl_sim/bin/cds.lib
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_23/sim/rtl_sim/bin/hdl.var
===================================================================
--- tags/rel_23/sim/rtl_sim/bin/hdl.var (nonexistent)
+++ tags/rel_23/sim/rtl_sim/bin/hdl.var (revision 148)
@@ -0,0 +1,9 @@
+#
+# hdl.var: Defines variables used by the INCA tools.
+# Created by ncprep on Tue Jul 3 11:40:44 2001
+#
+
+softinclude $CDS_INST_DIR/tools/inca/files/hdl.var
+
+define LIB_MAP ( $LIB_MAP, + => worklib )
+define VIEW_MAP ( $VIEW_MAP, .v => v)
tags/rel_23/sim/rtl_sim/bin/hdl.var
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_23/sim/rtl_sim/log/dir_keeper
===================================================================
--- tags/rel_23/sim/rtl_sim/log/dir_keeper (nonexistent)
+++ tags/rel_23/sim/rtl_sim/log/dir_keeper (revision 148)
@@ -0,0 +1 @@
+Only keeper of empty directories
tags/rel_23/sim/rtl_sim/log/dir_keeper
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_23/sim/rtl_sim/out/dir_keeper
===================================================================
--- tags/rel_23/sim/rtl_sim/out/dir_keeper (nonexistent)
+++ tags/rel_23/sim/rtl_sim/out/dir_keeper (revision 148)
@@ -0,0 +1 @@
+Only keeper of empty directories
tags/rel_23/sim/rtl_sim/out/dir_keeper
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tags/rel_23/doc/src/DbgSupp.doc
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/rel_23/doc/src/DbgSupp.doc
===================================================================
--- tags/rel_23/doc/src/DbgSupp.doc (nonexistent)
+++ tags/rel_23/doc/src/DbgSupp.doc (revision 148)
tags/rel_23/doc/src/DbgSupp.doc
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: tags/rel_23/doc/src/Debug Support Datasheet (prl.).doc
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/rel_23/doc/src/Debug Support Datasheet (prl.).doc
===================================================================
--- tags/rel_23/doc/src/Debug Support Datasheet (prl.).doc (nonexistent)
+++ tags/rel_23/doc/src/Debug Support Datasheet (prl.).doc (revision 148)
tags/rel_23/doc/src/Debug Support Datasheet (prl.).doc
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: tags/rel_23/doc/src/DbgSupp_PB.doc
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/rel_23/doc/src/DbgSupp_PB.doc
===================================================================
--- tags/rel_23/doc/src/DbgSupp_PB.doc (nonexistent)
+++ tags/rel_23/doc/src/DbgSupp_PB.doc (revision 148)
tags/rel_23/doc/src/DbgSupp_PB.doc
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: tags/rel_23/doc/DbgSupp.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/rel_23/doc/DbgSupp.pdf
===================================================================
--- tags/rel_23/doc/DbgSupp.pdf (nonexistent)
+++ tags/rel_23/doc/DbgSupp.pdf (revision 148)
tags/rel_23/doc/DbgSupp.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: tags/rel_23/doc/Debug Support Datasheet (prl.).pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/rel_23/doc/Debug Support Datasheet (prl.).pdf
===================================================================
--- tags/rel_23/doc/Debug Support Datasheet (prl.).pdf (nonexistent)
+++ tags/rel_23/doc/Debug Support Datasheet (prl.).pdf (revision 148)
tags/rel_23/doc/Debug Support Datasheet (prl.).pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: tags/rel_23/doc/DbgSupp_PB.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: tags/rel_23/doc/DbgSupp_PB.pdf
===================================================================
--- tags/rel_23/doc/DbgSupp_PB.pdf (nonexistent)
+++ tags/rel_23/doc/DbgSupp_PB.pdf (revision 148)
tags/rel_23/doc/DbgSupp_PB.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property