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URL https://opencores.org/ocsvn/dmt_tx/dmt_tx/trunk

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    from Rev 15 to Rev 16
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Rev 15 → Rev 16

/trunk/const_encoder/rtl/const_enc.v
1,6 → 1,15
/* *****************************************************************
*
* This file is part of Tone Order and Constellation Encoder Core.
* This file is part of the
*
* Tone Order and Constellation Encoder Core.
*
* Description:
*
* The conste_enc module implements the tone ordering and
* constellation encoding as described in ITU G.992.1
*
*********************************************************************
* Copyright (C) 2007 Guenter Dannoritzer
*
* This source is free software; you can redistribute it
17,7 → 26,7
* GNU General Public License for more details.
*
* You should have received a copy of the
* GNU General Public License along with this program.
* GNU General Public License along with this source.
* If not, see <http://www.gnu.org/licenses/>.
*
* *****************************************************************/
25,30 → 34,106
module const_encoder(
clk,
reset,
input_ready_o,
we_data_i,
data_i,
fast_ready_o,
we_fast_data_i,
fast_data_i,
inter_ready_o,
we_inter_data_i,
inter_data_i,
addr_i,
we_conf_i,
conf_data_i,
xy_ready_o,
bin_num_o,
carrier_num_o,
x_o,
y_o);
 
input clk;
input reset;
output input_ready_o;
input we_data_i;
input data_i;
input addr_i;
input we_conf_i;
input conf_data_i;
output xy_ready_o;
output bin_num_o;
output x_o;
output y_o;
 
`include "parameters.vh"
//
// parameter
//
 
input clk;
input reset;
output fast_ready_o;
input we_fast_data_i;
input [DW-1:0] fast_data_i;
output inter_ready_o;
input we_inter_data_i;
input [DW-1:0] inter_data_i;
input [CONFAW-1:0] addr_i;
input we_conf_i;
input [CONFDW-1:0] conf_data_i;
output xy_ready_o;
output [CNUMW-1:0] carrier_num_o;
output [CONSTW-1:0] x_o;
output [CONSTW-1:0] y_o;
 
 
 
//
// local wire/regs
//
wire [DW-1:0] fast_data_o;
wire [DW-1:0] inter_data_o;
 
reg [SHIFTW-1:0] fast_shift_reg;
reg [SHIFTW-1:0] inter_shift_reg;
reg [MAXBITNUM-1:0] const_input_reg;
 
reg [CONFDW-1:0] BitLoading [0:TABLELEN-1];
reg [CONFDW-1:0] CarrierNumber [0:TABLELEN-1];
reg [USEDCREGW-1:0] UsedCarrier;
reg [FBITSW-1:0] FastBits;
 
//
// intantiate the fast path and interleaved path FIFOs
//
fifo #(.AWIDTH(AW), .DWIDTH(DW))
fifo_fast ( .clk(clk),
.reset(reset),
.empty_o(fast_empty_o),
.full_o(fast_full_o),
.one_available_o(fast_one_available_o),
.two_available_o(fast_two_available_o),
.we_i(we_fast_i),
.data_i(fast_data_i),
.re_i(re_fast_i),
.data_o(fast_data_o)
);
 
fifo #(.AWIDTH(AW), .DWIDTH(DW))
fifo_inter ( .clk(clk),
.reset(reset),
.empty_o(inter_empty_o),
.full_o(inter_full_o),
.one_available_o(inter_one_available_o),
.two_available_o(inter_two_available_o),
.we_i(we_inter_i),
.data_i(inter_data_i),
.re_i(re_inter_i),
.data_o(inter_data_o)
);
 
//
// configuration register access
//
always @(posedge clk or posedge reset) begin
 
if(reset) begin
UsedCarrier <= 0;
FastBits <= 0;
 
end
else begin
UsedCarrier <= 1;
end
end
 
 
 
endmodule
/trunk/const_encoder/rtl/fifo.v
119,7 → 119,6
end
else begin
 
// TODO: fix this to allow read/write at one clock cycle
if(dp_we_i & ~ dp_re_i) begin
fill_ctr <= fill_ctr + 1;
end
/trunk/const_encoder/rtl/defs.vh
3,3 → 3,4
`define VENDOR_FPGA
 
 
 
/trunk/const_encoder/tb/tb_const_enc.v
1,6 → 1,9
/* *****************************************************************
*
* This file is part of Tone Order and Constellation Encoder Core.
* This file is part of the
*
* Tone Order and Constellation Encoder Core.
*
* Copyright (C) 2007 Guenter Dannoritzer
*
* This source is free software; you can redistribute it
17,7 → 20,7
* GNU General Public License for more details.
*
* You should have received a copy of the
* GNU General Public License along with this program.
* GNU General Public License along with this source.
* If not, see <http://www.gnu.org/licenses/>.
*
* *****************************************************************/
24,45 → 27,192
 
module tb_const_encoder();
 
reg clk;
reg reset;
wire input_ready_o;
reg we_data_i;
parameter TW = 10;
 
`include "parameters.vh"
 
 
reg clk;
reg reset;
wire fast_ready_o;
reg we_fast_data_i;
reg [DW-1:0] fast_data_i;
wire inter_ready_o;
reg we_inter_data_i;
reg [DW-1:0] inter_data_i;
 
reg we_conf_i;
reg [CONFAW-1:0] addr_i;
reg [CONFDW-1:0] conf_data_i;
wire [CNUMW-1:0] carrier_num_o;
wire [CONSTW-1:0] x_o;
wire [CONSTW-1:0] y_o;
 
//
// instantiate the DUT
//
const_encoder dut ( .clk(clk),
.reset(reset),
.input_ready_o(input_ready_o),
.we_data_i(we_data_i),
.data_i(data_i),
.fast_ready_o(fast_ready_o),
.we_fast_data_i(we_fast_data_i),
.fast_data_i(fast_data_i),
.inter_ready_o(inter_ready_o),
.we_inter_data_i(we_inter_data_i),
.inter_data_i(inter_data_i),
.addr_i(addr_i),
.we_conf_i(we_conf_i),
.conf_data_i(conf_data_i),
.xy_ready_o(xy_ready_o),
.bin_num_o(bin_num_o),
.carrier_num_o(carrier_num_o),
.x_o(x_o),
.y_o(y_o));
 
 
initial begin
clk = 0;
we_fast_data_i = 0;
we_inter_data_i = 0;
we_conf_i = 0;
reset = 0;
end
 
always begin
#TW clk = ~clk;
end
 
//
// dump signals
//
initial begin
$dumpfile("tb_const_enc.vcd");
$dumpvars;
end
 
 
//
// main test
//
initial begin
 
$monitor($time, " clk: ", clk, " reset: ", reset);
$monitor($time, " reset: ", reset);
clk = 0;
reset = 0;
apply_reset;
 
#50 reset = 1;
#50 reset = 0;
//
// write configuration
//
write_config(BIT_LOAD_ST_ADR, 2);
write_config(BIT_LOAD_ST_ADR+1, 3);
write_config(BIT_LOAD_ST_ADR+2, 4);
write_config(BIT_LOAD_ST_ADR+3, 5);
 
write_config(C_NUM_ST_ADR, 48);
write_config(C_NUM_ST_ADR+1, 49);
write_config(C_NUM_ST_ADR+2, 50);
write_config(C_NUM_ST_ADR+3, 51);
write_config(USED_C_ADR, 4);
write_config(F_BITS_ADR, 7);
//
// check written configuration
//
check_config(BIT_LOAD_ST_ADR, 2);
check_config(BIT_LOAD_ST_ADR+1, 3);
check_config(BIT_LOAD_ST_ADR+2, 4);
check_config(BIT_LOAD_ST_ADR+3, 5);
 
check_config(C_NUM_ST_ADR, 48);
check_config(C_NUM_ST_ADR+1, 49);
check_config(C_NUM_ST_ADR+2, 50);
check_config(C_NUM_ST_ADR+3, 51);
 
check_config(USED_C_ADR, 4);
check_config(F_BITS_ADR, 7);
#1000 $finish();
 
end
end // main test
 
 
// ////////////////////////////////////////////////////////////////////
//
// bus functional models
//
// ////////////////////////////////////////////////////////////////////
 
task apply_reset;
begin
reset = 0;
#20
reset = 1;
@(posedge clk);
reset = 0;
end
endtask
//
// write data to the configuration registers
//
task write_config(input [CONFAW-1:0] addr, input[CONFDW-1:0] data);
begin
addr_i = addr;
conf_data_i = data;
@(negedge clk);
we_conf_i = 1;
@(negedge clk);
we_conf_i = 0;
end
endtask
 
//
// check the written configuration
//
task check_config(input [CONFAW-1:0] addr, input [CONFDW-1:0] exp_data);
begin
 
if(addr >= 0 && addr < C_NUM_ST_ADR) begin
if(dut.BitLoading[addr] !== exp_data) begin
$display("ERROR! => BitLoading does not match @ %x!", addr);
$display(" Got: %d expected: %d",
dut.BitLoading[addr], exp_data);
end
end
else if(addr >= C_NUM_ST_ADR && addr < USED_C_ADR) begin
 
if(dut.CarrierNumber[addr-C_NUM_ST_ADR] !== exp_data) begin
$display("ERROR! => CarrierNumber does not match @ %x!", addr);
$display(" Got: %d expected: %d",
dut.CarrierNumber[addr-C_NUM_ST_ADR], exp_data);
end
end
else if(addr == USED_C_ADR) begin
if(dut.UsedCarrier !== exp_data) begin
$display("ERROR! => UsedCarrier does not match @ %x!", addr);
$display(" Got: %d expected: %d",
dut.UsedCarrier, exp_data);
end
end
else if(addr == F_BITS_ADR) begin
if(dut.FastBits !== exp_data) begin
$display("ERROR! => FastBits does not match @ %x!", addr);
$display(" Got: %d expected: %d",
dut.FastBits, exp_data);
end
 
end
end
endtask
 
 
endmodule
/trunk/const_encoder/tb/tb_fifo.v
242,9 → 242,12
 
 
 
// =====================================================================
// ////////////////////////////////////////////////////////////////////
//
// bus functional models
//
//
// ////////////////////////////////////////////////////////////////////
 
task test_reset;
begin
//$display("Testing reset");
/trunk/const_encoder/Makefile
6,6 → 6,13
vpath %.v rtl tb
vpath %.vh rtl
 
FIFO = fifo.v \
generic_dpram.v
CONST_ENC = $(FIFO) \
const_enc.v
 
 
 
.PHONY: all sim doc clean
 
all: sim
18,7 → 25,7
@echo -e "\n--> Simulating $@"
$(SIM) $^
 
const_enc.vvp: const_enc.v tb_const_enc.v
const_enc.vvp: tb_const_enc.v $(CONST_ENC)
$(CC) $(CFLAGS) $^ -s tb_const_encoder -o $@
 
fifo: fifo.vvp
25,7 → 32,7
@echo -e "\n--> Simulating $@"
$(SIM) $^
fifo.vvp: fifo.v tb_fifo.v generic_dpram.v
fifo.vvp: tb_fifo.v $(FIFO)
@echo -e "\n--> Compiling $@"
$(CC) $(CFLAGS) $^ -s tb_fifo -o $@
 

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