URL
https://opencores.org/ocsvn/fir_wishbone/fir_wishbone/trunk
Subversion Repositories fir_wishbone
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- This comparison shows the changes necessary to convert path
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- from Rev 15 to Rev 16
- ↔ Reverse comparison
Rev 15 → Rev 16
/fir_wishbone/trunk/workspaces/synthesis/quartus/fir.qsf
38,10 → 38,10
|
set_global_assignment -name FAMILY "Cyclone IV E" |
set_global_assignment -name DEVICE AUTO |
set_global_assignment -name TOP_LEVEL_ENTITY tb_fir |
set_global_assignment -name TOP_LEVEL_ENTITY fir |
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.1 |
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:57:28 MARCH 05, 2014" |
set_global_assignment -name LAST_QUARTUS_VERSION 12.1 |
set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0 |
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files |
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" |
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation |
50,7 → 50,8
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top |
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 |
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF |
set_global_assignment -name VHDL_FILE "../../../design/quartus-synthesis/fir.vhdl" |
set_global_assignment -name VHDL_FILE "../../../design/quartus-synthesis/tb_fir.vhdl" |
set_global_assignment -name VHDL_FILE ../../../tester/stp.vhd |
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |
set_global_assignment -name VHDL_FILE "../../../hw/quartus-synthesis/fir.vhdl" |
#set_global_assignment -name VHDL_FILE ../../../tester/tb_fir.vhdl |
set_global_assignment -name VHDL_FILE ./synthesis/quartus/stp/synthesis/stp.vhd |
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |
/fir_wishbone/trunk/workspaces/synthesis/quartus/stp/synthesis/stp.vhd
0,0 → 1,71
-- stp.vhd |
|
-- Generated using ACDS version 16.0 211 |
|
library IEEE; |
use IEEE.std_logic_1164.all; |
use IEEE.numeric_std.all; |
|
entity stp is |
port ( |
acq_clk : in std_logic := '0'; -- acq_clk.clk |
acq_data_in : in std_logic_vector(127 downto 0) := (others => '0'); -- tap.acq_data_in |
acq_trigger_in : in std_logic_vector(0 downto 0) := (others => '0') -- .acq_trigger_in |
); |
end entity stp; |
|
architecture rtl of stp is |
component sld_signaltap is |
generic ( |
sld_data_bits : integer := 1; |
sld_sample_depth : integer := 128; |
sld_ram_block_type : string := "AUTO"; |
sld_storage_qualifier_mode : string := "OFF"; |
sld_trigger_bits : integer := 1; |
sld_trigger_level : integer := 1; |
sld_trigger_in_enabled : integer := 0; |
sld_enable_advanced_trigger : integer := 0; |
sld_trigger_level_pipeline : integer := 1; |
sld_trigger_pipeline : integer := 0; |
sld_ram_pipeline : integer := 0; |
sld_counter_pipeline : integer := 0; |
sld_node_info : integer := 806383104; |
sld_node_crc_bits : integer := 32; |
sld_node_crc_hiword : integer := 12345; |
sld_node_crc_loword : integer := 19899 |
); |
port ( |
acq_data_in : in std_logic_vector(127 downto 0) := (others => 'X'); -- acq_data_in |
acq_trigger_in : in std_logic_vector(0 downto 0) := (others => 'X'); -- acq_trigger_in |
acq_clk : in std_logic := 'X' -- clk |
); |
end component sld_signaltap; |
|
begin |
|
signaltap_ii_logic_analyzer_0 : component sld_signaltap |
generic map ( |
sld_data_bits => 128, |
sld_sample_depth => 128, |
sld_ram_block_type => "AUTO", |
sld_storage_qualifier_mode => "OFF", |
sld_trigger_bits => 1, |
sld_trigger_level => 1, |
sld_trigger_in_enabled => 0, |
sld_enable_advanced_trigger => 0, |
sld_trigger_level_pipeline => 1, |
sld_trigger_pipeline => 0, |
sld_ram_pipeline => 0, |
sld_counter_pipeline => 0, |
sld_node_info => 806383104, |
sld_node_crc_bits => 32, |
sld_node_crc_hiword => 24613, |
sld_node_crc_loword => 48613 |
) |
port map ( |
acq_data_in => acq_data_in, -- tap.acq_data_in |
acq_trigger_in => acq_trigger_in, -- .acq_trigger_in |
acq_clk => acq_clk -- acq_clk.clk |
); |
|
end architecture rtl; -- of stp |
/fir_wishbone/trunk/workspaces/synthesis/quartus/stp.qsys
0,0 → 1,87
<?xml version="1.0" encoding="UTF-8"?> |
<system name="$${FILENAME}"> |
<component |
name="$${FILENAME}" |
displayName="$${FILENAME}" |
version="1.0" |
description="" |
tags="INTERNAL_COMPONENT=true" |
categories="" /> |
<parameter name="bonusData"><![CDATA[bonusData |
{ |
element signaltap_ii_logic_analyzer_0 |
{ |
datum _sortIndex |
{ |
value = "0"; |
type = "int"; |
} |
} |
} |
]]></parameter> |
<parameter name="clockCrossingAdapter" value="HANDSHAKE" /> |
<parameter name="device" value="EP4CE10E22A7" /> |
<parameter name="deviceFamily" value="Cyclone IV E" /> |
<parameter name="deviceSpeedGrade" value="7" /> |
<parameter name="fabricMode" value="QSYS" /> |
<parameter name="generateLegacySim" value="false" /> |
<parameter name="generationId" value="0" /> |
<parameter name="globalResetBus" value="false" /> |
<parameter name="hdlLanguage" value="VERILOG" /> |
<parameter name="hideFromIPCatalog" value="true" /> |
<parameter name="lockedInterfaceDefinition" value="" /> |
<parameter name="maxAdditionalLatency" value="1" /> |
<parameter name="projectName" value="" /> |
<parameter name="sopcBorderPoints" value="false" /> |
<parameter name="systemHash" value="0" /> |
<parameter name="testBenchDutName" value="" /> |
<parameter name="timeStamp" value="0" /> |
<parameter name="useTestBenchNamingPattern" value="false" /> |
<instanceScript></instanceScript> |
<interface |
name="acq_clk" |
internal="signaltap_ii_logic_analyzer_0.acq_clk" |
type="clock" |
dir="end"> |
<port name="acq_clk" internal="acq_clk" /> |
</interface> |
<interface |
name="tap" |
internal="signaltap_ii_logic_analyzer_0.tap" |
type="conduit" |
dir="end"> |
<port name="acq_data_in" internal="acq_data_in" /> |
<port name="acq_trigger_in" internal="acq_trigger_in" /> |
</interface> |
<module |
name="signaltap_ii_logic_analyzer_0" |
kind="altera_signaltap_ii_logic_analyzer" |
version="16.0" |
enabled="1" |
autoexport="1"> |
<parameter name="device_family" value="Cyclone IV E" /> |
<parameter name="gui_num_segments" value="2" /> |
<parameter name="gui_ram_type" value="AUTO" /> |
<parameter name="gui_sq" value="Continuous" /> |
<parameter name="gui_trigger_out_enabled" value="false" /> |
<parameter name="gui_use_segmented" value="false" /> |
<parameter name="sld_counter_pipeline" value="0" /> |
<parameter name="sld_data_bits" value="128" /> |
<parameter name="sld_enable_advanced_trigger" value="0" /> |
<parameter name="sld_node_crc_bits" value="32" /> |
<parameter name="sld_node_info" value="806383104" /> |
<parameter name="sld_pipeline_factor" value="0" /> |
<parameter name="sld_ram_pipeline" value="0" /> |
<parameter name="sld_sample_depth" value="128" /> |
<parameter name="sld_storage_qualifier_gap_record" value="0" /> |
<parameter name="sld_trigger_bits" value="1" /> |
<parameter name="sld_trigger_in_enabled" value="0" /> |
<parameter name="sld_trigger_level" value="1" /> |
<parameter name="sld_trigger_level_pipeline" value="1" /> |
<parameter name="sld_trigger_pipeline" value="0" /> |
</module> |
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> |
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" /> |
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" /> |
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" /> |
</system> |
/fir_wishbone/trunk/workspaces/synthesis/quartus/synthesise.sh
58,7 → 58,7
echo "Build error(s) exist. Refer to report files in the output_files directory for more details. Exiting."; exit; |
else |
echo $(date "+[%Y-%m-%d %H:%M:%S]: Configuring device..."); |
quartus_pgm -c 'USB-Blaster [1-1.1]' -m jtag -o 'p;./output_files/flight-controller.sof' | tee -ai ./synthesise.log; |
quartus_pgm -c 'USB-Blaster [1-1.1]' -m jtag -o 'p;./output_files/fir.sof' | tee -ai ./synthesise.log; |
fi |
|
errorStr=`grep 'Error (' ./synthesise.log` |