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URL https://opencores.org/ocsvn/mem_ctrl/mem_ctrl/trunk

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/trunk/bench/verilog/wb_mast_model.v
13,7 → 13,7
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
37,10 → 37,10
 
// CVS Log
//
// $Id: wb_mast_model.v,v 1.2 2001-11-11 01:52:03 rudi Exp $
// $Id: wb_mast_model.v,v 1.3 2001-11-29 02:17:36 rudi Exp $
//
// $Date: 2001-11-11 01:52:03 $
// $Revision: 1.2 $
// $Date: 2001-11-29 02:17:36 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,10
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/11/11 01:52:03 rudi
//
// Minor fixes to testbench ...
//
// Revision 1.1 2001/07/29 07:34:40 rudi
//
//
320,11 → 324,29
integer delay;
integer rcount;
integer wcount;
 
begin
wb_rmw2(a,a,s,delay,rcount,wcount);
end
endtask
 
 
task wb_rmw2;
input [31:0] ra;
input [31:0] wa;
input [3:0] s;
input delay;
input rcount;
input wcount;
 
integer delay;
integer rcount;
integer wcount;
integer n;
 
begin
 
@(posedge clk);
//@(posedge clk);
#1;
cyc = 1;
we = 0;
333,7 → 355,7
 
for(n=0;n<rcount-1;n=n+1)
begin
adr = a + (n*4);
adr = ra + (n*4);
stb = 1;
while(~ack & ~err) @(posedge clk);
rd_mem[n + rd_cnt] = din;
352,7 → 374,7
sel = s;
end
 
adr = a+(n*4);
adr = ra+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
376,7 → 398,7
@(posedge clk);
#1;
end
adr = a + (n*4);
adr = wa + (n*4);
dout = wr_mem[n + wr_cnt];
stb = 1;
we=1;
418,7 → 440,7
 
begin
 
@(posedge clk);
//@(posedge clk);
#1;
cyc = 1;
we = 1'bx;
/trunk/bench/verilog/test_bench_top.v
37,10 → 37,10
 
// CVS Log
//
// $Id: test_bench_top.v,v 1.5 2001-11-13 00:45:15 rudi Exp $
// $Id: test_bench_top.v,v 1.6 2001-11-29 02:17:36 rudi Exp $
//
// $Date: 2001-11-13 00:45:15 $
// $Revision: 1.5 $
// $Date: 2001-11-29 02:17:36 $
// $Revision: 1.6 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,10
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.5 2001/11/13 00:45:15 rudi
//
// Just minor test bench update, syncing all the files.
//
// Revision 1.4 2001/11/11 01:52:02 rudi
//
// Minor fixes to testbench ...
234,7 → 238,8
 
// HERE IS WHERE THE TEST CASES GO ...
 
if(1) // Full Regression Run
LVL = 2;
if(0) // Full Regression Run
begin
$display(" ......................................................");
$display(" : :");
257,6 → 262,7
sdram_wp(0);
sdram_rmw1(0);
sdram_rmw2(0);
rmw_cross1(0);
 
`ifdef MULTI_SDRAM
sdram_rd5(0);
276,7 → 282,6
`endif
 
scs_rdwr1(0);
 
end
else
if(1) // Quick Regression Run
286,35 → 291,37
$display(" : Short Regression Run ... :");
$display(" :....................................................:");
verbose = 0;
 
`ifdef FLASH
boot(2);
boot(LVL);
`endif
m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0000_0000);
 
sdram_rd1(2);
sdram_wr1(2);
sdram_rd1(LVL);
sdram_wr1(LVL);
 
sdram_rd2(2);
sdram_wr2(2);
sdram_rd2(LVL);
sdram_wr2(LVL);
 
sdram_rd3(2);
sdram_wr3(2);
sdram_rd3(LVL);
sdram_wr3(LVL);
 
sdram_rd4(2);
sdram_wr4(2);
sdram_rd4(LVL);
sdram_wr4(LVL);
 
sdram_wp(2);
sdram_rmw1(2);
sdram_rmw2(2);
sdram_wp(LVL);
sdram_rmw1(LVL);
sdram_rmw2(LVL);
rmw_cross1(LVL);
 
`ifdef MULTI_SDRAM
sdram_rd5(2);
sdram_wr5(2);
sdram_rd5(LVL);
sdram_wr5(LVL);
`endif
 
 
`ifdef FLASH
asc_rdwr1(2);
asc_rdwr1(LVL);
`endif
 
`ifdef SRAM
324,24 → 331,20
sram_rmw1;
sram_rmw2;
`endif
//scs_rdwr1(2);
scs_rdwr1(LVL);
 
mc_reset;
end
//else
if(1) // Suspend resume testing
if(0) // Suspend resume testing
begin
$display(" ......................................................");
$display(" : :");
$display(" : Suspend Resume Testing ... :");
$display(" :....................................................:");
 
verbose = 0;
done = 0;
LVL = 2;
 
fork
 
begin
 
`ifdef FLASH
356,7 → 359,6
while(susp_req | suspended) @(posedge clk);
sdram_rd2(LVL);
 
 
while(susp_req | suspended) @(posedge clk);
sdram_wr2(LVL);
 
375,6 → 377,8
sdram_rmw1(LVL);
while(susp_req | suspended) @(posedge clk);
sdram_rmw2(LVL);
while(susp_req | suspended) @(posedge clk);
rmw_cross1(LVL);
 
`ifdef MULTI_SDRAM
while(susp_req | suspended) @(posedge clk);
390,7 → 394,6
`endif
 
`ifdef SRAM
 
while(susp_req | suspended) @(posedge clk);
sram_rd1;
while(susp_req | suspended) @(posedge clk);
407,10 → 410,9
while(susp_req | suspended) @(posedge clk);
sram_rmw2;
`endif
//while(susp_req | suspended) @(posedge clk);
//scs_rdwr1(LVL);
while(susp_req | suspended) @(posedge clk);
scs_rdwr1(LVL);
 
 
done = 1;
end
 
427,7 → 429,7
mc_reset;
end
//else
if(1) // Bus Request testing
if(0) // Bus Request testing
begin
$display(" ......................................................");
$display(" : :");
435,14 → 437,14
$display(" :....................................................:");
verbose = 0;
done = 0;
LVL = 2;
fork
 
begin
`ifdef FLASH
boot(LVL);
`endif
 
m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0000_0000);
 
sdram_rd1(LVL);
sdram_wr1(LVL);
sdram_rd1(LVL);
460,6 → 462,7
sdram_wr5(LVL);
`endif
 
 
`ifdef FLASH
asc_rdwr1(LVL);
`endif
471,8 → 474,7
sram_rmw1;
sram_rmw2;
`endif
//scs_rdwr1(LVL);
 
scs_rdwr1(LVL);
done = 1;
end
 
496,8 → 498,8
$display(" :....................................................:");
//verbose = 0;
//boot(2);
 
/*
 
`define CSR 8'h00
`define POC 8'h04
`define BA_MASK 8'h08
514,8 → 516,11
m0.wb_wr1(`REG_BASE + `CSC1, 4'hf, 32'hffff_ffff);
m0.wb_wr1(`REG_BASE + `TMS1, 4'hf, 32'hffff_ffff);
m0.wb_wr1(`REG_BASE + `CSC2, 4'hf, 32'hffff_ffff);
@(posedge clk);
m0.wb_wr1(`REG_BASE + `TMS2, 4'hf, 32'hffff_ffff);
@(posedge clk);
m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'hffff_ffff);
@(posedge clk);
m0.wb_wr1(`REG_BASE + `TMS3, 4'hf, 32'hffff_ffff);
 
m0.wb_rd1(`REG_BASE + `CSR, 4'hf, data);
528,9 → 533,9
m0.wb_rd1(`REG_BASE + `TMS2, 4'hf, data);
m0.wb_rd1(`REG_BASE + `CSC3, 4'hf, data);
m0.wb_rd1(`REG_BASE + `TMS3, 4'hf, data);
*/
 
 
*/
 
 
m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0000_0000);
537,11 → 542,12
//sdram_rd1(2);
//sdram_wr1(2);
//asc_rdwr1(2);
//sram_rd1;
//sram_wr1;
// sram_rd1;
// sram_wr1;
//sram_rmw1;
//sram_rmw2;
//sram_wp;
//scs_rdwr1(2);
 
//scs_rdwr1(2);
 
558,13 → 564,33
//sdram_bo;
//sdram_rd1b(2);
 
 
 
//sdram_rd1(2);
//sdram_wr1(2);
 
 
//sdram_rd4(2);
//sdram_wr4(2);
//sdram_rd5(2);
//sdram_wr5(2);
sdram_wr4(2);
 
//sdram_wp(2);
//sdram_rmw1(2);
//sdram_rmw2(2);
 
//rmw_cross1(2);
 
/*
sram_rd1;
sram_wr1;
sram_rmw1;
sram_rmw2;
sram_wp;
*/
 
 
sdram_rd1(2);
sdram_wr1(2);
sdram_rd2(2);
575,15 → 601,13
sdram_wr4(2);
sdram_rd5(2);
sdram_wr5(2);
 
sdram_wp(2);
sdram_rmw1(2);
sdram_rmw2(2);
rmw_cross1(2);
 
*/
 
 
 
repeat(100) @(posedge clk);
$finish;
end
596,7 → 620,7
$display("\n\n");
$display("*****************************************************");
$display("*** Test Development ... ***");
$display("*****************************************************\n" );
$display("*****************************************************\n");
 
 
show_errors;
677,6 → 701,17
always @(error_cnt)
if(error_cnt > 25) #500 $finish;
 
/*
time mc_time;
 
always @(posedge mc_clk)
mc_time = $time;
 
always @(mc_cke_)
if($time != (mc_time+1) )
$display("WARNING: Unsexpected change of CKE (%t)", $time);
*/
/////////////////////////////////////////////////////////////////////
//
// IO Buffers
743,7 → 778,7
assign mc_we_ = mc_c_oe ? _mc_we_ : 1'bz;
assign mc_cas_ = mc_c_oe ? _mc_cas_ : 1'bz;
assign mc_ras_ = mc_c_oe ? _mc_ras_ : 1'bz;
assign #1.5 mc_cke_ = mc_c_oe ? _mc_cke_ : 1'bz;
assign mc_cke_ = mc_c_oe ? _mc_cke_ : 1'bz;
assign mc_cs_ = mc_c_oe ? _mc_cs_ : 8'bz;
assign mc_rp_ = mc_c_oe ? _mc_rp_ : 1'bz;
assign mc_vpen = mc_c_oe ? _mc_vpen : 1'bz;
/trunk/bench/verilog/tests.v
37,10 → 37,10
 
// CVS Log
//
// $Id: tests.v,v 1.5 2001-11-13 00:45:19 rudi Exp $
// $Id: tests.v,v 1.6 2001-11-29 02:17:36 rudi Exp $
//
// $Date: 2001-11-13 00:45:19 $
// $Revision: 1.5 $
// $Date: 2001-11-29 02:17:36 $
// $Revision: 1.6 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,10
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.5 2001/11/13 00:45:19 rudi
//
// Just minor test bench update, syncing all the files.
//
// Revision 1.4 2001/11/11 01:52:03 rudi
//
// Minor fixes to testbench ...
230,7 → 234,7
 
size = 4;
del = 1;
mode = 0;
mode = 2;
write = 0;
//force sdram0.Debug = 1;
 
380,12 → 384,12
case(quick)
0: del_max = 16;
1: del_max = 8;
2: del_max = 4;
2: del_max = 6;
endcase
 
size = 4;
del = 1;
mode = 9;
del = 0;
mode = 2;
write = 0;
//force sdram0.Debug = 1;
 
531,12 → 535,12
case(quick)
0: del_max = 16;
1: del_max = 8;
2: del_max = 4;
2: del_max = 6;
endcase
 
size = 1;
del = 0;
mode = 19;
del = 2;
mode = 16;
read = 1;
//force sdram0.Debug = 1;
 
584,7 → 588,7
begin
m0.mem_fill;
 
if(verbose) $display("Mode: %b, Size: %0d, Delay: %0d", mode, size, del);
if(verbose) $display("Mode: %b, Size: %0d, Delay: %0d (%t)", mode, size, del, $time);
 
m0.wb_wr_mult(`MEM_BASE + 0, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE + 0, 4'hf, del, size);
1340,8 → 1344,8
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0421 | (bas[0]<<9));
 
size = 2;
del = 0;
mode = 8;
del = 3;
mode = 0;
write = 1;
//force sdram0.Debug = 1;
 
1388,6 → 1392,7
if(verbose) $display("BAS: %0d, Mode: %b, Size: %0d, Delay: %0d",
bas, mode, size, del);
 
//$display("Accessing Bank 0");
if(write)
m0.wb_wr_mult(`MEM_BASE + (page_size*0*4) + size*0*4, 4'hf, del, size);
m0.wb_rd_mult(`MEM_BASE + (page_size*0*4) + size*0*4, 4'hf, del, size);
1395,6 → 1400,7
m0.wb_wr_mult(`MEM_BASE + (page_size*0*4) + size*1*4, 4'hf, del, size);
m0.wb_rd_mult(`MEM_BASE + (page_size*0*4) + size*1*4, 4'hf, del, size);
 
//$display("Accessing Bank 1");
if(write)
m0.wb_wr_mult(`MEM_BASE + (page_size*1*4) + size*2*4, 4'hf, del, size);
m0.wb_rd_mult(`MEM_BASE + (page_size*1*4) + size*2*4, 4'hf, del, size);
1402,6 → 1408,7
m0.wb_wr_mult(`MEM_BASE + (page_size*1*4) + size*3*4, 4'hf, del, size);
m0.wb_rd_mult(`MEM_BASE + (page_size*1*4) + size*3*4, 4'hf, del, size);
 
//$display("Accessing Bank 2");
if(write)
m0.wb_wr_mult(`MEM_BASE + (page_size*2*4) + size*4*4, 4'hf, del, size);
m0.wb_rd_mult(`MEM_BASE + (page_size*2*4) + size*4*4, 4'hf, del, size);
1409,6 → 1416,7
m0.wb_wr_mult(`MEM_BASE + (page_size*2*4) + size*5*4, 4'hf, del, size);
m0.wb_rd_mult(`MEM_BASE + (page_size*2*4) + size*5*4, 4'hf, del, size);
 
//$display("Accessing Bank 3");
if(write)
m0.wb_wr_mult(`MEM_BASE + (page_size*3*4) + size*6*4, 4'hf, del, size);
m0.wb_rd_mult(`MEM_BASE + (page_size*3*4) + size*6*4, 4'hf, del, size);
1512,12 → 1520,12
case(quick)
0: del_max = 16;
1: del_max = 8;
2: del_max = 4;
2: del_max = 8;
endcase
 
size = 1;
del = 0;
mode = 8;
del = 3;
mode = 4;
read = 1;
 
for(mode=0;mode<20;mode=mode+1)
1720,7 → 1728,7
 
size = 2;
del = 0;
mode = 8;
mode = 4;
write = 1;
if(0)
begin
2034,8 → 2042,8
endcase
 
size = 5;
del = 1;
mode = 6;
del = 0;
mode = 0;
read = 1;
 
if(0)
2238,6 → 2246,296
`endif
 
 
task rmw_cross1;
input quick;
 
integer quick;
integer x,s,n,m,adr;
integer del, size;
reg [7:0] mode, a_mode;
reg [2:0] bs;
integer sz_inc;
integer sz_max, del_max;
integer read;
reg [2:0] bas;
reg [31:0] data, exp;
integer page_size;
integer cycle;
 
begin
$display("\n\n");
$display("*****************************************************");
$display("*** RMW CS Cross Test 1 ... ***");
$display("*****************************************************\n");
 
page_size = 256; // 64 mbit x 32 SDRAM
 
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0300);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS3, 4'hf, 32'hffff_f40c);
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0, // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2, // CL
1'b0, // Burst Type (0=Seq;1=Inter)
3'd3 // Burst Length
});
 
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821);
 
case(quick)
0: sz_max = 32;
1: sz_max = 16;
2: sz_max = 8;
endcase
 
case(quick)
0: del_max = 16;
1: del_max = 8;
2: del_max = 4;
endcase
 
size = 16;
del = 0;
mode = 4;
a_mode = 0;
read = 1;
write = 1;
cycle = 1;
 
for(cycle=0;cycle<7;cycle = cycle + 1)
for(mode=0;mode<19;mode=mode+1)
for(a_mode=0;a_mode<3;a_mode=a_mode+1)
begin
 
repeat(1) @(posedge clk);
 
sdram0.mem_fill(1024);
 
case(mode[4:2])
0: bs = 0;
1: bs = 1;
2: bs = 2;
3: bs = 3;
4: bs = 7;
endcase
case(mode[4:2])
0: sz_inc = 1;
1: sz_inc = 2;
2: sz_inc = 4;
3: sz_inc = 8;
4: sz_inc = 1;
endcase
 
 
m0.wb_wr1(`REG_BASE + `TMS0, 4'hf, {
4'd0, // RESERVED [31:28]
4'd7, // Trfc [27:24]
4'd2, // Trp [23:20]
3'd2, // Trcd [19:17]
2'd1, // Twr [16:15]
5'd0, // RESERVED [14:10]
1'd0+mode[1], // Wr. Burst Len (1=Single)
2'd0, // Op Mode
3'd2+mode[0], // CL
1'b0, // Burst Type (0=Seq;1=Inter)
3'd0+bs // Burst Length
});
 
case(a_mode)
0: m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0060_0025); // 32 bit bus
1: m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0060_0005); // 8 bit bus
2: m0.wb_wr1(`REG_BASE + `CSC3, 4'hf, 32'h0060_0015); // 16 bit bus
endcase
 
repeat(10) @(posedge clk);
if(!verbose) $display("Mode: %b", mode);
 
for(del=0;del<del_max;del=del+1)
for(size=sz_inc;size<sz_max;size=size+sz_inc)
begin
m0.mem_fill;
for(n=0;n<1024;n=n+1)
m0.wr_mem[n] = {n[15:0],n[15:0]};
 
if(verbose) $display("Mode: %0d, A_mode: %0d, Size: %0d, Delay: %0d, Cyc. Delay: %0d", mode, a_mode, size, del, cycle);
 
repeat(cycle) @(posedge clk);
m0.wb_rmw2(`MEM_BASE3 + size*0*4,
`MEM_BASE + (page_size*0*4) + size*0*4, 4'hf, del, size, size);
 
repeat(cycle) @(posedge clk);
m0.wb_rmw2(`MEM_BASE3 + size*1*4,
`MEM_BASE + (page_size*0*4) + size*1*4, 4'hf, del, size, size);
 
repeat(cycle) @(posedge clk);
m0.wb_rmw2(`MEM_BASE3 + size*2*4,
`MEM_BASE + (page_size*1*4) + size*2*4, 4'hf, del, size, size);
 
repeat(cycle) @(posedge clk);
m0.wb_rmw2(`MEM_BASE3 + size*3*4,
`MEM_BASE + (page_size*1*4) + size*3*4, 4'hf, del, size, size);
 
repeat(cycle) @(posedge clk);
m0.wb_rmw2(`MEM_BASE3 + size*4*4,
`MEM_BASE + (page_size*2*4) + size*4*4, 4'hf, del, size, size);
 
repeat(cycle) @(posedge clk);
m0.wb_rmw2(`MEM_BASE3 + size*5*4,
`MEM_BASE + (page_size*2*4) + size*5*4, 4'hf, del, size, size);
 
repeat(cycle) @(posedge clk);
m0.wb_rmw2(`MEM_BASE3 + size*6*4,
`MEM_BASE + (page_size*3*4) + size*6*4, 4'hf, del, size, size);
 
repeat(cycle) @(posedge clk);
m0.wb_rmw2(`MEM_BASE3 + size*7*4,
`MEM_BASE + (page_size*3*4) + size*7*4, 4'hf, del, size, size);
 
 
repeat(10) @(posedge clk);
 
x = 0;
for(n=0;n<(size*8);n=n+1)
begin
 
case(a_mode)
0: data = {16'hxxxx, n[15:0]};
1:
begin
data[31:24] = x[7:0]+3;
data[23:16] = x[7:0]+2;
data[15:08] = x[7:0]+1;
data[07:00] = x[7:0]+0;
end
2: begin
data[31:16] = x[15:0]+1;
data[15:00] = x[15:0]+0;
end
endcase
 
case(a_mode)
0: x = x + 1;
1: x = x + 4;
2: x = x + 2;
endcase
 
exp = m0.rd_mem[n];
if(a_mode==0) exp[31:16] = data[31:16];
 
if(data !== exp)
begin
$display("ERROR: RD[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
n, data, exp, $time);
error_cnt = error_cnt + 1;
end
 
end
 
for(m=0;m<4;m=m+1)
for(n=0;n<size*2;n=n+1)
begin
 
case(m)
0: data = sdram0.Bank0[n];
1: data = sdram0.Bank1[n+1*size*2];
2: data = sdram0.Bank2[n+2*size*2];
3: data = sdram0.Bank3[n+3*size*2];
endcase
 
if((data !== m0.wr_mem[(m*size*2)+n]) | (|data === 1'bx) |
(|m0.wr_mem[(m*size*2)+n] === 1'bx) )
begin
$display("ERROR: WR Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
(m*size*2)+n, data, m0.wr_mem[(m*size*2)+n], $time);
error_cnt = error_cnt + 1;
end
end
 
 
 
 
/*
m0.mem_fill;
for(n=0;n<1024;n=n+1)
m0.wr_mem[n] = 32'hffff_ffff;
if(verbose) $display("Mode: %0d, Size: %0d, Delay: %0d", mode, size, del);
 
if(write) m0.wb_wr_mult(`MEM_BASE3 + size*0*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE3 + size*0*4, 4'hf, del, size);
 
if(write) m0.wb_wr_mult(`MEM_BASE3 + size*1*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE3 + size*1*4, 4'hf, del, size);
 
if(write) m0.wb_wr_mult(`MEM_BASE3 + size*2*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE3 + size*2*4, 4'hf, del, size);
 
if(write) m0.wb_wr_mult(`MEM_BASE3 + size*3*4, 4'hf, del, size);
if(read) m0.wb_rd_mult(`MEM_BASE3 + size*3*4, 4'hf, del, size);
 
repeat(10) @(posedge clk);
 
x = 0;
for(n=0;n<(size*4);n=n+1)
begin
 
case(mode)
0: data = {16'hxxxx, n[15:0]};
1:
begin
data[31:24] = x[7:0]+3;
data[23:16] = x[7:0]+2;
data[15:08] = x[7:0]+1;
data[07:00] = x[7:0]+0;
end
2: begin
data[31:16] = x[15:0]+1;
data[15:00] = x[15:0]+0;
end
endcase
 
case(mode)
0: x = x + 1;
1: x = x + 4;
2: x = x + 2;
endcase
 
exp = m0.rd_mem[n];
if(mode==0) exp[31:16] = data[31:16];
 
if(data !== exp)
begin
$display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
n, data, exp, $time);
error_cnt = error_cnt + 1;
end
 
end
*/
 
end
 
end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ... ***");
$display("*****************************************************\n\n");
 
end
endtask
 
 
task asc_rdwr1;
input quick;
 
2261,7 → 2559,7
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0300);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS3, 4'hf, 32'hffff_f40a);
m0.wb_wr1(`REG_BASE + `TMS3, 4'hf, 32'hffff_f40b);
 
case(quick)
0: sz_max = 32;
2276,7 → 2574,7
endcase
 
size = 16;
del = 4;
del = 0;
mode = 0;
read = 1;
write = 1;
2297,8 → 2595,8
repeat(10) @(posedge clk);
if(!verbose) $display("Mode: %b", mode);
 
//for(del=0;del<del_max;del=del+1)
//for(size=1;size<sz_max;size=size+1)
for(del=0;del<del_max;del=del+1)
for(size=1;size<sz_max;size=size+1)
begin
m0.mem_fill;
for(n=0;n<1024;n=n+1)
2830,7 → 3128,7
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0300);
m0.wb_wr1(`REG_BASE + `BA_MASK, 4'hf, 32'h0000_00f0);
 
m0.wb_wr1(`REG_BASE + `TMS5, 4'hf, 32'hf03f_4104);
m0.wb_wr1(`REG_BASE + `TMS5, 4'hf, 32'hf03f_4105);
m0.wb_wr1(`REG_BASE + `CSC5, 4'hf, 32'h00a0_0027);
 
 
2955,7 → 3253,7
endcase
 
size = 4;
del = 4;
del = 1;
mode = 0;
read = 1;
//force sdram0.Debug = 1;
2962,7 → 3260,8
 
for(mode=0;mode<20;mode=mode+1)
begin
sdram0.mem_fill(1024);
//sdram0.mem_fill(1024);
fill_mem(1024);
 
case(mode[4:2])
0: bs = 0;
3152,6 → 3451,7
reg [31:0] mem1[0:1024];
reg [31:0] mem2[0:1024];
reg [31:0] mem3[0:1024];
integer cycle;
 
begin
 
3165,7 → 3465,7
 
case(quick)
0: sz_max = 32;
1: sz_max = 32;
1: sz_max = 16;
2: sz_max = 16;
endcase
 
3172,7 → 3472,7
case(quick)
0: del_max = 16;
1: del_max = 8;
2: del_max = 4;
2: del_max = 8;
endcase
 
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0300);
3193,13 → 3493,15
});
 
kro = 1;
cycle=3;
for(cycle=0;cycle<8;cycle=cycle+1)
for(kro=0;kro<2;kro=kro+1) // Don't Need this for this test
begin
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821 | (kro[0]<<10));
 
size = 2;
del = 0;
mode = 8;
del = 5;
mode = 2;
 
//force sdram0.Debug = 1;
 
3238,7 → 3540,7
 
repeat(50) @(posedge clk);
 
if(!verbose) $display("KRO: %0d, Mode: %b", kro, mode);
if(!verbose) $display("KRO: %0d, Mode: %b, Cyc. Delay: %0d", kro, mode, cycle);
 
for(del=0;del<del_max;del=del+1)
for(size=sz_inc;size<sz_max;size=size+sz_inc)
3254,21 → 3556,30
3: mem3[n] = sdram0.Bank3[n+3*size*2];
endcase
 
if(verbose) $display("KRO: %0d, Mode: %b, Size: %0d, Delay: %0d",
kro, mode, size, del);
if(verbose) $display("KRO: %0d, Mode: %b, Size: %0d, Delay: %0d, Cyc. Delay: %0d (%t)",
kro, mode, size, del, cycle, $time);
 
repeat(cycle) @(posedge clk);
m0.wb_rmw(`MEM_BASE + (page_size*0*4) + size*0*4, 4'hf, del, size, size);
repeat(cycle) @(posedge clk);
m0.wb_rmw(`MEM_BASE + (page_size*0*4) + size*1*4, 4'hf, del, size, size);
 
repeat(cycle) @(posedge clk);
m0.wb_rmw(`MEM_BASE + (page_size*1*4) + size*2*4, 4'hf, del, size, size);
repeat(cycle) @(posedge clk);
m0.wb_rmw(`MEM_BASE + (page_size*1*4) + size*3*4, 4'hf, del, size, size);
 
repeat(cycle) @(posedge clk);
m0.wb_rmw(`MEM_BASE + (page_size*2*4) + size*4*4, 4'hf, del, size, size);
repeat(cycle) @(posedge clk);
m0.wb_rmw(`MEM_BASE + (page_size*2*4) + size*5*4, 4'hf, del, size, size);
 
repeat(cycle) @(posedge clk);
m0.wb_rmw(`MEM_BASE + (page_size*3*4) + size*6*4, 4'hf, del, size, size);
repeat(cycle) @(posedge clk);
m0.wb_rmw(`MEM_BASE + (page_size*3*4) + size*7*4, 4'hf, del, size, size);
 
repeat(cycle) @(posedge clk);
for(m=0;m<4;m=m+1)
for(n=0;n<(size*2);n=n+1)
begin
3339,6 → 3650,7
reg [2:0] kro;
reg [31:0] data, data1;
integer page_size;
integer cycle;
 
begin
 
3352,14 → 3664,14
 
case(quick)
0: sz_max = 32;
1: sz_max = 32;
2: sz_max = 16;
1: sz_max = 16;
2: sz_max = 10;
endcase
 
case(quick)
0: del_max = 16;
1: del_max = 8;
2: del_max = 4;
2: del_max = 8;
endcase
 
m0.wb_wr1(`REG_BASE + `CSR, 4'hf, 32'h6030_0300);
3379,7 → 3691,8
3'd3 // Burst Length
});
 
kro = 0;
kro = 1;
for(cycle=0;cycle<8;cycle=cycle+1)
for(kro=0;kro<2;kro=kro+1) // Don't Need this for this test
begin
m0.wb_wr1(`REG_BASE + `CSC0, 4'hf, 32'h0000_0821 | (kro[0]<<10));
3427,7 → 3740,7
 
repeat(50) @(posedge clk);
 
if(!verbose) $display("KRO: %0d, Mode: %b", kro, mode);
if(!verbose) $display("KRO: %0d, Mode: %b, Cyc.Del: %0d", kro, mode, cycle);
 
for(del=0;del<del_max;del=del+1)
for(size=sz_inc;size<sz_max;size=size+sz_inc)
3436,21 → 3749,30
fill_mem(1024);
 
 
if(verbose) $display("KRO: %0d, Mode: %b, Size: %0d, Delay: %0d",
kro, mode, size, del);
if(verbose) $display("KRO: %0d, Mode: %b, Size: %0d, Delay: %0d, Cyc.Del: %0d (%t)",
kro, mode, size, del, cycle, $time);
 
repeat(cycle) @(posedge clk);
m0.wb_wmr(`MEM_BASE + (page_size*0*4) + size*0*4, 4'hf, del, size, size);
repeat(cycle) @(posedge clk);
m0.wb_wmr(`MEM_BASE + (page_size*0*4) + size*1*4, 4'hf, del, size, size);
 
repeat(cycle) @(posedge clk);
m0.wb_wmr(`MEM_BASE + (page_size*1*4) + size*2*4, 4'hf, del, size, size);
repeat(cycle) @(posedge clk);
m0.wb_wmr(`MEM_BASE + (page_size*1*4) + size*3*4, 4'hf, del, size, size);
 
repeat(cycle) @(posedge clk);
m0.wb_wmr(`MEM_BASE + (page_size*2*4) + size*4*4, 4'hf, del, size, size);
repeat(cycle) @(posedge clk);
m0.wb_wmr(`MEM_BASE + (page_size*2*4) + size*5*4, 4'hf, del, size, size);
 
repeat(cycle) @(posedge clk);
m0.wb_wmr(`MEM_BASE + (page_size*3*4) + size*6*4, 4'hf, del, size, size);
repeat(cycle) @(posedge clk);
m0.wb_wmr(`MEM_BASE + (page_size*3*4) + size*7*4, 4'hf, del, size, size);
 
repeat(cycle) @(posedge clk);
for(n=0;n<(size*2);n=n+1)
begin
 
/trunk/bench/verilog/160b3ver/adv_bb.v
931,8 → 931,8
 
// record the time for addr changes .
always @(addr) begin
if ($time != 0) begin
if ((curr_addr_time + TAVAV) > $time & !ceb) //Read/Write Cycle Time --- Added "& !ceb" RU 9/9/99 9pm
if ($time != 0 & !ceb) begin
if (((curr_addr_time + TAVAV) > $time) & !ceb) //Read/Write Cycle Time --- Added "& !ceb" RU 9/9/99 9pm
$display("FLASH: [",$time,"] Timing Violation: Read/Write Cycle Time (TAVAV), Last addr change: %d",curr_addr_time) ;
curr_addr_time = $time ;
end
/trunk/bench/verilog/sdram_models/16Mx16/mt48lc16m16a2.v
212,9 → 212,11
@ (posedge Clk) begin
Sys_clk = CkeZ;
CkeZ = Cke;
 
if (Cke == 1'b0 && (Data_in_enable == 1'b1 || Data_out_enable == 1'b1)) begin
$display ("at time %t ERROR: Illegal power down or self refresh. Please make sure data bus is idle.", $time);
end
 
end
@ (negedge Clk) begin
Sys_clk = 1'b0;
/trunk/rtl/verilog/mc_cs_rf.v
37,10 → 37,10
 
// CVS Log
//
// $Id: mc_cs_rf.v,v 1.3 2001-09-24 00:38:21 rudi Exp $
// $Id: mc_cs_rf.v,v 1.4 2001-11-29 02:16:28 rudi Exp $
//
// $Date: 2001-09-24 00:38:21 $
// $Revision: 1.3 $
// $Date: 2001-11-29 02:16:28 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,10
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/09/24 00:38:21 rudi
//
// Changed Reset to be active high and async.
//
// Revision 1.2 2001/08/10 08:16:21 rudi
//
// - Changed IO names to be more clear.
133,19 → 137,24
// Write Logic
//
 
assign sel = addr[6:3] == reg_select[3:0];
reg [6:0] addr_r;
 
always @(posedge clk or posedge rst)
if(rst) csc <= #1 (this_cs[2:0] == `MC_DEF_SEL) ?
always @(posedge clk)
addr_r <= #1 addr[6:0];
 
assign sel = addr_r[6:3] == reg_select[3:0];
 
always @(posedge clk)
if(rst) csc <= #1 (this_cs[2:0] == `MC_DEF_SEL) ?
{26'h0, poc[1:0], 1'b0, poc[3:2], (poc[3:2] != 2'b00)} : 32'h0;
else
if(rf_we & sel & !addr[2]) csc <= #1 din;
if(rf_we & sel & !addr_r[2]) csc <= #1 din;
 
always @(posedge clk or posedge rst)
always @(posedge clk)
if(rst) tms <= #1 (this_cs[2:0] == `MC_DEF_SEL) ?
`MC_DEF_POR_TMS : 32'h0;
else
if(rf_we & sel & addr[2]) tms <= #1 din;
if(rf_we & sel & addr_r[2]) tms <= #1 din;
 
////////////////////////////////////////////////////////////////////
//
152,7 → 161,7
// Load Mode Register Request/Ack Logic
//
always @(posedge clk)
lmr_req_we <= #1 rf_we & sel & addr[2];
lmr_req_we <= #1 rf_we & sel & addr_r[2];
 
always @(posedge clk or posedge rst)
if(rst) lmr_req <= #1 1'b0;
167,7 → 176,7
// Initialize SDRAM Request/Ack & tracking logic
//
always @(posedge clk)
init_req_we <= #1 rf_we & sel & !addr[2];
init_req_we <= #1 rf_we & sel & !addr_r[2];
 
always @(posedge clk or posedge rst)
if(rst) init_req <= #1 1'b0;
/trunk/rtl/verilog/mc_mem_if.v
38,10 → 38,10
 
// CVS Log
//
// $Id: mc_mem_if.v,v 1.3 2001-09-24 00:38:21 rudi Exp $
// $Id: mc_mem_if.v,v 1.4 2001-11-29 02:16:28 rudi Exp $
//
// $Date: 2001-09-24 00:38:21 $
// $Revision: 1.3 $
// $Date: 2001-11-29 02:16:28 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,10
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/09/24 00:38:21 rudi
//
// Changed Reset to be active high and async.
//
// Revision 1.2 2001/09/02 02:28:28 rudi
//
// Many fixes for minor bugs that showed up in gate level simulations.
91,11 → 95,12
module mc_mem_if(clk, rst, mc_clk, mc_br, mc_bg,
mc_addr, mc_data_o, mc_dp_o, mc_data_oe,
mc_dqm, mc_oe_, mc_we_, mc_cas_, mc_ras_, mc_cke_, mc_cs_,
mc_adsc_, mc_adv_, mc_ack, mc_rp, mc_rp_d,
mc_br_r, mc_bg_d, mc_data_od, mc_dp_od, mc_addr_d, mc_ack_r, we_,
ras_, cas_, cke_, mc_adsc_d, mc_adv_d, cs_en, rfr_ack, cs_need_rfr,
lmr_sel, spec_req_cs, cs, data_oe, susp_sel, mc_c_oe, oe_,
wb_stb_i, wb_sel_i, wb_cycle, wr_cycle
mc_adsc_, mc_adv_, mc_ack, mc_rp, mc_c_oe, mc_c_oe_d,
mc_br_r, mc_bg_d, mc_data_od, mc_dp_od, mc_addr_d, mc_ack_r,
we_, ras_, cas_, cke_, mc_adsc_d, mc_adv_d, cs_en, rfr_ack,
cs_need_rfr, lmr_sel, spec_req_cs, cs, fs, data_oe, susp_sel,
suspended_o, oe_, wb_stb_i, wb_sel_i, wb_cycle, wr_cycle,
mc_data_ir, mc_data_i, mc_dp_i, mc_sts_ir, mc_sts_i, mc_zz_o
);
// Memory Interface
input clk;
118,6 → 123,10
output mc_adv_;
input mc_ack;
output mc_rp;
output mc_c_oe;
output [35:0] mc_data_ir;
output mc_sts_ir;
output mc_zz_o;
 
// Internal Interface
output mc_br_r;
124,7 → 133,7
input mc_bg_d;
input data_oe;
input susp_sel;
input mc_c_oe;
input suspended_o;
input [31:0] mc_data_od;
input [3:0] mc_dp_od;
input [23:0] mc_addr_d;
144,9 → 153,13
input lmr_sel;
input [7:0] spec_req_cs;
input [7:0] cs;
input fs;
input mc_adsc_d;
input mc_adv_d;
input mc_rp_d;
input mc_c_oe_d;
input [31:0] mc_data_i;
input [3:0] mc_dp_i;
input mc_sts_i;
 
////////////////////////////////////////////////////////////////////
//
171,8 → 184,11
reg mc_br_r;
reg mc_ack_r;
reg mc_rp;
reg mc_c_oe;
reg mc_zz_o;
 
//integer n;
reg [35:0] mc_data_ir;
reg mc_sts_ir;
 
////////////////////////////////////////////////////////////////////
//
180,9 → 196,21
//
 
always @(posedge mc_clk)
mc_rp <= #1 mc_rp_d;
mc_zz_o <= #1 suspended_o;
 
always @(posedge mc_clk)
mc_sts_ir <= #1 mc_sts_i;
 
always @(posedge mc_clk)
mc_data_ir <= #1 {mc_dp_i, mc_data_i};
 
always @(posedge mc_clk)
mc_c_oe <= #1 mc_c_oe_d;
 
always @(posedge mc_clk)
mc_rp <= #1 !suspended_o & !fs;
 
always @(posedge mc_clk)
mc_br_r <= #1 mc_br;
 
always @(posedge mc_clk)
193,7 → 221,7
 
always @(posedge mc_clk or posedge rst)
if(rst) mc_data_oe <= #1 1'b0;
else mc_data_oe <= #1 data_oe & !susp_sel & mc_c_oe;
else mc_data_oe <= #1 data_oe & !susp_sel & mc_c_oe_d;
 
always @(posedge mc_clk)
mc_data_o <= #1 mc_data_od;
228,16 → 256,6
 
assign mc_cke_ = cke_;
 
/* Apparently Synopsys Can't handle this ....
always @(posedge mc_clk)
for(n=0;n<8;n=n+1)
mc_cs_[n] <= #1 ~(cs_en & (
(rfr_ack | susp_sel) ? cs_need_rfr[n] :
lmr_sel ? spec_req_cs[n] :
cs[n]
));
*/
 
always @(posedge mc_clk or posedge rst)
if(rst) mc_cs_[0] <= #1 1'b1;
else
/trunk/rtl/verilog/mc_defines.v
37,10 → 37,10
 
// CVS Log
//
// $Id: mc_defines.v,v 1.3 2001-09-10 13:44:17 rudi Exp $
// $Id: mc_defines.v,v 1.4 2001-11-29 02:16:28 rudi Exp $
//
// $Date: 2001-09-10 13:44:17 $
// $Revision: 1.3 $
// $Date: 2001-11-29 02:16:28 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,9
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/09/10 13:44:17 rudi
// *** empty log message ***
//
// Revision 1.2 2001/08/10 08:16:21 rudi
//
// - Changed IO names to be more clear.
62,7 → 65,8
// Revision 1.3 2001/06/12 15:19:49 rudi
//
//
// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
// Minor changes after running lint, and a small bug
// fix reading csr and ba_mask registers.
//
// Revision 1.2 2001/06/03 11:37:17 rudi
//
108,9 → 112,18
// This are the default Power-On Reset values for Chip Select
//
 
// This will be defined by the run script for my test bench ...
//`define RUDIS_TB 1
 
// Defines which chip select is used for Power On booting
`define MC_DEF_SEL 3'h1
 
// To run my default testbench default boot CS must be 3 !!!
`ifdef RUDIS_TB
`define MC_DEF_SEL 3'h3
`else
`define MC_DEF_SEL 3'h0
`endif
 
// Defines the default (reset) TMS value for the DEF_SEL chip select
`define MC_DEF_POR_TMS 32'hffff_ffff
 
128,6 → 141,14
//`define MC_HAVE_CS7 1
 
 
// To run my default testbench those need to there !!!
`ifdef RUDIS_TB
`define MC_HAVE_CS2 1
`define MC_HAVE_CS3 1
`define MC_HAVE_CS4 1
`define MC_HAVE_CS5 1
`endif
 
/////////////////////////////////////////////////////////////////////
//
// Init Refresh
/trunk/rtl/verilog/mc_top.v
37,10 → 37,10
 
// CVS Log
//
// $Id: mc_top.v,v 1.4 2001-09-10 13:44:17 rudi Exp $
// $Id: mc_top.v,v 1.5 2001-11-29 02:16:28 rudi Exp $
//
// $Date: 2001-09-10 13:44:17 $
// $Revision: 1.4 $
// $Date: 2001-11-29 02:16:28 $
// $Revision: 1.5 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,9
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.4 2001/09/10 13:44:17 rudi
// *** empty log message ***
//
// Revision 1.3 2001/09/02 02:28:28 rudi
//
// Many fixes for minor bugs that showed up in gate level simulations.
168,12 → 171,9
wire wb_first;
wire wb_wait;
wire mem_ack;
wire mem_wb_ack_o, rf_wb_ack_o;
 
// --------------------------------------
// Suspend Resume Interface
wire susp_sel;
reg mc_zz_pad_o;
 
// Register File Interconnects
wire [31:0] rf_dout;
187,7 → 187,6
wire [7:0] cs_need_rfr;
wire [2:0] ref_int;
wire [31:0] mem_dout;
wire rf_wb_err_o;
wire wp_err;
 
// Address Select Signals
216,6 → 215,7
wire [31:0] mc_data_od;
wire [3:0] mc_dp_od;
wire [23:0] mc_addr_d;
wire [35:0] mc_data_ir;
 
// Refresh Counter Signals
wire rfr_req;
238,6 → 238,7
wire wb_cycle, wr_cycle;
wire [31:0] tms_s;
wire [31:0] csc_s;
wire mc_c_oe_d;
wire mc_br_r;
wire mc_bg_d;
wire mc_adsc_d;
244,39 → 245,16
wire mc_adv_d;
wire mc_ack_r;
wire err;
wire mc_sts_i;
 
wire mc_rp_d;
 
/*
// synopsys translate_off
initial // FOR RICHARD TEST BENCH ONLY ... FIX_ME
begin
$shm_open("waves");
$shm_probe("AS",mc_top,"AS");
$display("INFO: Signal dump enabled ...\n\n");
repeat(4000) @(posedge clk_i);
$finish;
end
// synopsys translate_on
*/
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
assign mc_rp_d = !suspended_o & !fs;
 
always @(posedge mc_clk_i)
mc_zz_pad_o <= #1 suspended_o;
 
assign wb_err_o = wb_cyc_i & wb_stb_i &
(`MC_MEM_SEL ? ((par_err & !wb_we_i) | err | wp_err) : rf_wb_err_o);
assign wb_data_o = `MC_MEM_SEL ? mem_dout : rf_dout;
assign wb_ack_o = `MC_MEM_SEL ? mem_wb_ack_o : rf_wb_ack_o;
 
assign obct_cs = (rfr_ack | susp_sel) ? cs_need_rfr :
(lmr_ack | init_ack) ? spec_req_cs : cs;
 
assign lmr_sel = lmr_ack | init_ack;
 
assign tms_s = lmr_sel ? sp_tms : tms;
296,8 → 274,7
.wb_we_i( wb_we_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_stb_i( wb_stb_i ),
.wb_ack_o( rf_wb_ack_o ),
.wb_err_o( rf_wb_err_o ),
.wb_ack_o( ),
.wp_err( wp_err ),
.csc( csc ),
.tms( tms ),
305,8 → 282,8
.sp_csc( sp_csc ),
.sp_tms( sp_tms ),
.cs( cs ),
.mc_data_i( mc_data_pad_i ),
.mc_sts( mc_sts_pad_i ),
.mc_data_i( mc_data_ir[31:0]),
.mc_sts( mc_sts_ir ),
.mc_vpen( mc_vpen_pad_o ),
.fs( fs ),
.cs_le( cs_le ),
325,8 → 302,9
.csc( csc_s ),
.tms( tms_s ),
.wb_stb_i( wb_stb_i ),
.wb_ack_o( mem_wb_ack_o ),
.wb_ack_o( wb_ack_o ),
.wb_addr_i( wb_addr_i ),
.wb_we_i( wb_we_i ),
.wb_write_go( wb_write_go ),
.wr_hold( wr_hold ),
.cas_( cas_ ),
363,11 → 341,15
.rst( rst_i ),
.csc( csc ),
.wb_cyc_i( wb_cyc_i ),
.mem_wb_ack_o( mem_wb_ack_o ),
.wb_stb_i( wb_stb_i ),
.mem_ack( mem_ack ),
.wb_ack_o( wb_ack_o ),
.wb_we_i( wb_we_i ),
.wb_data_i( wb_data_i ),
.wb_data_o( mem_dout ),
.wb_read_go( wb_read_go ),
.mc_data_i( mc_data_pad_i ),
.mc_clk( mc_clk_i ),
.mc_data_del( mc_data_ir ),
.mc_dp_i( mc_dp_pad_i ),
.mc_data_o( mc_data_od ),
.mc_dp_o( mc_dp_od ),
418,7 → 400,7
.cs_en( cs_en ),
.mc_adsc( mc_adsc_d ),
.mc_adv( mc_adv_d ),
.mc_c_oe( mc_coe_pad_coe_o),
.mc_c_oe( mc_c_oe_d ),
.wb_cycle( wb_cycle ),
.wr_cycle( wr_cycle ),
.csc( csc_s ),
455,7 → 437,7
.wb_cyc_i( wb_cyc_i ),
.wb_stb_i( wb_stb_i ),
.wb_we_i( wb_we_i ),
.wb_ack_o( mem_wb_ack_o ),
.wb_ack_o( wb_ack_o ),
.wb_err( wb_err_o ),
.wb_read_go( wb_read_go ),
.wb_write_go( wb_write_go ),
462,7 → 444,13
.wb_first( wb_first ),
.wb_wait( wb_wait ),
.mem_ack( mem_ack ),
.wr_hold( wr_hold )
.wr_hold( wr_hold ),
.err( err ),
.par_err( par_err ),
.wp_err( wp_err ),
.wb_data_o( wb_data_o ),
.mem_dout( mem_dout ),
.rf_dout( rf_dout )
);
 
mc_mem_if u7(
469,7 → 457,6
.clk( clk_i ),
.rst( rst_i ),
.mc_rp( mc_rp_pad_o_ ),
.mc_rp_d( mc_rp_d ),
.mc_clk( mc_clk_i ),
.mc_br( mc_br_pad_i ),
.mc_bg( mc_bg_pad_o ),
492,6 → 479,7
.mc_dp_od( mc_dp_od ),
.mc_addr_d( mc_addr_d ),
.mc_ack( mc_ack_pad_i ),
.mc_zz_o( mc_zz_pad_o ),
.we_( we_ ),
.ras_( ras_ ),
.cas_( cas_ ),
504,15 → 492,23
.lmr_sel( lmr_sel ),
.spec_req_cs( spec_req_cs ),
.cs( cs ),
.fs( fs ),
.data_oe( data_oe ),
.susp_sel( susp_sel ),
.suspended_o( suspended_o ),
.mc_c_oe( mc_coe_pad_coe_o),
.mc_c_oe_d( mc_c_oe_d ),
.mc_ack_r( mc_ack_r ),
.oe_( oe_ ),
.wb_stb_i( wb_stb_i ),
.wb_sel_i( wb_sel_i ),
.wb_cycle( wb_cycle ),
.wr_cycle( wr_cycle )
.wr_cycle( wr_cycle ),
.mc_data_i( mc_data_pad_i ),
.mc_dp_i( mc_dp_pad_i ),
.mc_data_ir( mc_data_ir ),
.mc_sts_i( mc_sts_pad_i ),
.mc_sts_ir( mc_sts_ir )
);
 
endmodule
/trunk/rtl/verilog/mc_dp.v
38,10 → 38,10
 
// CVS Log
//
// $Id: mc_dp.v,v 1.3 2001-09-24 00:38:21 rudi Exp $
// $Id: mc_dp.v,v 1.4 2001-11-29 02:16:28 rudi Exp $
//
// $Date: 2001-09-24 00:38:21 $
// $Revision: 1.3 $
// $Date: 2001-11-29 02:16:28 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,10
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/09/24 00:38:21 rudi
//
// Changed Reset to be active high and async.
//
// Revision 1.2 2001/08/10 08:16:21 rudi
//
// - Changed IO names to be more clear.
85,9 → 89,9
`include "mc_defines.v"
 
module mc_dp( clk, rst, csc,
wb_cyc_i, mem_wb_ack_o, wb_data_i, wb_data_o,
wb_read_go,
mc_data_i, mc_dp_i, mc_data_o, mc_dp_o,
wb_cyc_i, wb_stb_i, wb_ack_o, mem_ack, wb_data_i, wb_data_o,
wb_read_go, wb_we_i,
mc_clk, mc_data_del, mc_dp_i, mc_data_o, mc_dp_o,
 
dv, pack_le0, pack_le1, pack_le2,
byte_en, par_err
97,12 → 101,16
input [31:0] csc;
 
input wb_cyc_i;
input mem_wb_ack_o;
input wb_stb_i;
input mem_ack;
input wb_ack_o;
input [31:0] wb_data_i;
output [31:0] wb_data_o;
input wb_read_go;
input wb_we_i;
 
input [31:0] mc_data_i;
input mc_clk;
input [35:0] mc_data_del;
input [3:0] mc_dp_i;
output [31:0] mc_data_o;
output [3:0] mc_dp_o;
120,7 → 128,6
reg [31:0] wb_data_o;
reg [31:0] mc_data_o;
wire [35:0] rd_fifo_out;
reg [35:0] mc_data_del;
wire rd_fifo_clr;
reg [3:0] mc_dp_o;
reg par_err_r;
143,18 → 150,14
// WB READ Data Path
//
 
always @(posedge clk)
if(mem_type == `MC_MEM_TYPE_SDRAM) wb_data_o <= #1 rd_fifo_out[31:0];
else
if(mem_type == `MC_MEM_TYPE_SRAM) wb_data_o <= #1 rd_fifo_out[31:0];
else wb_data_o <= #1 mc_data_d;
always @(mem_type or rd_fifo_out or mc_data_d)
if( (mem_type == `MC_MEM_TYPE_SDRAM) |
(mem_type == `MC_MEM_TYPE_SRAM) ) wb_data_o = rd_fifo_out[31:0];
else wb_data_o = mc_data_d;
 
always @(posedge clk)
mc_data_del <= #1 {mc_dp_i, mc_data_i};
assign rd_fifo_clr = !(rst | !wb_cyc_i | (wb_we_i & wb_stb_i) );
assign re = wb_ack_o & wb_read_go;
 
assign rd_fifo_clr = !rst & wb_cyc_i;
assign re = mem_wb_ack_o & wb_read_go;
 
mc_rd_fifo u0(
.clk( clk ),
.rst( rd_fifo_clr ),
170,7 → 173,7
//
 
always @(posedge clk)
if(mem_wb_ack_o | (mem_type != `MC_MEM_TYPE_SDRAM) )
if(wb_ack_o | (mem_type != `MC_MEM_TYPE_SDRAM) )
mc_data_o <= #1 wb_data_i;
 
////////////////////////////////////////////////////////////////////
179,21 → 182,21
//
 
always @(posedge clk)
if(pack_le0) byte0 <= #1 mc_data_i[7:0];
if(pack_le0) byte0 <= #1 mc_data_del[7:0];
 
always @(posedge clk)
if(pack_le1 & (bus_width == `MC_BW_8)) byte1 <= #1 mc_data_i[7:0];
if(pack_le1 & (bus_width == `MC_BW_8)) byte1 <= #1 mc_data_del[7:0];
else
if(pack_le0 & (bus_width == `MC_BW_16)) byte1 <= #1 mc_data_i[15:8];
if(pack_le0 & (bus_width == `MC_BW_16)) byte1 <= #1 mc_data_del[15:8];
 
always @(posedge clk)
if(pack_le2) byte2 <= #1 mc_data_i[7:0];
if(pack_le2) byte2 <= #1 mc_data_del[7:0];
 
always @(bus_width or mc_data_i or byte0 or byte1 or byte2)
if(bus_width == `MC_BW_8) mc_data_d = {mc_data_i[7:0], byte2, byte1, byte0};
always @(bus_width or mc_data_del or byte0 or byte1 or byte2)
if(bus_width == `MC_BW_8) mc_data_d = {mc_data_del[7:0], byte2, byte1, byte0};
else
if(bus_width == `MC_BW_16) mc_data_d = {mc_data_i[15:0], byte1, byte0};
else mc_data_d = mc_data_i;
if(bus_width == `MC_BW_16) mc_data_d = {mc_data_del[15:0], byte1, byte0};
else mc_data_d = mc_data_del[31:0];
 
////////////////////////////////////////////////////////////////////
//
201,7 → 204,7
//
 
always @(posedge clk)
if(mem_wb_ack_o | (mem_type != `MC_MEM_TYPE_SDRAM) )
if(wb_ack_o | (mem_type != `MC_MEM_TYPE_SDRAM) )
mc_dp_o <= #1 { ^wb_data_i[31:24], ^wb_data_i[23:16],
^wb_data_i[15:08], ^wb_data_i[07:00] };
 
210,10 → 213,7
// Parity Checking
//
 
assign par_err = par_err_r & mem_wb_ack_o;
 
always @(posedge clk)
par_err_r <= #1 pen & (
assign par_err = !wb_we_i & mem_ack & pen & (
(( ^rd_fifo_out[31:24] ^ rd_fifo_out[35] ) & byte_en[3] ) |
(( ^rd_fifo_out[23:16] ^ rd_fifo_out[34] ) & byte_en[2] ) |
(( ^rd_fifo_out[15:08] ^ rd_fifo_out[33] ) & byte_en[1] ) |
/trunk/rtl/verilog/mc_wb_if.v
38,10 → 38,10
 
// CVS Log
//
// $Id: mc_wb_if.v,v 1.3 2001-09-24 00:38:21 rudi Exp $
// $Id: mc_wb_if.v,v 1.4 2001-11-29 02:16:28 rudi Exp $
//
// $Date: 2001-09-24 00:38:21 $
// $Revision: 1.3 $
// $Date: 2001-11-29 02:16:28 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,10
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/09/24 00:38:21 rudi
//
// Changed Reset to be active high and async.
//
// Revision 1.2 2001/08/10 08:16:21 rudi
//
// - Changed IO names to be more clear.
63,7 → 67,8
// Revision 1.3 2001/06/12 15:19:49 rudi
//
//
// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
// Minor changes after running lint, and a small bug
// fix reading csr and ba_mask registers.
//
// Revision 1.2 2001/06/03 11:37:17 rudi
//
92,7 → 97,9
module mc_wb_if(clk, rst,
wb_addr_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_err, wb_ack_o,
wb_read_go, wb_write_go,
wb_first, wb_wait, mem_ack, wr_hold);
wb_first, wb_wait, mem_ack, wr_hold,
err, par_err, wp_err,
wb_data_o, mem_dout, rf_dout);
 
input clk, rst;
input [31:0] wb_addr_i;
99,7 → 106,7
input wb_cyc_i;
input wb_stb_i;
input wb_we_i;
input wb_err;
output wb_err;
output wb_ack_o;
output wb_read_go;
output wb_write_go;
107,6 → 114,9
output wb_wait;
input mem_ack;
output wr_hold;
input err, par_err, wp_err;
output [31:0] wb_data_o;
input [31:0] mem_dout, rf_dout;
 
////////////////////////////////////////////////////////////////////
//
124,6 → 134,9
wire rmw;
reg rmw_r;
reg rmw_en;
reg wb_ack_o;
reg wb_err;
reg [31:0] wb_data_o;
 
////////////////////////////////////////////////////////////////////
//
135,7 → 148,7
always @(posedge clk or posedge rst)
if(rst) rmw_en <= #1 1'b0;
else
if(mem_ack) rmw_en <= #1 1'b1;
if(wb_ack_o) rmw_en <= #1 1'b1;
else
if(!wb_cyc_i) rmw_en <= #1 1'b0;
 
144,14 → 157,14
 
assign rmw = rmw_r | (!wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en);
 
 
always @(posedge clk)
read_go_r1 <= #1 !rmw & wb_cyc_i & ((wb_stb_i & mem_sel & !wb_we_i) | read_go_r);
read_go_r1 <= #1 !rmw & wb_cyc_i &
((wb_stb_i & mem_sel & !wb_we_i) | read_go_r);
 
always @(posedge clk)
read_go_r <= #1 read_go_r1 & wb_cyc_i;
 
assign wb_read_go = !rmw & read_go_r1 & wb_cyc_i;
assign wb_read_go = !rmw & read_go_r1 & wb_cyc_i;
 
always @(posedge clk)
write_go_r1 <= #1 wb_cyc_i & ((wb_stb_i & mem_sel & wb_we_i) | write_go_r);
160,11 → 173,11
write_go_r <= #1 write_go_r1 & wb_cyc_i &
((wb_we_i & wb_stb_i) | !wb_stb_i);
 
assign wb_write_go = !rmw & write_go_r1 & wb_cyc_i &
assign wb_write_go = !rmw & write_go_r1 & wb_cyc_i &
((wb_we_i & wb_stb_i) | !wb_stb_i);
 
assign wb_first_set = mem_sel & wb_cyc_i & wb_stb_i & !(read_go_r | write_go_r);
assign wb_first = wb_first_set | (wb_first_r & !mem_ack & !wb_err);
assign wb_first = wb_first_set | (wb_first_r & !wb_ack_o & !wb_err);
 
always @(posedge clk or posedge rst)
if(rst) wb_first_r <= #1 1'b0;
171,7 → 184,7
else
if(wb_first_set) wb_first_r <= #1 1'b1;
else
if(mem_ack | wb_err) wb_first_r <= #1 1'b0;
if(wb_ack_o | wb_err) wb_first_r <= #1 1'b0;
 
always @(posedge clk)
if(wb_cyc_i & wb_stb_i) wr_hold <= #1 wb_we_i;
181,8 → 194,14
// WB Ack
//
 
assign wb_ack_o = mem_ack;
always @(posedge clk)
wb_ack_o <= #1 `MC_MEM_SEL ? mem_ack :
`MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o;
 
always @(posedge clk)
wb_err <= #1 wb_cyc_i & wb_stb_i & `MC_MEM_SEL &
(par_err | err | wp_err) & !wb_err;
 
////////////////////////////////////////////////////////////////////
//
// Memory Wait Logic
190,4 → 209,12
 
assign wb_wait = wb_cyc_i & !wb_stb_i & (wb_write_go | wb_read_go);
 
////////////////////////////////////////////////////////////////////
//
// WISHBONE Data Output
//
 
always @(posedge clk)
wb_data_o <= #1 `MC_MEM_SEL ? mem_dout : rf_dout;
 
endmodule
/trunk/rtl/verilog/mc_obct.v
38,10 → 38,10
 
// CVS Log
//
// $Id: mc_obct.v,v 1.2 2001-09-24 00:38:21 rudi Exp $
// $Id: mc_obct.v,v 1.3 2001-11-29 02:16:28 rudi Exp $
//
// $Date: 2001-09-24 00:38:21 $
// $Revision: 1.2 $
// $Date: 2001-11-29 02:16:28 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,10
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/09/24 00:38:21 rudi
//
// Changed Reset to be active high and async.
//
// Revision 1.1 2001/07/29 07:34:41 rudi
//
//
182,10 → 186,10
// Raw address checking
//
 
assign row0_same = b0_last_row == row_adr;
assign row1_same = b1_last_row == row_adr;
assign row2_same = b2_last_row == row_adr;
assign row3_same = b3_last_row == row_adr;
assign row0_same = (b0_last_row == row_adr);
assign row1_same = (b1_last_row == row_adr);
assign row2_same = (b2_last_row == row_adr);
assign row3_same = (b3_last_row == row_adr);
 
always @(bank_adr or row0_same or row1_same or row2_same or row3_same)
case(bank_adr) // synopsys full_case parallel_case
/trunk/rtl/verilog/mc_rf.v
37,10 → 37,10
 
// CVS Log
//
// $Id: mc_rf.v,v 1.4 2001-10-04 03:19:37 rudi Exp $
// $Id: mc_rf.v,v 1.5 2001-11-29 02:16:28 rudi Exp $
//
// $Date: 2001-10-04 03:19:37 $
// $Revision: 1.4 $
// $Date: 2001-11-29 02:16:28 $
// $Revision: 1.5 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.4 2001/10/04 03:19:37 rudi
//
// Fixed Register reads
// Tightened up timing for register rd/wr
//
// Revision 1.3 2001/09/24 00:38:21 rudi
//
// Changed Reset to be active high and async.
95,7 → 100,7
module mc_rf(clk, rst,
 
wb_data_i, rf_dout, wb_addr_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o, wp_err,
wb_stb_i, wb_ack_o, wp_err,
 
csc, tms, poc,
sp_csc, sp_tms, cs,
119,7 → 124,6
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
output wp_err;
 
// --------------------------------------
156,7 → 160,6
//
 
reg wb_ack_o;
reg ack_r;
 
reg [31:0] csc;
reg [31:0] tms;
165,7 → 168,7
reg [31:0] rf_dout;
reg [7:0] cs;
 
wire rf_we;
reg rf_we;
wire [31:0] csr;
reg [10:0] csr_r;
reg [7:0] csr_r2;
207,8 → 210,6
wire [7:0] spec_req_cs_d;
reg [7:0] spec_req_cs;
reg init_req, lmr_req;
wire [2:0] cs_sel;
wire [2:0] sp_cs_sel;
reg sreq_cs_le;
 
// Aliases
220,31 → 221,30
// WISHBONE Register Read logic
//
 
assign wb_err_o = 1'b0;
 
always @(posedge clk)
if(wb_cyc_i & wb_stb_i & `MC_REG_SEL & !wb_we_i)
always @(wb_addr_i or csr or poc or csc_mask or csc0 or tms0 or csc1 or
tms1 or csc2 or tms2 or csc3 or tms3 or csc4 or tms4 or csc5 or
tms5 or csc6 or tms6 or csc7 or tms7)
case(wb_addr_i[6:2]) // synopsys full_case parallel_case
5'd0: rf_dout <= #1 csr;
5'd1: rf_dout <= #1 poc;
5'd2: rf_dout <= #1 csc_mask;
5'h00: rf_dout <= #1 csr;
5'h01: rf_dout <= #1 poc;
5'h02: rf_dout <= #1 csc_mask;
 
5'd4: rf_dout <= #1 csc0;
5'd5: rf_dout <= #1 tms0;
5'd6: rf_dout <= #1 csc1;
5'd7: rf_dout <= #1 tms1;
5'd8: rf_dout <= #1 csc2;
5'd9: rf_dout <= #1 tms2;
5'd10: rf_dout <= #1 csc3;
5'd11: rf_dout <= #1 tms3;
5'd12: rf_dout <= #1 csc4;
5'd13: rf_dout <= #1 tms4;
5'd14: rf_dout <= #1 csc5;
5'd15: rf_dout <= #1 tms5;
5'd16: rf_dout <= #1 csc6;
5'd17: rf_dout <= #1 tms6;
5'd18: rf_dout <= #1 csc7;
5'd19: rf_dout <= #1 tms7;
5'h04: rf_dout <= #1 csc0;
5'h05: rf_dout <= #1 tms0;
5'h06: rf_dout <= #1 csc1;
5'h07: rf_dout <= #1 tms1;
5'h08: rf_dout <= #1 csc2;
5'h09: rf_dout <= #1 tms2;
5'h0a: rf_dout <= #1 csc3;
5'h0b: rf_dout <= #1 tms3;
5'h0c: rf_dout <= #1 csc4;
5'h0d: rf_dout <= #1 tms4;
5'h0e: rf_dout <= #1 csc5;
5'h0f: rf_dout <= #1 tms5;
5'h10: rf_dout <= #1 csc6;
5'h11: rf_dout <= #1 tms6;
5'h12: rf_dout <= #1 csc7;
5'h13: rf_dout <= #1 tms7;
endcase
 
////////////////////////////////////////////////////////////////////
252,18 → 252,24
// WISHBONE Register Write logic
//
 
assign rf_we = `MC_REG_SEL & wb_we_i & wb_cyc_i & wb_stb_i;
reg [6:0] wb_addr_r;
 
always @(posedge clk)
wb_addr_r <= #1 wb_addr_i[6:0];
 
always @(posedge clk)
rf_we <= #1 `MC_REG_SEL & wb_we_i & wb_cyc_i & wb_stb_i & !rf_we;
 
always @(posedge clk or posedge rst)
if(rst) csr_r2 <= #1 8'h0;
else
if(rf_we & (wb_addr_i[6:2] == 5'h0) )
if(rf_we & (wb_addr_r[6:2] == 5'h0) )
csr_r2 <= #1 wb_data_i[31:24];
 
always @(posedge clk or posedge rst)
if(rst) csr_r[10:1] <= #1 10'h0;
else
if(rf_we & (wb_addr_i[6:2] == 5'h0) )
if(rf_we & (wb_addr_r[6:2] == 5'h0) )
csr_r[10:1] <= #1 wb_data_i[10:1];
 
always @(posedge clk)
276,7 → 282,7
always @(posedge clk or posedge rst)
if(rst) csc_mask_r <= #1 11'h7ff;
else
if(rf_we & (wb_addr_i[6:2] == 5'h2) )
if(rf_we & (wb_addr_r[6:2] == 5'h2) )
csc_mask_r <= #1 wb_data_i[10:0];
 
always @(posedge clk)
288,10 → 294,6
//
 
always @(posedge clk)
ack_r <= #1 `MC_REG_SEL & wb_cyc_i & wb_stb_i & !ack_r & !wb_ack_o;
 
always @(posedge clk)
//wb_ack_o <= #1 (ack_r & wb_we_i) | (`MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_we_i & !wb_ack_o) ;
wb_ack_o <= #1 `MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o;
 
////////////////////////////////////////////////////////////////////
309,65 → 311,81
else
if(!wb_cyc_i) wp_err <= #1 1'b0;
 
assign cs_sel[0] = cs1 | cs3 | cs5 | cs7;
assign cs_sel[1] = cs2 | cs3 | cs6 | cs7;
assign cs_sel[2] = cs4 | cs5 | cs6 | cs7;
 
always @(posedge clk)
if(cs_le)
case(cs_sel) // synopsys full_case parallel_case
3'h0: csc <= #1 csc0;
3'h1: csc <= #1 csc1;
3'h2: csc <= #1 csc2;
3'h3: csc <= #1 csc3;
3'h4: csc <= #1 csc4;
3'h5: csc <= #1 csc5;
3'h6: csc <= #1 csc6;
3'h7: csc <= #1 csc7;
endcase
begin
if(cs0) csc <= #1 csc0;
else
if(cs1) csc <= #1 csc1;
else
if(cs2) csc <= #1 csc2;
else
if(cs3) csc <= #1 csc3;
else
if(cs4) csc <= #1 csc4;
else
if(cs5) csc <= #1 csc5;
else
if(cs6) csc <= #1 csc6;
else csc <= #1 csc7;
end
 
always @(posedge clk)
if(cs_le | rf_we)
case(cs_sel) // synopsys full_case parallel_case
3'h0: tms <= #1 tms0;
3'h1: tms <= #1 tms1;
3'h2: tms <= #1 tms2;
3'h3: tms <= #1 tms3;
3'h4: tms <= #1 tms4;
3'h5: tms <= #1 tms5;
3'h6: tms <= #1 tms6;
3'h7: tms <= #1 tms7;
endcase
begin
if(cs0) tms <= #1 tms0;
else
if(cs1) tms <= #1 tms1;
else
if(cs2) tms <= #1 tms2;
else
if(cs3) tms <= #1 tms3;
else
if(cs4) tms <= #1 tms4;
else
if(cs5) tms <= #1 tms5;
else
if(cs6) tms <= #1 tms6;
else tms <= #1 tms7;
end
 
assign sp_cs_sel[0] = spec_req_cs[1] | spec_req_cs[3] | spec_req_cs[5] | spec_req_cs[7];
assign sp_cs_sel[1] = spec_req_cs[2] | spec_req_cs[3] | spec_req_cs[6] | spec_req_cs[7];
assign sp_cs_sel[2] = spec_req_cs[4] | spec_req_cs[5] | spec_req_cs[6] | spec_req_cs[7];
 
always @(posedge clk)
if(cs_le)
case(sp_cs_sel) // synopsys full_case parallel_case
3'h0: sp_csc <= #1 csc0;
3'h1: sp_csc <= #1 csc1;
3'h2: sp_csc <= #1 csc2;
3'h3: sp_csc <= #1 csc3;
3'h4: sp_csc <= #1 csc4;
3'h5: sp_csc <= #1 csc5;
3'h6: sp_csc <= #1 csc6;
3'h7: sp_csc <= #1 csc7;
endcase
begin
if(spec_req_cs[0]) sp_csc <= #1 csc0;
else
if(spec_req_cs[1]) sp_csc <= #1 csc1;
else
if(spec_req_cs[2]) sp_csc <= #1 csc2;
else
if(spec_req_cs[3]) sp_csc <= #1 csc3;
else
if(spec_req_cs[4]) sp_csc <= #1 csc4;
else
if(spec_req_cs[5]) sp_csc <= #1 csc5;
else
if(spec_req_cs[6]) sp_csc <= #1 csc6;
else sp_csc <= #1 csc7;
end
 
always @(posedge clk)
if(cs_le | rf_we)
case(sp_cs_sel) // synopsys full_case parallel_case
3'h0: sp_tms <= #1 tms0;
3'h1: sp_tms <= #1 tms1;
3'h2: sp_tms <= #1 tms2;
3'h3: sp_tms <= #1 tms3;
3'h4: sp_tms <= #1 tms4;
3'h5: sp_tms <= #1 tms5;
3'h6: sp_tms <= #1 tms6;
3'h7: sp_tms <= #1 tms7;
endcase
begin
if(spec_req_cs[0]) sp_tms <= #1 tms0;
else
if(spec_req_cs[1]) sp_tms <= #1 tms1;
else
if(spec_req_cs[2]) sp_tms <= #1 tms2;
else
if(spec_req_cs[3]) sp_tms <= #1 tms3;
else
if(spec_req_cs[4]) sp_tms <= #1 tms4;
else
if(spec_req_cs[5]) sp_tms <= #1 tms5;
else
if(spec_req_cs[6]) sp_tms <= #1 tms6;
else sp_tms <= #1 tms7;
end
 
assign cs_need_rfr[0] = csc0[0] & (csc0[3:1] == `MC_MEM_TYPE_SDRAM);
assign cs_need_rfr[1] = csc1[0] & (csc1[3:1] == `MC_MEM_TYPE_SDRAM);
405,14 → 423,14
sreq_cs_le <= #1 (!init_req & !lmr_req) | lmr_ack_fe | init_ack_fe;
 
// Make sure only one is serviced at a time
assign spec_req_cs_d[0] = spec_req_cs_t[0];
assign spec_req_cs_d[1] = spec_req_cs_t[1] & !spec_req_cs_t[0];
assign spec_req_cs_d[2] = spec_req_cs_t[2] & !( |spec_req_cs_t[1:0] );
assign spec_req_cs_d[3] = spec_req_cs_t[3] & !( |spec_req_cs_t[2:0] );
assign spec_req_cs_d[4] = spec_req_cs_t[4] & !( |spec_req_cs_t[3:0] );
assign spec_req_cs_d[5] = spec_req_cs_t[5] & !( |spec_req_cs_t[4:0] );
assign spec_req_cs_d[6] = spec_req_cs_t[6] & !( |spec_req_cs_t[5:0] );
assign spec_req_cs_d[7] = spec_req_cs_t[7] & !( |spec_req_cs_t[6:0] );
assign spec_req_cs_d[0] = spec_req_cs_t[0];
assign spec_req_cs_d[1] = spec_req_cs_t[1] & !spec_req_cs_t[0];
assign spec_req_cs_d[2] = spec_req_cs_t[2] & !( |spec_req_cs_t[1:0] );
assign spec_req_cs_d[3] = spec_req_cs_t[3] & !( |spec_req_cs_t[2:0] );
assign spec_req_cs_d[4] = spec_req_cs_t[4] & !( |spec_req_cs_t[3:0] );
assign spec_req_cs_d[5] = spec_req_cs_t[5] & !( |spec_req_cs_t[4:0] );
assign spec_req_cs_d[6] = spec_req_cs_t[6] & !( |spec_req_cs_t[5:0] );
assign spec_req_cs_d[7] = spec_req_cs_t[7] & !( |spec_req_cs_t[6:0] );
 
// Request Tracking
always @(posedge clk)
424,11 → 442,11
lmr_req4 | lmr_req5 | lmr_req6 | lmr_req7;
 
assign spec_req_cs_t = !init_req ? // Load Mode Register Requests
{lmr_req7, lmr_req6, lmr_req5, lmr_req4,
lmr_req3, lmr_req2, lmr_req1, lmr_req0 } :
// Initialize SDRAM Requests
{init_req7, init_req6, init_req5, init_req4,
init_req3, init_req2, init_req1, init_req0 };
{lmr_req7, lmr_req6, lmr_req5, lmr_req4,
lmr_req3, lmr_req2, lmr_req1, lmr_req0 } :
// Initialize SDRAM Requests
{init_req7, init_req6, init_req5, init_req4,
init_req3, init_req2, init_req1, init_req0 };
 
// Ack distribution
assign lmr_ack0 = spec_req_cs[0] & lmr_ack_fe;
/trunk/rtl/verilog/mc_timing.v
37,10 → 37,10
 
// CVS Log
//
// $Id: mc_timing.v,v 1.4 2001-09-24 00:38:21 rudi Exp $
// $Id: mc_timing.v,v 1.5 2001-11-29 02:16:28 rudi Exp $
//
// $Date: 2001-09-24 00:38:21 $
// $Revision: 1.4 $
// $Date: 2001-11-29 02:16:28 $
// $Revision: 1.5 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,10
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.4 2001/09/24 00:38:21 rudi
//
// Changed Reset to be active high and async.
//
// Revision 1.3 2001/09/02 02:28:28 rudi
//
// Many fixes for minor bugs that showed up in gate level simulations.
103,7 → 107,7
// Wishbone Interface
wb_cyc_i, wb_stb_i, wb_we_i,
wb_read_go, wb_write_go, wb_first, wb_wait, mem_ack,
err,
err,
 
// Suspend/Resume Interface
susp_req, resume_req, suspended, susp_sel,
211,37 → 215,33
 
// Number of states: 66
parameter [65:0] // synopsys enum state
// 6666666555555555544444444443333333333222222222211111111110000000000
// 6543210987654321098765432109876543210987654321098765432109876543210
POR = 66'b000000000000000000000000000000000000000000000000000000000000000001,
IDLE = 66'b000000000000000000000000000000000000000000000000000000000000000010,
IDLE_T = 66'b000000000000000000000000000000000000000000000000000000000000000100,
IDLE_T2 = 66'b000000000000000000000000000000000000000000000000000000000000001000,
PRECHARGE = 66'b000000000000000000000000000000000000000000000000000000000000010000,
 
PRECHARGE_W = 66'b000000000000000000000000000000000000000000000000000000000000100000,
ACTIVATE = 66'b000000000000000000000000000000000000000000000000000000000001000000,
ACTIVATE_W = 66'b000000000000000000000000000000000000000000000000000000000010000000,
SD_RD_WR = 66'b000000000000000000000000000000000000000000000000000000000100000000,
SD_RD = 66'b000000000000000000000000000000000000000000000000000000001000000000,
 
SD_RD_W = 66'b000000000000000000000000000000000000000000000000000000010000000000,
SD_RD_LOOP = 66'b000000000000000000000000000000000000000000000000000000100000000000,
 
SD_RD_W2 = 66'b000000000000000000000000000000000000000000000000000001000000000000,
SD_WR = 66'b000000000000000000000000000000000000000000000000000010000000000000,
SD_WR_W = 66'b000000000000000000000000000000000000000000000000000100000000000000,
 
BT = 66'b000000000000000000000000000000000000000000000000001000000000000000,
BT_W = 66'b000000000000000000000000000000000000000000000000010000000000000000,
REFR = 66'b000000000000000000000000000000000000000000000000100000000000000000,
LMR0 = 66'b000000000000000000000000000000000000000000000001000000000000000000,
LMR1 = 66'b000000000000000000000000000000000000000000000010000000000000000000,
 
LMR2 = 66'b000000000000000000000000000000000000000000000100000000000000000000,
INIT0 = 66'b000000000000000000000000000000000000000000001000000000000000000000,
INIT = 66'b000000000000000000000000000000000000000000010000000000000000000000,
INIT_W = 66'b000000000000000000000000000000000000000000100000000000000000000000,
INIT_REFR1 = 66'b000000000000000000000000000000000000000001000000000000000000000000,
 
INIT_REFR1_W = 66'b000000000000000000000000000000000000000010000000000000000000000000,
INIT_LMR = 66'b000000000000000000000000000000000000000100000000000000000000000000,
SUSP1 = 66'b000000000000000000000000000000000000001000000000000000000000000000,
301,11 → 301,11
wire cs_a;
reg [3:0] cmd;
 
reg mem_ack;
wire mem_ack;
wire mem_ack_s;
reg mem_ack_d;
reg err_d;
reg err;
wire err;
reg cmd_a10;
reg lmr_ack;
reg row_sel;
337,13 → 337,14
reg burst_act_rd;
wire single_write;
 
reg cs_le_d;
reg cs_le;
reg cs_le_r;
 
reg susp_req_r;
reg resume_req_r;
reg suspended;
reg suspended_d;
//wire susp_sel;
reg susp_sel_set, susp_sel_clr, susp_sel_r;
 
reg [3:0] cmd_del;
396,7 → 397,17
reg mc_c_oe;
 
reg mc_le;
reg mem_ack_r;
 
reg rsts, rsts1;
reg no_wb_cycle;
 
wire bc_dec;
reg ap_en; // Auto Precharge Enable
reg cmd_a10_r;
reg wb_stb_first;
reg tmr_ld_tavav;
 
////////////////////////////////////////////////////////////////////
//
// Aliases
404,14 → 415,23
assign mem_type = csc[3:1];
assign bus_width = csc[5:4];
assign kro = csc[10];
assign single_write = tms[9];
assign single_write = tms[9] | (tms[2:0] == 3'h0);
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
reg cs_le_r1;
 
reg rsts, rsts1;
always @(posedge clk)
cs_le_r <= #1 cs_le_r1;
 
always @(posedge clk)
cs_le_r1 <= #1 cs_le;
 
always @(posedge clk)
cs_le <= #1 cs_le_d;
 
always @(posedge mc_clk)
rsts1 <= #1 rst;
 
450,12 → 470,13
assign cs_a = |cs;
 
// Memory to Wishbone Ack
always @(posedge clk)
mem_ack <= #1 (mem_ack_d | mem_ack_s) & (wb_read_go | wb_write_go);
assign mem_ack = (mem_ack_d | mem_ack_s) & (wb_read_go | wb_write_go);
 
always @(posedge clk)
err <= #1 err_d;
mem_ack_r <= #1 mem_ack;
 
assign err = err_d;
 
// SDRAM Command, either delayed (for writes) or straight through
always @(posedge clk)
cmd_r <= #1 cmd;
512,10 → 533,10
 
// Indicates when the row_same and bank_open lookups are done
always @(posedge clk)
lookup_ready1 <= #1 cs_le;
lookup_ready1 <= #1 cs_le & wb_stb_i;
 
always @(posedge clk)
lookup_ready2 <= #1 lookup_ready1;
lookup_ready2 <= #1 lookup_ready1 & wb_stb_i;
 
// Keep Track if it is a SDRAM write cycle
always @(posedge clk or posedge rst)
533,11 → 554,17
else
if(!wb_cyc_i) wb_cycle <= #1 1'b0;
 
// Thses two signals are used to signal that no wishbone cycle is in
// progress. Need to register them to avoid a very long combinatorial
// path ....
always @(posedge clk)
no_wb_cycle <= #1 !wb_read_go & !wb_write_go;
 
// Track ack's for read cycles
always @(posedge clk or posedge rst)
if(rst) ack_cnt <= #1 4'h0;
else
if(!wb_read_go & !wb_write_go) ack_cnt <= #1 4'h0;
if(no_wb_cycle) ack_cnt <= #1 4'h0;
else
if(dv & !mem_ack_s) ack_cnt <= #1 ack_cnt + 4'h1;
else
545,7 → 572,7
 
assign ack_cnt_is_0 = (ack_cnt==4'h0);
 
assign mem_ack_s = (ack_cnt != 4'h0) & !wb_wait & !mem_ack & wb_read_go & !(wb_we_i & wb_stb_i);
assign mem_ack_s = (ack_cnt != 4'h0) & !wb_wait & !mem_ack_r & wb_read_go & !(wb_we_i & wb_stb_i);
 
// Internal Cycle Tracker
always @(posedge clk)
578,15 → 605,18
//
// Timing Logic
//
wire [3:0] twrp;
wire twd_is_zero;
wire [31:0] tms_x;
 
// FIX_ME
// Hard wire worst case or make it programmable ???
assign tms_x = (rfr_ack | rfr_ack_r | susp_sel | !mc_c_oe) ? 32'hffff_ffff : tms;
 
always @(posedge clk)
if(tmr2_ld_tscsto) timer2 <= #1 tms_x[24:16];
else
if(tmr2_ld_tsrdv) timer2 <= #1 9'd2; // SSRAM RD->1st DATA VALID
if(tmr2_ld_tsrdv) timer2 <= #1 9'd4; // SSRAM RD->1st DATA VALID
else
if(tmr2_ld_twpw) timer2 <= #1 { 5'h0, tms_x[15:12]};
else
600,7 → 630,6
else
if(!timer2_is_zero) timer2 <= #1 timer2 - 9'b1;
 
wire twd_is_zero;
assign twd_is_zero = (tms_x[19:16] == 4'h0);
 
assign timer2_is_zero = (timer2 == 9'h0);
609,10 → 638,8
tmr2_done <= #1 timer2_is_zero & !tmr2_ld_trdv & !tmr2_ld_trdz &
!tmr2_ld_twpw & !tmr2_ld_twd & !tmr2_ld_twwd & !tmr2_ld_tscsto;
 
wire [3:0] twrp;
assign twrp = {2'h0,tms_x[16:15]} + tms_x[23:20];
 
assign twrp = tms_x[16:15] + tms_x[23:20];
 
// SDRAM Memories timing tracker
always @(posedge clk or posedge rst)
`ifdef MC_POR_DELAY
625,7 → 652,6
else
if(tmr_ld_trdv) timer <= #1 tms_x[7:0];
else
//if(tmr_ld_twr) timer <= #1 { 6'h0, tms_x[16:15]};
if(tmr_ld_twr) timer <= #1 { 4'h0, twrp};
else
if(tmr_ld_trp) timer <= #1 { 4'h0, tms_x[23:20]};
636,8 → 662,10
else
if(tmr_ld_trfc) timer <= #1 { 4'h0, tms_x[27:24]};
else
if(tmr_ld_txsr) timer <= #1 8'd7;
if(tmr_ld_tavav) timer <= #1 8'h3;
else
if(tmr_ld_txsr) timer <= #1 8'h7;
else
if(!timer_is_zero & !mc_le) timer <= #1 timer - 8'b1;
 
assign timer_is_zero = (timer == 8'h0);
657,23 → 685,29
// Burst Counter
always @(tms_x or page_size)
case(tms_x[2:0]) // synopsys full_case parallel_case
3'h0: burst_val = 11'd1;
3'h1: burst_val = 11'd2;
3'h2: burst_val = 11'd4;
3'h3: burst_val = 11'd8;
3'h0: burst_val = 11'h1;
3'h1: burst_val = 11'h2;
3'h2: burst_val = 11'h4;
3'h3: burst_val = 11'h8;
3'h7: burst_val = page_size;
endcase
 
assign bc_dec = wr_cycle ? mem_ack_d : dv;
 
always @(posedge clk)
if(burst_cnt_ld_4) burst_cnt <= #1 11'h4;
if(burst_cnt_ld_4) burst_cnt <= #1 11'h4; // for SSRAM only
else
if(burst_cnt_ld) burst_cnt <= #1 burst_val;
if(burst_cnt_ld) burst_cnt <= #1 burst_val;
else
if(wr_cycle ? mem_ack_d : dv) burst_cnt <= #1 burst_cnt - 11'h1;
if(bc_dec) burst_cnt <= #1 burst_cnt - 11'h1;
 
always @(posedge clk)
if(burst_cnt_ld) burst_fp <= #1 (tms_x[2:0] == 3'h7);
 
// Auto Precharge Enable
always @(posedge clk)
if(burst_cnt_ld) ap_en <= #1 (tms_x[2:0] == 3'h0) & !kro;
 
assign burst_act = |burst_cnt & ( |tms_x[2:0] );
 
always @(posedge clk)
682,12 → 716,27
always @(posedge clk)
dv_r <= #1 dv;
 
always @(posedge clk) // Auto Precharge Holding Register
cmd_a10_r <= #1 cmd_a10;
 
////////////////////////////////////////////////////////////////////
//
// Main State Machine
//
reg wb_write_go_r;
 
always @(posedge clk)
wb_write_go_r <= #1 wb_write_go;
 
 
always @(posedge clk or posedge rst)
if(rst) wb_stb_first <= #1 1'b0;
else
if(mem_ack) wb_stb_first <= #1 1'b0;
else
if(wb_first & wb_stb_i) wb_stb_first <= #1 1'b1;
 
always @(posedge clk or posedge rst)
`ifdef MC_POR_DELAY
if(rst) state <= #1 POR;
`else
695,16 → 744,16
`endif
else state <= #1 next_state;
 
always @(state or cs_a or
twd_is_zero or wb_stb_i or
wb_first or wb_read_go or wb_write_go or wb_wait or mem_ack or wb_we_i or
ack_cnt_is_0 or wb_wait_r or cnt or wb_cycle or
mem_type or kro or lookup_ready1 or lookup_ready2 or row_same or
always @(state or cs_a or cs_le or cs_le_r or
twd_is_zero or wb_stb_i or wb_write_go_r or
wb_first or wb_read_go or wb_write_go or wb_wait or mem_ack_r or wb_we_i or
ack_cnt_is_0 or wb_wait_r or cnt or wb_cycle or wr_cycle or
mem_type or kro or lookup_ready2 or row_same or cmd_a10_r or
bank_open or single_write or
cmd_asserted or tmr_done or tmr2_done or ir_cnt_done or cmd_asserted2 or
burst_act or burst_act_rd or burst_fp or cke_ or cke_r or cke_o_del or
rfr_req or lmr_req or init_req or rfr_ack_r or susp_req_r or resume_req_r or
mc_br or bw8 or bw16 or dv_r or mc_adv_r or mc_ack
mc_br or bw8 or bw16 or dv_r or mc_adv_r or mc_ack or wb_stb_first or ap_en
)
begin
next_state = state; // Default keep current state
711,7 → 760,7
cnt_next = 1'b0;
 
cmd = `MC_CMD_NOP;
cmd_a10 = ~kro;
cmd_a10 = ap_en;
oe_d = 1'b0;
data_oe_d = 1'b0;
cke_d = 1'b1;
734,6 → 783,7
tmr_ld_trdv = 1'b0;
tmr_ld_trdz = 1'b0;
tmr_ld_twr2 = 1'b0;
tmr_ld_tavav = 1'b0;
 
tmr2_ld_trdv = 1'b0;
tmr2_ld_trdz = 1'b0;
754,7 → 804,7
ir_cnt_ld = 1'b0;
 
row_sel = 1'b0;
cs_le = 1'b0;
cs_le_d = 1'b0;
wr_clr = 1'b0;
wr_set = 1'b0;
wb_cycle_set = 1'b0;
781,10 → 831,14
`endif
IDLE:
begin
cs_le = (wb_first & wb_stb_i) | lmr_req;
cs_le_d = wb_stb_first | lmr_req;
burst_cnt_ld = 1'b1;
wr_clr = 1'b1;
 
if(mem_type == `MC_MEM_TYPE_SCS) tmr2_ld_tscsto = 1'b1;
if(mem_type == `MC_MEM_TYPE_SRAM) tmr2_ld_tsrdv = 1'b1;
 
 
if(rfr_req)
begin
rfr_ack = 1'b1;
793,7 → 847,7
else
if(init_req)
begin
cs_le = 1'b1;
cs_le_d = 1'b1;
next_state = INIT0;
end
else
800,23 → 854,23
if(lmr_req & lookup_ready2)
begin
lmr_ack = 1'b1;
cs_le = 1'b1;
cs_le_d = 1'b1;
next_state = LMR0;
end
else
if(susp_req_r & !wb_cycle)
begin
cs_le = 1'b1;
cs_le_d = 1'b1;
susp_sel_set = 1'b1;
next_state = SUSP1;
end
else
if(cs_a & (wb_read_go | wb_write_go) & (lookup_ready1 | wb_cycle) )
if(cs_a & (wb_read_go | wb_write_go) & lookup_ready2)
begin
wb_cycle_set = 1'b1;
case(mem_type) // synopsys full_case parallel_case
`MC_MEM_TYPE_SDRAM: // SDRAM
if((lookup_ready2 | wb_cycle) & !wb_wait)
if((lookup_ready2) & !wb_wait)
begin
if(wb_write_go | (wb_we_i & wb_stb_i)) wr_set = 1'b1;
if(kro & bank_open & row_same) next_state = SD_RD_WR;
828,13 → 882,13
begin // Async Chip Select
if(!wb_wait)
begin
cs_le = 1'b1;
cs_le_d = 1'b1;
if(wb_write_go)
begin
data_oe_d = 1'b1;
next_state = ACS_WR;
data_oe_d = 1'b1;
next_state = ACS_WR;
end
else next_state = ACS_RD;
else next_state = ACS_RD;
end
end
`MC_MEM_TYPE_SCS:
841,8 → 895,7
begin // Sync Chip Select
if(!wb_wait)
begin
tmr2_ld_tscsto = 1'b1;
cs_le = 1'b1;
cs_le_d = 1'b1;
if(wb_write_go)
begin
cmd = `MC_CMD_XWR;
863,7 → 916,7
begin // SRAM
if(!wb_wait)
begin
cs_le = 1'b1;
cs_le_d = 1'b1;
if(wb_write_go)
begin
data_oe_d = 1'b1;
875,7 → 928,6
cmd = `MC_CMD_XRD;
oe_d = 1'b1;
mc_adsc = 1'b1;
tmr2_ld_tsrdv = 1'b1;
next_state = SRAM_RD;
end
end
885,19 → 937,28
else
if(mc_br)
begin
if(!cmd_asserted2) next_state = BG0;
if(!cmd_asserted2)
begin
next_state = BG0;
mc_c_oe_d = 1'b0;
end
end
end
 
IDLE_T:
begin
cs_le = (wb_first & wb_stb_i) | lmr_req;
cmd_a10 = cmd_a10_r; // Hold Auto Precharge 'til cycle finishes
if(tmr_done & wb_cycle & !wb_wait) cs_le_d = 1'b1;
if(tmr_done) next_state = IDLE;
end
 
IDLE_T2:
begin
if(tmr2_done) next_state = IDLE;
if(tmr2_done & (!wb_wait | !wb_cycle) )
begin
cs_le_d = 1'b1;
if(cs_le_r) next_state = IDLE;
end
end
 
/////////////////////////////////////////
962,7 → 1023,6
/////////////////////////////////////////
// SSRAM STATES ....
/////////////////////////////////////////
 
SRAM_RD:
begin
cmd = `MC_CMD_XRD;
1014,7 → 1074,7
else
if(!wb_wait)
begin
cs_le = 1'b1;
cs_le_d = 1'b1;
next_state = SRAM_RD;
end
end
1025,7 → 1085,7
next_state = IDLE;
end
 
SRAM_WR: // 80
SRAM_WR:
begin
cmd = `MC_CMD_XWR;
mc_adsc = 1'b1;
1042,12 → 1102,12
else
begin
data_oe_d = 1'b1;
mem_ack_d = ~mem_ack;
mem_ack_d = ~mem_ack_r;
end
end
end
 
SRAM_WR0: // 81
SRAM_WR0:
begin
if(wb_wait) next_state = SRAM_WR0;
else
1059,12 → 1119,8
else
begin
data_oe_d = 1'b1;
//mem_ack_d = ~mem_ack;
next_state = SRAM_WR;
end
 
//data_oe_d = 1'b1;
//if(!wb_wait) next_state = SRAM_WR;
end
 
/////////////////////////////////////////
1089,7 → 1145,6
else
if(bw16) next_state = ACS_RD_8_5;
else next_state = ACS_RD2A;
//else next_state = ACS_RD3;
end
end
 
1249,7 → 1304,7
end
end
 
ACTIVATE: // 4
ACTIVATE:
begin
if(!wb_wait_r)
begin
1271,8 → 1326,8
begin
if(wb_write_go)
begin
mem_ack_d = !mem_ack;
cmd_a10 = ~kro;
mem_ack_d = ~mem_ack_r;
cmd_a10 = ap_en | (single_write & !kro);
next_state = SD_WR;
end
else
1280,7 → 1335,7
end
end
 
SD_RD_WR: // 6
SD_RD_WR:
begin
if(wb_write_go | (wb_we_i & wb_stb_i)) wr_set = 1'b1;
 
1287,8 → 1342,8
if(wb_write_go & !wb_wait)
begin // Write
data_oe_d = 1'b1;
mem_ack_d = !mem_ack;
cmd_a10 = ~kro;
mem_ack_d = ~mem_ack_r;
cmd_a10 = ap_en | (single_write & !kro);
next_state = SD_WR;
end
else
1302,32 → 1357,35
end
end
 
SD_WR: // Write Command A
SD_WR: // Write Command
begin // Does the first single write
data_oe_d = 1'b1;
tmr_ld_twr = 1'b1;
cnt_next = ~cnt;
cmd = `MC_CMD_WR;
cmd_a10 = ~kro;
 
if(!cnt & wb_cycle & burst_act) cke_d = !wb_wait;
cmd_a10 = ap_en | (single_write & !kro);
 
if(!cnt & wb_cycle & burst_act) cke_d = ~wb_wait;
else cke_d = cke_r;
 
if(cmd_asserted)
begin
mem_ack_d = !mem_ack & wb_write_go & !wb_wait & wb_cycle & burst_act;
mem_ack_d = !mem_ack_r & wb_write_go & !wb_wait & wb_cycle & burst_act;
 
if(wb_cycle & !burst_act) next_state = IDLE_T;
else
if(wb_cycle) next_state = SD_WR_W;
if(wb_write_go) next_state = SD_WR_W;
else
if(burst_act & !single_write) next_state = BT;
else
if(!ap_en) next_state = BT_W;
else next_state = IDLE_T;
end
 
end
 
SD_WR_W: // B
SD_WR_W:
begin // Does additional Writes or Times them
tmr_ld_twr = 1'b1;
cnt_next = ~cnt;
1335,46 → 1393,48
if(single_write & wb_cycle)
begin
cmd = `MC_CMD_WR;
if(burst_act) cmd_a10 = 1'b0;
else cmd_a10 = ~kro;
end
cmd_a10 = ap_en | (single_write & !kro);
 
data_oe_d = 1'b1;
mem_ack_d = !mem_ack & wb_write_go & !wb_wait & wb_cycle & burst_act;
mem_ack_d = !mem_ack_r & wb_write_go & !wb_wait & wr_cycle & burst_act;
 
if(!cnt) cke_d = ~wb_wait;
else cke_d = cke_r;
if(cke_r)
 
if( (single_write & cke_r) | (!single_write & !cnt & !wb_wait) | (!single_write & cnt & cke_r) )
begin
if(single_write & !wb_cycle) next_state = IDLE_T;
else
if(burst_act & !single_write & !wb_write_go )
next_state = BT;
if(burst_act & !single_write & !wb_write_go_r)
begin
cmd = `MC_CMD_BT;
next_state = BT;
end
else
if(!burst_act & !ap_en) next_state = BT_W;
else
if(!burst_act) next_state = IDLE_T;
else
if(!wb_write_go & wb_read_go) next_state = IDLE_T; // Added for WMR
if(!wb_write_go_r & wb_read_go) next_state = IDLE_T; // Added for WMR
end
end
 
SD_RD: // Read Command 7
SD_RD: // Read Command
begin
cmd = `MC_CMD_RD;
if(burst_fp) cmd_a10 = 1'b0;
else cmd_a10 = ~kro;
cmd_a10 = ap_en;
tmr_ld_tcl = 1'b1;
if(cmd_asserted) next_state = SD_RD_W;
end
 
SD_RD_W: // 8
SD_RD_W:
begin
if(tmr_done) next_state = SD_RD_LOOP;
end
 
SD_RD_LOOP: // 9
SD_RD_LOOP:
begin
 
cnt_next = ~cnt;
 
if(cnt & !(burst_act & !wb_cycle) & burst_act ) cke_rd = !wb_wait;
1389,14 → 1449,17
if(!burst_act) next_state = SD_RD_W2;
end
 
SD_RD_W2: //32
SD_RD_W2:
begin
if(wb_cycle & wb_write_go) next_state = IDLE;
else
if(!wb_cycle | ack_cnt_is_0) next_state = IDLE;
if(wb_write_go | ack_cnt_is_0)
begin
if(!ap_en & !kro) next_state = BT_W;
else
if(!wb_wait & !mem_ack_r) next_state = IDLE_T;
end
end
 
BT: // Burst Terminate C
BT:
begin
cmd = `MC_CMD_BT;
tmr_ld_trp = 1'b1;
1403,25 → 1466,29
if(cmd_asserted) next_state = BT_W;
end
 
BT_W: // D
BT_W:
begin
if(kro) next_state = IDLE;
cmd_a10 = cmd_a10_r; // Hold Auto Precharge 'til cycle finishes
 
if(kro & tmr_done)
begin
if(kro & !wb_wait & (wb_read_go | wb_write_go) ) cs_le_d = 1'b1;
next_state = IDLE;
end
else
if(tmr_done & (!burst_fp | kro)) next_state = IDLE;
else
if(tmr_done & burst_fp & !kro) // Must PRECHARGE Full Page Bursts
if(!kro & tmr_done) // Must do a PRECHARGE after Burst Terminate
begin
bank_clr = 1'b1;
cmd = `MC_CMD_PC;
cmd_a10 = `MC_SINGLE_BANK;
tmr_ld_trp = 1'b1;
if(cmd_asserted) next_state = IDLE_T;
if(cmd_asserted) next_state = IDLE_T;
end
end
 
REFR: // Refresh Cycle
begin
cs_le = 1'b1;
cs_le_d = 1'b1;
cmd = `MC_CMD_ARFR;
tmr_ld_trfc = 1'b1;
rfr_ack = 1'b1;
1459,7 → 1526,7
 
INIT0:
begin
cs_le = 1'b1;
cs_le_d = 1'b1;
next_state = INIT;
end
 
1492,7 → 1559,7
end
end
 
INIT_REFR1_W: // 21
INIT_REFR1_W:
begin
init_ack = 1'b1;
if(tmr_done)
1523,18 → 1590,19
BG1:
begin // Bus Grant
mc_bg = 1'b1;
cs_le = 1'b1;
cs_le_d = 1'b1;
mc_c_oe_d = 1'b0;
next_state = BG2;
end
BG2:
begin // Bus Grant
cs_le_d = 1'b1;
mc_bg = !wb_read_go & !wb_write_go &
!rfr_req & !init_req & !lmr_req &
!susp_req_r;
tmr_ld_tcl = 1'b1;
tmr_ld_tavav = 1'b1;
mc_c_oe_d = mc_br;
if(!mc_br) next_state = IDLE_T;
else mc_c_oe_d = 1'b0;
end
 
/////////////////////////////////////////
/trunk/rtl/verilog/mc_rd_fifo.v
38,10 → 38,10
 
// CVS Log
//
// $Id: mc_rd_fifo.v,v 1.1 2001-07-29 07:34:41 rudi Exp $
// $Id: mc_rd_fifo.v,v 1.2 2001-11-29 02:16:28 rudi Exp $
//
// $Date: 2001-07-29 07:34:41 $
// $Revision: 1.1 $
// $Date: 2001-11-29 02:16:28 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/07/29 07:34:41 rudi
//
//
// 1) Changed Directory Structure
// 2) Fixed several minor bugs
//
// Revision 1.1.1.1 2001/05/13 09:39:44 rudi
// Created Directory Structure
//
92,8 → 98,6
if(we & wr_adr[3]) r3 <= #1 din;
 
always @(rd_adr or r0 or r1 or r2 or r3 or re or we or din)
if(re & we) dout = din;
else
case(rd_adr) // synopsys full_case parallel_case
4'h1: dout = r0;
4'h2: dout = r1;
/trunk/rtl/verilog/mc_adr_sel.v
37,10 → 37,10
 
// CVS Log
//
// $Id: mc_adr_sel.v,v 1.2 2001-08-10 08:16:21 rudi Exp $
// $Id: mc_adr_sel.v,v 1.3 2001-11-29 02:16:28 rudi Exp $
//
// $Date: 2001-08-10 08:16:21 $
// $Revision: 1.2 $
// $Date: 2001-11-29 02:16:28 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/08/10 08:16:21 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Removed "Refresh Early" configuration
//
// Revision 1.1 2001/07/29 07:34:41 rudi
//
//
67,7 → 73,7
 
`include "mc_defines.v"
 
module mc_adr_sel(clk, csc, tms, wb_ack_o, wb_stb_i, wb_addr_i,
module mc_adr_sel(clk, csc, tms, wb_ack_o, wb_stb_i, wb_addr_i, wb_we_i,
wb_write_go, wr_hold, cas_,
mc_addr, row_adr, bank_adr, rfr_ack,
cs_le, cmd_a10, row_sel, lmr_sel, next_adr, wr_cycle,
78,6 → 84,7
input [31:0] tms;
input wb_ack_o, wb_stb_i;
input [31:0] wb_addr_i;
input wb_we_i;
input wb_write_go;
input wr_hold;
input cas_;
139,7 → 146,6
// Async Devices Address Latch & Counter
//
 
//assign asc_addr_pl1 = asc_addr + 1;
mc_incn_r #(24) u0( .clk( clk ),
.inc_in( acs_addr ),
.inc_out( acs_addr_pl1 ) );
148,10 → 154,7
if(wb_stb_i) sram_addr <= #1 wb_addr_i[25:2];
 
always @(posedge clk)
// *** Use same address for write and read ***
//if(wb_write_go) acs_addr <= #1 wb_addr_i[25:2];
//else
if(cs_le)
if(cs_le | wb_we_i)
case(bus_width) // synopsys full_case parallel_case
`MC_BW_8: acs_addr <= #1 wb_addr_i[23:0];
`MC_BW_16: acs_addr <= #1 wb_addr_i[24:1];

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