URL
https://opencores.org/ocsvn/ppx16/ppx16/trunk
Subversion Repositories ppx16
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 15 to Rev 16
- ↔ Reverse comparison
Rev 15 → Rev 16
/trunk/syn/xilinx/bin/p16c55.tcl
19,20 → 19,21
load_library xis2 |
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read -technology xis2 { |
../../../rtl/vhdl/AX_Pack.vhd |
../../../rtl/vhdl/AX_Reg.vhd |
../../../rtl/vhdl/AX_ALU.vhd |
../../../rtl/vhdl/AX_PCS.vhd |
../../../rtl/vhdl/AX8.vhd |
../../../rtl/vhdl/AX_Port.vhd |
../../../rtl/vhdl/AX_TC8.vhd |
../src/ROM1200_Echo_leo.vhd |
../../../rtl/vhdl/A90S1200.vhd |
../../../rtl/vhdl/PPX_Pack.vhd |
../../../rtl/vhdl/PPX_ALU.vhd |
../../../rtl/vhdl/PPX_Ctrl.vhd |
../../../rtl/vhdl/PPX_PCS.vhd |
../../../rtl/vhdl/PPX16.vhd |
../../../rtl/vhdl/PPX_RAM.vhd |
../../../rtl/vhdl/PPX_Port.vhd |
../../../rtl/vhdl/PPX_TMR.vhd |
../src/ROM55_Test_leo.vhd |
../../../rtl/vhdl/P16C55.vhd |
} |
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pre_optimize |
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optimize -hierarchy=auto |
optimize -hierarchy=auto -delay -pass 1 -pass 2 -pass 3 -pass 4 |
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optimize_timing |
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40,4 → 41,4
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report_delay |
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write a90s1200.edf |
write p16c55_leo.edf |
/trunk/syn/xilinx/bin/p16c55_leo.pin
0,0 → 1,7
#NET "clk" TNM_NET = "clk"; |
#TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50%; |
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NET "Clk" LOC = "P77"; |
NET "Reset_n" LOC = "P133"; |
NET "Port_A(0)" LOC = "P96"; |
NET "Port_A(1)" LOC = "P98"; |
/trunk/syn/xilinx/bin/p16c55.pin
1,2 → 1,7
#NET "clock" LOC = "P77"; |
#NET "rst_n" LOC = "P133"; |
#NET "clk" TNM_NET = "clk"; |
#TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50%; |
|
NET "clk" LOC = "P77"; |
NET "reset_n" LOC = "P133"; |
NET "port_a<0>" LOC = "P96"; |
NET "port_a<1>" LOC = "P98"; |
/trunk/syn/xilinx/bin/p16f84.tcl
33,7 → 33,7
|
pre_optimize |
|
optimize -hierarchy=auto |
optimize -hierarchy=auto -delay -pass 1 -pass 2 -pass 3 -pass 4 |
|
optimize_timing |
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41,4 → 41,4
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report_delay |
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write p16f84.edf |
write p16f84_leo.edf |
/trunk/syn/xilinx/bin/p16f84_leo.pin
0,0 → 1,13
NET "clk" TNM_NET = "clk"; |
TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50%; |
|
NET "Clk" LOC = "P77"; |
NET "Reset_n" LOC = "P133"; |
NET "Port_B(0)" LOC = "P29"; |
NET "Port_B(1)" LOC = "P31"; |
NET "Port_B(2)" LOC = "P34"; |
NET "Port_B(3)" LOC = "P36"; |
NET "Port_B(4)" LOC = "P41"; |
NET "Port_B(5)" LOC = "P43"; |
NET "Port_B(6)" LOC = "P45"; |
NET "Port_B(7)" LOC = "P47"; |
/trunk/syn/xilinx/bin/p16f84.pin
1,5 → 1,13
NET "clk" TNM_NET = "clk"; |
TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50%; |
|
#NET "clock" LOC = "P77"; |
#NET "rst_n" LOC = "P133"; |
NET "clk" LOC = "P77"; |
NET "reset_n" LOC = "P133"; |
NET "port_b<0>" LOC = "P29"; |
NET "port_b<1>" LOC = "P31"; |
NET "port_b<2>" LOC = "P34"; |
NET "port_b<3>" LOC = "P36"; |
NET "port_b<4>" LOC = "P41"; |
NET "port_b<5>" LOC = "P43"; |
NET "port_b<6>" LOC = "P45"; |
NET "port_b<7>" LOC = "P47"; |