URL
https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk
Subversion Repositories versatile_fifo
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- from Rev 15 to Rev 16
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Rev 15 → Rev 16
/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram.v
25,8 → 25,8
`endif |
); |
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parameter DATA_WIDTH = 8; |
parameter ADDR_WIDTH = 9; |
parameter DATA_WIDTH = `DATA_WIDTH; |
parameter ADDR_WIDTH = `ADDR_WIDTH; |
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input [(DATA_WIDTH-1):0] d_a; |
input [(ADDR_WIDTH-1):0] adr_a; |
51,7 → 51,7
`endif |
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// Declare the RAM variable |
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/; |
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/; |
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`ifdef DC |
always @ (posedge clk_a) |