OpenCores
URL https://opencores.org/ocsvn/alternascope/alternascope/trunk

Subversion Repositories alternascope

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 17 to Rev 18
    ↔ Reverse comparison
  •

Rev 17 → Rev 18

/trunk/d_TopLevel.v
109,6 → 109,8
wire[7:0] mask_charMap;
reg[7:0] mask_charMap_buf;
 
wire[1:0] sm_trig;
 
always @ (posedge CLK_50MHZ) begin
if(R_BUTTON) begin
data_charRamRead_buf <= data_charRamRead_buf;
126,8 → 128,21
);
 
wire[7:0] leds;
assign leds = mask_charMap_buf;
assign leds[1:0] = sm_trig;
assign leds[7:2] = 6'b0;
 
/*- - - - - - - - - - - - - */
/* Fake ADC data */
/*- - - - - - - - - - - - - */
reg[7:0] fake_adcData;
always @ (posedge CLK_VGA or posedge MASTER_RST) begin
if(MASTER_RST)
fake_adcData <= 8'd0;
else
fake_adcData <= fake_adcData+1;
end
 
 
//==================================================================//
// SUBROUTINES //
//==================================================================//
182,9 → 197,11
.CLK180_64MHZ(CLK180_64MHZ),
.TIME_BASE(TIME_BASE),
.RAM_ADDR(ADC_RAM_ADDR), .RAM_DATA(ADC_RAM_DATA), .RAM_CLK(ADC_RAM_CLK),
.ADC_DATA(ADC_DATA), .ADC_CLK(ADC_CLK),
// .ADC_DATA(ADC_DATA), .ADC_CLK(ADC_CLK),
.ADC_DATA(fake_adcData), .ADC_CLK(ADC_CLK),
.TRIG_ADDR(TRIG_ADDR), .VGA_WRITE_DONE(VGA_WRITE_DONE),
.TRIGGER_LEVEL(TRIGGER_LEVEL[8:0])
.TRIGGER_LEVEL(TRIGGER_LEVEL[8:0]),
.sm_trig(sm_trig)
);
 
 
199,8 → 216,7
CharacterDisplay charTest(
.MASTER_CLK(CLK_50MHZ), .MASTER_RST(MASTER_RST),
.CLK_VGA(CLK_VGA), .HCNT(HCNT), .VCNT(VCNT),
.RGB_OUT(RGB_CHAR),
.data_charMap(mask_charMap), .data_charRamRead(data_charRamRead)
.RGB_OUT(RGB_CHAR)
);
 
 
/trunk/AdcDriver/d_Driver_ADC.v
66,7 → 66,7
wire[5:0] TIME_BASE;
wire[7:0] ADC_DATA;
reg ADC_CLK;
wire [7:0] DATA_OUT;
reg [7:0] DATA_OUT;
 
//----------------------//
// VARIABLES //
179,7 → 179,6
//------------------------------------------------------------------//
// ADC DATA READING //
//------------------------------------------------------------------//
/*
always @ (negedge ADC_CLK or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1) begin
DATA_OUT <= 8'b0;
187,9 → 186,8
DATA_OUT <= ADC_DATA;
end
end
*/
 
assign DATA_OUT = ADC_DATA;
//assign DATA_OUT = ADC_DATA;
 
endmodule
 
/trunk/AdcDriver/d_Driver_RamBuffer.v
18,7 → 18,8
ADC_DATA, ADC_CLK,
TRIG_ADDR,
VGA_WRITE_DONE,
TRIGGER_LEVEL
TRIGGER_LEVEL,
sm_trig
);
//==================================================================//
53,6 → 54,9
input VGA_WRITE_DONE;
input[8:0] TRIGGER_LEVEL;
 
output[1:0] sm_trig;
 
 
//----------------------//
// WIRES / NODES //
//----------------------//
76,7 → 80,6
//==================================================================//
// 'SUB-ROUTINES' //
//==================================================================//
 
//------------------------------------------------------------------//
// Instanstiate the ADC //
//------------------------------------------------------------------//
98,7 → 101,7
// Access A: 8bit + 1parity (ADC_Write) //
// Access B: 8bit + 1parity (Read) //
//------------------------------------------------------------------//
reg[10:0] ADDRA;
reg[10:0] ADDRA;
wire VCC, GND;
assign VCC = 1'b1;
assign GND = 1'b0;
132,7 → 135,7
sm_trig <= ss_fill_mem_half;
else if(sm_trig == ss_fill_mem_half && mem_half_full == 1'b1)
sm_trig <= ss_write_buffer;
else if(sm_trig == ss_write_buffer && trigger_detected == 1'b0 && VGA_WRITE_DONE == 1'b1)
else if(sm_trig == ss_write_buffer && /*trigger_detected == 1'b0 &&*/ VGA_WRITE_DONE == 1'b1)
sm_trig <= ss_wait_for_trig;
else if(sm_trig == ss_invalid)
sm_trig <= ss_wait_for_trig;
150,11 → 153,11
ADDRA <= ADDRA + 1;
else
ADDRA <= ADDRA;
// ADDRA <= ADDRA + 1;
end
 
/* LATCHING THE TRIGGER */
always @ (ADC_DATA) begin
// if(ADC_DATA >= P_trigger_level)
if(ADC_DATA >= TRIGGER_LEVEL)
trigger_detected = 1'b1;
else
168,7 → 171,8
else if(sm_trig == ss_fill_mem_half)
cnt_1024bytes <= cnt_1024bytes + 1;
else
cnt_1024bytes <= cnt_1024bytes;
cnt_1024bytes <= 10'b0;
// cnt_1024bytes <= cnt_1024bytes;
end
 
always @ (cnt_1024bytes) begin
/trunk/VGA/d_VGAdriver.v
37,7 → 37,7
VGA_RAM_OE, VGA_RAM_WE, VGA_RAM_CS,
VGA_RAM_ACCESS_OK,
H_SYNC, V_SYNC, VGA_OUTPUT,
XCOORD, YCOORD, ram_vshift,
XCOORD, YCOORD,
TRIGGER_LEVEL,
SHOW_LEVELS,
HCNT, VCNT,
176,10 → 176,6
end else if(SHOW_LEVELS == 1'b1 && vcnt == (TRIGGER_LEVEL-1'b1) && hcnt == 10'd557) begin
VGA_OUTPUT = P_yellow;
//------------------------------------------------------------------------------//
// MOVE THE WAVEFORM TO THE 'TOP' //
end else if(vga_out != 0) begin
VGA_OUTPUT = vga_out;
//------------------------------------------------------------------------------//
// TOP, BOTTOM, LEFT AND RIGHT GRID LINES //
end else if(vcnt == 10'd0 || vcnt == 10'd399 || vcnt == 10'd441) begin
VGA_OUTPUT = P_cyan;
186,6 → 182,14
end else if(hcnt == 10'd0 || hcnt == 10'd639) begin
VGA_OUTPUT = P_cyan;
//------------------------------------------------------------------------------//
// CHARACTER DISPLAY
end else if(vcnt <= 10'd520 && vcnt >= 10'd441) begin
VGA_OUTPUT = RGB_CHAR;
//------------------------------------------------------------------------------//
// THE WAVEFORM //
end else if(vga_out != 0) begin
VGA_OUTPUT = vga_out;
//------------------------------------------------------------------------------//
// MIDDLE GRID LINES (dashed at 8pxls) //
end else if(vcnt == 10'd199 && hcnt[3] == 1'b1) begin
VGA_OUTPUT = P_cyan;
200,10 → 204,6
end else if(((hcnt[5:0] == 6'b111111) && (vcnt <= 10'd399)) && (vcnt[2] == 1'b1)) begin
VGA_OUTPUT = P_cyan;
//------------------------------------------------------------------------------//
// CHARACTER DISPLAY
end else if(vcnt <= 10'd520 && vcnt >= 10'd441) begin
VGA_OUTPUT = RGB_CHAR;
//------------------------------------------------------------------------------//
// OTHERWISE... //
end else
VGA_OUTPUT = P_black;
228,7 → 228,7
ram_vshift <= 16'h8000;
end else if(vcnt > 10'd399) begin
ram_vshift <= 16'h8000;
end else if((vcnt <= 10'd399) && (hcnt == 10'd655)) begin
end else if(/*(vcnt <= 10'd399) && */(hcnt == 10'd640)) begin
if(ram_vshift == 16'h0001)
ram_vshift <= 16'h8000;
else
239,13 → 239,13
 
always @ (posedge CLK_25MHZ or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1) begin
ram_vcnt <= 5'd0;
end else if(vcnt < 10'd30) begin
ram_vcnt <= 5'd0;
end else if((vcnt >= 10'd30) && (hcnt == 10'd655) && (ram_vshift == 16'h0001)) begin
ram_vcnt <= 5'd24;//5'b0
end else if(vcnt > 10'd399) begin
ram_vcnt <= 5'd24;
end else if(/*(vcnt >= 10'd30) &&*/ (hcnt == 10'd640) && (ram_vshift == 16'h0001)) begin
if(ram_vcnt == 5'd0)
ram_vcnt <= 5'd24;
else
else
ram_vcnt <= ram_vcnt - 1'b1;
end else begin
ram_vcnt <= ram_vcnt;
256,6 → 256,7
 
always @ (hcnt or ram_vcnt) begin
VGA_RAM_ADDR = ram_vcnt + (hcnt * 7'd25);
// VGA_RAM_ADDR = vcnt * hcnt;
end
 
 
278,7 → 279,7
// ALL CLEAR? //
//------------------------------------------------------------------//
always @ (vcnt) begin
if((vcnt >= 10'd400) && (vcnt <= 10'd440))
if(vcnt > 10'd399)
VGA_RAM_ACCESS_OK = 1'b1;
else
VGA_RAM_ACCESS_OK = 1'b0;
/trunk/VGA/CharDecode/d_CharDecode.v
1,5 → 1,5
//==================================================================//
// File: d_xxxxxxxxxxxx //
// File: d_CharDecodeSmall.v //
// Version: 0.0.0.1 //
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -//
// Copyright (C) Stephen Pickett //
24,6 → 24,7
//------------------------------------------------------------------//
// Revisions: //
// Ver 0.0.0.1 Jun 17, 2005 Initial Development Release //
// Based on "d_CharDecode.v" //
// //
//==================================================================//
 
30,8 → 31,7
module CharacterDisplay(
MASTER_CLK, MASTER_RST,
CLK_VGA, HCNT, VCNT,
RGB_OUT,
data_charRamRead, data_charMap
RGB_OUT
);
//==================================================================//
57,10 → 57,7
input[9:0] VCNT; // Vertical Sync Counter
output[2:0] RGB_OUT; // The RGB data
 
output[7:0] data_charRamRead;
output[7:0] data_charMap;
 
 
//----------------------//
// WIRES / NODES //
//----------------------//
74,9 → 71,9
// REGISTERS //
//----------------------//
reg[3:0] cnt_charPxls;
reg[5:0] cnt_Hchar;
reg[6:0] cnt_Hchar;
reg[10:0] cnt_Vchar;
wire charRow1, charRow2, charRow3, charRow4;
wire charRow1, charRow2, charRow3, charRow4, charRow5, charRow6, charRow7, charRow8;
 
wire[10:0] addr_charRamRead;
wire[7:0] data_charRamRead;
114,42 → 111,51
 
always @ (posedge CLK_VGA or posedge MASTER_RST) begin
if(MASTER_RST) begin
cnt_charPxls <= 4'd10;
end else if(HCNT >= 10'd6) begin //7
cnt_charPxls <= 4'd5;
end else if(HCNT >= 10'd1) begin //6
if(cnt_charPxls == 4'd0)
cnt_charPxls <= 4'd10;
cnt_charPxls <= 4'd5;
else
cnt_charPxls <= cnt_charPxls-1;
end else begin
cnt_charPxls <= 4'd10;
cnt_charPxls <= 4'd5;
end
end
 
always @ (posedge CLK_VGA or posedge MASTER_RST) begin
if(MASTER_RST) begin
cnt_Hchar <= 6'd0;
end else if(HCNT >= 10'd6 && cnt_charPxls == 4'd0) begin
if(cnt_Hchar == 6'd56)
cnt_Hchar <= 6'd0;
cnt_Hchar <= 7'd0;
end else if(HCNT >= 10'd1 && cnt_charPxls == 4'd0) begin
if(cnt_Hchar == 7'd105)
cnt_Hchar <= 7'd0;
else
cnt_Hchar <= cnt_Hchar+1;
end else if(HCNT < 10'd6) begin
cnt_Hchar <= 6'd0;
end else if(HCNT < 10'd1) begin
cnt_Hchar <= 7'd0;
end else begin
cnt_Hchar <= cnt_Hchar;
end
end
 
assign charRow1 = ((VCNT <= 512) && (VCNT >= 498)); // one more
assign charRow2 = ((VCNT <= 494) && (VCNT >= 480));
assign charRow3 = ((VCNT <= 476) && (VCNT >= 462));
assign charRow4 = ((VCNT <= 458) && (VCNT >= 444));
assign charRow1 = ((VCNT <= 10'd512) && (VCNT >= 10'd506));
assign charRow2 = ((VCNT <= 10'd503) && (VCNT >= 10'd497));
assign charRow3 = ((VCNT <= 10'd494) && (VCNT >= 10'd488));
assign charRow4 = ((VCNT <= 10'd485) && (VCNT >= 10'd479));
assign charRow5 = ((VCNT <= 10'd476) && (VCNT >= 10'd470));
assign charRow6 = ((VCNT <= 10'd467) && (VCNT >= 10'd461));
assign charRow7 = ((VCNT <= 10'd458) && (VCNT >= 10'd452));
assign charRow8 = ((VCNT <= 10'd449) && (VCNT >= 10'd443));
 
always @ (charRow1 or charRow2 or charRow3 or charRow4) begin
always @ (charRow1 or charRow2 or charRow3 or charRow4 or charRow5 or charRow6 or charRow7 or charRow8) begin
if(charRow1) cnt_Vchar = 11'd0;
else if(charRow2) cnt_Vchar = 11'd57;
else if(charRow3) cnt_Vchar = 11'd114;
else cnt_Vchar = 11'd174;
else if(charRow2) cnt_Vchar = 11'd106;
else if(charRow3) cnt_Vchar = 11'd212;
else if(charRow4) cnt_Vchar = 11'd318;
else if(charRow5) cnt_Vchar = 11'd424;
else if(charRow6) cnt_Vchar = 11'd530;
else if(charRow7) cnt_Vchar = 11'd636;
else if(charRow8) cnt_Vchar = 11'd742;
else cnt_Vchar = 11'd0;
end
 
assign addr_charRamRead = cnt_Vchar + cnt_Hchar;
156,8 → 162,6
 
 
 
 
 
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - //
// DECODE the Character Map via HCNT and VCNT and CHAR_DATA //
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - //
165,7 → 169,7
if(MASTER_RST) begin
mask_charMap <= 8'd0;
end else if(VCNT <= 10'd512) begin
if(HCNT == 10'd0 && VCNT[0] == 1'b1) begin //1B0
if(HCNT == 10'd0) begin
if(mask_charMap == 8'd0)
mask_charMap <= 8'b10000000;
else
179,7 → 183,7
 
 
 
assign addr_charMap = (data_charRamRead * 8'd5) + (cnt_charPxls[3:1]);
assign addr_charMap = ((data_charRamRead * 8'd5) + cnt_charPxls);
 
 
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - //
188,12 → 192,11
reg[2:0] rgb_buf;
 
always @ (mask_charMap or data_charMap) begin
if((charRow1 | charRow2 | charRow3 | charRow4) && ((mask_charMap & data_charMap) != 8'b0) && (cnt_charPxls != 4'd10) && (HCNT >= 10'd7) && (HCNT <= 10'd632))
if((charRow1 | charRow2 | charRow3 | charRow4 | charRow5 | charRow6 | charRow7 | charRow8) && ((mask_charMap & data_charMap) != 8'b0) && (cnt_charPxls != 4'd5) && (HCNT >= 10'd2) && (HCNT <= 10'd637))
rgb_buf = P_yellow;
else
rgb_buf = P_black;
end
always @ (posedge CLK_VGA) begin
RGB_OUT <= rgb_buf;
end
214,30 → 217,30
 
always @ (posedge MASTER_CLK or posedge MASTER_RST) begin
if(MASTER_RST)
test_cntAddr <= 11'd41;
else if(test_cntAddr == 11'd56)
test_cntAddr <= 11'd41;
test_cntAddr <= 11'd61;
else if(test_cntAddr == 11'd76)
test_cntAddr <= 11'd61;
else
test_cntAddr <= test_cntAddr+1;
end
 
always @ (test_cntAddr or test_cnt) begin
if(test_cntAddr == 11'd41) data_time[3:0] = test_cnt[63:60];
else if(test_cntAddr == 11'd42) data_time[3:0] = test_cnt[59:56];
else if(test_cntAddr == 11'd43) data_time[3:0] = test_cnt[55:52];
else if(test_cntAddr == 11'd44) data_time[3:0] = test_cnt[51:48];
else if(test_cntAddr == 11'd45) data_time[3:0] = test_cnt[47:44];
else if(test_cntAddr == 11'd46) data_time[3:0] = test_cnt[43:40];
else if(test_cntAddr == 11'd47) data_time[3:0] = test_cnt[39:36];
else if(test_cntAddr == 11'd48) data_time[3:0] = test_cnt[35:32];
else if(test_cntAddr == 11'd49) data_time[3:0] = test_cnt[31:28];
else if(test_cntAddr == 11'd50) data_time[3:0] = test_cnt[27:24];
else if(test_cntAddr == 11'd51) data_time[3:0] = test_cnt[23:20];
else if(test_cntAddr == 11'd52) data_time[3:0] = test_cnt[19:16];
else if(test_cntAddr == 11'd53) data_time[3:0] = test_cnt[15:12];
else if(test_cntAddr == 11'd54) data_time[3:0] = test_cnt[11:8];
else if(test_cntAddr == 11'd55) data_time[3:0] = test_cnt[7:4];
else if(test_cntAddr == 11'd56) data_time[3:0] = test_cnt[3:0];
if(test_cntAddr == 11'd61) data_time[3:0] = test_cnt[63:60];
else if(test_cntAddr == 11'd62) data_time[3:0] = test_cnt[59:56];
else if(test_cntAddr == 11'd63) data_time[3:0] = test_cnt[55:52];
else if(test_cntAddr == 11'd64) data_time[3:0] = test_cnt[51:48];
else if(test_cntAddr == 11'd65) data_time[3:0] = test_cnt[47:44];
else if(test_cntAddr == 11'd66) data_time[3:0] = test_cnt[43:40];
else if(test_cntAddr == 11'd67) data_time[3:0] = test_cnt[39:36];
else if(test_cntAddr == 11'd68) data_time[3:0] = test_cnt[35:32];
else if(test_cntAddr == 11'd69) data_time[3:0] = test_cnt[31:28];
else if(test_cntAddr == 11'd70) data_time[3:0] = test_cnt[27:24];
else if(test_cntAddr == 11'd71) data_time[3:0] = test_cnt[23:20];
else if(test_cntAddr == 11'd72) data_time[3:0] = test_cnt[19:16];
else if(test_cntAddr == 11'd73) data_time[3:0] = test_cnt[15:12];
else if(test_cntAddr == 11'd74) data_time[3:0] = test_cnt[11:8];
else if(test_cntAddr == 11'd75) data_time[3:0] = test_cnt[7:4];
else if(test_cntAddr == 11'd76) data_time[3:0] = test_cnt[3:0];
else data_time[3:0] = 4'b0000;
end
 
264,14 → 267,17
 
RAMB16_S9_S9 #(
// 6666555555555544444444443333333333222222222211111111110000000000
.INIT_00(256'h920de29292928ee0101010fe449292927c668A9292662242FE02027C8282827C),
.INIT_00(256'h920de29292928ee0101010fe449292927c668A9292660042FE02007C86BAC27C),
// CCCCCCCCBBBBBBBBBBAAAAAAAAAA999999999988888888887777777777666666
.INIT_01(256'h828282c6Fe9292926c7e9090907e609292927d6d9292926d808698a0C07d9292),
// --SPACE---FFFFFFFFFFEEEEEEEEEEDDDDDDDDDDCC
.INIT_02(256'h00000000000000000000000000000000Fe909090c0Fe929292c6FE8282827c7c),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
// JJIIIIIIIIIIHHHHHHHHHHGGGGGGGGGGFFFFFFFFFFEEEEEEEEEEDDDDDDDDDDCC
.INIT_02(256'h808282Fe8282Fe101010Fe7c829294deFe909090c0Fe929292c6FE8282827c7c),
// PPPPPPOOOOOOOOOONNNNNNNNNNMMMMMMMMMMLLLLLLLLLLKKKKKKKKKKJJJJJJJJ
.INIT_03(256'h9090607C8282827CFe403804FeFe402040FeFe02020206Fe102844828482FC80),
// VVVVVVVVVVUUUUUUUUUUTTTTTTTTTTSSSSSSSSSSRRRRRRRRRRQQQQQQQQQQPPPP
.INIT_04(256'hf8040204f8fC020202fCC080Fe80C0649292924c7e909894627C828A7C027C90),
// !!!!!!!!!!--space---ZZZZZZZZZZYYYYYYYYYYXXXXXXXXXWWWWWWWWWWW
.INIT_05(256'h000000f6f600000000000000868aa2a2c2c0201e20c0c628102cC6Fe040804Fe),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
333,7 → 339,7
) RAM_Character_Map (
.DOA(), .DOB(data_charMap),
.DOPA(), .DOPB(),
.ADDRA(11'b111), .ADDRB(addr_charMap),
.ADDRA(), .ADDRB(addr_charMap),
.CLKA(GND), .CLKB(MASTER_CLK),
.DIA(8'b0), .DIB(8'b0),
.DIPA(GND), .DIPB(GND),
344,33 → 350,33
 
 
RAMB16_S9_S9 #(
.INIT_00(256'h1010101010101010101010100F0E0D0C0B0A0908070605040302010010101010),
.INIT_01(256'h1010101010101010101010101010101010101010101010101010101010101010),
.INIT_02(256'h1010101010101010101010101010101010101010101010101010101010101010),
.INIT_03(256'h1010101010101010101010101010101010101010101010101010101010101010),
.INIT_04(256'h1010101010101010101010101010101010101010101010101010101010101010),
.INIT_05(256'h1010101010101010101010101010101010101010101010101010101010101010),
.INIT_06(256'h1010101010101010101010101010101010101010101010101010101010101010),
.INIT_07(256'h1010101010101010101010101010101010101010101010101010101010101010),
.INIT_08(256'h1010101010101010101010101010101010101010101010101010101010101010),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_01(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_02(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_03(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_04(256'h201f1e1d1c1b1a191817161514131211100f0e0d0c0b0a090807060504030201),
.INIT_05(256'h2424242424242424242424242424242424242424242424242424242424232221),
.INIT_06(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_07(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_08(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_09(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_0A(256'h2424242424242424242424250e17121b0e111d0a14241e1822240e1f18152412),
.INIT_0B(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_0C(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_0D(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_0E(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_0F(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_10(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_11(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_12(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_13(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_14(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_15(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_16(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_17(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_18(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_19(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_1A(256'h2424242424242424242424242424242424242424242424242424242424242424),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
/trunk/VGA/d_VgaRamBuffer.v
110,7 → 110,7
/* TRIG_ADDR modified */
always @ (TRIG_ADDR) begin
if(TRIG_ADDR < 10'd320)
TRIG_ADDR_buffered = (10'd2048 - 10'd1 - 10'd320) - TRIG_ADDR;
TRIG_ADDR_buffered = (11'd2047 - 10'd320) - TRIG_ADDR;
else
TRIG_ADDR_buffered = TRIG_ADDR;
end
129,11 → 129,30
end
end
 
reg[7:0] TESTING_CNT;
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1) begin
TESTING_CNT <= 8'd0;
end else if(VGA_RAM_ACCESS_OK) begin
if(vcnt == 5'd24)
TESTING_CNT <= TESTING_CNT+1;
else
TESTING_CNT <= TESTING_CNT;
end else begin
TESTING_CNT <= 8'b0;
end
end
 
 
always @ (ADC_RAM_DATA) begin
adc_data_scale = ADC_RAM_DATA + (ADC_RAM_DATA>>1);
// adc_data_scale = TESTING_CNT + (TESTING_CNT>>1) + (TESTING_CNT>>4) + (TESTING_CNT>>6);
// adc_data_scale = ADC_RAM_DATA + (ADC_RAM_DATA>>1) + (ADC_RAM_DATA>>4) + (ADC_RAM_DATA>>6);
adc_data_scale = ADC_RAM_DATA;
end
 
 
 
 
always @ (posedge CLK_50MHZ or posedge MASTER_RST) begin
if(MASTER_RST == 1'b1) begin
VGA_RAM_ADDR <= 18'b0;

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