URL
https://opencores.org/ocsvn/ethernet_tri_mode/ethernet_tri_mode/trunk
Subversion Repositories ethernet_tri_mode
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 17 to Rev 18
- ↔ Reverse comparison
Rev 17 → Rev 18
/trunk/rtl/verilog/MAC_rx/MAC_rx_FF.v
39,6 → 39,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2006/01/19 14:07:54 maverickist |
// verification is complete. |
// |
// Revision 1.3 2005/12/16 06:44:16 Administrator |
// replaced tab with space. |
// passed 9.6k length frame test. |
166,6 → 169,9
reg [35:0] Dout_dl1; |
reg [4:0] Fifo_data_count; |
reg Rx_mac_pa_tmp ; |
|
reg [4:0] Rx_Hwmark_pl ; |
reg [4:0] Rx_Lwmark_pl ; |
integer i ; |
//****************************************************************************** |
//domain Clk_MAC,write data to dprom.a-port for write |
512,13 → 518,25
Fifo_data_count <=0; |
else |
Fifo_data_count <=Add_wr_ungray[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]; |
|
always @ (posedge Clk_SYS or posedge Reset) |
if (Reset) |
begin |
Rx_Hwmark_pl <=0; |
Rx_Lwmark_pl <=0; |
end |
else |
begin |
Rx_Hwmark_pl <=Rx_Hwmark; |
Rx_Lwmark_pl <=Rx_Lwmark; |
end |
|
always @ (posedge Clk_SYS or posedge Reset) |
if (Reset) |
Rx_mac_ra <=0; |
else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark) |
else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark_pl) |
Rx_mac_ra <=0; |
else if (Packet_number_inFF>=1||Fifo_data_count>=Rx_Hwmark) |
else if (Packet_number_inFF>=1||Fifo_data_count>=Rx_Hwmark_pl) |
Rx_mac_ra <=1; |
|
|
/trunk/rtl/verilog/MAC_tx/MAC_tx_FF.v
39,6 → 39,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2006/01/19 14:07:54 maverickist |
// verification is complete. |
// |
// Revision 1.3 2005/12/16 06:44:18 Administrator |
// replaced tab with space. |
// passed 9.6k length frame test. |
190,6 → 193,9
reg Add_rd_reg_rdy ; |
reg Add_rd_reg_rdy_dl1 ; |
reg Add_rd_reg_rdy_dl2 ; |
reg [4:0] Tx_Hwmark_pl ; |
reg [4:0] Tx_Lwmark_pl ; |
|
integer i ; |
//****************************************************************************** |
//write data to from FF . |
420,13 → 426,24
else |
Fifo_ra_tmp <=0; |
|
always @ (posedge Clk_SYS or posedge Reset) |
if (Reset) |
begin |
Tx_Hwmark_pl <=0; |
Tx_Lwmark_pl <=0; |
end |
else |
begin |
Tx_Hwmark_pl <=Tx_Hwmark; |
Tx_Lwmark_pl <=Tx_Lwmark; |
end |
|
always @ (posedge Clk_SYS or posedge Reset) |
if (Reset) |
Tx_mac_wa <=0; |
else if (Fifo_data_count>=Tx_Hwmark) |
else if (Fifo_data_count>=Tx_Hwmark_pl) |
Tx_mac_wa <=0; |
else if (Fifo_data_count<Tx_Lwmark) |
else if (Fifo_data_count<Tx_Lwmark_pl) |
Tx_mac_wa <=1; |
|
//****************************************************************************** |