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URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

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Rev 17 → Rev 18

/iso7816_3_master/trunk/test/FiDiAnalyzer.v
41,7 → 41,7
output wire [7:0] fMax //in 0.1MHz units
);
 
reg [13+8:0] fiStuff;
reg [13+8-1:0] fiStuff;
assign {fi,fMax} = fiStuff;
always @(*) begin:fiBlock
case(fiCode)
/iso7816_3_master/trunk/test/tsAnalyzer.v
76,11 → 76,11
default: ts<=rxData;
endcase
end
resetCnt<=resetCnt+1;
resetCnt<=resetCnt+1'b1;
end
end else begin
//if(isoVdd & isoReset) begin
resetCnt<=resetCnt + 1;
resetCnt<=resetCnt + 1'b1;
//end else begin
// resetCnt<=16'b0;
//end
/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
67,6 → 67,13
wire isoSioTerm;
wire isoSioCard;
 
wire isTxTerm;
reg isoSioInTerm;
wire isoSioOutTerm;
assign isoSioTerm = isTx ? isoSioOutTerm : 1'bz;
pullup(isoSioTerm);
always @(*) isoSioInTerm = isoSioTerm;
 
wire COM_statusOut=statusOut;
wire COM_clk=isoClk;
integer COM_errorCnt;
113,7 → 120,10
.tsReceived(tsReceived),
.atrIsEarly(atrIsEarly),
.atrIsLate(atrIsLate),
.isoSio(isoSioTerm),
//.isoSio(isoSioTerm),
.isTx(isTxTerm),
.isoSioIn(isoSioInTerm),
.isoSioOut(isoSioOutTerm),
.isoClk(isoClk),
.isoReset(isoReset),
.isoVdd(isoVdd)
/iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
98,7 → 98,7
//wire txRun=1'b0;
 
wire rxRun, rxStartBit, overrunErrorFlag, frameErrorFlag, bufferFull;
assign overrunErrorFlag = overrunError;
//assign overrunErrorFlag = overrunError;
assign frameErrorFlag = frameError;
 
wire [7:0] rxData;
121,7 → 121,7
 
always @(posedge clk, negedge rxCore_nReset) begin
if(~rxCore_nReset) begin
safeClocksPerBit<=clocksPerBit;
safeClocksPerBit<={CLOCK_PER_BIT_WIDTH{1'b0}};
end else if(endOfRx|~comOnGoing) begin
safeClocksPerBit<=clocksPerBit;
end
221,13 → 221,13
end
end
reg ppsValidSoFar;
reg ppsAccepted;
//reg ppsAccepted;
wire ppsDataMatch = (tpduHeader[(CLA_I-(tempBytesCnt*8))+:8]==dataOut);
wire [3:0] earlyAtrK = (4'h0==tdiCnt) ? dataOut[3:0] : atrK;
always @(posedge isoClk, negedge rxCore_nReset) begin
if(~rxCore_nReset) begin
ppsValidSoFar<=1'b0;
ppsAccepted<=1'b0;
//ppsAccepted<=1'b0;
fiCode<=4'b0001;
diCode<=4'b0001;
useT0<=1'b1;
253,7 → 253,7
atrK <= dataOut[3:0];
end
tempBytesCnt <= 2'h0;
tdiStruct <= {tdiCnt+1,dataOut};
tdiStruct <= {tdiCnt+1'b1,dataOut};
if(12'h0=={dataOut,atrK}) begin
atrCompleted <= 1'b1;
{waitCardTx,waitTermTx}<=2'b01;
268,7 → 268,7
end else begin //TA, TB or TC bytes
//TODO: get relevant info
tempBytesCnt <= tempBytesCnt+1;
tempBytesCnt <= tempBytesCnt+1'b1;
end
end
end
284,7 → 284,7
fsmState <= T0_HEADER;
end
end else begin
tempBytesCnt <= tempBytesCnt+1;
tempBytesCnt <= tempBytesCnt+1'b1;
end
end
end
318,9 → 318,9
fsmState <= T0_PPS_RESPONSE;
{waitCardTx,waitTermTx}<=2'b10;
ppsValidSoFar<=1'b1;
ppsAccepted<=1'b0;
//ppsAccepted<=1'b0;
end else begin
tempBytesCnt <= tempBytesCnt+1;
tempBytesCnt <= tempBytesCnt+1'b1;
end
end
end
356,7 → 356,7
end
endcase
end else begin
tempBytesCnt <= tempBytesCnt+1;
tempBytesCnt <= tempBytesCnt+1'b1;
end
end
end
368,7 → 368,7
fsmState <= T0_PB;
{waitCardTx,waitTermTx}<=2'b10;
end else begin
tempBytesCnt <= tempBytesCnt+1;
tempBytesCnt <= tempBytesCnt+1'b1;
end
end
end
403,7 → 403,7
if(endOfRx) begin
fsmState <= T0_PB;
{waitCardTx,waitTermTx}<=2'b10;
tempBytesCnt <= tempBytesCnt+1;
tempBytesCnt <= tempBytesCnt+1'b1;
end
end
T0_SW1: begin
426,7 → 426,7
fsmState <= T0_SW1;
{waitCardTx,waitTermTx}<=2'b10;
end else begin
tempBytesCnt <= tempBytesCnt+1;
tempBytesCnt <= tempBytesCnt+1'b1;
end
end
end
/iso7816_3_master/trunk/sources/Uart.v
88,10 → 88,14
reg safeMsbFirst;
always @(posedge clk, negedge nReset) begin
if(~nReset) begin
safeClocksPerBit<=clocksPerBit;
/*safeClocksPerBit<=clocksPerBit;
safeStopBit2<=stopBit2;
safeOddParity<=oddParity;
safeMsbFirst<=msbFirst;
safeMsbFirst<=msbFirst;*/
safeClocksPerBit<={CLOCK_PER_BIT_WIDTH{1'b0}};
safeStopBit2<=1'b0;
safeOddParity<=1'b0;
safeMsbFirst<=1'b0;
end else if(endOfRx|endOfTx|~(rxRun|rxStartBit|txRun)) begin
safeClocksPerBit<=clocksPerBit;
safeStopBit2<=stopBit2;
/iso7816_3_master/trunk/sources/Iso7816_3_Master.v
50,18 → 50,22
output wire atrIsEarly,//high if TS received before 400 cycles after reset release
output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
//ISO7816 signals
inout wire isoSio,
//inout wire isoSio,//not synthesisable on FPGA :-S
output wire isTx,
input wire isoSioIn,
output wire isoSioOut,
output wire isoClk,
output reg isoReset,
output reg isoVdd
);
 
wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull;
wire txRun,txPending, rxRun, rxStartBit, overrunErrorFlag, frameErrorFlag, bufferFull;
assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut;
 
wire serialOut;
assign isoSio = isTx ? serialOut : 1'bz;
pullup(isoSio);
//wire serialOut;
//not synthesisable on FPGA :-S
//assign isoSio = isTx ? serialOut : 1'bz;
//pullup(isoSio);
wire comClk;
 
wire stopBit2=1'b1;//0: 1 stop bit, 1: 2 stop bits
92,8 → 96,8
.nCsDataOut(nCsDataOut),
.statusOut(statusOut),
.nCsStatusOut(nCsStatusOut),
.serialIn(isoSio),
.serialOut(serialOut),
.serialIn(isoSioIn),
.serialOut(isoSioOut),
.comClk(comClk)
);
126,7 → 130,7
default: ts<=dataOut;
endcase
end
resetCnt<=resetCnt+1;
resetCnt<=resetCnt+1'b1;
end
if(startDeactivation) begin
isoVdd <= 1'b0;
144,7 → 148,7
isActivated <=1'b1;
isoReset <=1'b1;
end else
resetCnt<=resetCnt + 1;
resetCnt<=resetCnt + 1'b1;
end else begin
resetCnt<=16'b0;
end
/iso7816_3_master/trunk/sources/RxCore.v
111,7 → 111,7
STOP2_STATE: begin
//make the rx operation is one cycle shorter,
//since we detect the start bit at least one cycle later it starts.
bitClocksCounterCompare = clocksPerBit-1;
bitClocksCounterCompare = clocksPerBit-1'b1;
bitClocksCounterInc = 1;
bitClocksCounterClear = 0;
end
/iso7816_3_master/trunk/sources/TxCore.v
116,14 → 116,14
 
assign bitClocksCounterInitVal=0;
 
always @(nextState) begin
always @(*) begin
case(nextState)
START_STATE:
assign bitClocksCounterCompare = clocksPerBit-1;
bitClocksCounterCompare = clocksPerBit-1'b1;
SEND_STOP2_STATE:
assign bitClocksCounterCompare = clocksPerBit-1;
bitClocksCounterCompare = clocksPerBit-1'b1;
default:
assign bitClocksCounterCompare = clocksPerBit;
bitClocksCounterCompare = clocksPerBit;
endcase
end
 
/iso7816_3_master/trunk/sources/HalfDuplexUartIf.v
119,7 → 119,7
end
end
end
 
wire endOfTx;
BasicHalfDuplexUart #(
.DIVIDER_WIDTH(DIVIDER_WIDTH),
.CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH)
131,6 → 131,7
.frameErrorFlag(frameErrorFlag),
.txRun(txRun),
.endOfRx(endOfRx),
.endOfTx(endOfTx),
.rxRun(rxRun),
.rxStartBit(rxStartBit),
.txFull(txFull),

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