URL
https://opencores.org/ocsvn/8051/8051/trunk
Subversion Repositories 8051
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 171 to Rev 172
- ↔ Reverse comparison
Rev 171 → Rev 172
/trunk/rtl/verilog/oc8051_defines.v
79,6 → 79,12
//`define OC8051_SERIAL |
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// |
// oc8051 bist |
// |
//`define OC8051_BIST |
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// |
// operation codes for alu |
// |
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/trunk/rtl/verilog/oc8051_ram_top.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2003/04/02 16:12:04 simont |
// generic_dpram used |
// |
// Revision 1.7 2003/04/02 11:26:21 simont |
// updating... |
// |
65,7 → 68,25
`include "oc8051_defines.v" |
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|
module oc8051_ram_top (clk, rst, rd_addr, rd_data, wr_addr, bit_addr, wr_data, wr, bit_data_in, bit_data_out); |
module oc8051_ram_top (clk, |
rst, |
rd_addr, |
rd_data, |
wr_addr, |
bit_addr, |
wr_data, |
wr, |
bit_data_in, |
bit_data_out |
`ifdef OC8051_BIST |
, |
scanb_rst, |
scanb_clk, |
scanb_si, |
scanb_so, |
scanb_en |
`endif |
); |
|
// on-chip ram-size (2**ram_aw bytes) |
parameter ram_aw = 8; // default 256 bytes |
89,6 → 110,13
output bit_data_out; |
output [7:0] rd_data; |
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`ifdef OC8051_BIST |
input scanb_rst; |
input scanb_clk; |
input scanb_si; |
output scanb_so; |
input scanb_en; |
`endif |
|
// rd_addr_m read address modified |
// wr_addr_m write address modified |
/trunk/rtl/verilog/oc8051_top.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.30 2003/06/03 16:51:24 simont |
// include "8051_defines" added. |
// |
// Revision 1.29 2003/05/07 12:36:03 simont |
// chsnge comp.des to des1 |
// |
164,6 → 167,14
t2_i, t2ex_i, |
`endif |
|
// BIST |
`ifdef OC8051_BIST |
scanb_rst, |
scanb_clk, |
scanb_si, |
scanb_so, |
scanb_en, |
`endif |
// external access (active low) |
ea_in |
); |
238,6 → 249,14
t2ex_i; // |
`endif |
|
`ifdef OC8051_BIST |
input scanb_rst; |
input scanb_clk; |
input scanb_si; |
output scanb_so; |
input scanb_en; |
`endif |
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wire [7:0] dptr_hi, |
dptr_lo, |
ri, |
398,7 → 417,16
.wr_data(wr_dat), |
.wr(wr_o && (!wr_addr[7] || wr_ind)), |
.bit_data_in(desCy), |
.bit_data_out(bit_data)); |
.bit_data_out(bit_data) |
`ifdef OC8051_BIST |
, |
.scanb_rst(scanb_rst), |
.scanb_clk(scanb_clk), |
.scanb_si(scanb_si), |
.scanb_so(scanb_so), |
.scanb_en(scanb_en) |
`endif |
); |
|
// |
|
581,7 → 609,7
.srcAc(srcAc), |
.cy(cy), |
// ports |
.rmw(rmw), |
.rmw(rmw), |
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`ifdef OC8051_PORTS |
`ifdef OC8051_PORT0 |
611,9 → 639,9
`endif |
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// int |
.int_ack(int_ack), |
.intr(intr), |
.int0(int0_i), |
.int_ack(int_ack), |
.intr(intr), |
.int0(int0_i), |
.int1(int1_i), |
.reti(reti), |
.int_src(int_src), |
626,12 → 654,12
|
// t/c 2 |
`ifdef OC8051_TC2 |
.t2(t2_i), |
.t2(t2_i), |
.t2ex(t2ex_i), |
`endif |
|
// dptr |
.dptr_hi(dptr_hi), |
.dptr_hi(dptr_hi), |
.dptr_lo(dptr_lo), |
.wait_data(wait_data) |
); |