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URL https://opencores.org/ocsvn/8051/8051/trunk

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    from Rev 173 to Rev 174
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Rev 173 → Rev 174

/trunk/rtl/verilog/oc8051_icache.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2003/05/05 10:35:35 simont
// change to fit xrom.
//
// Revision 1.6 2003/04/03 19:15:37 simont
// fix some bugs, use oc8051_cache_ram.
//
68,10 → 71,19
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
module oc8051_icache (rst, clk,
adr_i, dat_o, stb_i, ack_o, cyc_i,
adr_o, dat_i, stb_o, ack_i, cyc_o
`ifdef OC8051_BIST
,
scanb_rst,
scanb_clk,
scanb_si,
scanb_so,
scanb_en
`endif
);
//
// rst (in) reset - pin
109,6 → 121,14
reg stb_o,
cyc_o;
 
`ifdef OC8051_BIST
input scanb_rst;
input scanb_clk;
input scanb_si;
output scanb_so;
input scanb_en;
`endif
 
parameter ADR_WIDTH = 6; // cache address wihth
parameter LINE_WIDTH = 2; // line address width (2 => 4x32)
parameter BL_WIDTH = ADR_WIDTH - LINE_WIDTH; // block address width
170,44 → 190,30
assign adr_o = {mis_adr[15:LINE_WIDTH+2], cyc, 2'b00};
 
 
oc8051_ram_64x32_dual_bist oc8051_cache_ram(
.clk ( clk ),
.rst ( rst ),
.adr0 ( adr_i[ADR_WIDTH+1:2] ),
.dat0_o ( data0 ),
.en0 ( 1'b1 ),
.adr1 ( addr1 ),
.dat1_o ( data1_o ),
.dat1_i ( data1_i ),
.en1 ( 1'b1 ),
.wr1 ( wr1 )
`ifdef OC8051_BIST
,
.scanb_rst(scanb_rst),
.scanb_clk(scanb_clk),
.scanb_si(scanb_soi),
.scanb_so(scanb_so),
.scanb_en(scanb_en)
`endif
);
 
oc8051_cache_ram oc8051_cache_ram1(
.clk(clk),
.rst(rst),
.addr0(adr_i[ADR_WIDTH+1:2]),
.addr1(addr1),
.data0(data0),
.data1_o(data1_o),
.data1_i(data1_i),
.wr1(wr1)
);
defparam oc8051_cache_ram.ADR_WIDTH = ADR_WIDTH;
 
defparam oc8051_cache_ram1.ADR_WIDTH = ADR_WIDTH;
defparam oc8051_cache_ram1.CACHE_RAM = CACHE_RAM;
 
 
 
/*
generic_dpram #(ADR_WIDTH, 32) oc8051_cache_ram1(
.rclk ( clk ),
.rrst ( rst ),
.rce ( 1'b1 ),
.oe ( 1'b1 ),
.raddr ( adr_i[ADR_WIDTH+1:2] ),
.do ( data0 ),
 
.wclk ( clk ),
.wrst ( rst ),
.wce ( 1'b1 ),
.we ( wr1 ),
.waddr ( addr1 ),
.di ( data1_i )
);
*/
 
 
 
 
always @(stb_b or data0 or data1 or byte_sel)
begin
if (stb_b) begin
/trunk/rtl/verilog/oc8051_defines.v
69,8 → 69,13
//
//`define OC8051_CACHE
//`define OC8051_WB
 
//`define OC8051_RAM_XILINX
//`define OC8051_RAM_VIRTUALSILICON
//`define OC8051_RAM_GENERIC
 
 
`define OC8051_XILINX_ROM
//`define OC8051_XILINX_RAMB
 
//
// oc8051 simulation defines
/trunk/rtl/verilog/oc8051_ram_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2003/06/17 14:17:22 simont
// BIST signals added.
//
// Revision 1.8 2003/04/02 16:12:04 simont
// generic_dpram used
//
131,23 → 134,27
assign bit_data_out = rd_data[bit_select];
 
 
generic_dpram #(ram_aw, 8) oc8051_ram1(
.rclk ( clk ),
.rrst ( rst ),
.rce ( 1'b1 ),
.oe ( 1'b1 ),
.raddr ( rd_addr_m ),
.do ( rd_data ),
 
.wclk ( clk ),
.wrst ( rst ),
.wce ( 1'b1 ),
.we ( wr ),
.waddr ( wr_addr_m ),
.di ( wr_data_m )
);
oc8051_ram_256x8_two_bist oc8051_idata(
.clk ( clk ),
.rst ( rst ),
.rd_addr ( rd_addr_m ),
.rd_data ( rd_data ),
.rd_en ( 1'b1 ),
.wr_addr ( wr_addr_m ),
.wr_data ( wr_data_m ),
.wr_en ( 1'b1 ),
.wr ( wr )
`ifdef OC8051_BIST
,
.scanb_rst(scanb_rst),
.scanb_clk(scanb_clk),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en)
`endif
);
 
 
always @(posedge clk or posedge rst)
if (rst) begin
bit_addr_r <= #1 1'b0;
/trunk/rtl/verilog/oc8051_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.31 2003/06/17 14:17:22 simont
// BIST signals added.
//
// Revision 1.30 2003/06/03 16:51:24 simont
// include "8051_defines" added.
//
255,6 → 258,7
input scanb_si;
output scanb_so;
input scanb_en;
wire scanb_soi;
`endif
 
wire [7:0] dptr_hi,
422,7 → 426,7
,
.scanb_rst(scanb_rst),
.scanb_clk(scanb_clk),
.scanb_si(scanb_si),
.scanb_si(scanb_soi),
.scanb_so(scanb_so),
.scanb_en(scanb_en)
`endif
682,7 → 686,16
.stb_o(wbi_stb_o),
.adr_o(wbi_adr_o),
.ack_i(wbi_ack_i),
.cyc_o(wbi_cyc_o));
.cyc_o(wbi_cyc_o)
`ifdef OC8051_BIST
,
.scanb_rst(scanb_rst),
.scanb_clk(scanb_clk),
.scanb_si(scanb_si),
.scanb_so(scanb_soi),
.scanb_en(scanb_en)
`endif
);
 
defparam oc8051_icache1.ADR_WIDTH = 6; // cache address wihth
defparam oc8051_icache1.LINE_WIDTH = 2; // line address width (2 => 4x32)
689,11 → 702,25
defparam oc8051_icache1.BL_NUM = 15; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH
defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
 
 
`ifdef OC8051_SIMULATION
initial
$display(" Instruction cache enabled");
 
 
`endif
 
 
//
// no cache
//
`else
 
`ifdef OC8051_BIST
assign scanb_soi=scanb_si;
`endif
 
`ifdef OC8051_WB
 
oc8051_wb_iinterface oc8051_wb_iinterface(.rst(wb_rst_i), .clk(wb_clk_i),
710,6 → 737,13
.ack_i(wbi_ack_i),
.cyc_o(wbi_cyc_o));
 
`ifdef OC8051_SIMULATION
initial
$display(" Wishbone instruction interface enabled");
 
 
`endif
 
`else
 
assign wbi_adr_o = iadr_o ;
718,6 → 752,13
assign iack_i = wbi_ack_i ;
assign wbi_cyc_o = 1'b1 ;
 
`ifdef OC8051_SIMULATION
initial
$display(" Pipelined instruction interface enabled");
 
`endif
 
 
`endif
 
`endif

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