URL
https://opencores.org/ocsvn/8051/8051/trunk
Subversion Repositories 8051
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 175 to Rev 176
- ↔ Reverse comparison
Rev 175 → Rev 176
/trunk/sim/rtl_sim/run/run_sim.scr
59,8 → 59,11
echo "../../../rtl/verilog/oc8051_wb_iinterface.v " >> ncvlog.args |
echo "../../../rtl/verilog/oc8051_sfr.v " >> ncvlog.args |
echo "../../../rtl/verilog/oc8051_rom.v " >> ncvlog.args |
echo "../../../rtl/verilog/oc8051_cache_ram.v " >> ncvlog.args |
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echo "../../../rtl/verilog/oc8051_ram_256x8_two_bist.v " >> ncvlog.args |
echo "../../../rtl/verilog/oc8051_ram_64x32_dual_bist.v " >> ncvlog.args |
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echo "../../../../common/generic_memories/rtl/verilog/generic_dpram.v" >> ncvlog.args |
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/trunk/sim/rtl_sim/run/make
1,8 → 59,11
../../../bench/verilog/oc8051_tb.v ../../../bench/verilog/oc8051_xram.v ../../../bench/verilog/oc8051_uart_test.v ../../../bench/verilog/oc8051_xrom.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src_sel.v ../../../rtl/verilog/oc8051_alu.v ../../../rtl/verilog/oc8051_decoder.v ../../../rtl/verilog/oc8051_divide.v ../../../rtl/verilog/oc8051_multiply.v ../../../rtl/verilog/oc8051_memory_interface.v ../../../rtl/verilog/oc8051_ram_top.v ../../../rtl/verilog/oc8051_acc.v ../../../rtl/verilog/oc8051_comp.v ../../../rtl/verilog/oc8051_sp.v ../../../rtl/verilog/oc8051_dptr.v ../../../rtl/verilog/oc8051_cy_select.v ../../../rtl/verilog/oc8051_psw.v ../../../rtl/verilog/oc8051_indi_addr.v ../../../rtl/verilog/oc8051_ports.v ../../../rtl/verilog/oc8051_b_register.v ../../../rtl/verilog/oc8051_uart.v ../../../rtl/verilog/oc8051_int.v ../../../rtl/verilog/oc8051_tc.v ../../../rtl/verilog/oc8051_tc2.v ../../../rtl/verilog/oc8051_icache.v ../../../rtl/verilog/oc8051_wb_iinterface.v ../../../rtl/verilog/oc8051_sfr.v ../../../rtl/verilog/oc8051_rom.v ../../../rtl/verilog/oc8051_cache_ram.v ../../../../common/generic_memories/rtl/verilog/generic_dpram.v |
../../../bench/verilog/oc8051_tb.v ../../../bench/verilog/oc8051_xram.v ../../../bench/verilog/oc8051_uart_test.v ../../../bench/verilog/oc8051_xrom.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src_sel.v ../../../rtl/verilog/oc8051_alu.v ../../../rtl/verilog/oc8051_decoder.v ../../../rtl/verilog/oc8051_divide.v ../../../rtl/verilog/oc8051_multiply.v ../../../rtl/verilog/oc8051_memory_interface.v ../../../rtl/verilog/oc8051_ram_top.v ../../../rtl/verilog/oc8051_acc.v ../../../rtl/verilog/oc8051_comp.v ../../../rtl/verilog/oc8051_sp.v ../../../rtl/verilog/oc8051_dptr.v ../../../rtl/verilog/oc8051_cy_select.v ../../../rtl/verilog/oc8051_psw.v ../../../rtl/verilog/oc8051_indi_addr.v ../../../rtl/verilog/oc8051_ports.v ../../../rtl/verilog/oc8051_b_register.v ../../../rtl/verilog/oc8051_uart.v ../../../rtl/verilog/oc8051_int.v ../../../rtl/verilog/oc8051_tc.v ../../../rtl/verilog/oc8051_tc2.v ../../../rtl/verilog/oc8051_icache.v ../../../rtl/verilog/oc8051_wb_iinterface.v ../../../rtl/verilog/oc8051_sfr.v ../../../rtl/verilog/oc8051_rom.v ../../../rtl/verilog/oc8051_ram_256x8_two_bist.v ../../../rtl/verilog/oc8051_ram_64x32_dual_bist.v ../../../../common/generic_memories/rtl/verilog/generic_dpram.v |