URL
https://opencores.org/ocsvn/8051/8051/trunk
Subversion Repositories 8051
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 178 to Rev 179
- ↔ Reverse comparison
Rev 178 → Rev 179
/trunk/rtl/verilog/oc8051_icache.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2003/06/20 13:36:37 simont |
// ram modules added. |
// |
// Revision 1.7 2003/05/05 10:35:35 simont |
// change to fit xrom. |
// |
217,11 → 220,11
always @(stb_b or data0 or data1 or byte_sel) |
begin |
if (stb_b) begin |
case (byte_sel) |
case (byte_sel) /* synopsys full_case parallel_case */ |
2'b00 : dat_o = data0; |
2'b01 : dat_o = {data1[7:0], data0[31:8]}; |
2'b10 : dat_o = {data1[15:0], data0[31:16]}; |
default: dat_o = {8'h00, data1, data0[31:24]}; |
2'b11 : dat_o = {8'h00, data1, data0[31:24]}; |
endcase |
end else begin |
dat_o = 32'h0; |
/trunk/rtl/verilog/oc8051_defines.v
72,7 → 72,7
|
//`define OC8051_RAM_XILINX |
//`define OC8051_RAM_VIRTUALSILICON |
//`define OC8051_RAM_GENERIC |
`define OC8051_RAM_GENERIC |
|
|
`define OC8051_XILINX_ROM |
/trunk/rtl/verilog/oc8051_alu.v
46,6 → 46,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.18 2003/07/01 18:51:11 simont |
// x replaced with 0. |
// |
// Revision 1.17 2003/06/09 16:51:16 simont |
// fix bug in DA operation. |
// |
196,7 → 199,7
or sub4 or sub8 or subc or da_tmp or inc or dec or sub_result) |
begin |
|
case (op_code) |
case (op_code) /* synopsys full_case parallel_case */ |
//operation add |
`OC8051_ALU_ADD: begin |
des_acc = {addc[0],add8[2:0],add4[3:0]}; |
391,7 → 394,7
enable_mul = 1'b0; |
enable_div = 1'b0; |
end |
default: begin |
`OC8051_ALU_NOP: begin |
des_acc = src1; |
des1 = src1; |
des2 = src2; |
/trunk/rtl/verilog/oc8051_acc.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.13 2003/06/03 17:16:16 simont |
// `ifdef added. |
// |
// Revision 1.12 2003/04/09 16:24:03 simont |
// change wr_sft to 2 bit wire. |
// |
105,7 → 108,7
else if (wr_acc) |
acc = data_in; |
else if (wr_bit_acc) |
case (wr_addr[2:0]) |
case (wr_addr[2:0]) /* synopsys full_case parallel_case */ |
3'b000: acc = {data_out[7:1], bit_in}; |
3'b001: acc = {data_out[7:2], bit_in, data_out[0]}; |
3'b010: acc = {data_out[7:3], bit_in, data_out[1:0]}; |
113,7 → 116,7
3'b100: acc = {data_out[7:5], bit_in, data_out[3:0]}; |
3'b101: acc = {data_out[7:6], bit_in, data_out[4:0]}; |
3'b110: acc = {data_out[7], bit_in, data_out[5:0]}; |
default: acc = {bit_in, data_out[6:0]}; |
3'b111: acc = {bit_in, data_out[6:0]}; |
endcase |
else |
acc = data_out; |
/trunk/rtl/verilog/oc8051_sfr.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.14 2003/05/07 12:39:20 simont |
// fix bug in case of sequence of inc dptr instrucitons. |
// |
// Revision 1.13 2003/05/05 15:46:37 simont |
// add aditional alu destination to solve critical path. |
// |
587,7 → 590,7
wait_data <= #1 1'b1; |
|
end else begin |
case (adr0) |
case (adr0) /* synopsys full_case parallel_case */ |
`OC8051_SFR_ACC: dat0 <= #1 acc; |
`OC8051_SFR_PSW: dat0 <= #1 psw; |
|
640,7 → 643,7
`OC8051_SFR_T2CON: dat0 <= #1 t2con; |
`endif |
|
default: dat0 <= #1 8'h00; |
// default: dat0 <= #1 8'h00; |
endcase |
wait_data <= #1 1'b0; |
end |
663,7 → 666,7
else if ((adr1==adr0) & we & wr_bit_r) |
bit_out <= #1 bit_in; |
else |
case (adr0[7:3]) |
case (adr0[7:3]) /* synopsys full_case parallel_case */ |
`OC8051_SFR_B_ACC: bit_out <= #1 acc[adr0[2:0]]; |
`OC8051_SFR_B_PSW: bit_out <= #1 psw[adr0[2:0]]; |
|
698,7 → 701,7
`OC8051_SFR_B_T2CON: bit_out <= #1 t2con[adr0[2:0]]; |
`endif |
|
default: bit_out <= #1 1'b0; |
// default: bit_out <= #1 1'b0; |
endcase |
end |
|
/trunk/rtl/verilog/oc8051_int.v
46,6 → 46,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.9 2003/06/03 17:12:05 simont |
// fix some bugs. |
// |
// Revision 1.8 2003/04/07 14:58:02 simont |
// change sfr's interface. |
// |
186,7 → 189,7
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin |
tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]}; |
end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin |
case (wr_addr[2:0]) |
case (wr_addr[2:0]) /* synopsys full_case parallel_case */ |
3'b000: tcon_s[0] <= #1 bit_in; |
3'b010: tcon_s[1] <= #1 bit_in; |
3'b100: tcon_s[2] <= #1 bit_in; |
/trunk/rtl/verilog/oc8051_comp.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.7 2003/04/25 17:15:51 simont |
// change branch instruction execution (reduse needed clock periods). |
// |
// Revision 1.6 2003/04/02 11:26:21 simont |
// updating... |
// |
86,12 → 89,11
|
always @(sel or b_in or cy or acc or des) |
begin |
case (sel) |
case (sel) /* synopsys full_case parallel_case */ |
`OC8051_CSS_AZ : eq_r = (acc == 8'h00); |
`OC8051_CSS_DES : eq_r = (des == 8'h00); |
`OC8051_CSS_CY : eq_r = cy; |
`OC8051_CSS_BIT : eq_r = b_in; |
default: eq_r = 1'bx; |
endcase |
end |
|
/trunk/rtl/verilog/oc8051_ports.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.9 2003/04/10 12:43:19 simont |
// defines for pherypherals added |
// |
// Revision 1.8 2003/04/07 14:58:02 simont |
// change sfr's interface. |
// |
168,7 → 171,7
`endif |
end else if (wr) begin |
if (!wr_bit) begin |
case (wr_addr) |
case (wr_addr) /* synopsys full_case parallel_case */ |
// |
// bytaddresable |
`ifdef OC8051_PORT0 |
188,7 → 191,7
`endif |
endcase |
end else begin |
case (wr_addr[7:3]) |
case (wr_addr[7:3]) /* synopsys full_case parallel_case */ |
|
// |
// bit addressable |
/trunk/rtl/verilog/oc8051_cy_select.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2003/04/02 11:26:21 simont |
// updating... |
// |
// Revision 1.2 2002/09/30 17:33:59 simont |
// prepared header |
// |
72,12 → 75,11
|
always @(cy_sel or cy_in or data_in) |
begin |
case (cy_sel) |
case (cy_sel) /* synopsys full_case parallel_case */ |
`OC8051_CY_0: data_out = 1'b0; |
`OC8051_CY_PSW: data_out = cy_in; |
`OC8051_CY_RAM: data_out = data_in; |
`OC8051_CY_1: data_out = 1'b1; |
default: data_out = 1'bx; |
endcase |
end |
|
/trunk/rtl/verilog/oc8051_indi_addr.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.6 2003/05/05 15:46:37 simont |
// add aditional alu destination to solve critical path. |
// |
// Revision 1.5 2003/01/13 14:14:41 simont |
// replace some modules |
// |
94,7 → 97,7
buff[3'b111] <= #1 8'h00; |
end else begin |
if ((wr) & !(wr_bit_r)) begin |
case (wr_addr) |
case (wr_addr) /* synopsys full_case parallel_case */ |
8'h00: buff[3'b000] <= #1 data_in; |
8'h01: buff[3'b001] <= #1 data_in; |
8'h08: buff[3'b010] <= #1 data_in; |
/trunk/rtl/verilog/oc8051_memory_interface.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.11 2003/06/20 13:35:10 simont |
// simualtion `ifdef added |
// |
// Revision 1.10 2003/06/05 11:15:02 simont |
// fix bug. |
// |
397,7 → 400,7
|
always @(rd_sel or sp or ri or rn or imm or dadr_o[15:0] or bank) |
begin |
case (rd_sel) |
case (rd_sel) /* synopsys full_case parallel_case */ |
`OC8051_RRS_RN : rd_addr = {3'h0, rn}; |
`OC8051_RRS_I : rd_addr = ri; |
`OC8051_RRS_D : rd_addr = imm; |
407,7 → 410,7
`OC8051_RRS_DPTR : rd_addr = `OC8051_SFR_DPTR_LO; |
`OC8051_RRS_PSW : rd_addr = `OC8051_SFR_PSW; |
`OC8051_RRS_ACC : rd_addr = `OC8051_SFR_ACC; |
default : rd_addr = 2'bxx; |
// default : rd_addr = 2'bxx; |
endcase |
|
end |
417,7 → 420,7
// |
always @(wr_sel or sp_w or rn_r or imm_r or ri_r or imm2_r or op1_r or dadr_o[15:0]) |
begin |
case (wr_sel) |
case (wr_sel) /* synopsys full_case parallel_case */ |
`OC8051_RWS_RN : wr_addr = {3'h0, rn_r}; |
`OC8051_RWS_I : wr_addr = ri_r; |
`OC8051_RWS_D : wr_addr = imm_r; |
424,7 → 427,7
`OC8051_RWS_SP : wr_addr = sp_w; |
`OC8051_RWS_D3 : wr_addr = imm2_r; |
`OC8051_RWS_B : wr_addr = `OC8051_SFR_B; |
default : wr_addr = 2'bxx; |
// default : wr_addr = 2'bxx; |
endcase |
end |
|
498,7 → 501,7
dstb_o <= #1 1'b0; |
dmem_wait <= #1 1'b0; |
end else begin |
case (mem_act) |
case (mem_act) /* synopsys full_case parallel_case */ |
`OC8051_MAS_DPTR_R: begin // read from external rom: acc=(dptr) |
dwe_o <= #1 1'b0; |
dstb_o <= #1 1'b1; |
566,7 → 569,7
|
always @(op_pos or idat_cur or idat_old) |
begin |
case (op_pos) |
case (op_pos) /* synopsys parallel_case */ |
3'b000: begin |
op1 = idat_old[7:0] ; |
op2 = idat_old[15:8] ; |
677,7 → 680,7
|
always @(op1_out) |
begin |
casex (op1_out) |
casex (op1_out) /* synopsys parallel_case */ |
`OC8051_ACALL : op_length = 2'h2; |
`OC8051_AJMP : op_length = 2'h2; |
|
939,7 → 942,7
end else if (pc_wr) begin |
// |
//case of writing new value to pc (jupms) |
case (pc_wr_sel) |
case (pc_wr_sel) /* synopsys full_case parallel_case */ |
`OC8051_PIS_ALU: pc_buf <= #1 alu; |
`OC8051_PIS_AL: pc_buf[7:0] <= #1 alu[7:0]; |
`OC8051_PIS_AH: pc_buf[15:8] <= #1 alu[7:0]; |
/trunk/rtl/verilog/oc8051_alu_src_sel.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2003/06/03 17:13:57 simont |
// remove pc_r register. |
// |
// Revision 1.2 2003/05/06 09:41:35 simont |
// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. |
// |
91,7 → 94,7
/////// |
always @(sel1 or op1_r or op2_r or op3_r or pc or acc or ram) |
begin |
case (sel1) |
case (sel1) /* synopsys full_case parallel_case */ |
`OC8051_AS1_RAM: src1 = ram; |
`OC8051_AS1_ACC: src1 = acc; |
`OC8051_AS1_OP1: src1 = op1_r; |
99,7 → 102,7
`OC8051_AS1_OP3: src1 = op3_r; |
`OC8051_AS1_PCH: src1 = pc[15:8]; |
`OC8051_AS1_PCL: src1 = pc[7:0]; |
default: src1 = 8'h00; |
// default: src1 = 8'h00; |
endcase |
end |
|
110,12 → 113,12
/////// |
always @(sel2 or op2_r or acc or ram or op1_r) |
begin |
case (sel2) |
case (sel2) /* synopsys full_case parallel_case */ |
`OC8051_AS2_ACC: src2= acc; |
`OC8051_AS2_ZERO: src2= 8'h00; |
`OC8051_AS2_RAM: src2= ram; |
`OC8051_AS2_OP2: src2= op2_r; |
default: src2= 8'h00; |
// default: src2= 8'h00; |
endcase |
end |
|
127,10 → 130,10
|
always @(sel3 or pc[15:8] or dptr[15:8] or op1_r) |
begin |
case (sel3) |
case (sel3) /* synopsys full_case parallel_case */ |
`OC8051_AS3_DP: src3= dptr[15:8]; |
`OC8051_AS3_PC: src3= pc[15:8]; |
default: src3= 16'h0; |
// default: src3= 16'h0; |
endcase |
end |
|
/trunk/rtl/verilog/oc8051_rom.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2003/06/03 17:09:57 simont |
// pipelined acces to axternal instruction interface added. |
// |
// Revision 1.2 2003/04/03 19:17:19 simont |
// add `include "oc8051_defines.v" |
// |
230,7 → 233,7
// always read tree bits in row |
always @(posedge clk) |
begin |
case(addr[6:0]) |
case(addr[6:0]) /* synopsys parallel_case */ |
7'd0: begin |
data1 <= #1 int_data0; |
data2 <= #1 int_data1; |
/trunk/rtl/verilog/oc8051_decoder.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.21 2003/06/03 17:09:57 simont |
// pipelined acces to axternal instruction interface added. |
// |
// Revision 1.20 2003/05/06 11:10:38 simont |
// optimize state machine. |
// |
165,9 → 168,9
// unregisterd outputs |
always @(op_cur or eq or state_dec or mem_wait) |
begin |
case (state_dec) |
case (state_dec) /* synopsys full_case parallel_case */ |
2'b01: begin |
casex (op_cur) |
casex (op_cur) /* synopsys parallel_case */ |
`OC8051_DIV : begin |
ram_rd_sel = `OC8051_RRS_B; |
end |
186,7 → 189,7
rmw = `OC8051_RMW_N; |
end |
2'b10: begin |
casex (op_cur) |
casex (op_cur) /* synopsys parallel_case */ |
`OC8051_SJMP : begin |
ram_rd_sel = `OC8051_RRS_DC; |
pc_wr = `OC8051_PCW_Y; |
333,7 → 336,7
stb_i = 1'b1; |
end |
2'b11: begin |
casex (op_cur) |
casex (op_cur) /* synopsys parallel_case */ |
`OC8051_CJNE_R : begin |
ram_rd_sel = `OC8051_RRS_DC; |
pc_wr = `OC8051_PCW_N; |
395,8 → 398,8
stb_i = 1'b1; |
bit_addr = 1'b0; |
end |
default: begin |
casex (op_cur) |
2'b00: begin |
casex (op_cur) /* synopsys parallel_case */ |
`OC8051_ACALL :begin |
ram_rd_sel = `OC8051_RRS_DC; |
pc_wr = `OC8051_PCW_Y; |
1198,9 → 1201,9
src_sel3 <= #1 `OC8051_AS3_DC; |
wr_sfr <= #1 `OC8051_WRS_N; |
end else if (!wait_data) begin |
case (state_dec) |
case (state_dec) /* synopsys parallel_case */ |
2'b01: begin |
casex (op_cur) |
casex (op_cur) /* synopsys parallel_case */ |
`OC8051_MOVC_DP :begin |
ram_wr_sel <= #1 `OC8051_RWS_DC; |
src_sel1 <= #1 `OC8051_AS1_OP1; |
1296,7 → 1299,7
src_sel3 <= #1 `OC8051_AS3_DC; |
end |
2'b10: begin |
casex (op_cur) |
casex (op_cur) /* synopsys parallel_case */ |
`OC8051_ACALL :begin |
ram_wr_sel <= #1 `OC8051_RWS_SP; |
src_sel1 <= #1 `OC8051_AS1_PCH; |
1352,7 → 1355,7
end |
|
2'b11: begin |
casex (op_cur) |
casex (op_cur) /* synopsys parallel_case */ |
`OC8051_RET : begin |
src_sel1 <= #1 `OC8051_AS1_RAM; |
src_sel2 <= #1 `OC8051_AS2_DC; |
1391,7 → 1394,7
wr_sfr <= #1 `OC8051_WRS_N; |
end |
default: begin |
casex (op_cur) |
casex (op_cur) /* synopsys parallel_case */ |
`OC8051_ACALL :begin |
ram_wr_sel <= #1 `OC8051_RWS_SP; |
src_sel1 <= #1 `OC8051_AS1_PCL; |
2637,11 → 2640,11
if (rst) |
state <= #1 2'b11; |
else if (!mem_wait & !wait_data) begin |
case (state) |
case (state) /* synopsys parallel_case */ |
2'b10: state <= #1 2'b01; |
2'b11: state <= #1 2'b10; |
2'b00: |
casex (op_in) |
casex (op_in) /* synopsys full_case parallel_case */ |
`OC8051_ACALL : state <= #1 2'b10; |
`OC8051_AJMP : state <= #1 2'b10; |
`OC8051_CJNE_R : state <= #1 2'b10; |
2671,7 → 2674,7
`OC8051_JZ : state <= #1 2'b10; |
`OC8051_DIV : state <= #1 2'b11; |
`OC8051_MUL : state <= #1 2'b11; |
default : state <= #1 2'b00; |
// default : state <= #1 2'b00; |
endcase |
default: state <= #1 2'b00; |
endcase |
2688,7 → 2691,7
end else if (!rd) begin |
mem_act <= #1 `OC8051_MAS_NO; |
end else |
casex (op_cur) |
casex (op_cur) /* synopsys parallel_case */ |
`OC8051_MOVX_AI : mem_act <= #1 `OC8051_MAS_RI_W; |
`OC8051_MOVX_AP : mem_act <= #1 `OC8051_MAS_DPTR_W; |
`OC8051_MOVX_IA : mem_act <= #1 `OC8051_MAS_RI_R; |
/trunk/rtl/verilog/oc8051_tc.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2003/04/10 12:43:19 simont |
// defines for pherypherals added |
// |
// Revision 1.7 2003/04/07 14:58:02 simont |
// change sfr's interface. |
// |
139,7 → 142,7
tf0 <= #1 1'b0; |
tf1_0 <= #1 1'b0; |
end else begin |
case (tmod[1:0]) |
case (tmod[1:0]) /* synopsys full_case parallel_case */ |
`OC8051_MODE0: begin // mode 0 |
tf1_0 <= #1 1'b0; |
if (tc0_add) |
173,10 → 176,10
{tf1_0, th0} <= #1 {1'b0, th0} +1'b1; |
|
end |
default:begin |
/* default:begin |
tf0 <= #1 1'b0; |
tf1_0 <= #1 1'b0; |
end |
end*/ |
endcase |
end |
end |
197,7 → 200,7
th1 <= #1 data_in; |
tf1_1 <= #1 1'b0; |
end else begin |
case (tmod[5:4]) |
case (tmod[5:4]) /* synopsys full_case parallel_case */ |
`OC8051_MODE0: begin // mode 0 |
if (tc1_add) |
{tf1_1, th1,tl1[4:0]} <= #1 {1'b0, th1, tl1[4:0]}+ 1'b1; |
219,9 → 222,9
end |
end |
end |
default:begin |
/* default:begin |
tf1_1 <= #1 1'b0; |
end |
end*/ |
endcase |
end |
end |
/trunk/rtl/verilog/oc8051_psw.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.11 2003/04/09 15:49:42 simont |
// Register oc8051_sfr dato output, add signal wait_data. |
// |
// Revision 1.10 2003/04/07 14:58:02 simont |
// change sfr's interface. |
// |
115,7 → 118,7
else if (wr & wr_bit & (wr_addr[7:3]==`OC8051_SFR_B_PSW)) |
data[wr_addr[2:0]] <= #1 cy_in; |
else begin |
case (set) |
case (set) /* synopsys full_case parallel_case */ |
`OC8051_PS_CY: begin |
// |
//write carry |
/trunk/rtl/verilog/oc8051_uart.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.14 2003/04/29 11:25:42 simont |
// prepared start of receiving if ren is not active. |
// |
// Revision 1.13 2003/04/10 08:57:16 simont |
// remove signal sbuf_txd [12:11] |
// |
186,7 → 189,7
// start transmiting |
// |
end else if (wr_sbuf) begin |
case (scon[7:6]) |
case (scon[7:6]) /* synopsys parallel_case */ |
2'b00: begin // mode 0 |
sbuf_txd <= #1 {3'b001, data_in}; |
end |
283,7 → 286,7
{sbuf_rxd_tmp, rx_done} <= #1 {rxd, sbuf_rxd_tmp}; |
end else if (receive & (scon[7:6]!=2'b00) & shift_re) begin //mode 1, 2, 3 |
re_count <= #1 re_count + 4'd1; |
case (re_count) |
case (re_count) /* synopsys full_case parallel_case */ |
4'h7: rx_sam[0] <= #1 rxd; |
4'h8: rx_sam[1] <= #1 rxd; |
4'h9: begin |