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URL https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk

Subversion Repositories axi4_tlm_bfm

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 19 to Rev 20
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Rev 19 → Rev 20

/axi4_tlm_bfm/trunk/tester/questa/waves.do
10,9 → 10,22
add wave -position end sim:/user/clk
add wave -position end sim:/user/nReset
add wave -position end sim:/user/irq_write
add wave -position end sim:/user/axiMaster/trigger
add wave -position end sim:/user/axiMaster/i_trigger
add wave -position end -hexadecimal sim:/user/prbs
 
# Paper publication:
#add wave -position end sim:/user/irq_write
#add wave -position end -hexadecimal sim:/user/axiMaster_in.tReady
#add wave -position end -hexadecimal sim:/user/axiMaster_out.tValid
#add wave -position end -hexadecimal sim:/user/axiMaster_out.tData
#add wave -position end -hexadecimal sim:/user/prbs
#add wave -position end -hexadecimal sim:/user/writeRequest.trigger
#add wave -position end -hexadecimal sim:/user/writeResponse.trigger
 
add wave -position end -expand -hexadecimal sim:/user/axiMaster_in
add wave -position end -expand -hexadecimal sim:/user/axiMaster_out
add wave -position end -expand -hexadecimal sim:/user/axiMaster/i_axiMaster_out
#add wave -position end -expand -hexadecimal sim:/user/axiMaster/i_axiMaster_out
add wave -position end -decimal sim:/user/readRequest
add wave -position end -expand -hexadecimal sim:/user/writeRequest
add wave -position end -decimal sim:/user/readResponse
20,8 → 33,22
add wave -position end -expand -hexadecimal sim:/user/writeResponse
add wave -position end sim:/user/txFSM
add wave -position end sim:/user/i_txFSM
add wave -position end -unsigned -format analog-step -height 80 -scale 0.4e-17 sim:/user/axiMaster_out.tData
 
#OS-VVM solution:
#add wave -position end -unsigned -format analog-step -height 80 -scale 0.4e-17 sim:/user/axiMaster_out.tData
 
#LFSR solution:
add wave -position end -unsigned -format analog-step -height 80 -scale 0.18e-7 sim:/user/axiMaster_out.tData
 
add wave -position end sim:/i_prbs/isParallelLoad
add wave -position end sim:/i_prbs/loadEn
add wave -position end sim:/i_prbs/loaded
add wave -position end sim:/i_prbs/i_loaded
add wave -position end sim:/i_prbs/load
add wave -position end -hexadecimal sim:/i_prbs/d
add wave -position end -hexadecimal sim:/i_prbs/seed
add wave -position end -hexadecimal sim:/user/prbs
 
run 80 ns;
 
wave zoomfull
/axi4_tlm_bfm/trunk/tester/questa/simulate.sh
39,18 → 39,21
vlib osvvm; vmap osvvm osvvm;
vlib tauhop; vmap tauhop tauhop;
 
vcom -2008 -work osvvm ../../rtl/packages/os-vvm/SortListPkg_int.vhd \
../../rtl/packages/os-vvm/RandomBasePkg.vhd \
../../rtl/packages/os-vvm/RandomPkg.vhd \
../../rtl/packages/os-vvm/CoveragePkg.vhd \
vcom -2008 -work osvvm ../../../rtl/packages/os-vvm/SortListPkg_int.vhd \
../../../rtl/packages/os-vvm/RandomBasePkg.vhd \
../../../rtl/packages/os-vvm/RandomPkg.vhd \
../../../rtl/packages/os-vvm/CoveragePkg.vhd \
| tee -ai ./simulate.log;
 
vcom -2008 -work tauhop ../../rtl/packages/pkg-tlm.vhdl \
../../rtl/packages/pkg-axi-tlm.vhdl \
vcom -2008 -work tauhop ../../../rtl/packages/pkg-tlm.vhdl \
../../../rtl/packages/pkg-axi-tlm.vhdl \
../../../rtl/packages/pkg-types.vhdl \
../../../rtl/axi4-stream-bfm-master.vhdl \
../../../rtl/galois-lfsr.vhdl \
../../../rtl/prbs-31.vhdl \
| tee -ai ./simulate.log;
 
vcom -2008 -work work ../../rtl/axi4-stream-bfm-master.vhdl \
../../rtl/user.vhdl \
vcom -2008 -work work ../../../rtl/user.vhdl \
| tee -ai ./simulate.log;
 
errorStr=`grep "\*\* Error: " ./simulate.log`

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