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URL https://opencores.org/ocsvn/async_8b10b_encoder_decoder/async_8b10b_encoder_decoder/trunk

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/async_8b10b_encoder_decoder/trunk/VECTLIB.vhd File deleted \ No newline at end of file
/async_8b10b_encoder_decoder/trunk/Enc8B10B.vhd
1,41 → 1,37
----------------------------------------------------------------------------------
-- Company : OCST Co.,Ltd.
-- Engineer : RyuShinHyung
--
-- Create Date : 02/23/2005
-- Design Name :
-- Module Name : ENC8B10B - RTL
-- Project Name : DSP Application
--
-- Revision
-- Revision 0.01 - File Created
-- Comments : General ENC8B10B
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.vect_pack.ALL;
 
entity ENC8B10B is
port
(
CLK_IN : in STD_LOGIC;
RUNDP_RESET_IN : in STD_LOGIC;
----------------------------------------------------------------------------------
-- Company : OCST Co.,Ltd.
-- Engineer : RyuShinHyung
--
-- Create Date : 02/23/2005
-- Design Name :
-- Module Name : ENC8B10B - RTL
-- Project Name : Fiber Optic Application
--
-- Revision
-- Revision 0.01 - File Created.
-- 1.00 - publishing on the opencores.org.
-- 1.01 - eliminate needing the VECTLIB.vhd in the original revision.(20110424)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity ENC8B10B is
port
(
CLK_IN : in STD_LOGIC;
RUNDP_RESET_IN : in STD_LOGIC;
CTRL_IN : in STD_LOGIC;
DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
RUNDP_OUT : out STD_LOGIC;
ENCODE_OUT : out STD_LOGIC_VECTOR(9 downto 0)
DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
RUNDP_OUT : out STD_LOGIC;
ENCODE_OUT : out STD_LOGIC_VECTOR(9 downto 0)
);
attribute FAST : string;
attribute SLOW : string;
attribute FAST of ENC8B10B : entity is "TRUE";
attribute SLOW of ENC8B10B : entity is "FALSE";
end ENC8B10B;
 
architecture RTL of ENC8B10B is
 
end ENC8B10B;
 
architecture RTL of ENC8B10B is
 
type TYPE_ENC8b10b is array (0 to 1023) of std_logic_vector (10 downto 0); -- RD & Dx.y
signal TBL_ENC8b10b : TYPE_ENC8b10b:=
(
1065,61 → 1061,58
"11110100001", -- "11111110" +K30.7+ [1022]
"11110001010" -- "11111111" +K31.7+ [1023]
);
 
constant ENC_K28D0R0 : std_logic_vector := "00010111100"; -- -1 + K28.0 => -1
constant ENC_K28D1R0 : std_logic_vector := "11001111100"; -- -1 + K28.1 => 1
constant ENC_K28D2R0 : std_logic_vector := "11010111100"; -- -1 + K28.2 => 1
constant ENC_K28D3R0 : std_logic_vector := "11100111100"; -- -1 + K28.3 => 1
constant ENC_K28D4R0 : std_logic_vector := "00100111100"; -- -1 + K28.4 => -1
constant ENC_K28D5R0 : std_logic_vector := "10101111100"; -- -1 + K28.5 => 1
 
constant ENC_K28D6R0 : std_logic_vector := "10110111100"; -- -1 + K28.6 => 1
constant ENC_K28D7R0 : std_logic_vector := "00001111100"; -- -1 + K28.7 => -1
constant ENC_K23D7R0 : std_logic_vector := "00001010111"; -- -1 + K23.7 => -1
constant ENC_K27D7R0 : std_logic_vector := "00001011011"; -- -1 + K27.7 => -1
constant ENC_K29D7R0 : std_logic_vector := "00001011101"; -- -1 + K29.7 => -1
constant ENC_K30D7R0 : std_logic_vector := "00001011110"; -- -1 + K30.7 => -1
constant ENC_K28D0R1 : std_logic_vector := "11101000011"; -- 1 + K28.0 => 1
constant ENC_K28D1R1 : std_logic_vector := "00110000011"; -- 1 + K28.1 => -1
constant ENC_K28D2R1 : std_logic_vector := "00101000011"; -- 1 + K28.2 => -1
constant ENC_K28D3R1 : std_logic_vector := "00011000011"; -- 1 + K28.3 => -1
constant ENC_K28D4R1 : std_logic_vector := "11011000011"; -- 1 + K28.4 => 1
constant ENC_K28D5R1 : std_logic_vector := "01010000011"; -- 1 + K28.5 => -1
constant ENC_K28D6R1 : std_logic_vector := "01001000011"; -- 1 + K28.6 => -1
constant ENC_K28D7R1 : std_logic_vector := "11110000011"; -- 1 + K28.7 => 1
constant ENC_K23D7R1 : std_logic_vector := "11110101000"; -- 1 + K23.7 => 1
constant ENC_K27D7R1 : std_logic_vector := "11110100100"; -- 1 + K27.7 => 1
constant ENC_K29D7R1 : std_logic_vector := "11110100010"; -- 1 + K29.7 => 1
constant ENC_K30D7R1 : std_logic_vector := "11110100001"; -- 1 + K30.7 => 1
constant DEC_K28D0 : std_logic_vector := "00011100"; -- K28.0
constant DEC_K28D1 : std_logic_vector := "00111100"; -- K28.1
constant DEC_K28D2 : std_logic_vector := "01011100"; -- K28.2
constant DEC_K28D3 : std_logic_vector := "01111100"; -- K28.3
constant DEC_K28D4 : std_logic_vector := "10011100"; -- K28.4
constant DEC_K28D5 : std_logic_vector := "10111100"; -- K28.5
constant DEC_K28D6 : std_logic_vector := "11011100"; -- K28.6
constant DEC_K28D7 : std_logic_vector := "11111100"; -- K28.7
constant DEC_K23D7 : std_logic_vector := "11110111"; -- K23.7
constant DEC_K27D7 : std_logic_vector := "11111011"; -- K27.7
constant DEC_K29D7 : std_logic_vector := "11111101"; -- K29.7
constant DEC_K30D7 : std_logic_vector := "11111110"; -- K30.7
 
 
 
signal ENCODE : std_logic_vector (10 downto 0);
begin
 
RUNDP_OUT <= ENCODE(10);
ENCODE_OUT <= ENCODE(9 downto 0);
process (CLK_IN)
begin
if (CLK_IN='1' and CLK_IN'event)
then
ENCODE <= TBL_ENC8b10b(conv_integer(CTRL_IN & ((not RUNDP_RESET_IN) and ENCODE(10)) & DATA_IN));
--ENCODE <=ENC_K28D5R0;
--ENCODE <= '0' & CTRL_IN & ENCODE(10) & DATA_IN;
end if;
end process;
end RTL;
 
 
constant ENC_K28D0R0 : std_logic_vector := "00010111100"; -- -1 + K28.0 => -1
constant ENC_K28D1R0 : std_logic_vector := "11001111100"; -- -1 + K28.1 => 1
constant ENC_K28D2R0 : std_logic_vector := "11010111100"; -- -1 + K28.2 => 1
constant ENC_K28D3R0 : std_logic_vector := "11100111100"; -- -1 + K28.3 => 1
constant ENC_K28D4R0 : std_logic_vector := "00100111100"; -- -1 + K28.4 => -1
constant ENC_K28D5R0 : std_logic_vector := "10101111100"; -- -1 + K28.5 => 1
 
constant ENC_K28D6R0 : std_logic_vector := "10110111100"; -- -1 + K28.6 => 1
constant ENC_K28D7R0 : std_logic_vector := "00001111100"; -- -1 + K28.7 => -1
constant ENC_K23D7R0 : std_logic_vector := "00001010111"; -- -1 + K23.7 => -1
constant ENC_K27D7R0 : std_logic_vector := "00001011011"; -- -1 + K27.7 => -1
constant ENC_K29D7R0 : std_logic_vector := "00001011101"; -- -1 + K29.7 => -1
constant ENC_K30D7R0 : std_logic_vector := "00001011110"; -- -1 + K30.7 => -1
constant ENC_K28D0R1 : std_logic_vector := "11101000011"; -- 1 + K28.0 => 1
constant ENC_K28D1R1 : std_logic_vector := "00110000011"; -- 1 + K28.1 => -1
constant ENC_K28D2R1 : std_logic_vector := "00101000011"; -- 1 + K28.2 => -1
constant ENC_K28D3R1 : std_logic_vector := "00011000011"; -- 1 + K28.3 => -1
constant ENC_K28D4R1 : std_logic_vector := "11011000011"; -- 1 + K28.4 => 1
constant ENC_K28D5R1 : std_logic_vector := "01010000011"; -- 1 + K28.5 => -1
constant ENC_K28D6R1 : std_logic_vector := "01001000011"; -- 1 + K28.6 => -1
constant ENC_K28D7R1 : std_logic_vector := "11110000011"; -- 1 + K28.7 => 1
constant ENC_K23D7R1 : std_logic_vector := "11110101000"; -- 1 + K23.7 => 1
constant ENC_K27D7R1 : std_logic_vector := "11110100100"; -- 1 + K27.7 => 1
constant ENC_K29D7R1 : std_logic_vector := "11110100010"; -- 1 + K29.7 => 1
constant ENC_K30D7R1 : std_logic_vector := "11110100001"; -- 1 + K30.7 => 1
constant DEC_K28D0 : std_logic_vector := "00011100"; -- K28.0
constant DEC_K28D1 : std_logic_vector := "00111100"; -- K28.1
constant DEC_K28D2 : std_logic_vector := "01011100"; -- K28.2
constant DEC_K28D3 : std_logic_vector := "01111100"; -- K28.3
constant DEC_K28D4 : std_logic_vector := "10011100"; -- K28.4
constant DEC_K28D5 : std_logic_vector := "10111100"; -- K28.5
constant DEC_K28D6 : std_logic_vector := "11011100"; -- K28.6
constant DEC_K28D7 : std_logic_vector := "11111100"; -- K28.7
constant DEC_K23D7 : std_logic_vector := "11110111"; -- K23.7
constant DEC_K27D7 : std_logic_vector := "11111011"; -- K27.7
constant DEC_K29D7 : std_logic_vector := "11111101"; -- K29.7
constant DEC_K30D7 : std_logic_vector := "11111110"; -- K30.7
 
signal ENCODE : std_logic_vector (10 downto 0);
begin
 
RUNDP_OUT <= ENCODE(10);
ENCODE_OUT <= ENCODE(9 downto 0);
process (CLK_IN)
begin
if (CLK_IN='1' and CLK_IN'event)
then
ENCODE <= TBL_ENC8b10b(conv_integer(CTRL_IN & ((not RUNDP_RESET_IN) and ENCODE(10)) & DATA_IN));
end if;
end process;
 
end RTL;
 
/async_8b10b_encoder_decoder/trunk/Dec8B10B.vhd
1,39 → 1,35
----------------------------------------------------------------------------------
-- Company : OCST Co.,Ltd.
-- Engineer : RyuShinHyung
--
-- Create Date : 02/23/2005
-- Design Name :
-- Module Name : DEC8B10B - RTL
-- Project Name : DSP Application
--
-- Revision
-- Revision 0.01 - File Created
-- Comments : General DEC8B10B
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.vect_pack.ALL;
 
entity DEC8B10B is
port
----------------------------------------------------------------------------------
-- Company : OCST Co.,Ltd.
-- Engineer : RyuShinHyung
--
-- Create Date : 02/23/2005
-- Design Name :
-- Module Name : DEC8B10B - RTL
-- Project Name : Fiber Optic Application
--
-- Revision
-- Revision 0.01 - File Created
-- 1.00 - publishing on the opencores.org
-- 1.01 - eliminate needing the VECTLIB.vhd in the original revision.(20110424)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity DEC8B10B is
port
(
CLK_IN : IN STD_LOGIC;
ENCODE_IN : in STD_LOGIC_VECTOR(9 downto 0);
CTRL_OUT : out STD_LOGIC;
DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0)
);
--attribute FAST : string;
--attribute SLOW : string;
--attribute FAST of DEC8B10B : entity is "TRUE";
--attribute SLOW of DEC8B10B : entity is "FALSE";
end DEC8B10B;
 
architecture RTL of DEC8B10B is
 
CLK_IN : IN STD_LOGIC;
ENCODE_IN : in STD_LOGIC_VECTOR(9 downto 0);
CTRL_OUT : out STD_LOGIC;
DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0)
);
end DEC8B10B;
 
architecture RTL of DEC8B10B is
 
constant DEC8b10bERR : std_logic_vector := "100000000";
type TYPE_DEC8b10b is array (0 to 1023) of std_logic_vector (8 downto 0); -- Ctrl & Value
signal TBL_DEC8b10b : TYPE_DEC8b10b:=
1063,22 → 1059,22
DEC8b10bERR, -- "1111111110"
DEC8b10bERR -- "1111111111"
);
 
 
 
 
signal DECODE : std_logic_vector (8 downto 0);
 
begin
 
CTRL_OUT <= DECODE(8);
DATA_OUT <= DECODE(7 downto 0);
process (CLK_IN)
 
begin
 
CTRL_OUT <= DECODE(8);
DATA_OUT <= DECODE(7 downto 0);
process (CLK_IN)
begin
if(CLK_IN = '1' and CLK_IN'event)
then
then
DECODE <= TBL_DEC8B10B(conv_integer(ENCODE_IN));
end if;
end process;
 
end RTL;
 
end if;
end process;
 
end RTL;
 

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