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/trunk/rtl/verilog/ae18_core_tb.v
0,0 → 1,140
// -*- Mode: Verilog -*-
// Filename : ae18_core_tb.v
// Description : AE18 Simulation Testbench
// Author : Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
// Created On : Fri Dec 29 05:02:51 2006
// Last Modified By: Shawn Tan
// Last Modified On: 2006-12-29
// Update Count : 0
// Status : Beta/Stable
 
/*
*
* $Id: ae18_core_tb.v,v 1.1 2006-12-29 08:17:16 sybreon Exp $
*
* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
*
* This library is free software; you can redistribute it and/or modify it
* under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation; either version 2.1 of the License,
* or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
* License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* DESCRIPTION
* Simple unit test with fake ROM and fake RAM contents. It loads the ROM
* from the ae18_core.rom file. This file will usually contain the test
* software from ae18_core.asm in the software directory.
*
* 2006-12-29
* Initial Checkin
*/
 
module ae18_core_tb (/*AUTOARG*/);
parameter ISIZ = 16;
parameter DSIZ = 10;
wire [ISIZ-1:1] iwb_adr_o;
wire [DSIZ-1:0] dwb_adr_o;
wire [7:0] dwb_dat_o;
wire [7:0] dwb_dat_i;
wire [15:0] iwb_dat_o;
wire [1:0] iwb_sel_o;
wire iwb_stb_o, iwb_we_o, dwb_stb_o, dwb_we_o;
wire [1:0] qfsm_o, qmod_o;
wire [3:0] qena_o;
 
reg clk, rst;
reg [1:0] int_i;
reg dwb_ack_i, iwb_ack_i;
reg [15:0] iwb_dat_i;
 
// Dump Files
initial begin
$dumpfile("ae18_core.vcd");
$dumpvars(1, iwb_adr_o,iwb_dat_i,iwb_stb_o,iwb_we_o,iwb_sel_o);
$dumpvars(1, dwb_adr_o,dwb_dat_i,dwb_dat_o,dwb_we_o,dwb_stb_o);
$dumpvars(1, clk,int_i);
$dumpvars(1, dut);
end
 
initial begin
clk = 1;
rst = 0;
int_i = 2'b00;
 
#50 rst = 1;
#20000 int_i = 2'b10;
#50 int_i = 2'b00;
end
 
// Test Points
initial fork
#20000 if (dut.rFSM != 2'b11) $display("*** SLEEP error ***");
#30000 if (dut.rFSM != 2'b00) $display("*** WAKEUP error ***");
#40000 if (dut.rFSM != 2'b11) $display("*** RESET error ***");
#60000 if (dut.rFSM != 2'b00) $display("*** WDT error ***");
#70000 if (dut.rFSM == 2'b11) $display("Test response OK!!");
#80000
$finish;
join
always #5 clk = ~clk;
 
reg [15:0] rom [0:65535];
 
// Load ROM contents
initial begin
$readmemh ("ae18_core.rom", rom);
end
 
// Fake Memory Signals
always @(posedge clk) begin
dwb_ack_i <= dwb_stb_o;
iwb_ack_i <= iwb_stb_o;
if (iwb_stb_o) iwb_dat_i <= rom[iwb_adr_o];
end
 
ae18_sram #(8,DSIZ)
ram (
.radr(dwb_adr_o), .wadr(dwb_adr_o),
.rdat(dwb_dat_i), .wdat(dwb_dat_o),
.we(dwb_we_o & dwb_stb_o),
// Inputs
.clk (clk));
 
// AE18 test core
ae18_core #(ISIZ,DSIZ,11)
dut (
.clk_i(clk), .rst_i(rst),
.inte_i(2'b11),
// Outputs
.wb_clk_o (wb_clk_o),
.wb_rst_o (wb_rst_o),
.iwb_adr_o (iwb_adr_o),
.iwb_dat_o (iwb_dat_o[15:0]),
.iwb_stb_o (iwb_stb_o),
.iwb_we_o (iwb_we_o),
.iwb_sel_o (iwb_sel_o[1:0]),
.dwb_adr_o (dwb_adr_o),
.dwb_dat_o (dwb_dat_o[7:0]),
.dwb_stb_o (dwb_stb_o),
.dwb_we_o (dwb_we_o),
//.qena_o (qena_o[3:0]),
//.qfsm_o (qfsm_o[1:0]),
//.qmod_o (qmod_o[1:0]),
// Inputs
.iwb_dat_i (iwb_dat_i[15:0]),
.iwb_ack_i (iwb_ack_i),
.dwb_dat_i (dwb_dat_i[7:0]),
.dwb_ack_i (dwb_ack_i),
.int_i (int_i[1:0]));
endmodule // ae18_core_tb
/trunk/rtl/verilog/ae18_aram.v
0,0 → 1,61
// -*- Mode: Verilog -*-
// Filename : ae18_aram.v
// Description : AE18 Asynchronous RAM
// Author : Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
// Created On : Fri Dec 29 05:12:35 2006
// Last Modified By: Shawn Tan
// Last Modified On: 2006-12-29
// Update Count : 0
// Status : Unknown, Use with caution!
 
/*
*
* $Id: ae18_aram.v,v 1.1 2006-12-29 08:17:16 sybreon Exp $
*
* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
*
* This library is free software; you can redistribute it and/or modify it
* under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation; either version 2.1 of the License,
* or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
* License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* DESCRIPTION
* Basic asynchronous inferred RAM.
*
* 2006-12-29
* Initial Checkin
*/
 
module ae18_aram (/*AUTOARG*/
// Outputs
rdat,
// Inputs
wdat, radr, wadr, we, clk
);
parameter ISIZ = 24;
parameter SSIZ = 5;
 
output [ISIZ-1:0] rdat;
input [ISIZ-1:0] wdat;
input [SSIZ-1:0] radr, wadr;
input we;
input clk;
 
reg [ISIZ-1:0] rMEM [0:(1<<SSIZ)-1];
 
assign rdat = rMEM[radr];
always @(posedge clk) begin
if (we) rMEM[wadr] <= #1 wdat;
end
endmodule // ae18_sram
/trunk/rtl/verilog/ae18_sram.v
0,0 → 1,63
// -*- Mode: Verilog -*-
// Filename : ae18_sram.v
// Description : AE18 Synchronous RAM
// Author :
// Created On : Fri Dec 29 05:12:03 2006
// Last Modified By: .
// Last Modified On: .
// Update Count : 0
// Status : Unknown, Use with caution!
 
/*
*
* $Id: ae18_sram.v,v 1.1 2006-12-29 08:17:16 sybreon Exp $
*
* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
*
* This library is free software; you can redistribute it and/or modify it
* under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation; either version 2.1 of the License,
* or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
* License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* DESCRIPTION
* AE18 small block of RAM.
*
* 2006-12-29
* Initial checkin
*/
 
module ae18_sram (/*AUTOARG*/
// Outputs
rdat,
// Inputs
wdat, radr, wadr, we, clk
);
parameter ISIZ = 24;
parameter SSIZ = 5;
 
output [ISIZ-1:0] rdat;
input [ISIZ-1:0] wdat;
input [SSIZ-1:0] radr, wadr;
input we;
input clk;
 
reg [SSIZ-1:0] rADR;
reg [ISIZ-1:0] rMEM [0:(1<<SSIZ)-1];
 
assign rdat = rMEM[rADR];
always @(posedge clk) begin
if (we) rMEM[wadr] <= #1 wdat;
rADR <= #1 radr;
end
endmodule // ae18_sram
/trunk/rtl/verilog/ae18_core.v
4,11 → 4,13
// Author : Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
// Created On : Fri Dec 22 16:09:33 2006
// Last Modified By: Shawn Tan
// Last Modified On: 2006-12-28
// Last Modified On: 2006-12-29
// Update Count : 0
// Status : Unknown, Use with caution!
// Status : Beta/Stable
 
/*
* $Id: ae18_core.v,v 1.2 2006-12-29 08:17:16 sybreon Exp $
*
* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
*
* This library is free software; you can redistribute it and/or modify it
32,8 → 34,11
* need to be integrated with the core. This core provides the necessary
* signals to wire up WISHBONE compatible devices to it.
*
* 2006-12-29
* Fixed minor bug with BCC and TBL instructions.
*
* 2006-12-27
* Mostly working.
* CVS Checkin
*/
 
module ae18_core (/*AUTOARG*/
263,7 → 268,7
*/
// WB Registers
reg [ISIZ-2:0] rIWBADR;
reg [23:0] rIWBADR;
reg rIWBSTB, rIWBWE;
reg [1:0] rIWBSEL;
//reg [15:0] rIDAT;
285,7 → 290,7
if (!qrst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rIWBADR <= {(1+(ISIZ-2)){1'b0}};
rIWBADR <= 24'h0;
// End of automatics
end else if (qrun)
case (qfsm)
341,7 → 346,7
case (qfsm)
FSM_Q0: rROMLAT <= #1 iwb_dat_i;
FSM_Q3: rIREG <= #1 rROMLAT;
FSM_Q2: rILAT <= (rTBLPTRL[0]) ? iwb_dat_i[15:8] : iwb_dat_i[7:0];
FSM_Q2: rILAT <= (rTBLPTRL[0]) ? iwb_dat_i[7:0] : iwb_dat_i[15:8];
endcase // case(qfsm)
end
 
1078,9 → 1083,9
// Beginning of autoreset for uninitialized flops
rBCC <= 1'h0;
// End of automatics
end else if (qena[1] & rNSKP) begin
end else if (qena[0]) begin
case (rMXBCC)
default: rBCC <= #1 rZ;
MXBCC_BZ: rBCC <= #1 rZ;
MXBCC_BNZ: rBCC <= #1 ~rZ;
MXBCC_BC: rBCC <= #1 rC;
MXBCC_BNC: rBCC <= #1 ~rC;
1088,8 → 1093,8
MXBCC_BNOV: rBCC <= #1 ~rOV;
MXBCC_BN: rBCC <= #1 rN;
MXBCC_BNN: rBCC <= #1 ~rN;
endcase // case(rMXBCC)
end // if (qena[1] & rNSKP)
endcase // case(rMXBCC)
end
// SKIP register
wire wSKP =
1116,8 → 1121,7
.radr(rSTKPTR[4:0]), .wadr(rSTKPTR_[4:0]),
.we(wSTKE),
// Inputs
.clk (clk),
.rst (rst));
.clk (clk));
/*
* DESCRIPTION
1593,173 → 1597,3
end
endmodule // ae18_core
 
/*
* DESCRIPTION
* AE18 small block of RAM. Contains both synchronous and asynchronous
* RAM implementations. Use async RAM if possible to avoid inferring a
* large block of RAM.
*/
 
module ae18_sram (/*AUTOARG*/
// Outputs
rdat,
// Inputs
wdat, radr, wadr, we, clk, rst
);
parameter ISIZ = 24;
parameter SSIZ = 5;
 
output [ISIZ-1:0] rdat;
input [ISIZ-1:0] wdat;
input [SSIZ-1:0] radr, wadr;
input we;
input clk, rst;
 
reg [SSIZ-1:0] rADR;
reg [ISIZ-1:0] rMEM [0:(1<<SSIZ)-1];
 
assign rdat = rMEM[rADR];
always @(posedge clk) begin
if (we) rMEM[wadr] <= #1 wdat;
rADR <= #1 radr;
end
endmodule // ae18_sram
 
module ae18_aram (/*AUTOARG*/
// Outputs
rdat,
// Inputs
wdat, radr, wadr, we, clk, rst
);
parameter ISIZ = 24;
parameter SSIZ = 5;
 
output [ISIZ-1:0] rdat;
input [ISIZ-1:0] wdat;
input [SSIZ-1:0] radr, wadr;
input we;
input clk, rst;
 
reg [ISIZ-1:0] rMEM [0:(1<<SSIZ)-1];
 
assign rdat = rMEM[radr];
always @(posedge clk) begin
if (we) rMEM[wadr] <= #1 wdat;
end
endmodule // ae18_sram
 
 
/*
* DESCRIPTION
* Simple unit test with fake ROM and fake RAM contents. It loads the ROM
* from the ae18_core.rom file. This file will usually contain the test
* software from ae18_core.asm in the software directory.
*/
 
module ae18_core_tb (/*AUTOARG*/);
parameter ISIZ = 16;
parameter DSIZ = 10;
wire [ISIZ-1:1] iwb_adr_o;
wire [DSIZ-1:0] dwb_adr_o;
wire [7:0] dwb_dat_o;
wire [7:0] dwb_dat_i;
wire [15:0] iwb_dat_o;
wire [1:0] iwb_sel_o;
wire iwb_stb_o, iwb_we_o, dwb_stb_o, dwb_we_o;
wire [1:0] qfsm_o, qmod_o;
wire [3:0] qena_o;
 
reg clk, rst;
reg [1:0] int_i;
reg dwb_ack_i, iwb_ack_i;
reg [15:0] iwb_dat_i;
 
// Dump Files
initial begin
$dumpfile("ae18_core.vcd");
$dumpvars(1, iwb_adr_o,iwb_dat_i,iwb_stb_o,iwb_we_o,iwb_sel_o);
$dumpvars(1, dwb_adr_o,dwb_dat_i,dwb_dat_o,dwb_we_o,dwb_stb_o);
$dumpvars(1, clk,int_i);
$dumpvars(1, dut);
end
 
initial begin
clk = 1;
rst = 0;
int_i = 2'b00;
 
#50 rst = 1;
#20000 int_i = 2'b10;
#50 int_i = 2'b00;
end
 
// Test Points
initial fork
#20000 if (dut.rFSM != 2'b11) $display("*** SLEEP error ***");
#30000 if (dut.rFSM != 2'b00) $display("*** WAKEUP error ***");
#40000 if (dut.rFSM != 2'b11) $display("*** RESET error ***");
#60000 if (dut.rFSM != 2'b00) $display("*** WDT error ***");
#70000 if (dut.rFSM == 2'b11) $display("Test response OK!!");
#80000
$finish;
join
always #5 clk = ~clk;
 
reg [15:0] rom [0:65535];
 
// Load ROM contents
initial begin
$readmemh ("ae18_core.rom", rom);
end
 
// Fake Memory Signals
always @(posedge clk) begin
dwb_ack_i <= dwb_stb_o;
iwb_ack_i <= iwb_stb_o;
if (iwb_stb_o) iwb_dat_i <= rom[iwb_adr_o];
end
 
ae18_sram #(8,DSIZ)
ram (
.radr(dwb_adr_o), .wadr(dwb_adr_o),
.rdat(dwb_dat_i), .wdat(dwb_dat_o),
.we(dwb_we_o & dwb_stb_o),
// Inputs
.clk (clk),
.rst (rst));
 
// AE18 test core
ae18_core #(ISIZ,DSIZ,11)
dut (
.clk_i(clk), .rst_i(rst),
.inte_i(2'b11),
// Outputs
.wb_clk_o (wb_clk_o),
.wb_rst_o (wb_rst_o),
.iwb_adr_o (iwb_adr_o),
.iwb_dat_o (iwb_dat_o[15:0]),
.iwb_stb_o (iwb_stb_o),
.iwb_we_o (iwb_we_o),
.iwb_sel_o (iwb_sel_o[1:0]),
.dwb_adr_o (dwb_adr_o),
.dwb_dat_o (dwb_dat_o[7:0]),
.dwb_stb_o (dwb_stb_o),
.dwb_we_o (dwb_we_o),
//.qena_o (qena_o[3:0]),
//.qfsm_o (qfsm_o[1:0]),
//.qmod_o (qmod_o[1:0]),
// Inputs
.iwb_dat_i (iwb_dat_i[15:0]),
.iwb_ack_i (iwb_ack_i),
.dwb_dat_i (dwb_dat_i[7:0]),
.dwb_ack_i (dwb_ack_i),
.int_i (int_i[1:0]));
endmodule // ae18_core_tb
/trunk/sim/ae18_core.rom
2,7 → 2,7
F000
EF02
F000
EF0C
EF13
F001
0000
0000
10,25 → 10,25
0000
0000
0000
EF0C
EF13
F001
0000
0000
0004
D8DE
D8D4
D86A
D8BD
D8AC
D89A
D87E
D841
D86D
D8DF
D8C0
D830
D816
D80B
D8E5
D8DB
D870
D8C4
D8B3
D8A0
D884
D847
D873
D8E6
D8C7
D836
D81C
D811
D805
0003
0000
35,13 → 35,19
0000
00FF
D7FF
6AF7
6AF6
0009
50F5
0A10
E1FF
0009
0009
0009
50F5
0AEF
E1FF
0C00
0EA5
ED30
ED36
F000
0AA5
E1FF
190,6 → 196,7
2A22
0622
1822
0AFF
E1FF
0C00
0EA5
239,15 → 246,15
E1FF
0C00
D002
EFF1
EFF8
F000
D003
0012
EFF5
EFFC
F000
D7FC
EFF8
F000
EFFF
F001
0E0A
6E20
0DA0
/trunk/sim/cversim
1,2 → 1,4
#!/bin/sh
cver ../rtl/verilog/ae18_core.v
# $Id: cversim,v 1.2 2006-12-29 08:17:16 sybreon Exp $
#
cver ../rtl/verilog/*.v $@
/trunk/sim/iversim
1,2 → 1,4
#!/bin/sh
iverilog -I ../rtl/verilog ../rtl/verilog/ae18_core.v && vvp a.out && rm a.out
# $Id: iversim,v 1.2 2006-12-29 08:17:16 sybreon Exp $
#
iverilog ../rtl/verilog/*.v $@ && vvp a.out && rm a.out
/trunk/sw/asm/ae18_core.asm
1,4 → 1,6
;;;
;;; $Id: ae18_core.asm,v 1.2 2006-12-29 08:17:17 sybreon Exp $
;;;
;;; Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
;;;
;;; This library is free software; you can redistribute it and/or modify it
76,7 → 78,7
rcall _SHA_TEST
rcall _TBL_TEST
 
 
;; All tests OK!!
sleep
 
92,13 → 94,19
 
;;
;; TABLE tests - OK
;; Tests to check that TBLWT/TBLRD are working
;; Tests to check that TBLRD is working
;;
_TBL_TEST:
clrf TBLPTRH
clrf TBLPTRL
tblrd*+ ; TABLAT = 10
movf TABLAT,W
xorlw 0x10
bnz $
tblrd*+ ; TABLAT = EF
tblrd*+ ; TABLAT = 00
tblrd*+ ; TABLAT = FF
movf TABLAT,W
xorlw 0xEF
bnz $
retlw 0x00
;;
318,7 → 326,8
incf reg2,F ; REG2 = 0x5B
decf reg2,F ; REG2 = 0x5A
 
xorwf reg2,W ; WREG = 0x00
xorwf reg2,W ; WREG = 0xFF
xorlw 0xFF
bnz $
retlw 0x00
 
/trunk/sw/makerom
1,2 → 1,4
#!/bin/sh
# $Id: makerom,v 1.2 2006-12-29 08:17:17 sybreon Exp $
#
gpasm -c -o rom $1 && gplink -o rom rom.o && objcopy -I ihex -O binary rom.hex rom.bin && hexdump -v -e'1/2 "%.4X\n"' rom.bin > rom.rom && mv rom.rom ../sim/ae18_core.rom && mv rom.lst makerom.lst && rm rom.*

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