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/tags/TAG000/bench/verilog/debouncer_tb.v

/tags/TAG000/bench/verilog/arbiter_tb.v

/tags/TAG000/bench/verilog/bc_fifo_basic_tb.v

/tags/TAG000/bench/verilog/random_ff_tb.v

/tags/TAG000/bench/verilog/clock_switch_tb.v

/tags/TAG000/bench/verilog/clock_detect_tb.v

/tags/TAG000/bench/verilog/oc_fifo_basic_tb.v

/tags/TAG000/rtl/testbench/standard.cmd

tags/TAG000/rtl/testbench/standard.cmd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/TAG000/rtl/verilog/random_ff.v =================================================================== --- tags/TAG000/rtl/verilog/random_ff.v (nonexistent) +++ tags/TAG000/rtl/verilog/random_ff.v (revision 3) @@ -0,0 +1,211 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// random_ff.v //// +//// //// +//// This file is part of the boundaries opencores effort. //// +//// //// +//// //// +//// Module Description: //// +//// //// +//// This model of a set/reset D flipflop emits a random 0 or 1 //// +//// on a setup or hold violation; instead of going X like most //// +//// simulation models of D flipflops. Its output DOES go X if //// +//// the CLK, SETN, or CLRN inputs become undefined. //// +//// Not intended for synthesis. //// +//// //// +//// To Do: //// +//// Done. //// +//// //// +//// Author(s): //// +//// - Shannon Hill //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Shannon Hill and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// $Id: random_ff.v,v 1.1 2004-07-07 12:41:17 esquehill Exp $ +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// +// +module random_ff( /*AUTOARG*/ +// Outputs +Q, +// Inputs +D, CLK, CLRN, SETN, SI, SE +); + +input D; +input CLK; +output Q; +input CLRN; // reset when 0 +input SETN; // preset when 0 +input SI; // scan input +input SE; // scan enable + +parameter D2Q = 0.200; // Q delay + +// synopsys translate_off + +reg Q; +reg syn_notify; +reg asy_notify; +integer seed; + +initial +begin +seed = 19827; +syn_notify = 0; +asy_notify = 0; +end + +wire se_check; +wire dq_check; +wire sq_check; + +and u_se_check ( se_check, CLRN, SETN ); +and u_dq_check ( dq_check, CLRN, SETN, ~SE ); +and u_sq_check ( sq_check, CLRN, SETN, SE ); + +wire CLK_is_X = (CLK ===0) ? 1'b0 : ((CLK ===1) ? 1'b0 : ($stime > 0)); +wire CLR_is_X = (CLRN===0) ? 1'b0 : ((CLRN===1) ? 1'b0 : ($stime > 0)); +wire SET_is_X = (SETN===0) ? 1'b0 : ((SETN===1) ? 1'b0 : ($stime > 0)); + +wire #0.1 old_CLK = CLK; // X->1 should NOT work like a 0->1 edge + +// +// handle CLK input +// +always @( posedge CLK ) +begin + case( SE | old_CLK ) + 1'b0: Q <= #(D2Q) D; + 1'b1: Q <= #(D2Q) SI; + default: Q <= #(D2Q) 1'bX; + endcase +end + +// +// handle async inputs +// +always @( negedge CLRN or negedge SETN ) +begin + case( { SETN, CLRN } ) + + 2'b00: Q <= #(D2Q)1'b1; // both set & clr????? + + 2'b0Z, + 2'b0X, // set wins + 2'b01: Q <= #(D2Q)1'b1; + + 2'bZ0, + 2'bX0, // clr wins + 2'b10: Q <= #(D2Q)1'b0; + + default: Q <= #(D2Q)1'bX; // no good... + endcase +end + +// +// handle CLK, CLRN, or SETN going X/Z (Q -> X). +// handle setup/hold violation (Q -> 0 or 1). +// + +always @( syn_notify or posedge CLK_is_X or posedge CLR_is_X or posedge SET_is_X ) +if( CLK_is_X | CLR_is_X | SET_is_X ) +begin + Q <= 1'bX; + Q <= #(D2Q) 1'bX; +end +else +begin + Q <= 1'bX; + Q <= #(D2Q) $random(seed); +end + +// +// all these specparams are technology-specific; +// just provide place-holders for now... +// Note: Don't expect the testbench to work after you change all these values. +// + +specify +specparam + r_width = 0.48, + p_width = 0.49, + d_setup = 0.50, + d_hold = 0.51, + si_setup = 0.52, + si_hold = 0.53, + se_setup = 0.54, + se_hold = 0.55, + r_setup = 0.56, + r_hold = 0.57, + p_setup = 0.59, + p_hold = 0.60, + rvp_setup = 0.62, // reset vs. preset + rvp_hold = 0.63; + +// While no SETN and no CLRN and no SE; +// If D changes near CLK, Q is uncertain +$setuphold( posedge CLK &&& (dq_check===1), posedge D , d_setup, d_hold, syn_notify ); +$setuphold( posedge CLK &&& (dq_check===1), negedge D , d_setup, d_hold, syn_notify ); + +// While no SETN and no CLRN; +// If SE changes near CLK, Q is uncertain +$setuphold( posedge CLK &&& (se_check===1), posedge SE, se_setup, se_hold, syn_notify ); +$setuphold( posedge CLK &&& (se_check===1), negedge SE, se_setup, se_hold, syn_notify ); + +// While no SETN and no CLRN and is SE; +// If SI changes near CLK, Q is uncertain +$setuphold( posedge CLK &&& (sq_check===1), posedge SI, si_setup, si_hold, syn_notify ); +$setuphold( posedge CLK &&& (sq_check===1), negedge SI, si_setup, si_hold, syn_notify ); + +// While no SETN; +// If CLRN de-asserts near CLK, it's uncertain which wins; CLRN or CLK. +$setuphold( posedge CLK &&& (SETN===1), posedge CLRN, r_setup , r_hold, asy_notify ); + +// While no CLRN; +// If SETN de-asserts near CLK, it's uncertain which wins; SETN or CLK. +$setuphold( posedge CLK &&& (CLRN===1), posedge SETN, p_setup , p_hold, asy_notify ); + +// If CLRN de-asserts near SETN deassertion, it's uncertain which wins; SETN or CLRN. +$setuphold( posedge CLRN, posedge SETN, rvp_setup, rvp_hold, asy_notify ); + +// check for narrow CLRNs +$width( negedge CLRN, r_width , 0, asy_notify ); + +// check for narrow SETNs +$width( negedge SETN, p_width , 0, asy_notify ); + +endspecify + +// synopsys translate_on + +endmodule + Index: tags/TAG000/rtl/verilog/clock_switch2_basic.v =================================================================== --- tags/TAG000/rtl/verilog/clock_switch2_basic.v (nonexistent) +++ tags/TAG000/rtl/verilog/clock_switch2_basic.v (revision 3) @@ -0,0 +1,102 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// clock_switch2_basic.v //// +//// //// +//// This file is part of the boundaries opencores effort. //// +//// //// +//// //// +//// Module Description: //// +//// //// +//// 1-of-2 glitchless clock switcher //// +//// //// +//// The 2 clocks, enable, and select are assumed to be //// +//// asynchronous. //// +//// //// +//// Selecting/deselecting a stopped clock is not handled. //// +//// //// +//// To Do: //// +//// Verify in silicon. //// +//// //// +//// Author(s): //// +//// - Shannon Hill //// +//// (based on "Techniques to make clock switching glitch free" //// +//// By Rafey Mahmud; EEdesign.com June 26, 2003) //// +//// //// +//// http://www.eedesign.com/showArticle.jhtml?articleID=16501239 //// +//// //// +//// (modified to use positive edge flops; to stall the output //// +//// clock high). //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Shannon Hill and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// $Id: clock_switch2_basic.v,v 1.1 2004-07-07 12:41:17 esquehill Exp $ +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// +// +module clock_switch2_basic( /*AUTOARG*/ +// Outputs +clk_o, +// Inputs +rst0_i, clk0_i, rst1_i, clk1_i, enable, select +); + +input rst0_i; +input clk0_i; + +input rst1_i; +input clk1_i; + +input enable; // start&stop the clock +input select; // select which source clock +output clk_o; + +wire sel0 = ~select & enable; +wire sel1 = select & enable; + +reg [1:0] ssync0; // selection synchronizers +reg [1:0] ssync1; + +always @( posedge clk0_i or posedge rst0_i) +if( rst0_i ) + ssync0 <= 2'b0; +else ssync0 <= { ssync0[0] , (sel0 & ~ssync1[1] ) }; // async input + +always @( posedge clk1_i or posedge rst1_i) +if( rst1_i ) + ssync1 <= 2'b0; +else ssync1 <= { ssync1[0] , (sel1 & ~ssync0[1] ) }; // async input + +wire gclk0 = ~ssync0[1] | clk0_i; // forced 1 when not selected +wire gclk1 = ~ssync1[1] | clk1_i; // forced 1 when not selected + +wire clk_o = gclk0 & gclk1; // clock stalls high + +endmodule Index: tags/TAG000/rtl/verilog/clock_switch3_basic.v =================================================================== --- tags/TAG000/rtl/verilog/clock_switch3_basic.v (nonexistent) +++ tags/TAG000/rtl/verilog/clock_switch3_basic.v (revision 3) @@ -0,0 +1,120 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// clock_switch3_basic.v //// +//// //// +//// This file is part of the boundaries opencores effort. //// +//// //// +//// //// +//// Module Description: //// +//// //// +//// 1-of-3 glitchless clock switcher //// +//// //// +//// The 3 clocks, enable, and select are assumed to be //// +//// asynchronous. //// +//// //// +//// Selecting/deselecting a stopped clock is not handled. //// +//// //// +//// To Do: //// +//// Verify in silicon. //// +//// //// +//// Author(s): //// +//// - Shannon Hill //// +//// (based on "Techniques to make clock switching glitch free" //// +//// By Rafey Mahmud; EEdesign.com June 26, 2003) //// +//// //// +//// http://www.eedesign.com/showArticle.jhtml?articleID=16501239 //// +//// //// +//// (modified to use only positive edge flops; stall the output //// +//// clock high). //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Shannon Hill and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// $Id: clock_switch3_basic.v,v 1.1 2004-07-07 12:41:17 esquehill Exp $ +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// +// +module clock_switch3_basic( /*AUTOARG*/ +// Outputs +clk_o, +// Inputs +rst0_i, clk0_i, rst1_i, clk1_i, rst2_i, clk2_i, enable, select +); + +input rst0_i; +input clk0_i; +input rst1_i; +input clk1_i; +input rst2_i; +input clk2_i; +input enable; // start&stop output clock +input [1:0] select; // select source clock +output clk_o; + +reg [1:0] ssync0; // select synchronizers... +reg [1:0] ssync1; +reg [1:0] ssync2; + +reg [2:0] decode; // 1-of-3 decode + +always @( select or enable ) +begin + decode = 3'b000; + case( select ) + 2'b00: decode[0] = enable; + 2'b01: decode[1] = enable; + 2'b10: decode[2] = enable; + 2'b11: decode[2] = enable; // same as 2 + default: decode = 3'b000; + endcase +end + +always @( posedge clk0_i or posedge rst0_i ) +if( rst0_i ) + ssync0 <= 2'b0; +else ssync0 <= { ssync0[0], ( decode[0] & ~ssync1[1] & ~ssync2[1] ) }; // async input + +always @( posedge clk1_i or posedge rst1_i ) +if( rst1_i ) + ssync1 <= 2'b0; +else ssync1 <= { ssync1[0], (~ssync0[1] & decode[1] & ~ssync2[1] ) }; // async input + +always @( posedge clk2_i or posedge rst2_i ) +if( rst2_i ) + ssync2 <= 2'b0; +else ssync2 <= { ssync2[0], (~ssync0[1] & ~ssync1[1] & decode[2] ) }; // async input + +wire gclk0 = ~ssync0[1] | clk0_i; // forced high when not selected +wire gclk1 = ~ssync1[1] | clk1_i; // forced high when not selected +wire gclk2 = ~ssync2[1] | clk2_i; // forced high when not selected + +wire clk_o = gclk0 & gclk1 & gclk2; // clock stalls high + +endmodule Index: tags/TAG000/rtl/verilog/clock_switch4_basic.v =================================================================== --- tags/TAG000/rtl/verilog/clock_switch4_basic.v (nonexistent) +++ tags/TAG000/rtl/verilog/clock_switch4_basic.v (revision 3) @@ -0,0 +1,130 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// clock_switch4_basic.v //// +//// //// +//// This file is part of the boundaries opencores effort. //// +//// //// +//// //// +//// Module Description: //// +//// //// +//// 1-of-4 glitchless clock switcher //// +//// //// +//// The 4 clocks, enable, and select are assumed to be //// +//// asynchronous. //// +//// //// +//// Selecting/deselecting a stopped clock is not handled. //// +//// //// +//// To Do: //// +//// Verify in silicon. //// +//// //// +//// Author(s): //// +//// - Shannon Hill //// +//// (based on "Techniques to make clock switching glitch free" //// +//// By Rafey Mahmud; EEdesign.com June 26, 2003) //// +//// //// +//// http://www.eedesign.com/showArticle.jhtml?articleID=16501239 //// +//// //// +//// (modified to use only positive edge flops; stall the output //// +//// clock high). //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Shannon Hill and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// $Id: clock_switch4_basic.v,v 1.1 2004-07-07 12:41:17 esquehill Exp $ +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// +// +module clock_switch4_basic( /*AUTOARG*/ +// Outputs +clk_o, +// Inputs +rst0_i, clk0_i, rst1_i, clk1_i, rst2_i, clk2_i, rst3_i, clk3_i, +enable, select +); + +input rst0_i; +input clk0_i; +input rst1_i; +input clk1_i; +input rst2_i; +input clk2_i; +input rst3_i; +input clk3_i; +input enable; // start/stop clock +input [1:0] select; // select a source clock +output clk_o; + +reg [1:0] ssync0; // selection synchronizers... +reg [1:0] ssync1; +reg [1:0] ssync2; +reg [1:0] ssync3; + +reg [3:0] decode; // 1-of-4 decode + +always @( select or enable ) +begin + decode = 4'h0; + case( select ) + 2'b00: decode[0] = enable; + 2'b01: decode[1] = enable; + 2'b10: decode[2] = enable; + 2'b11: decode[3] = enable; + default: decode = 4'h0; + endcase +end + +always @( posedge clk0_i or posedge rst0_i ) +if( rst0_i ) + ssync0 <= 2'b0; +else ssync0 <= { ssync0[0], ( decode[0] & ~ssync1[1] & ~ssync2[1] & ~ssync3[1] ) }; // async input + +always @( posedge clk1_i or posedge rst1_i ) +if( rst1_i ) + ssync1 <= 2'b0; +else ssync1 <= { ssync1[0], (~ssync0[1] & decode[1] & ~ssync2[1] & ~ssync3[1] ) }; // async input + +always @( posedge clk2_i or posedge rst2_i ) +if( rst2_i ) + ssync2 <= 2'b0; +else ssync2 <= { ssync2[0], (~ssync0[1] & ~ssync1[1] & decode[2] & ~ssync3[1] ) }; // async input + +always @( posedge clk3_i or posedge rst3_i ) +if( rst3_i ) + ssync3 <= 2'b0; +else ssync3 <= { ssync3[0], (~ssync0[1] & ~ssync1[1] & ~ssync2[1] & decode[3] ) }; // async input + +wire gclk0 = ~ssync0[1] | clk0_i; // forced high when not selected +wire gclk1 = ~ssync1[1] | clk1_i; // forced high when not selected +wire gclk2 = ~ssync2[1] | clk2_i; // forced high when not selected +wire gclk3 = ~ssync3[1] | clk3_i; // forced high when not selected + +wire clk_o = gclk0 & gclk1 & gclk2 & gclk3; // clock stalls high + +endmodule Index: tags/TAG000/rtl/verilog/clock_detect.v =================================================================== --- tags/TAG000/rtl/verilog/clock_detect.v (nonexistent) +++ tags/TAG000/rtl/verilog/clock_detect.v (revision 3) @@ -0,0 +1,160 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// clock_detect.v //// +//// //// +//// This file is part of the boundaries opencores effort. //// +//// //// +//// //// +//// Module Description: //// +//// //// +//// Use a stable, faster clock to detect whether a slower //// +//// input clock (sclk_i) is actually running. //// +//// //// +//// If there is no change is the suspect clock for (1< //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// $Id: clock_detect.v,v 1.1 2004-07-07 12:41:17 esquehill Exp $ +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// +// +module clock_detect( /*AUTOARG*/ +// Outputs +alive_o, +// Inputs +rst_i, clk_i, sclk_i +); + +input rst_i; +input clk_i; + +input sclk_i; // suspect clock +output alive_o; + +parameter CW = 8; // if (1< //// +//// //// +//// Module Description: //// +//// //// +//// 1-of-8 glitchless clock switcher //// +//// //// +//// The 8 clocks, enable, and select are assumed to be //// +//// asynchronous. //// +//// //// +//// Selecting/deselecting a stopped clock is not handled. //// +//// //// +//// To Do: //// +//// Verify in silicon. //// +//// //// +//// Author(s): //// +//// - Shannon Hill //// +//// (based on "Techniques to make clock switching glitch free" //// +//// By Rafey Mahmud; EEdesign.com June 26, 2003) //// +//// //// +//// http://www.eedesign.com/showArticle.jhtml?articleID=16501239 //// +//// //// +//// (modified to use only positive edge flops; stall the output //// +//// clock high). //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Shannon Hill and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// $Id: clock_switch8_basic.v,v 1.1 2004-07-07 12:41:17 esquehill Exp $ +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// +// +module clock_switch8_basic( /*AUTOARG*/ +// Outputs +clk_o, +// Inputs +rst0_i, clk0_i, rst1_i, clk1_i, rst2_i, clk2_i, rst3_i, clk3_i, +rst4_i, clk4_i, rst5_i, clk5_i, rst6_i, clk6_i, rst7_i, clk7_i, +enable, select +); + +input rst0_i; +input clk0_i; +input rst1_i; +input clk1_i; +input rst2_i; +input clk2_i; +input rst3_i; +input clk3_i; +input rst4_i; +input clk4_i; +input rst5_i; +input clk5_i; +input rst6_i; +input clk6_i; +input rst7_i; +input clk7_i; + +input enable; // start/stop clock +input [2:0] select; // select a source clock +output clk_o; + +reg [1:0] ssync0; // selection synchronizers... +reg [1:0] ssync1; +reg [1:0] ssync2; +reg [1:0] ssync3; +reg [1:0] ssync4; +reg [1:0] ssync5; +reg [1:0] ssync6; +reg [1:0] ssync7; + +reg [7:0] decode; // 1-of-8 decode + +always @( select or enable ) +begin + decode = 8'h0; + case( select ) + 3'b000: decode[0] = enable; + 3'b001: decode[1] = enable; + 3'b010: decode[2] = enable; + 3'b011: decode[3] = enable; + 3'b100: decode[4] = enable; + 3'b101: decode[5] = enable; + 3'b110: decode[6] = enable; + 3'b111: decode[7] = enable; + default: decode = 8'h0; + endcase +end + +always @( posedge clk0_i or posedge rst0_i ) +if( rst0_i ) ssync0 <= 2'b0; +else ssync0 <= { ssync0[0], ( decode[0] & + ~ssync1[1] & + ~ssync2[1] & + ~ssync3[1] & + ~ssync4[1] & + ~ssync5[1] & + ~ssync6[1] & + ~ssync7[1] ) }; // async input + +always @( posedge clk1_i or posedge rst1_i ) +if( rst1_i ) ssync1 <= 2'b0; +else ssync1 <= { ssync1[0], (~ssync0[1] & + decode[1] & + ~ssync2[1] & + ~ssync3[1] & + ~ssync4[1] & + ~ssync5[1] & + ~ssync6[1] & + ~ssync7[1] ) }; // async input + +always @( posedge clk2_i or posedge rst2_i ) +if( rst2_i ) ssync2 <= 2'b0; +else ssync2 <= { ssync2[0], (~ssync0[1] & + ~ssync1[1] & + decode[2] & + ~ssync3[1] & + ~ssync4[1] & + ~ssync5[1] & + ~ssync6[1] & + ~ssync7[1] ) }; // async input + +always @( posedge clk3_i or posedge rst3_i ) +if( rst3_i ) ssync3 <= 2'b0; +else ssync3 <= { ssync3[0], (~ssync0[0] & + ~ssync1[1] & + ~ssync2[1] & + decode[3] & + ~ssync4[1] & + ~ssync5[1] & + ~ssync6[1] & + ~ssync7[1] ) }; // async input + +always @( posedge clk4_i or posedge rst4_i ) +if( rst4_i ) ssync4 <= 2'b0; +else ssync4 <= { ssync4[0], (~ssync0[0] & + ~ssync1[1] & + ~ssync2[1] & + ~ssync3[1] & + decode[4] & + ~ssync5[1] & + ~ssync6[1] & + ~ssync7[1] ) }; // async input + +always @( posedge clk5_i or posedge rst5_i ) +if( rst5_i ) ssync5 <= 2'b0; +else ssync5 <= { ssync5[0], (~ssync0[1] & + ~ssync1[1] & + ~ssync2[1] & + ~ssync3[1] & + ~ssync4[1] & + decode[5] & + ~ssync6[1] & + ~ssync7[1] ) }; // async input + +always @( posedge clk6_i or posedge rst6_i ) +if( rst6_i ) ssync6 <= 2'b0; +else ssync6 <= { ssync6[0], (~ssync0[1] & + ~ssync1[1] & + ~ssync2[1] & + ~ssync3[1] & + ~ssync4[1] & + ~ssync5[1] & + decode[6] & + ~ssync7[1] ) }; // async input + +always @( posedge clk7_i or posedge rst7_i ) +if( rst7_i ) ssync7 <= 2'b0; +else ssync7 <= { ssync7[0], (~ssync0[1] & + ~ssync1[1] & + ~ssync2[1] & + ~ssync3[1] & + ~ssync4[1] & + ~ssync5[1] & + ~ssync6[1] & + decode[7] ) }; // async input + +wire gclk0 = ~ssync0[1] | clk0_i; // forced high when not selected +wire gclk1 = ~ssync1[1] | clk1_i; // forced high when not selected +wire gclk2 = ~ssync2[1] | clk2_i; // forced high when not selected +wire gclk3 = ~ssync3[1] | clk3_i; // forced high when not selected +wire gclk4 = ~ssync4[1] | clk4_i; // forced high when not selected +wire gclk5 = ~ssync5[1] | clk5_i; // forced high when not selected +wire gclk6 = ~ssync6[1] | clk6_i; // forced high when not selected +wire gclk7 = ~ssync7[1] | clk7_i; // forced high when not selected + +wire clk_o = gclk0 & gclk1 & gclk2 & gclk3 & gclk4 & gclk5 & gclk6 & gclk7; + +endmodule + + + + + Index: tags/TAG000/rtl/verilog/oc_fifo_basic.v =================================================================== --- tags/TAG000/rtl/verilog/oc_fifo_basic.v (nonexistent) +++ tags/TAG000/rtl/verilog/oc_fifo_basic.v (revision 3) @@ -0,0 +1,140 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// oc_fifo_basic.v //// +//// //// +//// This file is part of the boundaries opencores effort. //// +//// //// +//// //// +//// Module Description: //// +//// //// +//// One Clock FIFO //// +//// //// +//// 2 Parameters: Address Width, Data Width //// +//// Data storage is internally inferred. //// +//// Protected against read-while-empty and write-while-full. //// +//// When empty, force data output to zero. //// +//// //// +//// The minimum address width (AW) is 2. //// +//// //// +//// To Do: //// +//// Verify in silicon. //// +//// //// +//// Author(s): //// +//// - Shannon Hill //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Shannon Hill and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// $Id: oc_fifo_basic.v,v 1.1 2004-07-07 12:41:17 esquehill Exp $ +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// +// +module oc_fifo_basic( /*AUTOARG*/ +// Outputs +have, take_do, need, +// Inputs +rst_i, clk_i, take, give, give_di +); + +parameter AW=3; // default address width +parameter DW=8; // default data width + +input rst_i; +input clk_i; + +output have; +input take; +output [DW-1:0] take_do; + +output need; +input give; +input [DW-1:0] give_di; + +reg [AW :0] rp; +reg [AW :0] wp; +wire [AW :0] rp_add1 = rp + 1'b1; +wire [AW :0] wp_add1 = wp + 1'b1; + +reg full; +reg emty; + +wire have = ~emty; +wire need = ~full; + +reg [DW-1:0] mem [0:(1< //// +//// //// +//// Module Description: //// +//// Debounce a mechanical switch or contact. //// +//// //// +//// To Do: //// +//// Verify in silicon. //// +//// //// +//// Author(s): //// +//// - Shannon Hill //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Shannon Hill and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// $Id: debouncer.v,v 1.1 2004-07-07 12:41:17 esquehill Exp $ +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// +// +module debouncer( /*AUTOARG*/ +// Outputs +button_o, +// Inputs +rst_i, clk_i, button_i +); + +parameter CW = 8; + +input rst_i; +input clk_i; // 1us period for a (1< //// +//// //// +//// Module Description: //// +//// //// +//// Parameterizable round-robin arbiter. //// +//// RNUM = log2( number of requestors ) //// +//// so, RNUM = 3 implies 8 requestors. //// +//// //// +//// To Do: //// +//// Verify in silicon. //// +//// //// +//// Author(s): //// +//// - Shannon Hill //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Shannon Hill and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// $Id: arbiter.v,v 1.1 2004-07-07 12:41:17 esquehill Exp $ +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// +// +module arbiter( /*AUTOARG*/ +// Outputs +grant, +// Inputs +rst_i, clk_i, reqst +); +parameter RNUM = 3; +parameter RCNT = 1<> inc_state; + +// maintain a list of which req_bit is mapped to which +// request number, so that we can issue the appropriate grant. +// +reg [RNUM-1:0] req_map [0:RCNT-1]; + +always @( inc_state ) +for( i = 0 ; i < RCNT ; i = i + 1 ) req_map[i] = i+inc_state; + +// +// issue the next grant... +// +always @( grant or req_bit or reqst or state ) +begin + nxt_state = state; + nxt_grant = grant; + granted = 1'b0; + +if( ( grant[ state ] & ~reqst[ state ] ) || // request going inactive? or... + ( ~|grant ) ) // no grants outstanding? +begin + + nxt_grant = {RCNT{1'b0}}; // de-assert all grants + + for( j = 0 ; j < RCNT ; j = j + 1 ) + if( req_bit[j] & ~granted ) // look for a pending request + begin + nxt_state = req_map[j]; // change state to granted number + nxt_grant[ req_map[j] ] = 1'b1; // issue the grant + granted = 1'b1; // issue only 1 grant (verilog has no "break;") + end +end +end + + +always @( posedge clk_i or posedge rst_i ) +if( rst_i ) +begin + grant <= {RCNT{1'b0}}; + state <= {RNUM{1'b0}}; +end +else +begin + grant <= nxt_grant; + state <= nxt_state; +end + +endmodule Index: tags/TAG000/rtl/verilog/bc_fifo_basic.v =================================================================== --- tags/TAG000/rtl/verilog/bc_fifo_basic.v (nonexistent) +++ tags/TAG000/rtl/verilog/bc_fifo_basic.v (revision 3) @@ -0,0 +1,216 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// bc_fifo_basic.v //// +//// //// +//// This file is part of the boundaries opencores effort. //// +//// //// +//// //// +//// Module Description: //// +//// //// +//// Asynchronous Boundary Crossing FIFO //// +//// //// +//// 2 Parameters: Address Width, Data Width //// +//// Data storage is internally inferred. //// +//// Protected against read-while-empty and write-while-full //// +//// The minimum address width (AW) is 2. //// +//// //// +//// To Do: //// +//// Verify in silicon. //// +//// //// +//// Author(s): //// +//// - Shannon Hill //// +//// (based on the generic_fifo_dc_gray design from //// +//// Rudolf Usselmann. This variant infers its own //// +//// data storage, defends itself against write-while-full //// +//// and read-while-empty, and forces its output data to 0 //// +//// when empty.) //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2004 Shannon Hill and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// $Id: bc_fifo_basic.v,v 1.1 2004-07-07 12:41:17 esquehill Exp $ +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// +// +module bc_fifo_basic( /*AUTOARG*/ +// Outputs +get_do, get_have, put_need, +// Inputs +put_rst_i, get_rst_i, get_clk_i, get, put_clk_i, put_di, put +); + +parameter AW=3; // default address width +parameter DW=8; // default data width + +input put_rst_i; // async reset from the put_clk_i domain +input get_rst_i; // async reset from the get_clk_i domain + +input get_clk_i; +output [DW-1:0] get_do; +input get; +output get_have; // fifo has 1 or more + +input put_clk_i; +input [DW-1:0] put_di; +input put; +output put_need; // fifo has room for 1 more + +reg [AW :0] rp_bin; +reg [AW :0] rp_gra; +reg [AW :0] rp_gra_sync; + +reg [AW :0] wp_bin; +reg [AW :0] wp_gra; +reg [AW :0] wp_gra_sync; + +reg put_full; +reg get_emty; + +wire get_have = ~get_emty; +wire put_need = ~put_full; + +reg [DW-1:0] mem [0:(1<>1); +end +endfunction + +////////////////////////// + +function [AW:0] gray_to_bin; +input [AW:0] g; +reg [AW:0] b; +integer i; +begin + for( i=0; i<=AW; i=i+1 ) b[i] = ^(g>>i); + gray_to_bin = b; +end +endfunction + +//////////////////////////// +// in the get_clk_i domain +//////////////////////////// + +wire [AW :0] rp_bin_add1 = rp_bin + 1'd1; +wire [AW :0] rp_gra_add1 = bin_to_gray( rp_bin_add1 ); +// +// get the gray-coded write pointer over to the get_clk_i domain +// +always @( posedge get_clk_i or posedge get_rst_i ) // put_clk_i to get_clk_i boundary crossing +if( get_rst_i ) + wp_gra_sync <= 0; +else wp_gra_sync <= wp_gra; + +// +// convert the sampled graycode read pointer to binary +// +// wire [AW :0] wp_bin_sync = gray_to_bin( wp_gra_sync ); + +// compare the write pointer and read pointer +// +// set empty when: getting AND the next read pointer == the current write pointer +// hold empty when: read pointer == write pointer +// clr empty when: read pointer no longer equal to write pointer +// +always @( posedge get_clk_i or posedge get_rst_i ) +if( get_rst_i ) +begin + rp_bin <= 0; + rp_gra <= 0; + get_emty <= 1'b1; +end +else +begin + + get_emty <= ( rp_gra == wp_gra_sync ) | + ( get & ~get_emty & ( rp_gra_add1 == wp_gra_sync ) ); + + if( get & ~get_emty ) + begin + rp_bin <= rp_bin_add1; + rp_gra <= rp_gra_add1; + end +end + +//////////////////////////////// +// over in the put_clk_i domain +//////////////////////////////// + +wire [AW :0] wp_bin_add1 = wp_bin + 1'd1; +wire [AW :0] wp_gra_add1 = bin_to_gray( wp_bin_add1 ); +// +// get the gray-coded read pointer over to the put_clk_i domain +// +always @( posedge put_clk_i or posedge put_rst_i ) // get_clk_i to put_clk_i boundary crossing +if( put_rst_i ) + rp_gra_sync <= 0; +else rp_gra_sync <= rp_gra; +// +// convert the sampled graycode read pointer to binary +// +wire [AW :0] rp_bin_sync = gray_to_bin( rp_gra_sync ); + +// compare the read pointer and write pointer +// +// set full when: putting AND the next write pointer == read pointer +// hold full when: full and write pointer == read pointer +// clr full when: write pointer no longer equal to read pointer +// +always @( posedge put_clk_i or posedge put_rst_i ) +if( put_rst_i ) + begin + wp_bin <= 0; + wp_gra <= 0; + put_full <= 1'b0; + end +else +begin + put_full <= + ( ( wp_bin[ AW-1:0] == rp_bin_sync[AW-1:0] ) & ( wp_bin[ AW] != rp_bin_sync[AW] ) ) | + ( put & ~put_full & ( wp_bin_add1[AW-1:0] == rp_bin_sync[AW-1:0] ) & ( wp_bin_add1[AW] != rp_bin_sync[AW] ) ); + +if( put & ~put_full ) + begin + wp_bin <= wp_bin_add1; + wp_gra <= wp_gra_add1; + end +end + +always @( posedge put_clk_i ) +if( put & ~put_full ) mem[ wp_bin[AW-1:0] ] <= put_di; // do the data write + +endmodule Index: tags/TAG000/sim/rtl_sim/bin/vcmp =================================================================== --- tags/TAG000/sim/rtl_sim/bin/vcmp (nonexistent) +++ tags/TAG000/sim/rtl_sim/bin/vcmp (revision 3) @@ -0,0 +1,8 @@ +#!/bin/tcsh -f +vcs -I -Mdelete -q -o ${1}.sim \ + +libext+.v+ \ + +incdir+../../../rtl/verilog+ \ + +incdir+../../../bench/verilog+ \ + -y ../../../rtl/verilog \ + -y ../../../bench/verilog \ + ../../../bench/verilog/${1}.v

tags/TAG000/sim/rtl_sim/bin/vcmp Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/TAG000/sim/rtl_sim/bin/vrun =================================================================== --- tags/TAG000/sim/rtl_sim/bin/vrun (nonexistent) +++ tags/TAG000/sim/rtl_sim/bin/vrun (revision 3) @@ -0,0 +1,17 @@ +#!/bin/tcsh -f + +set tbpath=${1} + +set tbname=${tbpath:t} + +vcs +plusarg_save +vcs+stop+0+9999 -k off -R -q \ + +libext+.v+ \ + +incdir+../../../rtl/verilog+ \ + +incdir+../../../bench/verilog+ \ + -y ../../../rtl/verilog \ + -y ../../../bench/verilog \ + -o ${tbname}.sim \ + -l ../log/${tbname}.log \ + ${tbpath}.v + +/bin/rm -rf csrc ${tbname}.sim

tags/TAG000/sim/rtl_sim/bin/vrun Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/TAG000/sim/rtl_sim/bin/run_sim =================================================================== --- tags/TAG000/sim/rtl_sim/bin/run_sim (nonexistent) +++ tags/TAG000/sim/rtl_sim/bin/run_sim (revision 3) @@ -0,0 +1,30 @@ +#!/bin/tcsh -f +# +/bin/rm -f ../log/*.log >&/dev/null +# +if( "${1}" == "-r" ) then + vrun ../../../bench/verilog/oc_fifo_basic_tb >&/dev/null + vrun ../../../bench/verilog/bc_fifo_basic_tb >&/dev/null + vrun ../../../bench/verilog/clock_detect_tb >&/dev/null + vrun ../../../bench/verilog/clock_switch_tb >&/dev/null + vrun ../../../bench/verilog/debouncer_tb >&/dev/null + vrun ../../../bench/verilog/random_ff_tb >&/dev/null + vrun ../../../bench/verilog/arbiter_tb >&/dev/null +else + vrun ../../../bench/verilog/oc_fifo_basic_tb + vrun ../../../bench/verilog/bc_fifo_basic_tb + vrun ../../../bench/verilog/clock_detect_tb + vrun ../../../bench/verilog/clock_switch_tb + vrun ../../../bench/verilog/debouncer_tb + vrun ../../../bench/verilog/random_ff_tb + vrun ../../../bench/verilog/arbiter_tb +endif + + set okcount=`grep ^OK$ ../log/*tb.log | wc -l` + if( ${okcount} == 7 ) then + echo OK + else + echo FAIL + endif + +exit 0

tags/TAG000/sim/rtl_sim/bin/run_sim Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tags/TAG000/sim/rtl_sim/bin/vsim =================================================================== --- tags/TAG000/sim/rtl_sim/bin/vsim (nonexistent) +++ tags/TAG000/sim/rtl_sim/bin/vsim (revision 3) @@ -0,0 +1,4 @@ +#!/bin/tcsh -f +vcs +dumpoff -k off -RIG -q -o ${1}.sim \ + ../../../bench/verilog/${1}.v \ + +vpdfile+${1}.vpd

tags/TAG000/sim/rtl_sim/bin/vsim Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property