URL
https://opencores.org/ocsvn/btc_dsha256/btc_dsha256/trunk
Subversion Repositories btc_dsha256
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- This comparison shows the changes necessary to convert path
/
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/btc_dsha256/trunk/rtl/vhdl/TestBench/sha_256_chunk_TB.vhd
1,3 → 1,31
------------------------------------------------------------------- |
-- -- |
-- Copyright (C) 2013 Author and VariStream Studio -- |
-- Author : Yu Peng -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- This source file is free software; you can redistribute it -- |
-- and/or modify it under the terms of the GNU Lesser General -- |
-- Public License as published by the Free Software Foundation; -- |
-- either version 2.1 of the License, or (at your option) any -- |
-- later version. -- |
-- -- |
-- This source is distributed in the hope that it will be -- |
-- useful, but WITHOUT ANY WARRANTY; without even the implied -- |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- |
-- PURPOSE. See the GNU Lesser General Public License for more -- |
-- details. -- |
-- -- |
-- You should have received a copy of the GNU Lesser General -- |
-- Public License along with this source; if not, download it -- |
-- from http://www.opencores.org/lgpl.shtml -- |
-- -- |
------------------------------------------------------------------- |
|
library hotan; |
use hotan.sha_256_pkg.all; |
library ieee; |
167,6 → 195,10
else |
svResultMatch(i) <= '0'; |
end if; |
|
assert ovH = cTEST_RESULT(i) |
report "The test " & integer'image(i) & " failed" |
severity ERROR; |
end if; |
end loop; |
end if; |
181,7 → 213,7
ivMsgDword <= cTEST_MSG(siTestInCnt); |
end if; |
end process; |
|
|
end TB_ARCHITECTURE; |
|
configuration TESTBENCH_FOR_sha_256_chunk of sha_256_chunk_tb is |
/btc_dsha256/trunk/rtl/vhdl/TestBench/btc_dsha_TB.vhd
1,3 → 1,31
------------------------------------------------------------------- |
-- -- |
-- Copyright (C) 2013 Author and VariStream Studio -- |
-- Author : Yu Peng -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- This source file is free software; you can redistribute it -- |
-- and/or modify it under the terms of the GNU Lesser General -- |
-- Public License as published by the Free Software Foundation; -- |
-- either version 2.1 of the License, or (at your option) any -- |
-- later version. -- |
-- -- |
-- This source is distributed in the hope that it will be -- |
-- useful, but WITHOUT ANY WARRANTY; without even the implied -- |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- |
-- PURPOSE. See the GNU Lesser General Public License for more -- |
-- details. -- |
-- -- |
-- You should have received a copy of the GNU Lesser General -- |
-- Public License along with this source; if not, download it -- |
-- from http://www.opencores.org/lgpl.shtml -- |
-- -- |
------------------------------------------------------------------- |
|
library hotan; |
use hotan.sha_256_pkg.all; |
library ieee; |
26,8 → 54,8
iValid_p : in STD_LOGIC; |
ivAddr : in STD_LOGIC_VECTOR(3 downto 0); |
ivData : in STD_LOGIC_VECTOR(31 downto 0); |
oReachEnd : out STD_LOGIC; |
oFoundNonce : out STD_LOGIC; |
oReachEnd_p : out STD_LOGIC; |
oFoundNonce_p : out STD_LOGIC; |
ovNonce : out STD_LOGIC_VECTOR(31 downto 0); |
ovDigest : out tDwordArray(0 to 7) ); |
end component; |
36,7 → 64,9
generic( |
gMSG_IS_CONSTANT : std_logic_vector(0 to 15) := (others=>'1'); |
gH_IS_CONST : std_logic_vector(0 to 7) := (others=>'1'); |
gBASE_DELAY : integer := 1 |
gBASE_DELAY : integer := 3; |
gOUT_VALID_GEN : boolean := false; |
gUSE_BRAM_AS_LARGE_SHIFTREG : boolean := false |
); |
port( |
iClk : in STD_LOGIC; |
58,7 → 88,8
ovH4 : out STD_LOGIC_VECTOR(31 downto 0); |
ovH5 : out STD_LOGIC_VECTOR(31 downto 0); |
ovH6 : out STD_LOGIC_VECTOR(31 downto 0); |
ovH7 : out STD_LOGIC_VECTOR(31 downto 0) ); |
ovH7 : out STD_LOGIC_VECTOR(31 downto 0); |
oValid : out std_logic); |
end component; |
|
component pipelines_without_reset IS |
80,20 → 111,24
signal ivAddr : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0'); |
signal ivData : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0'); |
-- Observed signals - signals mapped to the output ports of tested entity |
signal oReachEnd : STD_LOGIC := '0'; |
signal oFoundNonce : STD_LOGIC := '0'; |
signal oReachEnd_p : STD_LOGIC := '0'; |
signal oFoundNonce_p : STD_LOGIC := '0'; |
signal ovNonce : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0'); |
signal ovDigest : tDwordArray(0 to 7) := (others=>(others=>'0')); |
|
-- Add your code here ... |
constant cREG_CLK_PERIOD : time := 30 ns; -- 33M Register Clock |
constant cPROC_CLK_PERIOD : time := 10 ns; -- 100M Processing Clock |
constant cRESET_INTERVAL : time := 71 ns; |
constant cSTRAT_TEST : integer := 25; |
|
constant cCMD_ADDR : std_logic_vector(3 downto 0) := X"D"; |
constant cCMD_IDLE : std_logic_vector(15 downto 0) := X"0000"; |
constant cCMD_RESET : std_logic_vector(15 downto 0) := X"CAFE"; |
constant cCMD_NOP : std_logic_vector(15 downto 0) := X"0000"; |
constant cCMD_START : std_logic_vector(15 downto 0) := X"0001"; |
|
signal svWork : tDwordArray(0 to 31) := (others=>(others=>'0')); |
|
signal siWriteCnt : std_logic_vector(31 downto 0) := (others => '0'); |
signal svWriteCnt : std_logic_vector(31 downto 0) := (others => '0'); |
|
signal sHashMidStateValidIn : std_logic := '0'; |
signal sHashMidStateValidOut : std_logic := '0'; |
116,8 → 151,8
iValid_p => iValid_p, |
ivAddr => ivAddr, |
ivData => ivData, |
oReachEnd => oReachEnd, |
oFoundNonce => oFoundNonce, |
oReachEnd_p => oReachEnd_p, |
oFoundNonce_p => oFoundNonce_p, |
ovNonce => ovNonce, |
ovDigest => ovDigest |
); |
124,43 → 159,58
|
-- Add your stimulus here ... |
|
iClkReg <= not iClkReg after 5 ns; |
iClkProcess <= not iClkProcess after 5 ns; |
iRst_async <= '0' after 71 ns; |
iClkReg <= not iClkReg after (cREG_CLK_PERIOD / 2); |
iClkProcess <= not iClkProcess after (cPROC_CLK_PERIOD / 2); |
iRst_async <= '0' after cRESET_INTERVAL; |
|
svWork(0) <= X"02000000" after 251 ns; |
svWork(1) <= X"ea144059" after 251 ns; |
svWork(2) <= X"2a8b0d36" after 251 ns; |
svWork(3) <= X"b2e5f8a4" after 251 ns; |
svWork(4) <= X"85db1c04" after 251 ns; |
svWork(5) <= X"ca9290ca" after 251 ns; |
svWork(6) <= X"05bdc7f2" after 251 ns; |
svWork(7) <= X"05000000" after 251 ns; |
svWork(8) <= X"00000000" after 251 ns; |
svWork(9) <= X"11dfffb5" after 251 ns; |
svWork(10) <= X"ad285596" after 251 ns; |
svWork(11) <= X"8e4403d0" after 251 ns; |
svWork(12) <= X"60bdf636" after 251 ns; |
svWork(13) <= X"a023e387" after 251 ns; |
svWork(14) <= X"2870bbdc" after 251 ns; |
svWork(15) <= X"92e0aede" after 251 ns; |
svWork(16) <= X"acde4c0e" after 251 ns; |
svWork(17) <= X"032A6C52" after 251 ns; |
svWork(18) <= X"85fc0a19" after 251 ns; |
svWork(19) <= X"0BCFA6B6" after 251 ns; |
-- This test vector is derive from block 266243, notice the endianess changment of converting JSON data to test vector |
-- blockId: 266243 |
-- blockHash: 000000000000000399572203a6035acb2d68944c9c047435a5e9f11d40daa4ee |
-- merkleroot: 0e4cdeacdeaee092dcbb702887e323a036f6bd60d003448e965528adb5ffdf11 |
-- nonce: 3064385291 |
-- previousblockhash: 0000000000000005f2c7bd05ca9092ca041cdb85a4f8e5b2360d8b2a594014ea |
-- hash: 000000000000000399572203a6035acb2d68944c9c047435a5e9f11d40daa4ee |
-- version: 2 |
-- height: 266243 |
-- difficulty: 390928787.63808584 |
-- confirmations: 1 |
-- time: 1382820355 |
-- bits: 190afc85 |
-- size: 227682 |
svWork(0) <= X"02000000" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns); |
svWork(1) <= X"ea144059" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns); |
svWork(2) <= X"2a8b0d36" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns); |
svWork(3) <= X"b2e5f8a4" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns); |
svWork(4) <= X"85db1c04" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns); |
svWork(5) <= X"ca9290ca" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns); |
svWork(6) <= X"05bdc7f2" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns); |
svWork(7) <= X"05000000" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns); |
svWork(8) <= X"00000000" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns); |
svWork(9) <= X"11dfffb5" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns); |
svWork(10) <= X"ad285596" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns); |
svWork(11) <= X"8e4403d0" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns); |
svWork(12) <= X"60bdf636" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns); |
svWork(13) <= X"a023e387" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns); |
svWork(14) <= X"2870bbdc" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns); |
svWork(15) <= X"92e0aede" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns); |
|
svWork(16) <= X"acde4c0e" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns); |
svWork(17) <= X"032A6C52" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns); |
svWork(18) <= X"85fc0a19" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns); |
svWork(19) <= X"0BCFA6B6" after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns); |
|
|
process(iClkReg, iRst_async) |
begin |
if iRst_async = '1' then |
siWriteCnt <= (others => '0'); |
svWriteCnt <= (others => '0'); |
iValid_p <= '0'; |
elsif rising_edge(iClkReg) then |
if sMidStateValid = '1' then |
siWriteCnt <= siWriteCnt + '1'; |
svWriteCnt <= svWriteCnt + '1'; |
end if; |
|
if siWriteCnt(3 downto 0) = X"F" and siWriteCnt(15 downto 4) <= conv_std_logic_vector(13, 12) then |
if svWriteCnt(3 downto 0) = X"F" and svWriteCnt(15 downto 4) <= conv_std_logic_vector(13, 12) then |
iValid_p <= '1'; |
else |
iValid_p <= '0'; |
174,8 → 224,8
ivAddr <= (others=>'0'); |
ivData <= (others=>'0'); |
elsif rising_edge(iClkReg) then |
if siWriteCnt(3 downto 0) = X"F" then |
case siWriteCnt(15 downto 4) is |
if svWriteCnt(3 downto 0) = X"F" then |
case svWriteCnt(15 downto 4) is |
when X"000" => |
ivAddr <= X"0"; |
ivData <= svMidState(0); |
226,7 → 276,7
|
when X"00C" => |
ivAddr <= X"C"; |
ivData <= svWork(19); -- + X"02"; |
ivData <= svWork(19) + X"20"; |
|
when X"00D" => |
ivAddr <= cCMD_ADDR; |
234,7 → 284,7
|
when others => |
ivAddr <= cCMD_ADDR; |
ivData <= X"0000" & cCMD_IDLE; |
ivData <= X"0000" & cCMD_NOP; |
end case; |
end if; |
end if; |
241,13 → 291,14
end process; |
|
|
sHashMidStateValidIn <= '1' after 251 ns, '0' after 261 ns; |
sHashMidStateValidIn <= '1' after (cSTRAT_TEST * cPROC_CLK_PERIOD + 1 ns), '0' after (cSTRAT_TEST * cPROC_CLK_PERIOD + cPROC_CLK_PERIOD + 1 ns); |
|
sha_256_chunk_inst_HashMidState : sha_256_chunk |
generic map( |
gMSG_IS_CONSTANT => (others=>'0'), |
gH_IS_CONST => (others=>'1'), |
gBASE_DELAY => gBASE_DELAY |
gBASE_DELAY => gBASE_DELAY, |
gOUT_VALID_GEN => true |
) |
port map ( |
iClk => iClkProcess, |
272,18 → 323,20
ovH4 => svHashMidStateDataOut(4), |
ovH5 => svHashMidStateDataOut(5), |
ovH6 => svHashMidStateDataOut(6), |
ovH7 => svHashMidStateDataOut(7) |
ovH7 => svHashMidStateDataOut(7), |
|
oValid => sHashMidStateValidOut |
); |
|
pipelines_without_reset_Valid : pipelines_without_reset |
GENERIC map(gBUS_WIDTH => 1, gNB_PIPELINES => (64 * gBASE_DELAY + 1)) |
PORT map( |
iClk => iClkProcess, |
iInput => sHashMidStateValidIn, |
ivInput => (others=>'0'), |
oDelayed_output => sHashMidStateValidOut, |
ovDelayed_output => open |
); |
-- pipelines_without_reset_Valid : pipelines_without_reset |
-- GENERIC map(gBUS_WIDTH => 1, gNB_PIPELINES => (64 * gBASE_DELAY + 1)) |
-- PORT map( |
-- iClk => iClkProcess, |
-- iInput => sHashMidStateValidIn, |
-- ivInput => (others=>'0'), |
-- oDelayed_output => sHashMidStateValidOut, |
-- ovDelayed_output => open |
-- ); |
|
process(iClkProcess) |
begin |
/btc_dsha256/trunk/rtl/vhdl/sha256core/sha_256_chunk.vhd
1,5 → 1,30
-- Copyright (c) 2013 VariStream |
-- Auther : Yu Peng |
------------------------------------------------------------------- |
-- -- |
-- Copyright (C) 2013 Author and VariStream Studio -- |
-- Author : Yu Peng -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- This source file is free software; you can redistribute it -- |
-- and/or modify it under the terms of the GNU Lesser General -- |
-- Public License as published by the Free Software Foundation; -- |
-- either version 2.1 of the License, or (at your option) any -- |
-- later version. -- |
-- -- |
-- This source is distributed in the hope that it will be -- |
-- useful, but WITHOUT ANY WARRANTY; without even the implied -- |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- |
-- PURPOSE. See the GNU Lesser General Public License for more -- |
-- details. -- |
-- -- |
-- You should have received a copy of the GNU Lesser General -- |
-- Public License along with this source; if not, download it -- |
-- from http://www.opencores.org/lgpl.shtml -- |
-- -- |
------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
/btc_dsha256/trunk/rtl/vhdl/sha256core/sha_256_comp_func.vhd
1,6 → 1,32
-- Copyright (c) 2013 VariStream |
-- Author : Yu Peng |
------------------------------------------------------------------- |
-- -- |
-- Copyright (C) 2013 Author and VariStream Studio -- |
-- Author : Yu Peng -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- This source file is free software; you can redistribute it -- |
-- and/or modify it under the terms of the GNU Lesser General -- |
-- Public License as published by the Free Software Foundation; -- |
-- either version 2.1 of the License, or (at your option) any -- |
-- later version. -- |
-- -- |
-- This source is distributed in the hope that it will be -- |
-- useful, but WITHOUT ANY WARRANTY; without even the implied -- |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- |
-- PURPOSE. See the GNU Lesser General Public License for more -- |
-- details. -- |
-- -- |
-- You should have received a copy of the GNU Lesser General -- |
-- Public License along with this source; if not, download it -- |
-- from http://www.opencores.org/lgpl.shtml -- |
-- -- |
------------------------------------------------------------------- |
-- Notes : Introduce delay of 3 clock cycle |
------------------------------------------------------------------- |
|
library IEEE; |
|
/btc_dsha256/trunk/rtl/vhdl/sha256core/sha_256_ext_func.vhd
1,6 → 1,32
-- Copyright (c) 2013 VariStream |
-- Author : Yu Peng |
------------------------------------------------------------------- |
-- -- |
-- Copyright (C) 2013 Author and VariStream Studio -- |
-- Author : Yu Peng -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- This source file is free software; you can redistribute it -- |
-- and/or modify it under the terms of the GNU Lesser General -- |
-- Public License as published by the Free Software Foundation; -- |
-- either version 2.1 of the License, or (at your option) any -- |
-- later version. -- |
-- -- |
-- This source is distributed in the hope that it will be -- |
-- useful, but WITHOUT ANY WARRANTY; without even the implied -- |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- |
-- PURPOSE. See the GNU Lesser General Public License for more -- |
-- details. -- |
-- -- |
-- You should have received a copy of the GNU Lesser General -- |
-- Public License along with this source; if not, download it -- |
-- from http://www.opencores.org/lgpl.shtml -- |
-- -- |
------------------------------------------------------------------- |
-- Notes : Introduce delay of 3 clock cycle |
------------------------------------------------------------------- |
|
library IEEE; |
|
/btc_dsha256/trunk/rtl/vhdl/sha256core/sha_256_comp_func_1c.vhd
1,6 → 1,32
-- Copyright (c) 2013 VariStream |
-- Author : Yu Peng |
-- Notes : Introduce delay of 1 clock cycle |
------------------------------------------------------------------- |
-- -- |
-- Copyright (C) 2013 Author and VariStream Studio -- |
-- Author : Yu Peng -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- This source file is free software; you can redistribute it -- |
-- and/or modify it under the terms of the GNU Lesser General -- |
-- Public License as published by the Free Software Foundation; -- |
-- either version 2.1 of the License, or (at your option) any -- |
-- later version. -- |
-- -- |
-- This source is distributed in the hope that it will be -- |
-- useful, but WITHOUT ANY WARRANTY; without even the implied -- |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- |
-- PURPOSE. See the GNU Lesser General Public License for more -- |
-- details. -- |
-- -- |
-- You should have received a copy of the GNU Lesser General -- |
-- Public License along with this source; if not, download it -- |
-- from http://www.opencores.org/lgpl.shtml -- |
-- -- |
------------------------------------------------------------------- |
-- Notes : Introduce delay of 1 clock cycle |
------------------------------------------------------------------- |
|
library IEEE; |
|
/btc_dsha256/trunk/rtl/vhdl/sha256core/sha_256_ext_func_1c.vhd
1,6 → 1,32
-- Copyright (c) 2013 VariStream |
-- Author : Yu Peng |
-- Notes : Introduce delay of 1 clock cycle |
------------------------------------------------------------------- |
-- -- |
-- Copyright (C) 2013 Author and VariStream Studio -- |
-- Author : Yu Peng -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- This source file is free software; you can redistribute it -- |
-- and/or modify it under the terms of the GNU Lesser General -- |
-- Public License as published by the Free Software Foundation; -- |
-- either version 2.1 of the License, or (at your option) any -- |
-- later version. -- |
-- -- |
-- This source is distributed in the hope that it will be -- |
-- useful, but WITHOUT ANY WARRANTY; without even the implied -- |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- |
-- PURPOSE. See the GNU Lesser General Public License for more -- |
-- details. -- |
-- -- |
-- You should have received a copy of the GNU Lesser General -- |
-- Public License along with this source; if not, download it -- |
-- from http://www.opencores.org/lgpl.shtml -- |
-- -- |
------------------------------------------------------------------- |
-- Notes : Introduce delay of 1 clock cycle |
------------------------------------------------------------------- |
|
library IEEE; |
|
/btc_dsha256/trunk/rtl/vhdl/sha256core/btc_dsha.vhd
1,5 → 1,30
-- Copyright (c) 2013 VariStream |
-- Auther : Yu Peng |
------------------------------------------------------------------- |
-- -- |
-- Copyright (C) 2013 Author and VariStream Studio -- |
-- Author : Yu Peng -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- This source file is free software; you can redistribute it -- |
-- and/or modify it under the terms of the GNU Lesser General -- |
-- Public License as published by the Free Software Foundation; -- |
-- either version 2.1 of the License, or (at your option) any -- |
-- later version. -- |
-- -- |
-- This source is distributed in the hope that it will be -- |
-- useful, but WITHOUT ANY WARRANTY; without even the implied -- |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- |
-- PURPOSE. See the GNU Lesser General Public License for more -- |
-- details. -- |
-- -- |
-- You should have received a copy of the GNU Lesser General -- |
-- Public License along with this source; if not, download it -- |
-- from http://www.opencores.org/lgpl.shtml -- |
-- -- |
------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
13,9 → 38,10
gBASE_DELAY : integer := 1 |
); |
port( |
iRst_async : in std_logic := '0'; |
|
iClkReg : in std_logic := '0'; |
iClkProcess : in std_logic := '0'; |
iRst_async : in std_logic := '0'; |
|
iValid_p : in std_logic := '0'; |
ivAddr : in std_logic_vector(3 downto 0) := (others=>'0'); |
108,8 → 134,6
end component; |
|
constant cCMD_ADDR : std_logic_vector(3 downto 0) := X"D"; |
constant cCMD_IDLE : std_logic_vector(15 downto 0) := X"0000"; |
constant cCMD_RESET : std_logic_vector(15 downto 0) := X"CAFE"; |
constant cCMD_START : std_logic_vector(15 downto 0) := X"0001"; |
|
constant cPROCESS_DEALY : std_logic_vector(15 downto 0) := conv_std_logic_vector(64 * gBASE_DELAY * 2 + 1, 16); |
138,7 → 162,6
signal svNonce : std_logic_vector(31 downto 0) := (others=>'0'); |
signal svCmd : std_logic_vector(15 downto 0) := (others=>'0'); |
signal sCmdValid_syncReg_p : std_logic := '0'; |
signal sCmdReset : std_logic := '0'; |
signal sCmdStart_syncReg_p : std_logic := '0'; |
signal sCmdStart_syncProcess_p : std_logic := '0'; |
signal sCmdStart_syncProcess_p_1d : std_logic := '0'; |
165,6 → 188,7
signal sReachEndToIdle : std_logic := '0'; |
|
begin |
|
SyncReset_inst_Process : SyncReset |
port map( |
iClk => iClkProcess, |
225,22 → 249,14
end if; |
end if; |
end process; |
|
|
process(iClkReg, iRst_async) |
begin |
if iRst_async = '1' then |
sCmdReset <= '0'; |
sCmdValid_syncReg_p <= '0'; |
elsif rising_edge(iClkReg) then |
sCmdStart_syncReg_p <= '0'; |
elsif rising_edge(iClkReg) then |
if iValid_p = '1' and ivAddr = cCMD_ADDR then |
if ivData(15 downto 0) = cCMD_RESET then |
sCmdReset <= '1'; |
else |
sCmdReset <= '0'; |
end if; |
end if; |
|
if iValid_p = '1' and ivAddr = cCMD_ADDR then |
sCmdValid_syncReg_p <= '1'; |
else |
sCmdValid_syncReg_p <= '0'; |
/btc_dsha256/trunk/rtl/vhdl/sha256core/sha_256_pkg.vhd
1,5 → 1,30
-- Copyright (c) 2013 VariStream |
-- Author : Yu Peng |
------------------------------------------------------------------- |
-- -- |
-- Copyright (C) 2013 Author and VariStream Studio -- |
-- Author : Yu Peng -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- This source file is free software; you can redistribute it -- |
-- and/or modify it under the terms of the GNU Lesser General -- |
-- Public License as published by the Free Software Foundation; -- |
-- either version 2.1 of the License, or (at your option) any -- |
-- later version. -- |
-- -- |
-- This source is distributed in the hope that it will be -- |
-- useful, but WITHOUT ANY WARRANTY; without even the implied -- |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- |
-- PURPOSE. See the GNU Lesser General Public License for more -- |
-- details. -- |
-- -- |
-- You should have received a copy of the GNU Lesser General -- |
-- Public License along with this source; if not, download it -- |
-- from http://www.opencores.org/lgpl.shtml -- |
-- -- |
------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
/btc_dsha256/trunk/rtl/vhdl/misc/SyncReset.vhd
1,6 → 1,34
-- Copyright (c) 2013 VariStream |
-- Author : Yu Peng |
-- Notes: Generates a "synchronous" reset from the async global reset |
------------------------------------------------------------------- |
-- -- |
-- Copyright (C) 2013 Author and VariStream Studio -- |
-- Author : Yu Peng -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- This source file is free software; you can redistribute it -- |
-- and/or modify it under the terms of the GNU Lesser General -- |
-- Public License as published by the Free Software Foundation; -- |
-- either version 2.1 of the License, or (at your option) any -- |
-- later version. -- |
-- -- |
-- This source is distributed in the hope that it will be -- |
-- useful, but WITHOUT ANY WARRANTY; without even the implied -- |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- |
-- PURPOSE. See the GNU Lesser General Public License for more -- |
-- details. -- |
-- -- |
-- You should have received a copy of the GNU Lesser General -- |
-- Public License along with this source; if not, download it -- |
-- from http://www.opencores.org/lgpl.shtml -- |
-- -- |
------------------------------------------------------------------- |
-- Notes: |
-- Generates a "synchronous" reset from the async global |
-- reset. |
------------------------------------------------------------------- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
/btc_dsha256/trunk/rtl/vhdl/misc/edgedtc.vhd
1,11 → 1,35
---------------------------------------------------------------------------------------------------------------------- |
-- Copyright (c) 2013 VariStream |
-- Author : Yu Peng |
-- Description: |
-- Edge detector |
-- If iEdge = 1 > rising edge detect |
-- If iEdge = 0 > falling edge detect |
---------------------------------------------------------------------------------------------------------------------- |
------------------------------------------------------------------- |
-- -- |
-- Copyright (C) 2013 Author and VariStream Studio -- |
-- Author : Yu Peng -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- This source file is free software; you can redistribute it -- |
-- and/or modify it under the terms of the GNU Lesser General -- |
-- Public License as published by the Free Software Foundation; -- |
-- either version 2.1 of the License, or (at your option) any -- |
-- later version. -- |
-- -- |
-- This source is distributed in the hope that it will be -- |
-- useful, but WITHOUT ANY WARRANTY; without even the implied -- |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- |
-- PURPOSE. See the GNU Lesser General Public License for more -- |
-- details. -- |
-- -- |
-- You should have received a copy of the GNU Lesser General -- |
-- Public License along with this source; if not, download it -- |
-- from http://www.opencores.org/lgpl.shtml -- |
-- -- |
------------------------------------------------------------------- |
-- Description: |
-- Edge detector |
-- If iEdge = 1 > rising edge detect |
-- If iEdge = 0 > falling edge detect |
------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
/btc_dsha256/trunk/rtl/vhdl/misc/sdpram_infer_read_first_outreg.vhd
1,13 → 1,40
------------------------------------------------------------------------------- |
-- Copyright (c) 2013 VariStream |
-- Author : Yu Peng |
-- Description: |
-- Simple dual-port RAM in read-first mode with output register. |
-- This block infers block RAM or distribute RAM according to value of gADDRESS_WIDTH and gDATA_WIDTH, |
-- NOTE: |
-- Reset is on data output ONLY. |
-- This requirement follows the XST User Guide to synthesize into BRAM. |
------------------------------------------------------------------------------- |
------------------------------------------------------------------- |
-- -- |
-- Copyright (C) 2013 Author and VariStream Studio -- |
-- Author : Yu Peng -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- This source file is free software; you can redistribute it -- |
-- and/or modify it under the terms of the GNU Lesser General -- |
-- Public License as published by the Free Software Foundation; -- |
-- either version 2.1 of the License, or (at your option) any -- |
-- later version. -- |
-- -- |
-- This source is distributed in the hope that it will be -- |
-- useful, but WITHOUT ANY WARRANTY; without even the implied -- |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- |
-- PURPOSE. See the GNU Lesser General Public License for more -- |
-- details. -- |
-- -- |
-- You should have received a copy of the GNU Lesser General -- |
-- Public License along with this source; if not, download it -- |
-- from http://www.opencores.org/lgpl.shtml -- |
-- -- |
------------------------------------------------------------------- |
-- Description: |
-- Simple dual-port RAM in read-first mode with output |
-- register. |
-- This block infers block RAM or distribute RAM according |
-- to value of gADDRESS_WIDTH and gDATA_WIDTH. |
-- NOTE: |
-- Reset is on data output ONLY. |
-- This requirement follows the XST User Guide to synthesize |
-- into BRAM. |
------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
/btc_dsha256/trunk/rtl/vhdl/misc/sync_fifo_infer.vhd
1,10 → 1,34
--------------------------------------------------------------------------------------------------- |
-- Copyright (c) 2013 VariStream |
-- Author : Yu Peng |
------------------------------------------------------------------- |
-- -- |
-- Copyright (C) 2013 Author and VariStream Studio -- |
-- Author : Yu Peng -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- This source file is free software; you can redistribute it -- |
-- and/or modify it under the terms of the GNU Lesser General -- |
-- Public License as published by the Free Software Foundation; -- |
-- either version 2.1 of the License, or (at your option) any -- |
-- later version. -- |
-- -- |
-- This source is distributed in the hope that it will be -- |
-- useful, but WITHOUT ANY WARRANTY; without even the implied -- |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- |
-- PURPOSE. See the GNU Lesser General Public License for more -- |
-- details. -- |
-- -- |
-- You should have received a copy of the GNU Lesser General -- |
-- Public License along with this source; if not, download it -- |
-- from http://www.opencores.org/lgpl.shtml -- |
-- -- |
------------------------------------------------------------------- |
-- Description: |
-- Implement BRAM according to gADDRESS_WIDTH and gDATA_WIDTH |
-- Maxim number of data word is (2**gADDRESS_WIDTH - 1) |
--------------------------------------------------------------------------------------------------- |
------------------------------------------------------------------- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
/btc_dsha256/trunk/rtl/vhdl/misc/sdpram_infer_read_first_outreset.vhd
1,13 → 1,40
------------------------------------------------------------------------------- |
-- Copyright (c) 2013 VariStream |
-- Author : Yu Peng |
-- Description: |
-- Simple dual-port RAM in read-first mode with output register reset. |
-- This block infers block RAM or distribute RAM according to value of gADDRESS_WIDTH and gDATA_WIDTH, |
-- NOTE: |
-- Reset is on data output ONLY. |
-- This requirement follows the XST User Guide to synthesize into BRAM. |
------------------------------------------------------------------------------- |
------------------------------------------------------------------- |
-- -- |
-- Copyright (C) 2013 Author and VariStream Studio -- |
-- Author : Yu Peng -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- This source file is free software; you can redistribute it -- |
-- and/or modify it under the terms of the GNU Lesser General -- |
-- Public License as published by the Free Software Foundation; -- |
-- either version 2.1 of the License, or (at your option) any -- |
-- later version. -- |
-- -- |
-- This source is distributed in the hope that it will be -- |
-- useful, but WITHOUT ANY WARRANTY; without even the implied -- |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- |
-- PURPOSE. See the GNU Lesser General Public License for more -- |
-- details. -- |
-- -- |
-- You should have received a copy of the GNU Lesser General -- |
-- Public License along with this source; if not, download it -- |
-- from http://www.opencores.org/lgpl.shtml -- |
-- -- |
------------------------------------------------------------------- |
-- Description: |
-- Simple dual-port RAM in read-first mode with output |
-- register reset. |
-- This block infers block RAM or distribute RAM according |
-- to value of gADDRESS_WIDTH and gDATA_WIDTH, |
-- NOTE: |
-- Reset is on data output ONLY. |
-- This requirement follows the XST User Guide to |
-- synthesize into BRAM. |
------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
/btc_dsha256/trunk/rtl/vhdl/misc/HandShake.vhd
1,6 → 1,30
-- Copyright (c) 2013 VariStream |
-- Author : Yu Peng |
|
------------------------------------------------------------------- |
-- -- |
-- Copyright (C) 2013 Author and VariStream Studio -- |
-- Author : Yu Peng -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- This source file is free software; you can redistribute it -- |
-- and/or modify it under the terms of the GNU Lesser General -- |
-- Public License as published by the Free Software Foundation; -- |
-- either version 2.1 of the License, or (at your option) any -- |
-- later version. -- |
-- -- |
-- This source is distributed in the hope that it will be -- |
-- useful, but WITHOUT ANY WARRANTY; without even the implied -- |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- |
-- PURPOSE. See the GNU Lesser General Public License for more -- |
-- details. -- |
-- -- |
-- You should have received a copy of the GNU Lesser General -- |
-- Public License along with this source; if not, download it -- |
-- from http://www.opencores.org/lgpl.shtml -- |
-- -- |
------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
/btc_dsha256/trunk/rtl/vhdl/misc/pipelines_without_reset.vhd
1,5 → 1,30
-- Copyright (c) 2013 VariStream |
-- Author : Yu Peng |
------------------------------------------------------------------- |
-- -- |
-- Copyright (C) 2013 Author and VariStream Studio -- |
-- Author : Yu Peng -- |
-- -- |
-- This source file may be used and distributed without -- |
-- restriction provided that this copyright statement is not -- |
-- removed from the file and that any derivative work contains -- |
-- the original copyright notice and the associated disclaimer. -- |
-- -- |
-- This source file is free software; you can redistribute it -- |
-- and/or modify it under the terms of the GNU Lesser General -- |
-- Public License as published by the Free Software Foundation; -- |
-- either version 2.1 of the License, or (at your option) any -- |
-- later version. -- |
-- -- |
-- This source is distributed in the hope that it will be -- |
-- useful, but WITHOUT ANY WARRANTY; without even the implied -- |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR -- |
-- PURPOSE. See the GNU Lesser General Public License for more -- |
-- details. -- |
-- -- |
-- You should have received a copy of the GNU Lesser General -- |
-- Public License along with this source; if not, download it -- |
-- from http://www.opencores.org/lgpl.shtml -- |
-- -- |
------------------------------------------------------------------- |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |