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/trunk/looping/sbox4.vhd
0,0 → 1,59
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 01/22/2008
-- Last Update: 02/19/2008
-- Project Name: camellia-vhdl
-- Description: Asynchronous SBOX4
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
 
entity SBOX4 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end SBOX4;
 
architecture RTL of SBOX4 is
 
component SBOX1 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
 
-- SBOX1 signals
signal s1_data_in : STD_LOGIC_VECTOR(0 to 7);
signal s1_data_out : STD_LOGIC_VECTOR(0 to 7);
 
begin
 
S1 : SBOX1
port map(s1_data_in, s1_data_out);
 
s1_data_in <= data_in(1 to 7) & data_in(0);
data_out <= s1_data_out;
 
end RTL;
/trunk/looping/control.vhd
0,0 → 1,765
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 01/31/2008
-- Last Update: 03/25/2008
-- Project Name: camellia-vhdl
-- Description: Control unit and key handling
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity control is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (0 to 127);
key_in : in STD_LOGIC_VECTOR (0 to 255);
k_len : in STD_LOGIC_VECTOR (0 to 1);
new_key : in STD_LOGIC;
enc_dec : in STD_LOGIC;
input_rdy : in STD_LOGIC;
data_to : out STD_LOGIC_VECTOR (0 to 127); -- data to datapath
k1 : out STD_LOGIC_VECTOR (0 to 63);
k2 : out STD_LOGIC_VECTOR (0 to 63);
newdata : out STD_LOGIC;
sel : out STD_LOGIC;
pre_xor : out STD_LOGIC_VECTOR (0 to 127);
post_xor : out STD_LOGIC_VECTOR (0 to 127);
data_from : in STD_LOGIC_VECTOR (0 to 127) -- data from datapath
);
end control;
 
architecture RTL of control is
 
type STATUS is (RST,
KEYa, KEYb, KEYc, KEYd, KEYe, KEYf,
SIX1a, SIX1b, SIX1c, SIX1d, SIX1e, SIX1f,
FL1,
SIX2a, SIX2b, SIX2c, SIX2d, SIX2e, SIX2f,
FL2,
SIX3a, SIX3b, SIX3c, SIX3d, SIX3e, SIX3f,
FL3,
SIX4a, SIX4b, SIX4c, SIX4d, SIX4e, SIX4f);
signal PS, NS : STATUS;
type K1_TYPE is (SIG1, SIG2, SIG3, SIG4, SIG5, SIG6,
KL_L, KL_R, KR_L, KR_R, KA_L, KA_R, KB_L, KB_R);
signal k1_sel : K1_TYPE;
type K2_TYPE is (KL_L, KL_R, KR_L, KR_R, KA_L, KA_R, KB_L, KB_R);
signal k2_sel : K2_TYPE;
type POSTXOR_TYPE is (KL, KA, KB, ZERO);
signal postxor_sel : POSTXOR_TYPE;
type PREXOR_TYPE is (KL, KR, KA, KB, ZERO);
signal prexor_sel : PREXOR_TYPE;
 
-- keys
signal reg_kr : STD_LOGIC_VECTOR (0 to 127);
signal reg_ka : STD_LOGIC_VECTOR (0 to 127);
signal reg_kb : STD_LOGIC_VECTOR (0 to 127);
--keys shifted each step
signal reg_kl_s : STD_LOGIC_VECTOR (0 to 127);
signal reg_kr_s : STD_LOGIC_VECTOR (0 to 127);
signal reg_ka_s : STD_LOGIC_VECTOR (0 to 127);
signal reg_kb_s : STD_LOGIC_VECTOR (0 to 127);
 
-- input constant
constant KLEN_128 : STD_LOGIC_VECTOR (0 to 1) := "00";
constant KLEN_192 : STD_LOGIC_VECTOR (0 to 1) := "01";
constant KLEN_256 : STD_LOGIC_VECTOR (0 to 1) := "10";
constant ENC : STD_LOGIC := '0';
constant DEC : STD_LOGIC := '1';
constant SEL_F : STD_LOGIC := '0';
constant SEL_FL : STD_LOGIC := '1';
 
-- constant keys
constant sigma1 : STD_LOGIC_VECTOR (0 to 63) := X"A09E667F3BCC908B";
constant sigma2 : STD_LOGIC_VECTOR (0 to 63) := X"B67AE8584CAA73B2";
constant sigma3 : STD_LOGIC_VECTOR (0 to 63) := X"C6EF372FE94F82BE";
constant sigma4 : STD_LOGIC_VECTOR (0 to 63) := X"54FF53A5F1D36F1C";
constant sigma5 : STD_LOGIC_VECTOR (0 to 63) := X"10E527FADE682D1D";
constant sigma6 : STD_LOGIC_VECTOR (0 to 63) := X"B05688C2B3E6C1FD";
 
begin
 
with k1_sel select
k1 <= sigma1 when SIG1,
sigma2 when SIG2,
sigma3 when SIG3,
sigma4 when SIG4,
sigma5 when SIG5,
sigma6 when SIG6,
reg_kl_s(0 to 63) when KL_L,
reg_kl_s(64 to 127) when KL_R,
reg_kr_s(0 to 63) when KR_L,
reg_kr_s(64 to 127) when KR_R,
reg_ka_s(0 to 63) when KA_L,
reg_ka_s(64 to 127) when KA_R,
reg_kb_s(0 to 63) when KB_L,
reg_kb_s(64 to 127) when others;
with k2_sel select
k2 <= reg_kl_s(0 to 63) when KL_L,
reg_kl_s(64 to 127) when KL_R,
reg_kr_s(0 to 63) when KR_L,
reg_kr_s(64 to 127) when KR_R,
reg_ka_s(0 to 63) when KA_L,
reg_ka_s(64 to 127) when KA_R,
reg_kb_s(0 to 63) when KB_L,
reg_kb_s(64 to 127) when others;
with postxor_sel select
post_xor <= key_in(64 to 127) & key_in(0 to 63) when KL,
reg_ka_s(64 to 127) & reg_ka_s(0 to 63) when KA,
reg_kb_s(64 to 127) & reg_kb_s(0 to 63) when KB,
(others=>'0') when others;
with prexor_sel select
pre_xor <= key_in(0 to 127) when KL,
reg_kr_s when KR,
reg_ka_s when KA,
reg_kb_s when KB,
(others=>'0') when others;
 
REGISTERS_UPDATE : process(PS)
variable coming_from_key : STD_LOGIC;
begin
case PS is
when RST =>
reg_kr <= (others=>'0');
reg_ka <= (others=>'0');
reg_kb <= (others=>'0');
reg_kl_s <= (others=>'0');
reg_kr_s <= (others=>'0');
reg_ka_s <= (others=>'0');
reg_kb_s <= (others=>'0');
coming_from_key := '0';
when KEYa =>
coming_from_key := '1';
reg_kl_s <= key_in(0 to 127); -- kl
case k_len is
when KLEN_192 =>
reg_kr <= key_in(128 to 191) & not (key_in(128 to 191));
reg_kr_s <= key_in(128 to 191) & not (key_in(128 to 191));
when KLEN_256 =>
reg_kr <= key_in(128 to 255);
reg_kr_s <= key_in(128 to 255);
when others =>
reg_kr <= (others=>'0');
reg_kr_s <= (others=>'0');
end case;
k1_sel <= SIG1;
when KEYb =>
k1_sel <= SIG2;
when KEYc =>
k1_sel <= SIG3;
when KEYd =>
k1_sel <= SIG4;
when KEYe =>
reg_ka <= data_from;
reg_ka_s <= data_from;
k1_sel <= SIG5;
when KEYf =>
k1_sel <= SIG6;
when SIX1a =>
if (enc_dec = ENC) then
if (coming_from_key = '1') then
if (k_len = KLEN_128) then
reg_ka <= data_from;
reg_ka_s <= data_from;
else
reg_kb <= data_from;
reg_kb_s <= data_from;
end if;
else
reg_ka_s <= reg_ka;
reg_kb_s <= reg_kb;
reg_kl_s <= key_in(0 to 127); --kl
reg_kr_s <= reg_kr;
end if;
if (k_len = KLEN_128) then
k1_sel <= KA_L;
else
k1_sel <= KB_L;
end if;
else -- DEC
if (coming_from_key = '1') then
if (k_len = KLEN_128) then
reg_ka <= data_from;
reg_ka_s <= data_from(111 to 127) & data_from(0 to 110); -- >>> 17
else
reg_kb <= data_from;
reg_kb_s <= data_from(111 to 127) & data_from(0 to 110); -- >>> 17
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
end if;
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
else
reg_ka_s <= reg_ka(111 to 127) & reg_ka(0 to 110); -- >>> 17
reg_kb_s <= reg_kb(111 to 127) & reg_kb(0 to 110); -- >>> 17
reg_kl_s <= key_in(111 to 127) & key_in(0 to 110); --kl >>> 17
reg_kr_s <= reg_kr(111 to 127) & reg_kr(0 to 110); -- >>> 17
end if;
k1_sel <= KL_R;
end if;
when SIX1b =>
coming_from_key := '0';
if (enc_dec = ENC) then
if (k_len = KLEN_128) then
k1_sel <= KA_R;
else
k1_sel <= KB_R;
end if;
else -- DEC
k1_sel <= KL_L; -- for each value of k_len
end if;
when SIX1c =>
if (enc_dec = ENC) then
if (k_len = KLEN_128) then
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
else
k1_sel <= KR_L;
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
end if;
else -- DEC
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
k1_sel <= KA_R; -- for each value of k_len
end if;
when SIX1d =>
if (enc_dec = ENC) then
if (k_len = KLEN_128) then
k1_sel <= KL_R;
else
k1_sel <= KR_R;
end if;
else -- DEC
k1_sel <= KA_L; -- for each value of k_len
end if;
when SIX1e =>
if (enc_dec = ENC) then
if (k_len = KLEN_128) then
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KA_L;
else -- DEC
if (k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
k1_sel <= KL_R;
else
reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
k1_sel <= KR_R;
end if;
end if;
when SIX1f =>
if (enc_dec = ENC) then
k1_sel <= KA_R;
else -- DEC
if (k_len = KLEN_128) then
k1_sel <= KL_L;
else
k1_sel <= KR_L;
end if;
end if;
when FL1 =>
if (enc_dec = ENC) then
if (k_len = KLEN_128) then
k1_sel <= KA_L;
k2_sel <= KA_R;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
k1_sel <= KR_L;
k2_sel <= KR_R;
reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (k_len = KLEN_128) then
k1_sel <= KL_R;
k2_sel <= KL_L;
else
k1_sel <= KA_R;
k2_sel <= KA_L;
end if;
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
end if;
when SIX2a =>
if (enc_dec = ENC) then
if (k_len = KLEN_128) then
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
else
k1_sel <= KB_L;
reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (k_len = KLEN_128) then
k1_sel <= KA_R;
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
else
k1_sel <= KL_R;
reg_kb_s <= reg_kb_s(111 to 127) & reg_kb_s(0 to 110); -- >>> 17
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
end if;
end if;
when SIX2b =>
if (enc_dec = ENC) then
if (k_len = KLEN_128) then
k1_sel <= KL_R;
else
k1_sel <= KB_R;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (k_len = KLEN_128) then
k1_sel <= KA_L;
else
k1_sel <= KL_L;
reg_kb_s <= reg_kb_s(111 to 127) & reg_kb_s(0 to 110); -- >>> 17
end if;
end if;
when SIX2c =>
if (enc_dec = ENC) then
if (k_len = KLEN_128) then
k1_sel <= KA_L;
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (k_len = KLEN_128) then
k1_sel <= KL_R;
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
else
k1_sel <= KB_R;
reg_kb_s <= reg_kb_s(111 to 127) & reg_kb_s(0 to 110); -- >>> 17
end if;
end if;
when SIX2d =>
if (enc_dec = ENC) then
if (k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KL_R;
else -- DEC
if (k_len = KLEN_128) then
k1_sel <= KA_L;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
else
k1_sel <= KB_L;
reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
end if;
end if;
when SIX2e =>
if (enc_dec = ENC) then
if (k_len = KLEN_128) then
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KA_L;
else -- DEC
if (k_len = KLEN_128) then
k1_sel <= KL_R;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
else
k1_sel <= KR_R;
reg_kr_s <= reg_kr_s(111 to 127) & reg_kr_s(0 to 110); -- >>> 17
end if;
end if;
when SIX2f =>
if (enc_dec = ENC) then
k1_sel <= KA_R;
else -- DEC
if (k_len = KLEN_128) then
k1_sel <= KL_L;
else
k1_sel <= KR_L;
end if;
end if;
when FL2 =>
if (enc_dec = ENC) then
if (k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
else
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
end if;
k1_sel <= KL_L;
k2_sel <= KL_R;
else -- DEC
if (k_len = KLEN_128) then
k1_sel <= KA_R;
k2_sel <= KA_L;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
else
k1_sel <= KL_R;
k2_sel <= KL_L;
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
end if;
end if;
when SIX3a =>
if (enc_dec = ENC) then
if (k_len = KLEN_128) then
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
else
k1_sel <= KR_L;
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (k_len = KLEN_128) then
k1_sel <= KA_R;
else
k1_sel <= KA_R;
end if;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
end if;
when SIX3b =>
if (enc_dec = ENC) then
if (k_len = KLEN_128) then
k1_sel <= KL_R;
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else
k1_sel <= KR_R;
reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (k_len = KLEN_128) then
k1_sel <= KA_L;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
else
k1_sel <= KA_L;
end if;
end if;
when SIX3c =>
if (enc_dec = ENC) then
if (k_len = KLEN_128) then
k1_sel <= KA_L;
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else
k1_sel <= KB_L;
reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
end if;
else -- DEC
if (k_len = KLEN_128) then
k1_sel <= KL_R;
else
k1_sel <= KL_R;
end if;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
when SIX3d =>
if (enc_dec = ENC) then
if (k_len = KLEN_128) then
k1_sel <= KA_R;
else
k1_sel <= KB_R;
end if;
else -- DEC
if (k_len = KLEN_128) then
k1_sel <= KL_L;
else
k1_sel <= KL_L;
reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
end if;
end if;
when SIX3e =>
if (enc_dec = ENC) then
if (k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
else
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
end if;
k1_sel <= KL_L;
else -- DEC
if (k_len = KLEN_128) then
k1_sel <= KA_R;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
else
k1_sel <= KB_R;
reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
end if;
end if;
when SIX3f =>
if (enc_dec = ENC) then
if (k_len = KLEN_128) then
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KL_R;
else -- DEC
if (k_len = KLEN_128) then
k1_sel <= KA_L;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
else
k1_sel <= KB_L;
reg_kr_s <= reg_kr_s(113 to 127) & reg_kr_s(0 to 112); -- >>> 15
end if;
end if;
when FL3 =>
if (enc_dec = ENC) then
k1_sel <= KA_L;
k2_sel <= KA_R;
reg_kr_s <= reg_kr_s(17 to 127) & reg_kr_s(0 to 16); -- <<< 17
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KR_R;
k2_sel <= KR_L;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
reg_kr_s <= reg_kr_s(113 to 127) & reg_kr_s(0 to 112); -- >>> 15
end if;
when SIX4a =>
if (enc_dec = ENC) then
k1_sel <= KR_L;
reg_kr_s <= reg_kr_s(17 to 127) & reg_kr_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KA_R;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
end if;
when SIX4b =>
if (enc_dec = ENC) then
k1_sel <= KR_R;
else -- DEC
k1_sel <= KA_L;
end if;
when SIX4c =>
if (enc_dec = ENC) then
k1_sel <= KA_L;
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KR_R;
reg_kr_s <= reg_kr_s(113 to 127) & reg_kr_s(0 to 112); -- >>> 15
end if;
when SIX4d =>
if (enc_dec = ENC) then
k1_sel <= KA_R;
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
reg_kb_s <= reg_kb_s(17 to 127) & reg_kb_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KR_L;
reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
when SIX4e =>
if (enc_dec = ENC) then
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
reg_kb_s <= reg_kb_s(17 to 127) & reg_kb_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KB_R;
reg_kb_s <= reg_kb_s(113 to 127) & reg_kb_s(0 to 112); -- >>> 15
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
when SIX4f =>
if (enc_dec = ENC) then
k1_sel <= KL_R;
reg_kb_s <= reg_kb_s(17 to 127) & reg_kb_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KB_L;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
end case;
 
if (PS = KEYa) then
data_to <= key_in(0 to 127); --kl
else
data_to <= data_in;
end if;
 
case PS is
when KEYc =>
prexor_sel <= KL;
when KEYa | KEYe =>
prexor_sel <= KR;
when SIX1a =>
if (enc_dec = ENC) then
prexor_sel <= KL;
else
if (k_len = KLEN_128) then
prexor_sel <= KA;
else
prexor_sel <= KB;
end if;
end if;
when others =>
prexor_sel <= ZERO;
end case;
 
case PS is
when SIX3f =>
if (k_len = KLEN_128) then
if (enc_dec = ENC) then
postxor_sel <= KA;
else
postxor_sel <= KL;
end if;
else
postxor_sel <= ZERO;
end if;
when SIX4f =>
if (enc_dec = ENC) then
postxor_sel <= KB;
else
postxor_sel <= KL;
end if;
when others =>
postxor_sel <= ZERO;
end case;
 
if (PS = SIX1a or PS = KEYa) then
newdata <= '1';
else
newdata <= '0';
end if;
 
if (PS = FL1 or PS = FL2 or PS = FL3) then
sel <= SEL_FL;
else
sel <= SEL_F;
end if;
 
end process;
 
STATE_UPDATE: process (clk)
begin
 
if (clk'event and clk = '1') then
 
if (reset = '1') then
PS <= RST;
else
PS <= NS;
end if;
end if;
end process;
NEXT_STATE: process (PS, input_rdy, new_key)
begin
case PS is
when RST =>
NS <= KEYa;
when KEYa =>
if(input_rdy = '1') then
NS <= KEYb;
else
NS <= KEYa;
end if;
when KEYb =>
NS <= KEYc;
when KEYc =>
NS <= KEYd;
when KEYd =>
if (k_len = KLEN_128) then
NS <= SIX1a;
else
NS <= KEYe;
end if;
when KEYe =>
NS <= KEYf;
when KEYf =>
NS <= SIX1a;
when SIX1a =>
if(input_rdy = '1') then
NS <= SIX1b;
else
NS <= SIX1a;
end if;
when SIX1b =>
NS <= SIX1c;
when SIX1c =>
NS <= SIX1d;
when SIX1d =>
NS <= SIX1e;
when SIX1e =>
NS <= SIX1f;
when SIX1f =>
NS <= FL1;
when FL1 =>
NS <= SIX2a;
when SIX2a =>
NS <= SIX2b;
when SIX2b =>
NS <= SIX2c;
when SIX2c =>
NS <= SIX2d;
when SIX2d =>
NS <= SIX2e;
when SIX2e =>
NS <= SIX2f;
when SIX2f =>
NS <= FL2;
when FL2 =>
NS <= SIX3a;
when SIX3a =>
NS <= SIX3b;
when SIX3b =>
NS <= SIX3c;
when SIX3c =>
NS <= SIX3d;
when SIX3d =>
NS <= SIX3e;
when SIX3e =>
NS <= SIX3f;
when SIX3f =>
if (k_len = KLEN_128) then
if (new_key = '1') then
NS <= KEYa;
else
NS <= SIX1a;
end if;
else
NS <= FL3;
end if;
when FL3 =>
NS <= SIX4a;
when SIX4a =>
NS <= SIX4b;
when SIX4b =>
NS <= SIX4c;
when SIX4c =>
NS <= SIX4d;
when SIX4d =>
NS <= SIX4e;
when SIX4e =>
NS <= SIX4f;
when SIX4f =>
if (new_key = '1') then
NS <= KEYa;
else
NS <= SIX1a;
end if;
when others =>
NS <= RST;
end case;
end process;
 
end RTL;
/trunk/looping/fl.vhd
0,0 → 1,73
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 01/22/2008
-- Last Update: 02/21/2008
-- Project Name: camellia-vhdl
-- Description: Asynchronous FL and FL^-1 functions
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
 
entity FL is
port(
fl_in : in STD_LOGIC_VECTOR (0 to 63);
fli_in : in STD_LOGIC_VECTOR (0 to 63);
fl_k : in STD_LOGIC_VECTOR (0 to 63);
fli_k : in STD_LOGIC_VECTOR (0 to 63);
fl_out : out STD_LOGIC_VECTOR (0 to 63);
fli_out : out STD_LOGIC_VECTOR (0 to 63)
);
end FL;
 
architecture RTL of FL is
 
signal fl_a1 : STD_LOGIC_VECTOR (0 to 31);
signal fl_a2 : STD_LOGIC_VECTOR (0 to 31);
signal fl_b1 : STD_LOGIC_VECTOR (0 to 31);
signal fl_b2 : STD_LOGIC_VECTOR (0 to 31);
signal fli_a1 : STD_LOGIC_VECTOR (0 to 31);
signal fli_a2 : STD_LOGIC_VECTOR (0 to 31);
signal fli_b1 : STD_LOGIC_VECTOR (0 to 31);
signal fli_b2 : STD_LOGIC_VECTOR (0 to 31);
 
begin
 
--FL function
fl_a1 <= fl_in(0 to 31) and fl_k(0 to 31);
fl_a2 <= (fl_a1(1 to 31) & fl_a1(0)) xor fl_in(32 to 63);
 
fl_b1 <= fl_a2 or fl_k(32 to 63);
fl_b2 <= fl_in(0 to 31) xor fl_b1;
 
fl_out <= fl_b2 & fl_a2;
 
--FL^-1 function
fli_a1 <= fli_in(32 to 63) or fli_k(32 to 63);
fli_a2 <= fli_in(0 to 31) xor fli_a1;
 
fli_b1 <= fli_a2 and fli_k(0 to 31);
fli_b2 <= (fli_b1(1 to 31) & fli_b1(0)) xor fli_in(32 to 63);
 
fli_out <= fli_a2 & fli_b2;
 
end RTL;
/trunk/looping/f.vhd
0,0 → 1,131
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 01/22/2008
-- Last Update: 01/22/2008
-- Project Name: camellia-vhdl
-- Description: Asynchronous F function
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity F is
port (
x : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 63);
z : out STD_LOGIC_VECTOR (0 to 63)
);
end F;
 
architecture RTL of F is
 
-- S-BOX
component SBOX1 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
component SBOX2 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
component SBOX3 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
component SBOX4 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
 
 
signal y : STD_LOGIC_VECTOR (0 to 63);
signal y1, y2, y3, y4, y5, y6, y7, y8 : STD_LOGIC_VECTOR (0 to 7);
 
signal so1, so2, so3, so4, so5, so6, so7, so8 : STD_LOGIC_VECTOR (0 to 7);
 
signal pa1, pa2, pa3, pa4, pa5, pa6, pa7, pa8 : STD_LOGIC_VECTOR (0 to 7);
 
signal pb1, pb2, pb3, pb4, pb5, pb6, pb7, pb8 : STD_LOGIC_VECTOR (0 to 7);
 
begin
 
y <= x xor k;
 
y8 <= y(56 to 63);
y7 <= y(48 to 55);
y6 <= y(40 to 47);
y5 <= y(32 to 39);
y4 <= y(24 to 31);
y3 <= y(16 to 23);
y2 <= y(8 to 15);
y1 <= y(0 to 7);
 
 
-- S-FUNCTION
S1a : SBOX1
port map(y8, so8);
S1b : SBOX1
port map(y1, so1);
S2a : SBOX2
port map(y5, so5);
S2b : SBOX2
port map(y2, so2);
S3a : SBOX3
port map(y6, so6);
S3b : SBOX3
port map(y3, so3);
S4a : SBOX4
port map(y7, so7);
S4b : SBOX4
port map(y4, so4);
 
-- P-FUNCTION
pa8 <= so8 xor pa2;
pa7 <= so7 xor pa1;
pa6 <= so6 xor pa4;
pa5 <= so5 xor pa3;
pa4 <= so4 xor so5;
pa3 <= so3 xor so8;
pa2 <= so2 xor so7;
pa1 <= so1 xor so6;
 
pb8 <= pa8 xor pb3;
pb7 <= pa7 xor pb2;
pb6 <= pa6 xor pb1;
pb5 <= pa5 xor pb4;
pb4 <= pa4 xor pa7;
pb3 <= pa3 xor pa6;
pb2 <= pa2 xor pa5;
pb1 <= pa1 xor pa8;
 
 
z <= pb5 & pb6 & pb7 & pb8 & pb1 & pb2 & pb3 & pb4;
 
 
end RTL;
/trunk/looping/datapath.vhd
0,0 → 1,148
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 01/22/2008
-- Last Update: 03/04/2008
-- Project Name: camellia-vhdl
-- Description: Datapath
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity datapath is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (0 to 127);
k1 : in STD_LOGIC_VECTOR (0 to 63);
k2 : in STD_LOGIC_VECTOR (0 to 63);
newdata : in STD_LOGIC;
sel : in STD_LOGIC; -- 0 if F, 1 if FL
pre_xor : in STD_LOGIC_VECTOR (0 to 127);
post_xor : in STD_LOGIC_VECTOR (0 to 127);
data_out : out STD_LOGIC_VECTOR (0 to 127)
);
end datapath;
 
architecture RTL of datapath is
 
component F is
port (
x : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 63);
z : out STD_LOGIC_VECTOR (0 to 63)
);
end component;
 
component FL is
port(
fl_in : in STD_LOGIC_VECTOR (0 to 63);
fli_in : in STD_LOGIC_VECTOR (0 to 63);
fl_k : in STD_LOGIC_VECTOR (0 to 63);
fli_k : in STD_LOGIC_VECTOR (0 to 63);
fl_out : out STD_LOGIC_VECTOR (0 to 63);
fli_out : out STD_LOGIC_VECTOR (0 to 63)
);
end component;
 
signal f_in : STD_LOGIC_VECTOR (0 to 63);
signal f_k : STD_LOGIC_VECTOR (0 to 63);
signal f_out : STD_LOGIC_VECTOR (0 to 63);
signal fl_in : STD_LOGIC_VECTOR (0 to 63);
signal fl_k : STD_LOGIC_VECTOR (0 to 63);
signal fl_out : STD_LOGIC_VECTOR (0 to 63);
signal fli_in : STD_LOGIC_VECTOR (0 to 63);
signal fli_k : STD_LOGIC_VECTOR (0 to 63);
signal fli_out : STD_LOGIC_VECTOR (0 to 63);
 
signal data_in_sx : STD_LOGIC_VECTOR (0 to 63);
signal data_in_dx : STD_LOGIC_VECTOR (0 to 63);
signal pre_xor_sx : STD_LOGIC_VECTOR (0 to 63);
signal pre_xor_dx : STD_LOGIC_VECTOR (0 to 63);
 
signal mux1 : STD_LOGIC_VECTOR (0 to 63);
signal mux1_pxor : STD_LOGIC_VECTOR (0 to 63);
signal mux2 : STD_LOGIC_VECTOR (0 to 63);
signal mux2_pxor : STD_LOGIC_VECTOR (0 to 63);
signal f_out_xor : STD_LOGIC_VECTOR (0 to 63);
 
signal reg_fl_out : STD_LOGIC_VECTOR (0 to 63);
signal reg_fli_out : STD_LOGIC_VECTOR (0 to 63);
signal reg_f_out_xor : STD_LOGIC_VECTOR (0 to 63);
signal reg_mux2_pxor : STD_LOGIC_VECTOR (0 to 63);
signal reg_sel : STD_LOGIC;
 
constant SEL_F : STD_LOGIC := '0';
constant SEL_FL : STD_LOGIC := '1';
 
begin
 
F1 : F
port map(f_in, f_k, f_out);
 
FL1 : FL
port map(fl_in, fli_in, fl_k, fli_k, fl_out, fli_out);
 
 
data_in_sx <= data_in(0 to 63);
data_in_dx <= data_in(64 to 127);
pre_xor_sx <= pre_xor(0 to 63);
pre_xor_dx <= pre_xor(64 to 127);
f_in <= mux2_pxor;
f_k <= k1;
fl_in <= reg_f_out_xor;
fl_k <= k1;
fli_in <= reg_mux2_pxor;
fli_k <= k2;
f_out_xor <= f_out xor mux1_pxor;
 
mux1 <= reg_fli_out when newdata='0' and reg_sel=SEL_FL else
reg_mux2_pxor when newdata='0' and reg_sel=SEL_F else
data_in_dx;
mux2 <= reg_fl_out when newdata='0' and reg_sel=SEL_FL else
reg_f_out_xor when newdata='0' and reg_sel=SEL_F else
data_in_sx;
 
mux1_pxor <= mux1 xor pre_xor_dx;
mux2_pxor <= mux2 xor pre_xor_sx;
 
data_out <= (f_out_xor & mux2_pxor) xor post_xor;
 
REGISTERS: process(clk, reset)
begin
 
if (reset = '1') then
reg_fl_out <= (others=>'0');
reg_fli_out <= (others=>'0');
reg_f_out_xor <= (others=>'0');
reg_mux2_pxor <= (others=>'0');
reg_sel <= SEL_F;
elsif (clk'event and clk='1') then
reg_fl_out <= fl_out;
reg_fli_out <= fli_out;
reg_f_out_xor <= f_out_xor;
reg_mux2_pxor <= mux2_pxor;
reg_sel <= sel;
end if;
 
end process;
 
end RTL;
/trunk/looping/camellia.vhd
0,0 → 1,146
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 02/01/2008
-- Last Update: 03/06/2008
-- Project Name: camellia-vhdl
-- Description: Looping version of Camellia
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity camellia is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (0 to 127);
key : in STD_LOGIC_VECTOR (0 to 255);
k_len : in STD_LOGIC_VECTOR (0 to 1);
new_key : in STD_LOGIC;
enc_dec : in STD_LOGIC;
input_rdy : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (0 to 127)
);
end camellia;
 
architecture RTL of camellia is
 
signal s_clk : STD_LOGIC;
signal s_reset : STD_LOGIC;
signal s_data_in : STD_LOGIC_VECTOR (0 to 127);
signal s_key_in : STD_LOGIC_VECTOR (0 to 255);
signal s_k_len : STD_LOGIC_VECTOR (0 to 1);
signal s_new_key : STD_LOGIC;
signal s_enc_dec : STD_LOGIC;
signal s_input_rdy : STD_LOGIC;
signal s_nxt_input : STD_LOGIC;
signal s_data_to : STD_LOGIC_VECTOR (0 to 127);
signal s_k1 : STD_LOGIC_VECTOR (0 to 63);
signal s_k2 : STD_LOGIC_VECTOR (0 to 63);
signal s_newdata : STD_LOGIC;
signal s_sel : STD_LOGIC;
signal s_pre_xor : STD_LOGIC_VECTOR (0 to 127);
signal s_post_xor : STD_LOGIC_VECTOR (0 to 127);
signal s_data_from : STD_LOGIC_VECTOR (0 to 127);
 
component datapath is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (0 to 127);
k1 : in STD_LOGIC_VECTOR (0 to 63);
k2 : in STD_LOGIC_VECTOR (0 to 63);
newdata : in STD_LOGIC;
sel : in STD_LOGIC;
pre_xor : in STD_LOGIC_VECTOR (0 to 127);
post_xor : in STD_LOGIC_VECTOR (0 to 127);
data_out : out STD_LOGIC_VECTOR (0 to 127)
);
end component;
 
component control is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (0 to 127);
key_in : in STD_LOGIC_VECTOR (0 to 255);
k_len : in STD_LOGIC_VECTOR (0 to 1);
new_key : in STD_LOGIC;
enc_dec : in STD_LOGIC;
input_rdy : in STD_LOGIC;
data_to : out STD_LOGIC_VECTOR (0 to 127);
k1 : out STD_LOGIC_VECTOR (0 to 63);
k2 : out STD_LOGIC_VECTOR (0 to 63);
newdata : out STD_LOGIC;
sel : out STD_LOGIC;
pre_xor : out STD_LOGIC_VECTOR (0 to 127);
post_xor : out STD_LOGIC_VECTOR (0 to 127);
data_from : in STD_LOGIC_VECTOR (0 to 127)
);
end component;
 
begin
 
DP : datapath
port map(
clk => s_clk,
reset => s_reset,
data_in => s_data_to,
k1 => s_k1,
k2 => s_k2,
newdata => s_newdata,
sel => s_sel,
pre_xor => s_pre_xor,
post_xor => s_post_xor,
data_out => s_data_from
);
 
CTRL : control
port map(
clk => s_clk,
reset => s_reset,
data_in => s_data_in,
key_in => s_key_in,
k_len => s_k_len,
new_key => s_new_key,
enc_dec => s_enc_dec,
input_rdy => s_input_rdy,
data_to => s_data_to,
k1 => s_k1,
k2 => s_k2,
newdata => s_newdata,
sel => s_sel,
pre_xor => s_pre_xor,
post_xor => s_post_xor,
data_from => s_data_from
);
 
s_clk <= clk;
s_reset <= reset;
s_data_in <= data_in;
s_key_in <= key;
s_k_len <= k_len;
s_new_key <= new_key;
s_enc_dec <= enc_dec;
s_input_rdy <= input_rdy;
data_out <= s_data_from(64 to 127) & s_data_from(0 to 63);
 
end RTL;
/trunk/looping/f_tb.vhd
0,0 → 1,71
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 01/22/2008
-- Last Update: 02/25/2008
-- Project Name: camellia-vhdl
-- Description: VHDL Test Bench for module F
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity f_tb is
end f_tb;
 
ARCHITECTURE behavior of f_tb is
 
-- Component Declaration for the Unit Under Test (UUT)
component F
port (
x : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 63);
z : out STD_LOGIC_VECTOR (0 to 63)
);
end component;
 
--Inputs
signal x : STD_LOGIC_VECTOR(0 to 63) := (others=>'0');
signal k : STD_LOGIC_VECTOR(0 to 63) := (others=>'0');
 
--Outputs
signal z : STD_LOGIC_VECTOR(0 to 63);
 
begin
 
-- Instantiate the Unit Under Test (UUT)
uut: F port map(
x => x,
k => k,
z => z
);
 
tb : process
begin
x <= X"0123456789abcdef";
k <= X"a09e667f3bcc908b";
wait for 10 ns;
x <= X"0000000000000000";
k <= X"0000000000000000";
wait;
end process;
 
 
end;
/trunk/looping/f_tb.do
0,0 → 1,10
vcom -quiet sbox1.vhd
vcom -quiet sbox2.vhd
vcom -quiet sbox3.vhd
vcom -quiet sbox4.vhd
vcom -quiet f.vhd
vcom -quiet f_tb.vhd
vsim f_tb
view wave
add wave -HEX /uut/*
run 50 ns
/trunk/looping/camellia_tb.vhd
0,0 → 1,103
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 02/19/2008
-- Last Update: 03/06/2008
-- Project Name: camellia-vhdl
-- Description: VHDL Test Bench for module camellia
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
entity camellia_tb is
 
end camellia_tb;
 
architecture RTL of camellia_tb is
 
component camellia is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (0 to 127);
key : in STD_LOGIC_VECTOR (0 to 255);
k_len : in STD_LOGIC_VECTOR (0 to 1);
new_key : in STD_LOGIC;
enc_dec : in STD_LOGIC;
input_rdy : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (0 to 127)
);
end component;
 
signal clk : STD_LOGIC;
signal reset : STD_LOGIC;
signal data_in : STD_LOGIC_VECTOR (0 to 127);
signal key : STD_LOGIC_VECTOR (0 to 255);
signal k_len : STD_LOGIC_VECTOR (0 to 1);
signal new_key : STD_LOGIC;
signal enc_dec : STD_LOGIC;
signal input_rdy : STD_LOGIC;
signal data_out : STD_LOGIC_VECTOR (0 to 127);
 
-- constants
constant KLEN_128 : STD_LOGIC_VECTOR (0 to 1) := "00";
constant KLEN_192 : STD_LOGIC_VECTOR (0 to 1) := "01";
constant KLEN_256 : STD_LOGIC_VECTOR (0 to 1) := "10";
constant ENC : STD_LOGIC := '0';
constant DEC : STD_LOGIC := '1';
constant CLK_PERIOD : TIME := 20 ns;
 
begin
 
uut : camellia
port map(clk, reset, data_in, key, k_len, new_key,
enc_dec, input_rdy, data_out);
 
tb : process
begin
reset <= '1';
wait for 15 ns;
reset <= '0';
data_in <= X"0123456789abcdeffedcba9876543210";
key <= X"0123456789abcdeffedcba987654321000112233445566778899aabbccddeeff";
k_len <= KLEN_128;
new_key <= '1';
enc_dec <= '0';
input_rdy <= '1';
wait for 494 ns;
data_in <= X"67673138549669730857065648eabe43";
key <= X"0123456789abcdeffedcba987654321000112233445566778899aabbccddeeff";
k_len <= KLEN_128;
new_key <= '0';
enc_dec <= '1';
input_rdy <= '1';
wait;
end process;
 
clk_gen : process
begin
clk <= '0';
wait for CLK_PERIOD / 2;
clk <= '1';
wait for CLK_PERIOD / 2;
end process;
 
end RTL;
/trunk/looping/sbox1.vhd
0,0 → 1,300
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 01/22/2008
-- Last Update: 01/22/2008
-- Project Name: camellia-vhdl
-- Description: Asynchronous SBOX1
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
 
entity SBOX1 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end SBOX1;
 
architecture RTL of SBOX1 is
begin
 
with data_in select
data_out <= X"70" when X"00",
X"82" when X"01",
X"2C" when X"02",
X"EC" when X"03",
X"B3" when X"04",
X"27" when X"05",
X"C0" when X"06",
X"E5" when X"07",
X"E4" when X"08",
X"85" when X"09",
X"57" when X"0A",
X"35" when X"0B",
X"EA" when X"0C",
X"0C" when X"0D",
X"AE" when X"0E",
X"41" when X"0F",
X"23" when X"10",
X"EF" when X"11",
X"6B" when X"12",
X"93" when X"13",
X"45" when X"14",
X"19" when X"15",
X"A5" when X"16",
X"21" when X"17",
X"ED" when X"18",
X"0E" when X"19",
X"4F" when X"1A",
X"4E" when X"1B",
X"1D" when X"1C",
X"65" when X"1D",
X"92" when X"1E",
X"BD" when X"1F",
X"86" when X"20",
X"B8" when X"21",
X"AF" when X"22",
X"8F" when X"23",
X"7C" when X"24",
X"EB" when X"25",
X"1F" when X"26",
X"CE" when X"27",
X"3E" when X"28",
X"30" when X"29",
X"DC" when X"2A",
X"5F" when X"2B",
X"5E" when X"2C",
X"C5" when X"2D",
X"0B" when X"2E",
X"1A" when X"2F",
X"A6" when X"30",
X"E1" when X"31",
X"39" when X"32",
X"CA" when X"33",
X"D5" when X"34",
X"47" when X"35",
X"5D" when X"36",
X"3D" when X"37",
X"D9" when X"38",
X"01" when X"39",
X"5A" when X"3A",
X"D6" when X"3B",
X"51" when X"3C",
X"56" when X"3D",
X"6C" when X"3E",
X"4D" when X"3F",
X"8B" when X"40",
X"0D" when X"41",
X"9A" when X"42",
X"66" when X"43",
X"FB" when X"44",
X"CC" when X"45",
X"B0" when X"46",
X"2D" when X"47",
X"74" when X"48",
X"12" when X"49",
X"2B" when X"4A",
X"20" when X"4B",
X"F0" when X"4C",
X"B1" when X"4D",
X"84" when X"4E",
X"99" when X"4F",
X"DF" when X"50",
X"4C" when X"51",
X"CB" when X"52",
X"C2" when X"53",
X"34" when X"54",
X"7E" when X"55",
X"76" when X"56",
X"05" when X"57",
X"6D" when X"58",
X"B7" when X"59",
X"A9" when X"5A",
X"31" when X"5B",
X"D1" when X"5C",
X"17" when X"5D",
X"04" when X"5E",
X"D7" when X"5F",
X"14" when X"60",
X"58" when X"61",
X"3A" when X"62",
X"61" when X"63",
X"DE" when X"64",
X"1B" when X"65",
X"11" when X"66",
X"1C" when X"67",
X"32" when X"68",
X"0F" when X"69",
X"9C" when X"6A",
X"16" when X"6B",
X"53" when X"6C",
X"18" when X"6D",
X"F2" when X"6E",
X"22" when X"6F",
X"FE" when X"70",
X"44" when X"71",
X"CF" when X"72",
X"B2" when X"73",
X"C3" when X"74",
X"B5" when X"75",
X"7A" when X"76",
X"91" when X"77",
X"24" when X"78",
X"08" when X"79",
X"E8" when X"7A",
X"A8" when X"7B",
X"60" when X"7C",
X"FC" when X"7D",
X"69" when X"7E",
X"50" when X"7F",
X"AA" when X"80",
X"D0" when X"81",
X"A0" when X"82",
X"7D" when X"83",
X"A1" when X"84",
X"89" when X"85",
X"62" when X"86",
X"97" when X"87",
X"54" when X"88",
X"5B" when X"89",
X"1E" when X"8A",
X"95" when X"8B",
X"E0" when X"8C",
X"FF" when X"8D",
X"64" when X"8E",
X"D2" when X"8F",
X"10" when X"90",
X"C4" when X"91",
X"00" when X"92",
X"48" when X"93",
X"A3" when X"94",
X"F7" when X"95",
X"75" when X"96",
X"DB" when X"97",
X"8A" when X"98",
X"03" when X"99",
X"E6" when X"9A",
X"DA" when X"9B",
X"09" when X"9C",
X"3F" when X"9D",
X"DD" when X"9E",
X"94" when X"9F",
X"87" when X"A0",
X"5C" when X"A1",
X"83" when X"A2",
X"02" when X"A3",
X"CD" when X"A4",
X"4A" when X"A5",
X"90" when X"A6",
X"33" when X"A7",
X"73" when X"A8",
X"67" when X"A9",
X"F6" when X"AA",
X"F3" when X"AB",
X"9D" when X"AC",
X"7F" when X"AD",
X"BF" when X"AE",
X"E2" when X"AF",
X"52" when X"B0",
X"9B" when X"B1",
X"D8" when X"B2",
X"26" when X"B3",
X"C8" when X"B4",
X"37" when X"B5",
X"C6" when X"B6",
X"3B" when X"B7",
X"81" when X"B8",
X"96" when X"B9",
X"6F" when X"BA",
X"4B" when X"BB",
X"13" when X"BC",
X"BE" when X"BD",
X"63" when X"BE",
X"2E" when X"BF",
X"E9" when X"C0",
X"79" when X"C1",
X"A7" when X"C2",
X"8C" when X"C3",
X"9F" when X"C4",
X"6E" when X"C5",
X"BC" when X"C6",
X"8E" when X"C7",
X"29" when X"C8",
X"F5" when X"C9",
X"F9" when X"CA",
X"B6" when X"CB",
X"2F" when X"CC",
X"FD" when X"CD",
X"B4" when X"CE",
X"59" when X"CF",
X"78" when X"D0",
X"98" when X"D1",
X"06" when X"D2",
X"6A" when X"D3",
X"E7" when X"D4",
X"46" when X"D5",
X"71" when X"D6",
X"BA" when X"D7",
X"D4" when X"D8",
X"25" when X"D9",
X"AB" when X"DA",
X"42" when X"DB",
X"88" when X"DC",
X"A2" when X"DD",
X"8D" when X"DE",
X"FA" when X"DF",
X"72" when X"E0",
X"07" when X"E1",
X"B9" when X"E2",
X"55" when X"E3",
X"F8" when X"E4",
X"EE" when X"E5",
X"AC" when X"E6",
X"0A" when X"E7",
X"36" when X"E8",
X"49" when X"E9",
X"2A" when X"EA",
X"68" when X"EB",
X"3C" when X"EC",
X"38" when X"ED",
X"F1" when X"EE",
X"A4" when X"EF",
X"40" when X"F0",
X"28" when X"F1",
X"D3" when X"F2",
X"7B" when X"F3",
X"BB" when X"F4",
X"C9" when X"F5",
X"43" when X"F6",
X"C1" when X"F7",
X"15" when X"F8",
X"E3" when X"F9",
X"AD" when X"FA",
X"F4" when X"FB",
X"77" when X"FC",
X"C7" when X"FD",
X"80" when X"FE",
X"9E" when X"FF",
"--------" when others;
 
end RTL;
/trunk/looping/camellia_tb.do
0,0 → 1,28
vcom -quiet sbox1.vhd
vcom -quiet sbox2.vhd
vcom -quiet sbox3.vhd
vcom -quiet sbox4.vhd
vcom -quiet f.vhd
vcom -quiet fl.vhd
vcom -quiet datapath.vhd
vcom -quiet control.vhd
vcom -quiet camellia.vhd
vcom -quiet camellia_tb.vhd
vsim camellia_tb
view wave
add wave -divider "camellia"
add wave -HEX -ports /uut/*
add wave -divider "control"
add wave -HEX -ports /uut/CTRL/*
add wave /uut/CTRL/PS
add wave -divider "keys"
add wave -HEX /uut/CTRL/reg_kr
add wave -HEX /uut/CTRL/reg_ka
add wave -HEX /uut/CTRL/reg_kb
add wave -HEX /uut/CTRL/reg_kl_s
add wave -HEX /uut/CTRL/reg_kr_s
add wave -HEX /uut/CTRL/reg_ka_s
add wave -HEX /uut/CTRL/reg_kb_s
add wave -divider "datapath"
add wave -HEX -ports /uut/DP/*
run 1400 ns
/trunk/looping/sbox2.vhd
0,0 → 1,59
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 01/22/2008
-- Last Update: 01/22/2008
-- Project Name: camellia-vhdl
-- Description: Asynchronous SBOX2
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
 
entity SBOX2 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end SBOX2;
 
architecture RTL of SBOX2 is
 
component SBOX1 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
 
-- SBOX1 signals
signal s1_data_in : STD_LOGIC_VECTOR(0 to 7);
signal s1_data_out : STD_LOGIC_VECTOR(0 to 7);
 
begin
 
S1 : SBOX1
port map(s1_data_in, s1_data_out);
 
s1_data_in <= data_in;
data_out <= s1_data_out(1 to 7) & s1_data_out(0);
 
end RTL;
/trunk/looping/sbox3.vhd
0,0 → 1,59
 
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@opencores.org>
--
-- Create Date: 01/22/2008
-- Last Update: 01/22/2008
-- Project Name: camellia-vhdl
-- Description: Asynchronous SBOX3
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
 
 
entity SBOX3 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end SBOX3;
 
architecture RTL of SBOX3 is
 
component SBOX1 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
 
-- SBOX1 signals
signal s1_data_in : STD_LOGIC_VECTOR(0 to 7);
signal s1_data_out : STD_LOGIC_VECTOR(0 to 7);
 
begin
 
S1 : SBOX1
port map(s1_data_in, s1_data_out);
 
s1_data_in <= data_in;
data_out <= s1_data_out(7) & s1_data_out(0 to 6);
 
end RTL;

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