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URL https://opencores.org/ocsvn/e1framer/e1framer/trunk

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/tags/release/e1_defr.vhd
0,0 → 1,121
 
library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
 
 
entity e1_defr is
port(E1_in: in STD_LOGIC;--input serial stream
E1_CLK_in: in STD_LOGIC;--clock for input stream
reset: in STD_LOGIC; -- reset
frame_start,byte_ready,sync_ok: out STD_LOGIC;
-- fr1,fr2: out STD_LOGIC;
data: out STD_LOGIC_VECTOR (0 to 7);
-- erri: out integer range 0 to 3;
zero_frame: out STD_LOGIC_VECTOR (0 to 7)--;
-- output: out STD_LOGIC_VECTOR (1 downto 0)
);
end e1_defr ;
 
architecture BEHAVIOR of e1_defr is
 
constant BITS_IN_FRAME: integer :=255;--!!!!!!!!!!!!!!!!!!255
 
 
SIGNAL frame1_det,frame2_det: STD_LOGIC ;
signal prl_in:STD_LOGIC_VECTOR (0 to 7);
signal state: STD_LOGIC_VECTOR (1 downto 0);
 
begin
data<=prl_in;
-------------------------------------------------------------------------------------------------------
-- frame1 and frame2 detection
-------------------------------------------------------------------------------------------------------
frame2_det<=prl_in(1);
with prl_in select
frame1_det<='1' when "10011011",
'0' when others;
------------------------------------------------------------------------------------------------------
-- lower bits come first!!!
-- serial to parallel converter
------------------------------------------------------------------------------------------------------
process (E1_CLK_in)
begin
if (FALLING_EDGE(E1_CLK_in)) then
prl_in(0 to 6)<=prl_in(1 to 7);
prl_in(7)<=E1_in;
end if;
end process;
 
--------------------------------------------------------------------------------------------------------
-- state machine using GRAY CODE (or trying to use GRAY CODE :-) )
-- 00 - waiting for the first frame syncronization sygnal
-- 01 - skipping other frame bits + 8 bits of next syncro signal and trying to detect second frame sync.
-- signal, if all OK go to the 011 state, else to the 000 state
-- 11 - skipping other frame bits + 8 bits of next syncro signal and trying to detect first frame sync.
-- signal, if all OK go to the 010 state, else to the 000 state
-- 10 - start normal data receiving. Syncronizanion complete.
--------------------------------------------------------------------------------------------------------
process (E1_CLK_in,reset)
variable cnt : integer range 0 to 255;
variable s_err: integer range 0 to 3;
variable frame_flag: std_logic;-- determines type of the frame
begin
if (reset='1') then
state<="00";
elsif (RISING_EDGE(E1_CLK_in)) then
CASE state IS
WHEN "00" =>
sync_ok<='0';-- no syncronization
frame_start<='0';
state(0)<=frame1_det; -- waiting for the first frame alignment, if detected go to the next state
cnt:=0;
frame_flag:='0';
s_err:=0;
WHEN "01" =>
if (cnt = BITS_IN_FRAME) then
state(0)<=frame2_det;
state(1)<=frame2_det;
cnt:=0;
else
cnt:=cnt+1;
end if;
WHEN "11" =>
if (cnt = BITS_IN_FRAME) then
state(0)<='0';
state(1)<=frame1_det;
cnt:=0;
else
cnt:=cnt+1;
end if;
WHEN "10" =>
sync_ok<='1';-- syncronization established
if (cnt = BITS_IN_FRAME) then
if(frame_flag='0') then -- detecting wrong syncro signal ?????? according to g704
zero_frame<=prl_in;--store zero frame for future transmission
if(frame2_det='0') then
s_err:=s_err+1;
else
s_err:=0;
end if;
end if;
cnt:=0;
frame_start<='0';-- frame ended
frame_flag:=not(frame_flag);-- change type of zero time-slot
else
--byte_ready placed there to avoid byte_ready generation then time-slot 0 received (cnt = BITS_IN_RFAME)
frame_start<='1';--frame begins
byte_ready<=CONV_STD_LOGIC_VECTOR(cnt,3)(0) and CONV_STD_LOGIC_VECTOR(cnt,3)(1) and CONV_STD_LOGIC_VECTOR(cnt,3)(2);
cnt:=cnt+1;
end if;
-- if received 3 consecutive wrong frame alignment signals system detect "loss of frame alignment" situation
state(1)<=not(CONV_STD_LOGIC_VECTOR(s_err,2)(0) and CONV_STD_LOGIC_VECTOR(s_err,2)(1));
when others=> state<="00";
END CASE;
 
end if;
end process;
 
end BEHAVIOR;
 
/tags/release/e1_frm.vhd
0,0 → 1,101
library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
 
 
entity e1_frm is
port(E1_out,nr: out STD_LOGIC;--output serial stream
E1_CLK_in: in STD_LOGIC;--clock for output stream
reset: in STD_LOGIC; -- reset
frame_start,RD: out STD_LOGIC;-- determines frame start, RD - read signal for "look forvard" memory
data: in STD_LOGIC_VECTOR (0 to 7);
zero_frame: in STD_LOGIC_VECTOR (0 to 7)-- zero frame data
 
--isEmpty : in STD_LOGIC
);
end e1_frm;
 
architecture BEHAVIOR of e1_frm is
 
SIGNAL cnt: integer range 0 to 7;
signal ires,state,frame_type: STD_LOGIC;
signal iData: STD_LOGIC_VECTOR (0 to 7);
 
begin
nr<=ires;
------------------------------------------------------------------------------------------------------
-- lower bits come first!!!
-- parallel to serial converter
------------------------------------------------------------------------------------------------------
process (E1_CLK_in,ires)
begin
if (ires='1') then
cnt<=0;
E1_out<='0';
elsif (FALLING_EDGE(E1_CLK_in)) then
E1_out<=iData(cnt);
cnt<=cnt+1;
end if;
end process;
 
--------------------------------------------------------------------------------------------------------
--this trigger is used to eliminate "short reset" situation: when reset becomes low during "high" E1_CLK_in
--in this situation transmitter starts before state machine set up valid iData signal
--------------------------------------------------------------------------------------------------------
process (E1_CLK_in,reset)
begin
if (reset='1') then
ires<='1';
elsif (FALLING_EDGE(E1_CLK_in)) then
ires<='0';
end if;
end process;
 
--------------------------------------------------------------------------------------------------------
-- state machine
-- 0 - zero time slot generation.
-- 1 - transmission
--------------------------------------------------------------------------------------------------------
process (E1_CLK_in,ires)
variable byte_cnt: integer range 0 to 31;
begin
if (ires='1') then
state<='0';
frame_type<='0';
elsif (RISING_EDGE(E1_CLK_in)) then
CASE state IS
WHEN '0' =>
byte_cnt:=0;
frame_start<='1';
if(frame_type='0') then
iData<="10011011";
else
iData(0)<=zero_frame(0);
iData(2 to 7)<=zero_frame(2 to 7);
iData(1)<='1';--warranty of correct frame signal
end if;
state<=CONV_STD_LOGIC_VECTOR(cnt,3)(0) and CONV_STD_LOGIC_VECTOR(cnt,3)(1) and CONV_STD_LOGIC_VECTOR(cnt,3)(2);
WHEN '1' =>
frame_start<='0';
if (cnt = 0) then
iData<=data;
RD<='1';
else
RD<='0';
end if;
if(cnt=7)then
if(byte_cnt=30) then
state<='0';-- frame trensmitted
frame_type<=not(frame_type);
else
byte_cnt:=byte_cnt+1;
end if;
end if;
when others=> state<='0';
END CASE;
end if;
end process;
 
end BEHAVIOR;
 

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