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/fir_wishbone/trunk/design/quartus-synthesis/tb_fir.vhdl
0,0 → 1,154
/* Synthesisable testbench/BiST for FIR Filter design.
Copyright© 2012 Tauhop Solutions. All rights reserved.
This core is free hardware design; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
License as published by the Free Software Foundation; either
version 2 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Library General Public License for more details.
You should have received a copy of the GNU Library General Public
License along with this library; if not, write to the
Free Software Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA.
License: LGPL.
@dependencies:
@designer(s):
Daniel C.K. Kho [daniel.kho@gmail.com] | [daniel.kho@tauhop.com] | [daniel.kho@sophicdesign.com.my];
Tan Hooi Jing [hooijingtan@gmail.com]
@info:
Revision History: @see Mercurial log for full list of changes.
This notice and disclaimer must be retained as part of this text at all times.
*/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity tb_fir is generic(order:positive:=30; width:positive:=16);
port(
clk:in std_ulogic:='0';
nRst:in std_ulogic:='0';
--u:in signed(16-1 downto 0);
y:buffer signed(16-1 downto 0)
);
end entity tb_fir;
 
architecture rtl of tb_fir is
signal reset:std_ulogic:='0';
signal u:signed(16-1 downto 0);
signal trig:std_logic;
/* synthesis translate_off */
signal clk:std_ulogic:='0';
signal nRst:std_ulogic:='1';
/* synthesis translate_on */
signal count:unsigned(8 downto 0);
signal pwrUpCnt:unsigned(3 downto 0):=(others=>'0');
/* on-chip debugger */
signal dbgSignals:std_ulogic_vector(127 downto 0):=(others=>'0');
-- component fir is generic(order:positive:=31; width:positive:=16);
-- port(
-- /* General settings. */
-- reset:in std_ulogic; -- asserting reset will start protocol sequence transmission. To restart the re-transmission of the sequence, re-assert this reset signal, and the whole SPI sequence will be re-transmitted again.
-- clk:in std_ulogic:='0';
--
-- /* Filter ports. */
-- u:in signed(width-1 downto 0):=(others=>'0');
-- --y:buffer signed(width*2-1 downto 0)
-- y:buffer signed(width-1 downto 0)
-- );
-- end component fir;
/* Explicitly define all multiplications with the "*" operator to use dedicated DSP hardware multipliers. */
attribute multstyle:string; attribute multstyle of rtl:architecture is "dsp"; --altera:
-- attribute mult_style:string; attribute mult_style of fir:entity is "block"; --xilinx:
 
begin
/* synthesis translate_off*/
clk<=not clk after 10 ns;
/* synthesis translate_on*/
process(pwrUpCnt,nRst) is begin
if pwrUpCnt<10 or nRst='0' then reset<='1';
else reset<='0';
end if;
end process;
process(reset,clk) is begin
if reset='1' then count<=(others =>'0');
elsif rising_edge(clk) then
if count<300 then count<=count+1; end if;
end if;
end process;
process(nRst,clk) is begin
if nRst='0' then pwrUpCnt<=(others =>'0');
elsif rising_edge(clk) then
if pwrUpCnt<10 then pwrUpCnt<=pwrUpCnt+1; end if;
end if;
end process;
/* Impulse generator for impulse response measurement. */
u <= (0=>'1', others=>'0') when count=1 else (others=>'0');
filter: entity work.fir(rtl)
generic map(order=>order, width=>width)
port map(
reset=>reset,
clk=>clk,
/* Filter ports. */
u=>u,
y=>y
);
/* Simulation only. */
/* synthesis translate_off */
reporter: process(clk) is begin
if rising_edge(clk) then
/* (u,y) pairs will be exported to CSV and Matlab for plotting.
Results are then correlated to digital simulations and Matlab
simulations of the filter.
*/
report ";" & integer'image(to_integer(u)) & ";"
& integer'image(to_integer(y));
end if;
end process reporter;
process is begin
assert now<5 us report "simulation stopped." severity failure;
wait;
end process;
/* synthesis translate_on */
/* Hardware debugger (SignalTap II embedded logic analyser). */
trig<='1' when count<300 else '0'; -- Stop SignalTap Triggering after 300 counts, Total data=280
/* SignalTap debugger. */
dbgSignals(width-1 downto 0)<=std_ulogic_vector(u); -- u:16bits
dbgSignals(width*2-1 downto width)<=std_ulogic_vector(y); -- y:32bits
dbgSignals(8+width*2 downto width*2)<=std_ulogic_vector(count); --9bits (300<512)
/* debugger: entity work.stp(syn) port map(
acq_clk=>clk,
acq_data_in=>std_logic_vector(dbgSignals), -- Type conversion: std_ulogic_vector --> std_logic_vector
acq_trigger_in=>"1",
trigger_in=>trig
);
*/
end architecture rtl;
fir_wishbone/trunk/design/quartus-synthesis/tb_fir.vhdl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fir_wishbone/trunk/design/quartus-synthesis/fir.vhdl =================================================================== --- fir_wishbone/trunk/design/quartus-synthesis/fir.vhdl (nonexistent) +++ fir_wishbone/trunk/design/quartus-synthesis/fir.vhdl (revision 3) @@ -0,0 +1,148 @@ +/* FIR Filter. + + Copyright© 2012 Tauhop Solutions. All rights reserved. + This core is free hardware design; you can redistribute it and/or + modify it under the terms of the GNU Library General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Library General Public License for more details. + + You should have received a copy of the GNU Library General Public + License along with this library; if not, write to the + Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. + + License: LGPL. + + @dependencies: + @designer(s): + Daniel C.K. Kho [daniel.kho@gmail.com] | [daniel.kho@tauhop.com] | [daniel.kho@sophicdesign.com.my]; + Tan Hooi Jing [hooijingtan@gmail.com] + @info: + Revision History: @see Mercurial log for full list of changes. + + This notice and disclaimer must be retained as part of this text at all times. +*/ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +/* Filter order = number of unit delays. */ +entity fir is generic(order:positive:=30; width:positive:=16); + port( + reset:in std_ulogic; -- asserting reset will start protocol sequence transmission. To restart the re-transmission of the sequence, re-assert this reset signal, and the whole SPI sequence will be re-transmitted again. + clk:in std_ulogic:='0'; + + /* Filter ports. */ + u:in signed(width-1 downto 0):=(others=>'0'); + y:buffer signed(width-1 downto 0) + ); +end entity fir; + +architecture rtl of fir is + /* Memory I/Os: */ + signal q:signed(width-1 downto 0):=(others=>'0'); + --signal rst: std_ulogic; + --signal pwrUpCnt: unsigned(8 downto 0):=(others=>'0'); + --signal trig:std_logic; + + --signal c:unsigned(positive(ceil(log2(real(order))))-1 downto 0); --counter:5bits + + + -- debugger + --signal dbgSignals:std_ulogic_vector(127 downto 0); + + + /* Memories: */ + /* TODO: Change these arrays to internal process variables instead. */ + /* Read-only Memory (ROM). */ + type signed_vector is array(natural range <>) of signed(width-1 downto 0); -- 32-by-N matrix array structure (as in RAM). Similar to integer_vector, difference being base vector is 32-bit unsigned. + type signedx2_vector is array(natural range<>) of signed(width*2-1 downto 0); + + /* Filter length = number of taps = number of coefficients = order + 1 */ + constant b:signed_vector(0 to order):=( + x"FFEF", + x"FFED", + x"FFE8", + x"FFE6", + x"FFEB", + x"0000", + x"002C", + x"0075", + x"00DC", + x"015F", + x"01F4", + x"028E", + x"031F", + x"0394", + x"03E1", + x"03FC", + x"03E1", + x"0394", + x"031F", + x"028E", + x"01F4", + x"015F", + x"00DC", + x"0075", + x"002C", + x"0000", + x"FFEB", + x"FFE6", + x"FFE8", + x"FFED", + x"FFEF" + ); + + /*Memory Addressing*/ +-- signal c:natural range b'range; + + /* Pipes and delay chains. */ + signal y0:signed(width*2-1 downto 0); + signal u_pipe:signed_vector(b'range):=(others=>(others=>'0')); + signal y_pipe:signedx2_vector(b'range):=(others=>(others=>'0')); + + + /* Counters. */ +-- signal cnt:integer range 31 downto -1; -- symbol / bit counter. Counts the bits transmitted on the serial line. + +-- /* memory pointers (acts as the read/write address for the synchronous RAM). */ +-- signal instrPtr:natural range rfbSequencesCache'range; --RFB sequence memory addressing. Acts as instruction pointer. Points to the current SPI instruction to be transmitted on MOSI. Size is one more than the instruction cache size, so it points past the last valid address (used for counting). + /* [end]: Memories. */ + + /* Signal preservations. */ +-- attribute keep:boolean; + + /* Explicitly define all multiplications with the "*" operator to use dedicated DSP hardware multipliers. */ + attribute multstyle:string; attribute multstyle of rtl:architecture is "dsp"; --altera +-- attribute mult_style:string; attribute mult_style of fir:entity is "block"; --xilinx + +begin +-- /* 1-Dimensional Synchronous ROM. */ +-- readCoeffs: process(clk) is begin +-- if rising_edge(clk) then +-- if reset='1' then q<=(others=>'0'); +-- else q<=b(c); +-- end if; +-- end if; +-- end process readCoeffs; + + u_pipe(0)<=u; + u_dlyChain: for i in 1 to u_pipe'high generate + delayChain: process(clk) is begin + if rising_edge(clk) then u_pipe(i)<=u_pipe(i-1); end if; + end process delayChain; + end generate u_dlyChain; + + y_pipe(0)<=b(0)*u; + y_dlyChain: for i in 1 to y_pipe'high generate + y_pipe(i)<=b(i)*u_pipe(i) + y_pipe(i-1); + end generate y_dlyChain; + + y0<=y_pipe(y_pipe'high) when reset='0' else (others=>'0'); + y<=y0(width-1 downto 0); +end architecture rtl;
fir_wishbone/trunk/design/quartus-synthesis/fir.vhdl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: fir_wishbone/trunk/design/fir.vhdl =================================================================== --- fir_wishbone/trunk/design/fir.vhdl (revision 2) +++ fir_wishbone/trunk/design/fir.vhdl (revision 3) @@ -1,6 +1,6 @@ /* FIR Filter. - Copyright© 2012 Daniel C.K. Kho. All rights reserved. + Copyright© 2012 Tauhop Solutions. All rights reserved. This core is free hardware design; you can redistribute it and/or modify it under the terms of the GNU Library General Public License as published by the Free Software Foundation; either @@ -19,7 +19,9 @@ License: LGPL. @dependencies: - @designer: Daniel C.K. Kho [daniel.kho@gmail.com] | [daniel.kho@tauhop.com] | [daniel.kho@sophicdesign.com.my] + @designer(s): + Daniel C.K. Kho [daniel.kho@gmail.com] | [daniel.kho@tauhop.com] | [daniel.kho@sophicdesign.com.my]; + Tan Hooi Jing [hooijingtan@gmail.com] @info: Revision History: @see Mercurial log for full list of changes. @@ -28,37 +30,41 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ---use ieee.math_real.all; -- log,sin ---entity fir is generic(numCoeffs:positive:=145; width:positive:=28); -entity fir is generic(numCoeffs:positive:=31; width:positive:=16); +/* Filter order = number of unit delays. */ +entity fir is generic(order:positive:=30; width:positive:=16); port( - /* General settings. */ reset:in std_ulogic; -- asserting reset will start protocol sequence transmission. To restart the re-transmission of the sequence, re-assert this reset signal, and the whole SPI sequence will be re-transmitted again. clk:in std_ulogic:='0'; /* Filter ports. */ - u:in unsigned(width-1 downto 0):=(others=>'0'); - y:buffer unsigned(width*2-1 downto 0) + u:in signed(width-1 downto 0):=(others=>'0'); + y:buffer signed(width-1 downto 0) ); end entity fir; architecture rtl of fir is --- /* Memories. */ --- type rfbFsm_vector is array(natural range <>) of rfbFsm; --- /* Memory I/Os: */ - signal q:unsigned(width-1 downto 0):=(others=>'0'); + signal q:signed(width-1 downto 0):=(others=>'0'); + --signal rst: std_ulogic; + --signal pwrUpCnt: unsigned(8 downto 0):=(others=>'0'); + --signal trig:std_logic; - --signal c:unsigned(positive(ceil(log2(real(numCoeffs))))-1 downto 0); --counter:5bits + --signal c:unsigned(positive(ceil(log2(real(order))))-1 downto 0); --counter:5bits - /* Memory arrays: */ + + -- debugger + --signal dbgSignals:std_ulogic_vector(127 downto 0); + + + /* Memories: */ /* TODO: Change these arrays to internal process variables instead. */ /* Read-only Memory (ROM). */ - type unsigned_vector is array(natural range <>) of unsigned(width-1 downto 0); -- 32-by-N matrix array structure (as in RAM). Similar to integer_vector, difference being base vector is 32-bit unsigned. - type unsignedx2_vector is array(natural range<>) of unsigned(width*2-1 downto 0); + type signed_vector is array(natural range <>) of signed(width-1 downto 0); -- 32-by-N matrix array structure (as in RAM). Similar to integer_vector, difference being base vector is 32-bit unsigned. + type signedx2_vector is array(natural range<>) of signed(width*2-1 downto 0); - constant b:unsigned_vector(0 to numCoeffs-1):=( + /* Filter length = number of taps = number of coefficients = order + 1 */ + constant b:signed_vector(0 to order):=( x"FFEF", x"FFED", x"FFE8", @@ -91,12 +97,14 @@ x"FFED", x"FFEF" ); - /*Memory Addressing*/ - --signal c:natural range b'range; + /*Memory Addressing*/ +-- signal c:natural range b'range; + /* Pipes and delay chains. */ - signal u_pipe:unsigned_vector(b'range):=(others=>(others=>'0')); - signal y_pipe:unsignedx2_vector(b'range):=(others=>(others=>'0')); + signal y0:signed(width*2-1 downto 0); + signal u_pipe:signed_vector(b'range):=(others=>(others=>'0')); + signal y_pipe:signedx2_vector(b'range):=(others=>(others=>'0')); /* Counters. */ @@ -108,18 +116,13 @@ /* Signal preservations. */ -- attribute keep:boolean; --- attribute keep of u_pipe:signal is true; --- attribute keep of b:constant is true; --- attribute keep of y_pipe:signal is true; /* Explicitly define all multiplications with the "*" operator to use dedicated DSP hardware multipliers. */ - --altera: --- attribute multstyle:string; attribute multstyle of rtl:architecture is "dsp"; --- --xilinx: --- attribute mult_style:string; attribute mult_style of fir:entity is "block"; + attribute multstyle:string; attribute multstyle of rtl:architecture is "dsp"; --altera +-- attribute mult_style:string; attribute mult_style of fir:entity is "block"; --xilinx begin ----- /* 1-Dimensional Synchronous ROM. */ +-- /* 1-Dimensional Synchronous ROM. */ -- readCoeffs: process(clk) is begin -- if rising_edge(clk) then -- if reset='1' then q<=(others=>'0'); @@ -137,10 +140,9 @@ y_pipe(0)<=b(0)*u; y_dlyChain: for i in 1 to y_pipe'high generate - --y_pipe(i-1)<=b(i)*u_pipe(i) + y_pipe(i-2); --b(i-1)*u_pipe(i-1); - y_pipe(i)<=q*u_pipe(i) + y_pipe(i-1); --b(i-1)*u_pipe(i-1); - --y_pipe(c)<=q*u_pipe(c) + y_pipe(c-1); --b(i-1)*u_pipe(i-1); + y_pipe(i)<=b(i)*u_pipe(i) + y_pipe(i-1); end generate y_dlyChain; - y<=y_pipe(y_pipe'high) when reset='0' else (others=>'0'); + y0<=y_pipe(y_pipe'high) when reset='0' else (others=>'0'); + y<=y0(width-1 downto 0); end architecture rtl;

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