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/fluid_core_2/trunk/bench/tb_staller.v
0,0 → 1,65
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2014-2015 Azmath Moosa ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 3 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
 
module tb_staller;
 
// Inputs
reg Clk;
reg RST;
reg Stall;
 
// Outputs
wire [0:3] stall_lines;
 
// Instantiate the Unit Under Test (UUT)
Staller uut (
.Clk(Clk),
.RST(RST),
.Stall(Stall),
.stall_lines(stall_lines)
);
 
initial begin
// Initialize Inputs
Clk = 0;
RST = 1;
Stall = 0;
 
// Wait 100 ns for global reset to finish
#5 RST = 0;
#65 Stall = 1;
#5 Stall = 0;
// Add stimulus here
 
end
always begin
#10 Clk = ~Clk;
end
endmodule
 
/fluid_core_2/trunk/bench/tb_Test_Bed.v
0,0 → 1,63
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2014-2015 Azmath Moosa ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 3 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
 
module tb_Test_Bed;
 
// Inputs
reg Clk;
reg RST;
reg [0:3] Interrupt;
 
// Instantiate the Unit Under Test (UUT)
Test_Bed uut (
.Clk(Clk),
.RST(RST),
.Interrupt(Interrupt)
);
 
initial begin
// Initialize Inputs
Clk = 0;
RST = 1;
Interrupt = 0;
// Wait 100 ns for global reset to finish
#60;
RST = 0;
// Add stimulus here
 
end
always begin
#50 Clk = ~Clk;
end
// always begin
// #3400 Interrupt[1] <= 1;
// #100 Interrupt[1] <= 0;
// end
endmodule
 
/fluid_core_2/trunk/bench/tb_Reg_hist.v
0,0 → 1,81
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2014-2015 Azmath Moosa ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 3 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
 
 
module tb_Reg_hist;
 
// Inputs
reg Clk;
reg [0:2] nxt_reg_A;
reg [0:2] nxt_reg_B;
reg [0:2] nxt_dest;
 
// Outputs
wire [0:1] reg_src_A;
wire [0:1] reg_src_B;
 
// Instantiate the Unit Under Test (UUT)
Reg_Hist uut (
.Clk(Clk),
.nxt_reg_A(nxt_reg_A),
.nxt_reg_B(nxt_reg_B),
.nxt_dest(nxt_dest),
.reg_src_A(reg_src_A),
.reg_src_B(reg_src_B)
);
 
initial begin
// Initialize Inputs
Clk = 1;
nxt_reg_A = 0;
nxt_reg_B = 0;
nxt_dest = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
 
end
always begin
#50 Clk = ~Clk;
end
always begin
#100 nxt_dest = 0;
#100 nxt_dest = 1;
#100 nxt_dest = 2;
nxt_reg_A = 1;
nxt_reg_B = 0;
#100 nxt_dest = 3;
nxt_reg_A = 1;
nxt_reg_B = 2;
end
endmodule
 

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