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/trunk/openfire_top_syn/data/openfire_top_syn_v2_1_0.pao
0,0 → 1,30
##############################################################################
##
## ***************************************************************************
## ** **
## ** Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. **
## ** **
## ** You may copy and modify these files for your own internal use solely **
## ** with Xilinx programmable logic devices and Xilinx EDK system or **
## ** create IP modules solely for Xilinx programmable logic devices and **
## ** Xilinx EDK system. No rights are granted to distribute any files **
## ** unless they are distributed in Xilinx programmable logic devices. **
## ** **
## ***************************************************************************
##
##############################################################################
## Filename: /home/scraven/Research/multi_processing/openfire/implementation/pcores/openfire_top_syn/data/openfire_top_syn_v2_1_0.pao
## Description: Peripheral Analysis Order
## Date: Mon Apr 4 10:59:55 2005 (by Create and Import Peripheral Wizard)
##############################################################################
 
lib openfire_top_syn openfire_define
lib openfire_top_syn openfire_primitives
lib openfire_top_syn openfire_execute
lib openfire_top_syn openfire_decode
lib openfire_top_syn openfire_fetch
lib openfire_top_syn openfire_regfile
lib openfire_top_syn openfire_pipeline_ctrl
lib openfire_top_syn openfire_cpu
lib openfire_top_syn openfire_opb
lib openfire_top_syn openfire_top_syn
/trunk/openfire_top_syn/data/openfire_top_syn_v2_1_0.mpd
0,0 → 1,189
## Copyright (c) 2004 Xilinx, Inc. All Rights Reserved.
## You may copy and modify these files for your own internal use solely with
## Xilinx programmable logic devices and Xilinx EDK system or create IP
## modules solely for Xilinx programmable logic devices and Xilinx EDK system.
## No rights are granted to distribute any files unless they are distributed in
## Xilinx programmable logic devices.
###################################################################
##
## Name : openfire_top_syn
## Desc : Microprocessor Peripheral Description
## : Automatically generated by PsfUtility
##
###################################################################
 
BEGIN openfire_top_syn
 
## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VERILOG
OPTION CORE_STATE = ACTIVE
OPTION IP_GROUP = USER
 
## Bus Interfaces
BUS_INTERFACE BUS=SFSL0, BUS_STD=FSL, BUS_TYPE=SLAVE, ISVALID = (C_FSL_LINKS >= 1)
BUS_INTERFACE BUS=MFSL0, BUS_STD=FSL, BUS_TYPE=MASTER, ISVALID = (C_FSL_LINKS >= 1)
BUS_INTERFACE BUS=SFSL1, BUS_STD=FSL, BUS_TYPE=SLAVE, ISVALID = (C_FSL_LINKS >= 2)
BUS_INTERFACE BUS=MFSL1, BUS_STD=FSL, BUS_TYPE=MASTER, ISVALID = (C_FSL_LINKS >= 2)
BUS_INTERFACE BUS=SFSL2, BUS_STD=FSL, BUS_TYPE=SLAVE, ISVALID = (C_FSL_LINKS >= 3)
BUS_INTERFACE BUS=MFSL2, BUS_STD=FSL, BUS_TYPE=MASTER, ISVALID = (C_FSL_LINKS >= 3)
BUS_INTERFACE BUS=SFSL3, BUS_STD=FSL, BUS_TYPE=SLAVE, ISVALID = (C_FSL_LINKS >= 4)
BUS_INTERFACE BUS=MFSL3, BUS_STD=FSL, BUS_TYPE=MASTER, ISVALID = (C_FSL_LINKS >= 4)
BUS_INTERFACE BUS=SFSL4, BUS_STD=FSL, BUS_TYPE=SLAVE, ISVALID = (C_FSL_LINKS >= 5)
BUS_INTERFACE BUS=MFSL4, BUS_STD=FSL, BUS_TYPE=MASTER, ISVALID = (C_FSL_LINKS >= 5)
BUS_INTERFACE BUS=SFSL5, BUS_STD=FSL, BUS_TYPE=SLAVE, ISVALID = (C_FSL_LINKS >= 6)
BUS_INTERFACE BUS=MFSL5, BUS_STD=FSL, BUS_TYPE=MASTER, ISVALID = (C_FSL_LINKS >= 6)
BUS_INTERFACE BUS=SFSL6, BUS_STD=FSL, BUS_TYPE=SLAVE, ISVALID = (C_FSL_LINKS >= 7)
BUS_INTERFACE BUS=MFSL6, BUS_STD=FSL, BUS_TYPE=MASTER, ISVALID = (C_FSL_LINKS >= 7)
BUS_INTERFACE BUS=SFSL7, BUS_STD=FSL, BUS_TYPE=SLAVE, ISVALID = (C_FSL_LINKS >= 8)
BUS_INTERFACE BUS=MFSL7, BUS_STD=FSL, BUS_TYPE=MASTER, ISVALID = (C_FSL_LINKS >= 8)
BUS_INTERFACE BUS=MFSL_DBG, BUS_STD=FSL, BUS_TYPE=MASTER, ISVALID = (C_FSL_DEBUG >= 1)
BUS_INTERFACE BUS = DOPB, BUS_STD = OPB, BUS_TYPE = MASTER, ISVALID = (C_DOPB_ENABLE >= 1)
BUS_INTERFACE BUS = IOPB, BUS_STD = OPB, BUS_TYPE = MASTER, ISVALID = (C_IOPB_ENABLE >= 1)
 
## Parameters / Generics
PARAMETER C_EXT_RESET_HIGH = 0, DT = integer, RANGE = (0,1)
PARAMETER C_DOPB_ADDR_LO = 0x30000000, DT = std_logic_vector(31 to 0)
PARAMETER C_DOPB_ADDR_HI = 0x50000000, DT = std_logic_vector(31 to 0)
PARAMETER C_IOPB_ENABLE = 1, DT = integer, RANGE = (0,1)
PARAMETER C_DOPB_ENABLE = 1, DT = integer, RANGE = (0,1)
PARAMETER C_IOPB_CSCOPE = 0, DT = integer, RANGE = (0,1)
PARAMETER C_DOPB_CSCOPE = 0, DT = integer, RANGE = (0,1)
PARAMETER C_FSL_LINKS = 0, DT = integer, RANGE = (0:8)
PARAMETER C_FSL_DEBUG = 0, DT = integer, RANGE = (0,1)
PARAMETER C_OF_CSCOPE = 0, DT = integer, RANGE = (0,1)
 
## Ports
PORT clock = "", DIR = I
PORT reset = "", DIR = I
 
PORT FSL0_S_READ = FSL_S_READ, DIR=out, BUS=SFSL0
PORT FSL0_S_DATA = FSL_S_DATA, DIR=in, VEC=[0:31], BUS=SFSL0
PORT FSL0_S_CONTROL = FSL_S_CONTROL, DIR=in, BUS=SFSL0
PORT FSL0_S_EXISTS = FSL_S_EXISTS, DIR=in, BUS=SFSL0
PORT FSL0_S_CLK = FSL_S_CLK, DIR=out, BUS=SFSL0
PORT FSL0_M_WRITE = FSL_M_WRITE, DIR=out, BUS=MFSL0
PORT FSL0_M_DATA = FSL_M_DATA, DIR=out, VEC=[0:31], BUS=MFSL0
PORT FSL0_M_CONTROL = FSL_M_CONTROL, DIR=out, BUS=MFSL0
PORT FSL0_M_FULL = FSL_M_FULL, DIR=in, BUS=MFSL0
PORT FSL0_M_CLK = FSL_M_CLK, DIR=out, BUS=MFSL0
 
PORT FSL1_S_READ = FSL_S_READ, DIR=out, BUS=SFSL1
PORT FSL1_S_DATA = FSL_S_DATA, DIR=in, VEC=[0:31], BUS=SFSL1
PORT FSL1_S_CONTROL = FSL_S_CONTROL, DIR=in, BUS=SFSL1
PORT FSL1_S_EXISTS = FSL_S_EXISTS, DIR=in, BUS=SFSL1
PORT FSL1_S_CLK = FSL_S_CLK, DIR=out, BUS=SFSL1
PORT FSL1_M_WRITE = FSL_M_WRITE, DIR=out, BUS=MFSL1
PORT FSL1_M_DATA = FSL_M_DATA, DIR=out, VEC=[0:31], BUS=MFSL1
PORT FSL1_M_CONTROL = FSL_M_CONTROL, DIR=out, BUS=MFSL1
PORT FSL1_M_FULL = FSL_M_FULL, DIR=in, BUS=MFSL1
PORT FSL1_M_CLK = FSL_M_CLK, DIR=out, BUS=MFSL1
 
PORT FSL2_S_READ = FSL_S_READ, DIR=out, BUS=SFSL2
PORT FSL2_S_DATA = FSL_S_DATA, DIR=in, VEC=[0:31], BUS=SFSL2
PORT FSL2_S_CONTROL = FSL_S_CONTROL, DIR=in, BUS=SFSL2
PORT FSL2_S_EXISTS = FSL_S_EXISTS, DIR=in, BUS=SFSL2
PORT FSL2_S_CLK = FSL_S_CLK, DIR=out, BUS=SFSL2
PORT FSL2_M_WRITE = FSL_M_WRITE, DIR=out, BUS=MFSL2
PORT FSL2_M_DATA = FSL_M_DATA, DIR=out, VEC=[0:31], BUS=MFSL2
PORT FSL2_M_CONTROL = FSL_M_CONTROL, DIR=out, BUS=MFSL2
PORT FSL2_M_FULL = FSL_M_FULL, DIR=in, BUS=MFSL2
PORT FSL2_M_CLK = FSL_M_CLK, DIR=out, BUS=MFSL2
 
PORT FSL3_S_READ = FSL_S_READ, DIR=out, BUS=SFSL3
PORT FSL3_S_DATA = FSL_S_DATA, DIR=in, VEC=[0:31], BUS=SFSL3
PORT FSL3_S_CONTROL = FSL_S_CONTROL, DIR=in, BUS=SFSL3
PORT FSL3_S_EXISTS = FSL_S_EXISTS, DIR=in, BUS=SFSL3
PORT FSL3_S_CLK = FSL_S_CLK, DIR=out, BUS=SFSL3
PORT FSL3_M_WRITE = FSL_M_WRITE, DIR=out, BUS=MFSL3
PORT FSL3_M_DATA = FSL_M_DATA, DIR=out, VEC=[0:31], BUS=MFSL3
PORT FSL3_M_CONTROL = FSL_M_CONTROL, DIR=out, BUS=MFSL3
PORT FSL3_M_FULL = FSL_M_FULL, DIR=in, BUS=MFSL3
PORT FSL3_M_CLK = FSL_M_CLK, DIR=out, BUS=MFSL3
 
PORT FSL4_S_READ = FSL_S_READ, DIR=out, BUS=SFSL4
PORT FSL4_S_DATA = FSL_S_DATA, DIR=in, VEC=[0:31], BUS=SFSL4
PORT FSL4_S_CONTROL = FSL_S_CONTROL, DIR=in, BUS=SFSL4
PORT FSL4_S_EXISTS = FSL_S_EXISTS, DIR=in, BUS=SFSL4
PORT FSL4_S_CLK = FSL_S_CLK, DIR=out, BUS=SFSL4
PORT FSL4_M_WRITE = FSL_M_WRITE, DIR=out, BUS=MFSL4
PORT FSL4_M_DATA = FSL_M_DATA, DIR=out, VEC=[0:31], BUS=MFSL4
PORT FSL4_M_CONTROL = FSL_M_CONTROL, DIR=out, BUS=MFSL4
PORT FSL4_M_FULL = FSL_M_FULL, DIR=in, BUS=MFSL4
PORT FSL4_M_CLK = FSL_M_CLK, DIR=out, BUS=MFSL4
 
PORT FSL5_S_READ = FSL_S_READ, DIR=out, BUS=SFSL5
PORT FSL5_S_DATA = FSL_S_DATA, DIR=in, VEC=[0:31], BUS=SFSL5
PORT FSL5_S_CONTROL = FSL_S_CONTROL, DIR=in, BUS=SFSL5
PORT FSL5_S_EXISTS = FSL_S_EXISTS, DIR=in, BUS=SFSL5
PORT FSL5_S_CLK = FSL_S_CLK, DIR=out, BUS=SFSL5
PORT FSL5_M_WRITE = FSL_M_WRITE, DIR=out, BUS=MFSL5
PORT FSL5_M_DATA = FSL_M_DATA, DIR=out, VEC=[0:31], BUS=MFSL5
PORT FSL5_M_CONTROL = FSL_M_CONTROL, DIR=out, BUS=MFSL5
PORT FSL5_M_FULL = FSL_M_FULL, DIR=in, BUS=MFSL5
PORT FSL5_M_CLK = FSL_M_CLK, DIR=out, BUS=MFSL5
 
PORT FSL6_S_READ = FSL_S_READ, DIR=out, BUS=SFSL6
PORT FSL6_S_DATA = FSL_S_DATA, DIR=in, VEC=[0:31], BUS=SFSL6
PORT FSL6_S_CONTROL = FSL_S_CONTROL, DIR=in, BUS=SFSL6
PORT FSL6_S_EXISTS = FSL_S_EXISTS, DIR=in, BUS=SFSL6
PORT FSL6_S_CLK = FSL_S_CLK, DIR=out, BUS=SFSL6
PORT FSL6_M_WRITE = FSL_M_WRITE, DIR=out, BUS=MFSL6
PORT FSL6_M_DATA = FSL_M_DATA, DIR=out, VEC=[0:31], BUS=MFSL6
PORT FSL6_M_CONTROL = FSL_M_CONTROL, DIR=out, BUS=MFSL6
PORT FSL6_M_FULL = FSL_M_FULL, DIR=in, BUS=MFSL6
PORT FSL6_M_CLK = FSL_M_CLK, DIR=out, BUS=MFSL6
 
PORT FSL7_S_READ = FSL_S_READ, DIR=out, BUS=SFSL7
PORT FSL7_S_DATA = FSL_S_DATA, DIR=in, VEC=[0:31], BUS=SFSL7
PORT FSL7_S_CONTROL = FSL_S_CONTROL, DIR=in, BUS=SFSL7
PORT FSL7_S_EXISTS = FSL_S_EXISTS, DIR=in, BUS=SFSL7
PORT FSL7_S_CLK = FSL_S_CLK, DIR=out, BUS=SFSL7
PORT FSL7_M_WRITE = FSL_M_WRITE, DIR=out, BUS=MFSL7
PORT FSL7_M_DATA = FSL_M_DATA, DIR=out, VEC=[0:31], BUS=MFSL7
PORT FSL7_M_CONTROL = FSL_M_CONTROL, DIR=out, BUS=MFSL7
PORT FSL7_M_FULL = FSL_M_FULL, DIR=in, BUS=MFSL7
PORT FSL7_M_CLK = FSL_M_CLK, DIR=out, BUS=MFSL7
 
PORT FSL_M_WRITE_DBG = FSL_M_WRITE, DIR=out, BUS=MFSL_DBG
PORT FSL_M_DATA_DBG = FSL_M_DATA, DIR=out, VEC=[0:31], BUS=MFSL_DBG
PORT FSL_M_CONTROL_DBG = FSL_M_CONTROL, DIR=out, BUS=MFSL_DBG
PORT FSL_M_FULL_DBG = FSL_M_FULL, DIR=in, BUS=MFSL_DBG
PORT FSL_M_CLK_DBG = FSL_M_CLK, DIR=out, BUS=MFSL_DBG
 
## IOPB Ports - port listing copied from Xilinx MicroBlaze v5 mpd file.
PORT IOPB_DBus = OPB_DBus, DIR = I, VEC = [0:31], BUS = IOPB
PORT IOPB_errAck = OPB_errAck, DIR = I, BUS = IOPB
PORT IOPB_MGrant = OPB_MGrant, DIR = I, BUS = IOPB
PORT IOPB_retry = OPB_retry, DIR = I, BUS = IOPB
PORT IOPB_timeout = OPB_timeout, DIR = I, BUS = IOPB
PORT IOPB_xferAck = OPB_xferAck, DIR = I, BUS = IOPB
 
PORT IM_ABus = M_ABus, DIR = O, VEC = [0:31], BUS = IOPB
PORT IM_BE = M_BE, DIR = O, VEC = [0:3], BUS = IOPB
PORT IM_busLock = M_busLock, DIR = O, BUS = IOPB
PORT IM_DBus = M_DBus, DIR = O, VEC = [0:31], BUS = IOPB
PORT IM_request = M_request, DIR = O, BUS = IOPB
PORT IM_RNW = M_RNW, DIR = O, BUS = IOPB
PORT IM_select = M_select, DIR = O, BUS = IOPB
PORT IM_seqAddr = M_seqAddr, DIR = O, BUS = IOPB
 
## DOPB Ports - port listing copied from Xilinx MicroBlaze v5 mpd file.
PORT DOPB_DBus = OPB_DBus, DIR = I, VEC = [0:31], BUS = DOPB
PORT DOPB_errAck = OPB_errAck, DIR = I, BUS = DOPB
PORT DOPB_MGrant = OPB_MGrant, DIR = I, BUS = DOPB
PORT DOPB_retry = OPB_retry, DIR = I, BUS = DOPB
PORT DOPB_timeout = OPB_timeout, DIR = I, BUS = DOPB
PORT DOPB_xferAck = OPB_xferAck, DIR = I, BUS = DOPB
 
PORT DM_ABus = M_ABus, DIR = O, VEC = [0:31], BUS = DOPB
PORT DM_BE = M_BE, DIR = O, VEC = [0:3], BUS = DOPB
PORT DM_busLock = M_busLock, DIR = O, BUS = DOPB
PORT DM_DBus = M_DBus, DIR = O, VEC = [0:31], BUS = DOPB
PORT DM_request = M_request, DIR = O, BUS = DOPB
PORT DM_RNW = M_RNW, DIR = O, BUS = DOPB
PORT DM_select = M_select, DIR = O, BUS = DOPB
PORT DM_seqAddr = M_seqAddr, DIR = O, BUS = DOPB
 
END
trunk/openfire_top_syn/data/openfire_top_syn_v2_1_0.mpd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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