OpenCores
URL https://opencores.org/ocsvn/raggedstone/raggedstone/trunk

Subversion Repositories raggedstone

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  • This comparison shows the changes necessary to convert path 
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    from Rev 2 to Rev 3
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Rev 2 → Rev 3

/trunk/pci_7seg.ut
0,0 → 1,27
-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g ConfigRate:6
-g CclkPin:PullUp
-g M0Pin:PullUp
-g M1Pin:PullUp
-g M2Pin:PullUp
-g ProgPin:PullUp
-g DonePin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullUp
-g UserID:0xFFFFFFFF
-g DCIUpdateMode:AsRequired
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No
/trunk/pci_7seg.prj
0,0 → 1,16
verilog work "source/sync.v"
verilog work "source/disp_dec.v"
verilog work "source/wb_7seg.v"
verilog work "source/pcidec.v"
verilog work "source/pcidmux.v"
 
verilog work "source/pciwbsequ.v"
verilog work "source/pcipargen.v"
 
vhdl work "source/pciwbsequ.vhd"
vhdl work "source/pfs.vhd"
vhdl work "source/new_pciregs.vhd"
vhdl work "source/pcipargen.vhd"
vhdl work "source/new_pci32tlite.vhd"
vhdl work "source/vga_main.vhd"
vhdl work "source/top_pci_7seg.vhd"
/trunk/pci_7seg.ucf
0,0 → 1,68
NET "DISP_LED<0>" LOC = "AB20" | IOSTANDARD = LVCMOS33 ;
NET "DISP_LED<1>" LOC = "AA20" | IOSTANDARD = LVCMOS33 ;
NET "DISP_LED<2>" LOC = "V18" | IOSTANDARD = LVCMOS33 ;
NET "DISP_LED<3>" LOC = "Y17" | IOSTANDARD = LVCMOS33 ;
NET "DISP_LED<4>" LOC = "AB18" | IOSTANDARD = LVCMOS33 ;
NET "DISP_LED<5>" LOC = "AA18" | IOSTANDARD = LVCMOS33 ;
NET "DISP_LED<6>" LOC = "W18" | IOSTANDARD = LVCMOS33 ;
NET "DISP_SEL<0>" LOC = "AA17" | IOSTANDARD = LVCMOS33 ;
NET "DISP_SEL<1>" LOC = "U17" | IOSTANDARD = LVCMOS33 ;
NET "DISP_SEL<2>" LOC = "U16" | IOSTANDARD = LVCMOS33 ;
NET "DISP_SEL<3>" LOC = "U14" | IOSTANDARD = LVCMOS33 ;
NET "LED_ACCESS" LOC = "AB5" | IOSTANDARD = LVCMOS33 ;
NET "LED_INIT" LOC = "AA5" | IOSTANDARD = LVCMOS33 ;
NET "PCI_AD<0>" LOC = "A5" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<10>" LOC = "E9" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<11>" LOC = "F11" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<12>" LOC = "E10" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<13>" LOC = "A8" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<14>" LOC = "B9" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<15>" LOC = "B10" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<16>" LOC = "F17" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<17>" LOC = "F16" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<18>" LOC = "A14" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<19>" LOC = "B14" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<1>" LOC = "B5" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<20>" LOC = "B15" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<21>" LOC = "A15" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<22>" LOC = "F12" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<23>" LOC = "F13" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<24>" LOC = "D15" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<25>" LOC = "E15" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<26>" LOC = "D17" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<27>" LOC = "C17" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<28>" LOC = "B17" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<29>" LOC = "E17" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<2>" LOC = "E6" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<30>" LOC = "A18" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<31>" LOC = "B18" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<3>" LOC = "D6" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<4>" LOC = "C6" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<5>" LOC = "B6" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<6>" LOC = "D7" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<7>" LOC = "E7" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<8>" LOC = "B8" | IOSTANDARD = PCI33_3 ;
NET "PCI_AD<9>" LOC = "F10" | IOSTANDARD = PCI33_3 ;
NET "PCI_CBE<0>" LOC = "F9" | IOSTANDARD = PCI33_3 ;
NET "PCI_CBE<1>" LOC = "C10" | IOSTANDARD = PCI33_3 ;
NET "PCI_CBE<2>" LOC = "D13" | IOSTANDARD = PCI33_3 ;
NET "PCI_CBE<3>" LOC = "E13" | IOSTANDARD = PCI33_3 ;
NET "PCI_CLK" LOC = "A11" | IOSTANDARD = PCI33_3 ;
NET "PCI_IDSEL" LOC = "D14" | IOSTANDARD = PCI33_3 ;
NET "PCI_nDEVSEL" LOC = "E12" | IOSTANDARD = PCI33_3 ;
NET "PCI_nFRAME" LOC = "C13" | IOSTANDARD = PCI33_3 ;
NET "PCI_nINT" LOC = "B19" | IOSTANDARD = PCI33_3 | SLEW = FAST ;
NET "PCI_nIRDY" LOC = "A13" | IOSTANDARD = PCI33_3 ;
NET "PCI_nPERR" LOC = "D12" | IOSTANDARD = PCI33_3 | SLEW = FAST ;
NET "PCI_nRES" LOC = "A19" | IOSTANDARD = PCI33_3 ;
NET "PCI_nSERR" LOC = "B12" | IOSTANDARD = PCI33_3 | SLEW = FAST ;
NET "PCI_nSTOP" LOC = "A12" | IOSTANDARD = PCI33_3 | SLEW = FAST ;
NET "PCI_nTRDY" LOC = "B13" | IOSTANDARD = PCI33_3 | SLEW = FAST ;
NET "PCI_PAR" LOC = "A9" | IOSTANDARD = PCI33_3 | SLEW = FAST ;
NET "LED_ALIVE" LOC = "AB4" | IOSTANDARD = LVCMOS33 ;
NET "mclk" LOC = "E22";
NET "red" LOC = "E21";
NET "grn" LOC = "F21";
NET "blu" LOC = "F20";
NET "hs" LOC = "F19";
NET "vs" LOC = "G19";
/trunk/Makefile
0,0 → 1,81
PWD := $(shell pwd)
 
XST := $(shell which xst)
 
TMP = tmp/
$(shell mkdir tmp)
 
PROJECT := pci_7seg
 
all: gen_vhdl xst ngdbuild map par trace prom final
 
gen_vhdl:
cd source/generate_pci32tlite/ && make
cd source/generate_pciregs/ && make
 
log:
time make all &>build.log
 
xst: $(PROJECT).ngc
 
ngdbuild: $(PROJECT).ngc $(PROJECT).ngd
 
$(PROJECT).ngc:
@# echo synclib > $(PROJECT).lso # hmm. things are different in ise 9.1
echo work >> $(PROJECT).lso
xst -intstyle ise -ifn $(PROJECT).xst -ofn $(PROJECT).syr &> tmp/build.xst.log
#cat $(PROJECT).syr
mv $(PROJECT).syr $(TMP)
mv $(PROJECT).ngr $(PROJECT).lso $(TMP)
mv xst $(TMP)
 
$(PROJECT).ngd:
ngdbuild -intstyle ise -dd "$(PWD)/_ngo" -nt timestamp -uc $(PROJECT).ucf -p xc3s400-fg456-4 $(PROJECT).ngc $(PROJECT).ngd &> tmp/build.ngdbuild.log
mv $(PROJECT).bld $(TMP)
mv _ngo $(TMP)
 
map:
map -intstyle ise -p xc3s400-fg456-4 -cm area -pr b -k 4 -c 100 -o $(PROJECT)_map.ncd $(PROJECT).ngd $(PROJECT).pcf &> tmp/build.map.log
mv $(PROJECT)_map.mrp $(PROJECT)_map.ngm $(PROJECT).ngc $(TMP)
 
par:
@#par -w -intstyle ise -ol std -n 4 -t 1 $(PROJECT)_map.ncd $(PROJECT).dir $(PROJECT).pcf &> tmp/build.par.log
par -w -intstyle ise -ol std -t 1 $(PROJECT)_map.ncd $(PROJECT).ncd $(PROJECT).pcf &> tmp/build.par.log
mv $(PROJECT).xpi $(PROJECT).par $(PROJECT).pad $(TMP)
mv $(PROJECT)_pad.csv $(PROJECT)_pad.txt $(TMP)
 
trace:
trce -intstyle ise -e 3 -l 3 -s 4 -xml $(PROJECT) $(PROJECT).ncd -o $(PROJECT).twr $(PROJECT).pcf &> tmp/build.trce.log
#cat $(PROJECT).twr
mv $(PROJECT).twr $(TMP)
mv $(PROJECT).twx $(TMP)
mv $(PROJECT)_map.ncd $(PROJECT).ngd $(PROJECT).pcf $(TMP)
 
prom:
bitgen -intstyle ise -f $(PROJECT).ut $(PROJECT).ncd &> tmp/build.bitgen.log
# cp $(PROJECT).bit ../jcarr_last.bit
#cat $(PROJECT).drc
mv $(PROJECT).drc $(TMP)
#cat $(PROJECT).bgn
mv $(PROJECT).bgn $(TMP)
 
final:
-mv $(PROJECT).unroutes *.xml $(TMP)
-mv $(PROJECT)*.map $(TMP)
-mv $(PROJECT).ncd $(TMP)
-grep -A 8 -B 1 ^Selected\ Device tmp/build.xst.log
-grep -A 8 -B 1 ^Timing\ Summary tmp/build.xst.log
-grep -A 21 -B 1 ^Design\ Summary tmp/build.map.log
 
burn:
xc3sprog $(PROJECT).bit
 
clean:
rm -rf $(TMP)
rm -rf *.bit *.bgn *.mcs *.prm *.bld *.drc *.mcs *.ncd *.ngc *.ngd
rm -rf *.ngr *.pad *.par *.pcf *.prm *.syr *.twr *.twx *.xpi *.lso
rm -rf $(PROJECT)_map.* $(PROJECT)_pad.*
rm -rf _ngo xst
rm -rf build.log
rm -rf source/new_*
rm -rf $(PROJECT).unroutes *.xml
/trunk/pci_7seg.xst
0,0 → 1,51
set -xsthdpdir ./xst
run
-ifn pci_7seg.prj
-ifmt mixed
-ofn pci_7seg
-ofmt NGC
-p xc3s400-4-fg456
-top pci_7seg
-opt_mode Speed
-opt_level 1
-iuc NO
-lso pci_7seg.lso
-keep_hierarchy NO
-glob_opt AllClockNets
-rtlview Yes
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-rom_style Auto
-mux_extract YES
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-resource_sharing YES
-mult_style auto
-iobuf YES
-max_fanout 500
-bufg 8
-register_duplication YES
-equivalent_register_removal YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Yes
-use_sync_set Yes
-use_sync_reset Yes
-iob auto
-slice_utilization_ratio_maxmargin 5

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