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/wrimm/trunk/WrimmManual.pdf
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Index: wrimm/trunk/WrimmPackage.vhd
===================================================================
--- wrimm/trunk/WrimmPackage.vhd (nonexistent)
+++ wrimm/trunk/WrimmPackage.vhd (revision 3)
@@ -0,0 +1,116 @@
+--Propery of Tecphos Inc. See License.txt for license details
+--Latest version of all project files available at http://opencores.org/project,wrimm
+--See WrimmManual.pdf for the Wishbone Datasheet and implementation details.
+--See wrimm subversion project for version history
+
+library ieee;
+ use ieee.std_logic_1164.all;
+
+package WrimmPackage is
+
+ constant WbAddrBits : Integer := 4;
+ constant WbDataBits : Integer := 16;
+
+ subtype WbAddrType is std_logic_vector(0 to WbAddrBits-1);
+ subtype WbDataType is std_logic_vector(0 to WbDataBits-1);
+
+ type WbMasterOutType is record
+ Strobe : std_logic; --Required
+ WrEn : std_logic;
+ Addr : WbAddrType;
+ Data : WbDataType;
+ DataTag : std_logic_vector(0 to 1); --Write,Set,Clear,Toggle
+ Cyc : std_logic; --Required
+ CycType : std_logic_vector(0 to 2); --For Burst Cycles
+ end record WbMasterOutType;
+
+ type WbSlaveOutType is record
+ Ack : std_logic; --Required
+ Err : std_logic;
+ Rty : std_logic;
+ Data : WbDataType;
+ end record WbSlaveOutType;
+
+ type WbMasterOutArray is array (natural range <>) of WbMasterOutType;
+ type WbSlaveOutArray is array (natural range <>) of WbSlaveOutType;
+
+-------------------------------------------------------------------------------
+--
+-- Status Registers (Report internal results)
+--
+-------------------------------------------------------------------------------
+ type StatusFieldParams is record
+ BitWidth : integer;
+ MSBLoc : integer;
+ Address : WbAddrType;
+ end record StatusFieldParams;
+
+ type StatusFieldType is (
+ StatusA,
+ StatusB,
+ StatusC);
+
+ type StatusArrayType is Array (StatusFieldType'Left to StatusFieldType'Right) of WbDataType;
+ type StatusArrayBitType is Array (StatusFieldType'Left to StatusFieldType'Right) of std_logic;
+ type StatusFieldDefType is Array (StatusFieldType'Left to StatusFieldType'Right) of StatusFieldParams;
+
+ constant StatusParams : StatusFieldDefType :=(
+ StatusA => (BitWidth => 16, MSBLoc => 0, Address => x"0"),
+ StatusB => (BitWidth => 8, MSBLoc => 0, Address => x"1"),
+ StatusC => (BitWidth => 4, MSBLoc => 12, Address => x"2"));
+-------------------------------------------------------------------------------
+--
+-- Setting Registers
+--
+-------------------------------------------------------------------------------
+ type SettingFieldParams is record
+ BitWidth : integer;
+ MSBLoc : integer;
+ Address : WbAddrType;
+ Default : WbDataType;
+ end record SettingFieldParams;
+
+ type SettingFieldType is (
+ SettingX,
+ SettingY,
+ SettingZ);
+
+ type SettingArrayType is Array (SettingFieldType'Left to SettingFieldType'Right) of WbDataType;
+ type SettingArrayBitType is Array (SettingFieldType'Left to SettingFieldType'Right) of std_logic;
+ type SettingFieldDefType is Array (SettingFieldType'Left to SettingFieldType'Right) of SettingFieldParams;
+
+ constant SettingParams : SettingFieldDefType :=(
+ SettingX => (BitWidth => 32, MSBLoc => 0, Address => x"62", Default => x"0000"),
+ SettingY => (BitWidth => 32, MSBLoc => 0, Address => x"64", Default => x"0000"),
+ SettingZ => (BitWidth => 1, MSBLoc => 31, Address => x"67", Default => x"0000"));
+
+-------------------------------------------------------------------------------
+--
+-- Trigger Registers (Report internal results)
+--
+-------------------------------------------------------------------------------
+ type TriggerFieldParams is record
+ BitLoc : integer;
+ Address : WbAddrType;
+ end record TriggerFieldParams;
+
+ type TriggerFieldType is (
+ TriggerR,
+ TriggerS,
+ TriggerT);
+
+ type TriggerArrayType is Array (TriggerFieldType'Left to TriggerFieldType'Right) of std_logic;
+ type TriggerFieldDefType is Array (TriggerFieldType'Left to TriggerFieldType'Right) of TriggerFieldParams;
+
+ constant TriggerParams : TriggerFieldDefType :=(
+ TriggerR => (BitLoc => 31, Address => x"6"),
+ TriggerS => (BitLoc => 31, Address => x"8"),
+ TriggerT => (BitLoc => 31, Address => x"8"));
+
+end package WrimmPackage;
+
+--package body WishBonePackage is
+--
+--
+--
+--end package body WishBonePackage;
Index: wrimm/trunk/Wrimm.vhd
===================================================================
--- wrimm/trunk/Wrimm.vhd (nonexistent)
+++ wrimm/trunk/Wrimm.vhd (revision 3)
@@ -0,0 +1,219 @@
+--Latest version of all project files available at http://opencores.org/project,wrimm
+--See License.txt for license details
+--See WrimmManual.pdf for the Wishbone Datasheet and implementation details.
+--See wrimm subversion project for version history
+
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+library wrimm;
+ use wrimm.WrimmPackage.all;
+
+
+entity Wb2MasterIntercon is
+ generic (
+ MasterCount : integer := 1;
+ StatusParams : StatusFieldDefType;
+ SettingParams : SettingFieldDefType;
+ TriggerParams : TriggerFieldDefType);
+ port (
+ WbClk : in std_logic;
+ WbRst : out std_logic;
+
+ WbMasterIn : in WbMasterOutArray(0 to MasterCount-1); --Signals from Masters
+ WbMasterOut : out WbSlaveOutArray(0 to MasterCount-1); --Signals to Masters
+
+ WbSlaveIn : out WbMasterOutArray(0 to SlaveCount-1);
+ WbSlaveOut : in WbSlaveOutArray(0 to SlaveCount-1)
+
+ StatusRegs : in StatusArrayType;
+ SettingRegs : out SettingArrayType;
+ SettingRsts : in SettingArrayBitType;
+ Triggers : out TriggerArrayType;
+ TriggerClr : in TriggerArrayType;
+
+ rstZ : in std_logic); --Asynchronous reset
+end entity Wb2MasterIntercon;
+
+architecture behavior of Wb2MasterIntercon is
+ signal wbStrobe : std_logic;
+ signal validAddress : std_logic;
+ signal wbAddr : WbAddrType;
+ signal wbSData,wbMData : WbDataType;
+ signal wbWrEn,wbCyc : std_logic;
+ signal wbAck,wbRty,wbErr : std_logic;
+ signal wbMDataTag : std_logic_vector(0 to 1);
+ signal wbCycType : std_logic_vector(0 to 2);
+ signal iSettingRegs : SettingArrayType;
+ signal iTriggers : TriggerArrayType;
+ signal statusEnable : StatusArrayBitType;
+ signal settingEnable : SettingArrayBitType;
+ signal triggerEnable : TriggerArrayType;
+ signal testEnable,testClr : std_logic;
+ signal testNibble : std_logic_vector(0 to 3);
+ signal grant : std_logic_vector(0 to MasterCount-1);
+
+begin
+ SettingRegs <= iSettingRegs;
+ Triggers <= iTriggers;
+
+--=============================================================================
+-------------------------------------------------------------------------------
+-- Master Round Robin Arbitration
+-------------------------------------------------------------------------------
+ procArb: process(WbClk,rstZ) is --Round robin arbitration (descending)
+ variable vGrant : std_logic_vector(0 to MasterCount-1);
+ begin
+ if (rstZ='0') then
+ grant(0) <= '1';
+ grant(1 to MasterCount-1) <= (Others=>'0');
+ elsif rising_edge(WbClk) then
+ loopGrant: for i in 0 to (MasterCount-1) loop
+ if vGrant(i)='1' and WbMasterIn(i).Cyc='0' then --else maintain grant
+ loopNewGrantA: for j in i to (MasterCount-1) loop --last master with cyc=1 will be selected
+ if WbMasterIn(j).Cyc='1' then
+ vGrant := (Others=>'0');
+ vGrant(j) := '1';
+ end if;
+ end loop loopNewGrantA;
+ if i/=0 then
+ loopNewGrantB: for j in 0 to (i-1) loop
+ if WbMasterIn(j).Cyc='0' then
+ vGrant := (Others=>'1');
+ vGrant(j) := '1';
+ end if;
+ end loop loopNewGrantB; --grant only moves after new requester
+ end if;
+ end if;
+ end loop loopGrant;
+ grant <= vGrant;
+ end if; --Clk
+ end process procArb;
+--=============================================================================
+-------------------------------------------------------------------------------
+-- Master Mux
+-------------------------------------------------------------------------------
+ procWbIn: process(grant,WbMasterIn,wbSData,wbAck,wbErr,wbRty) is
+ variable grantId : integer;
+ begin
+ loopGrantMux: for i in 0 to (MasterCount-1) loop
+ --if grant(i)='1' then
+ -- grantId := i;
+ --end if;
+ grantID <= grantID + ((2**i)*to_integer(unsigned(grant(i)),1));
+ WbMasterOut(i).Ack <= grant(i) and wbAck;
+ WbMasterOut(i).Err <= grant(i) and wbErr;
+ WbMasterOut(i).Rty <= grant(i) and wbRty;
+ WbMasterOut(i).Data <= wbSData; --Data out can always be active.
+ end loop loopGrantMux;
+ wbStrobe <= WbMasterIn(grantId).Strobe;
+ wbWrEn <= WbMasterIn(grantId).WrEn;
+ wbAddr <= WbMasterIn(grantId).Addr;
+ wbMData <= WbMasterIn(grantId).Data;
+ wbMDataTag <= WbMasterIn(grantId).DataTag;
+ wbCyc <= WbMasterIn(grantId).Cyc;
+ wbCycType <= WbMasterIn(grantId).CycType;
+ end process procWbIn;
+
+ wbAck <= wbStrobe and validAddress;
+ wbErr <= wbStrobe and not(validAddress);
+ wbRty <= '0';
+ WbRst <= '0';
+--=============================================================================
+-------------------------------------------------------------------------------
+-- Address Decode, Asynchronous
+-------------------------------------------------------------------------------
+ procAddrDecode: process(wbAddr) is
+ variable vValidAddress : std_logic;
+ begin
+ vValidAddress := '0';
+ loopStatusEn: for f in StatusFieldType loop
+ if StatusParams(f).Address=wbAddr then
+ statusEnable(f) <= '1';
+ vValidAddress := '1';
+ else
+ statusEnable(f) <= '0';
+ end if;
+ end loop loopStatusEn;
+ loopSettingEn: for f in SettingFieldType loop
+ if SettingParams(f).Address=wbAddr then
+ settingEnable(f) <= '1';
+ vValidAddress := '1';
+ else
+ settingEnable(f) <= '0';
+ end if;
+ end loop loopSettingEn;
+ loopTriggerEn: for f in TriggerFieldType loop
+ if TriggerParams(f).Address=wbAddr then
+ triggerEnable(f) <= '1';
+ vValidAddress := '1';
+ else
+ triggerEnable(f) <= '0';
+ end if;
+ end loop loopTriggerEn;
+ validAddress <= vValidAddress;
+ end process procAddrDecode;
+--=============================================================================
+-------------------------------------------------------------------------------
+-- Read
+-------------------------------------------------------------------------------
+ procRegRead: process(StatusRegs,iSettingRegs,iTriggers,statusEnable,settingEnable,triggerEnable) is
+ variable vWbSData : std_logic_vector(0 to 31);
+ begin
+ vWbSData := (Others=>'0');
+ loopStatusRegs : for f in StatusFieldType loop
+ if statusEnable(f)='1' then
+ vWbSData(StatusParams(f).MSBLoc to (StatusParams(f).MSBLoc + StatusParams(f).BitWidth - 1)) := StatusRegs(f)((WbDataBits-StatusParams(f).BitWidth) to WbDataBits-1);
+ end if; --Address
+ end loop loopStatusRegs;
+ loopSettingRegs : for f in SettingFieldType loop
+ if settingEnable(f)='1' then
+ vWbSData(SettingParams(f).MSBLoc to (SettingParams(f).MSBLoc + SettingParams(f).BitWidth - 1)) := iSettingRegs(f)((WbDataBits-SettingParams(f).BitWidth) to WbDataBits-1);
+ end if; --Address
+ end loop loopSettingRegs;
+ loopTriggerRegs : for f in TriggerFieldType loop
+ if triggerEnable(f)='1' then
+ vWbSData(TriggerParams(f).BitLoc) := iTriggers(f);
+ end if; --Address
+ end loop loopTriggerRegs;
+ wbSData <= vWbSData;
+ end process procRegRead;
+--=============================================================================
+-------------------------------------------------------------------------------
+-- Write
+-------------------------------------------------------------------------------
+ procRegWrite: process(WbClk,rstZ) is
+ begin
+ if (rstZ='0') then
+ loopSettingRegDefault : for f in SettingFieldType loop
+ iSettingRegs(f) <= SettingParams(f).Default;
+ end loop loopSettingRegDefault;
+ loopTriggerRegDefault : for f in TriggerFieldType loop
+ iTriggers(f) <= '0';
+ end loop loopTriggerRegDefault;
+ elsif rising_edge(WbClk) then
+ loopSettingRegWr : for f in SettingFieldType loop
+ if settingEnable(f)='1' and wbStrobe='1' and wbWrEn='1' then
+ iSettingRegs(f)((WbDataBits-SettingParams(f).BitWidth) to WbDataBits-1) <= wbMData(SettingParams(f).MSBLoc to (SettingParams(f).MSBLoc + SettingParams(f).BitWidth-1));
+ end if;
+ end loop loopSettingRegWr;
+ loopSettingRegRst : for f in SettingFieldType loop
+ if SettingRsts(f)='1' then
+ iSettingRegs(f) <= SettingParams(f).Default;
+ end if;
+ end loop loopSettingRegRst;
+ loopTriggerRegWr : for f in TriggerFieldType loop
+ if triggerEnable(f)='1' and wbStrobe='1' and wbWrEn='1' then
+ iTriggers(f) <= wbMData(TriggerParams(f).BitLoc);
+ elsif TriggerClr(f)='1' then
+ iTriggers(f) <= '0';
+ end if; --Address or clear
+ end loop loopTriggerRegWr;
+ end if; --Clk
+ end process procRegWrite;
+
+ testEnable <= settingEnable(SetIntegrationQStop);
+ testClr <= settingRsts(SetIntegrationQStop);
+ testNibble <= iSettingRegs(SetIntegrationQStop)(28 to 31);
+
+end architecture behavior;
\ No newline at end of file