OpenCores
URL https://opencores.org/ocsvn/mytwoqcache/mytwoqcache/trunk

Subversion Repositories mytwoqcache

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    from Rev 21 to Rev 22
    Reverse comparison

Rev 21 → Rev 22

/mytwoqcache/trunk/2QCache.vhd
137,7 → 137,7
signal statetag: tType;
signal stateram: rType;
signal statequeue: fType;
signal enableram, enablequeue, queuedone, readsh, writesh, doneh, preempted, isfull, flag,
signal enableram, enablequeue, queuedone, readsh, writesh, doneh, preempted, isfull, flag, flag1,
interrupt, readb, writeb, writec, writet, accdone, accqueue, accinterrupt, serviced, oldint: std_ulogic;
signal gal: std_ulogic_vector( 7 downto 0);
 
358,6 → 358,7
accqueue <= '0';
isfull <= '0';
flag <= '0';
flag1 <= '1';
initcount1 <= ( others => '0');
FreeIn <= ( others => '0');
firstf <= ( others => '0');
391,6 → 392,7
tagBuff <= tagRAMOut;
end if;
if found /= 15 then
tagBuff <= tagRAMOut;
cindex <= tagRAMOut( found).cacheAddr;
isfull <= '0';
stateram <= ramupdate;
398,6 → 400,7
en := '1';
if emptyf = '1' and isfull = '0' then
isfull <= '1';
tagBuff <= tagRAMOut;
stateram <= ramwait;
else
cindex <= FreeOut;
411,6 → 414,7
tagRAMOut( free).cacheValid <= '1';
tagRAMOut( free).tag <= AddressInh( tagRAMOut( free).tag'range);
tagRAMOut( free).tagValid <= '1';
flag1 <= '1';
end if;
isfull <= '0';
getf <= '1';
465,6 → 469,10
when ramread =>
readb <= '0';
getf <= '0';
if flag1 = '1' then
tagBuff <= tagRAMOut;
flag1 <= '0';
end if;
stateram <= ramread1;
when ramread1 =>
if readsh = '0' then
474,6 → 482,10
stateram <= ramupdate2;
end if;
when ramupdate2 =>
if flag1 = '1' then
tagBuff <= tagRAMOut;
flag1 <= '0';
end if;
if IOCodeh(2) = '1' then
if IOCodeh(1) = '1' then
If IOCodeh(0) = '1' then

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