URL
https://opencores.org/ocsvn/ppx16/ppx16/trunk
Subversion Repositories ppx16
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 21 to Rev 22
- ↔ Reverse comparison
Rev 21 → Rev 22
/trunk/sim/rtl_sim/bin/compile.do
File deleted
/trunk/sw/hex2rom.cpp
File deleted
/trunk/sw/xrom.cpp
File deleted
/trunk/syn/xilinx/run/p16c55_leo.bat
File deleted
trunk/syn/xilinx/run/p16c55_leo.bat
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/syn/xilinx/run/p16c55.bat
===================================================================
--- trunk/syn/xilinx/run/p16c55.bat (revision 21)
+++ trunk/syn/xilinx/run/p16c55.bat (nonexistent)
@@ -1,46 +0,0 @@
-set name=p16c55
-rem set target=xc2v250-cs144-6
-rem set target=xcv300e-pq240-8
-set target=xc2s200-pq208-5
-
-if "%2" == "" goto default
-set target=%2
-:default
-
-cd ..\out
-
-if "%1" == "" goto xst
-
-set name=p16c55_leo
-
-copy ..\bin\%name%.pin %name%.ucf
-
-ngdbuild -p %target% %1 %name%.ngd
-
-goto builddone
-
-:xst
-
-xrom ROM55 9 12 > ..\src\ROM55_Test.vhd
-hex2rom ..\..\..\sw\c55.hex rom55 9l12u > rom55_test.ini
-copy ..\out\rom55_test.ini + ..\bin\%name%.pin %name%.ucf
-
-xst -ifn ../bin/%name%.scr -ofn ../log/%name%.srp
-ngdbuild -p %target% %name%.ngc
-
-:builddone
-
-move %name%.bld ..\log
-
-map -p %target% -cm speed -c 100 -timing -tx on -o %name%_map %name%
-move %name%_map.mrp ..\log\%name%.mrp
-
-par -ol 3 -t 1 -c 0 %name%_map -w %name%
-move %name%.par ..\log
-
-trce %name%.ncd -o ../log/%name%.twr %name%_map.pcf
-
-bitgen -w %name%
-move %name%.bgn ..\log
-
-cd ..\run
trunk/syn/xilinx/run/p16c55.bat
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/syn/xilinx/run/p16f84_leo.bat
===================================================================
--- trunk/syn/xilinx/run/p16f84_leo.bat (revision 21)
+++ trunk/syn/xilinx/run/p16f84_leo.bat (nonexistent)
@@ -1,10 +0,0 @@
-cd ..\out
-
-hex2rom ..\..\..\sw\f84.hex ROM84 10l14s > ..\src\ROM84_Test_leo.vhd
-
-spectrum -file ..\bin\p16f84.tcl
-move exemplar.log ..\log\p16f84_leo.srp
-
-cd ..\run
-
-p16f84 p16f84_leo.edf xc2s200-pq208-5
trunk/syn/xilinx/run/p16f84_leo.bat
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/syn/xilinx/run/p16f84.bat
===================================================================
--- trunk/syn/xilinx/run/p16f84.bat (revision 21)
+++ trunk/syn/xilinx/run/p16f84.bat (nonexistent)
@@ -1,46 +0,0 @@
-set name=p16f84
-rem set target=xc2v250-cs144-6
-rem set target=xcv300e-pq240-8
-set target=xc2s200-pq208-5
-
-if "%2" == "" goto default
-set target=%2
-:default
-
-cd ..\out
-
-if "%1" == "" goto xst
-
-set name=p16f84_leo
-
-copy ..\bin\%name%.pin %name%.ucf
-
-ngdbuild -p %target% %1 %name%.ngd
-
-goto builddone
-
-:xst
-
-xrom ROM84 10 14 > ..\src\ROM84_Test.vhd
-hex2rom ..\..\..\sw\f84.hex rom84 10b14u > rom84_test.ini
-copy ..\out\rom84_test.ini + ..\bin\%name%.pin %name%.ucf
-
-xst -ifn ../bin/%name%.scr -ofn ../log/%name%.srp
-ngdbuild -p %target% %name%.ngc
-
-:builddone
-
-move %name%.bld ..\log
-
-map -p %target% -cm speed -c 100 -timing -tx on -o %name%_map %name%
-move %name%_map.mrp ..\log\%name%.mrp
-
-par -ol 3 -t 1 -c 0 %name%_map -w %name%
-move %name%.par ..\log
-
-trce %name%.ncd -o ../log/%name%.twr %name%_map.pcf
-
-bitgen -w %name%
-move %name%.bgn ..\log
-
-cd ..\run
trunk/syn/xilinx/run/p16f84.bat
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/syn/xilinx/bin/p16c55_leo.pin
===================================================================
--- trunk/syn/xilinx/bin/p16c55_leo.pin (revision 21)
+++ trunk/syn/xilinx/bin/p16c55_leo.pin (nonexistent)
@@ -1,7 +0,0 @@
-#NET "clk" TNM_NET = "clk";
-#TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50%;
-
-NET "Clk" LOC = "P77";
-NET "Reset_n" LOC = "P133";
-NET "Port_A(0)" LOC = "P96";
-NET "Port_A(1)" LOC = "P98";
Index: trunk/syn/xilinx/bin/p16c55.pin
===================================================================
--- trunk/syn/xilinx/bin/p16c55.pin (revision 21)
+++ trunk/syn/xilinx/bin/p16c55.pin (nonexistent)
@@ -1,7 +0,0 @@
-#NET "clk" TNM_NET = "clk";
-#TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50%;
-
-NET "clk" LOC = "P77";
-NET "reset_n" LOC = "P133";
-NET "port_a<0>" LOC = "P96";
-NET "port_a<1>" LOC = "P98";
Index: trunk/syn/xilinx/bin/p16f84.tcl
===================================================================
--- trunk/syn/xilinx/bin/p16f84.tcl (revision 21)
+++ trunk/syn/xilinx/bin/p16f84.tcl (nonexistent)
@@ -1,44 +0,0 @@
-set process "5"
-set part "2s200pq208"
-set tristate_map "FALSE"
-set opt_auto_mode "TRUE"
-set opt_best_result "29223.458000"
-set dont_lock_lcells "auto"
-set input2output "20.000000"
-set input2register "20.000000"
-set register2output "20.000000"
-set register2register "20.000000"
-set wire_table "xis215-5_avg"
-set encoding "auto"
-set edifin_ground_port_names "GND"
-set edifin_power_port_names "VCC"
-set edif_array_range_extraction_style "%s\[%d:%d\]"
-
-set_xilinx_eqn
-
-load_library xis2
-
-read -technology xis2 {
-../../../rtl/vhdl/PPX_Pack.vhd
-../../../rtl/vhdl/PPX_ALU.vhd
-../../../rtl/vhdl/PPX_Ctrl.vhd
-../../../rtl/vhdl/PPX_PCS.vhd
-../../../rtl/vhdl/PPX16.vhd
-../../../rtl/vhdl/PPX_RAM.vhd
-../../../rtl/vhdl/PPX_Port.vhd
-../../../rtl/vhdl/PPX_TMR.vhd
-../src/ROM84_Test_leo.vhd
-../../../rtl/vhdl/P16F84.vhd
-}
-
-pre_optimize
-
-optimize -hierarchy=auto -delay -pass 1 -pass 2 -pass 3 -pass 4
-
-optimize_timing
-
-report_area
-
-report_delay
-
-write p16f84_leo.edf
Index: trunk/syn/xilinx/bin/p16c55.scr
===================================================================
--- trunk/syn/xilinx/bin/p16c55.scr (revision 21)
+++ trunk/syn/xilinx/bin/p16c55.scr (nonexistent)
@@ -1,7 +0,0 @@
-run
--ifn ../bin/p16c55.prj
--ifmt VHDL
--ofn ../out/p16c55.ngc
--ofmt NGC -p xc2s200-pq208-5
--opt_mode Speed
--opt_level 2
Index: trunk/syn/xilinx/bin/p16f84_leo.pin
===================================================================
--- trunk/syn/xilinx/bin/p16f84_leo.pin (revision 21)
+++ trunk/syn/xilinx/bin/p16f84_leo.pin (nonexistent)
@@ -1,13 +0,0 @@
-NET "clk" TNM_NET = "clk";
-TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50%;
-
-NET "Clk" LOC = "P77";
-NET "Reset_n" LOC = "P133";
-NET "Port_B(0)" LOC = "P29";
-NET "Port_B(1)" LOC = "P31";
-NET "Port_B(2)" LOC = "P34";
-NET "Port_B(3)" LOC = "P36";
-NET "Port_B(4)" LOC = "P41";
-NET "Port_B(5)" LOC = "P43";
-NET "Port_B(6)" LOC = "P45";
-NET "Port_B(7)" LOC = "P47";
Index: trunk/syn/xilinx/bin/p16f84.pin
===================================================================
--- trunk/syn/xilinx/bin/p16f84.pin (revision 21)
+++ trunk/syn/xilinx/bin/p16f84.pin (nonexistent)
@@ -1,13 +0,0 @@
-NET "clk" TNM_NET = "clk";
-TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50%;
-
-NET "clk" LOC = "P77";
-NET "reset_n" LOC = "P133";
-NET "port_b<0>" LOC = "P29";
-NET "port_b<1>" LOC = "P31";
-NET "port_b<2>" LOC = "P34";
-NET "port_b<3>" LOC = "P36";
-NET "port_b<4>" LOC = "P41";
-NET "port_b<5>" LOC = "P43";
-NET "port_b<6>" LOC = "P45";
-NET "port_b<7>" LOC = "P47";
Index: trunk/syn/xilinx/bin/p16c55.prj
===================================================================
--- trunk/syn/xilinx/bin/p16c55.prj (revision 21)
+++ trunk/syn/xilinx/bin/p16c55.prj (nonexistent)
@@ -1,10 +0,0 @@
-../../../rtl/vhdl/PPX_Pack.vhd
-../../../rtl/vhdl/PPX_ALU.vhd
-../../../rtl/vhdl/PPX_Ctrl.vhd
-../../../rtl/vhdl/PPX_PCS.vhd
-../../../rtl/vhdl/PPX16.vhd
-../../../rtl/vhdl/PPX_RAM.vhd
-../../../rtl/vhdl/PPX_Port.vhd
-../../../rtl/vhdl/PPX_TMR.vhd
-../src/ROM55_Test.vhd
-../../../rtl/vhdl/P16C55.vhd
Index: trunk/syn/xilinx/bin/p16f84.scr
===================================================================
--- trunk/syn/xilinx/bin/p16f84.scr (revision 21)
+++ trunk/syn/xilinx/bin/p16f84.scr (nonexistent)
@@ -1,7 +0,0 @@
-run
--ifn ../bin/p16f84.prj
--ifmt VHDL
--ofn ../out/p16f84.ngc
--ofmt NGC -p xc2s200-pq208-5
--opt_mode Speed
--opt_level 2
Index: trunk/syn/xilinx/bin/p16f84.prj
===================================================================
--- trunk/syn/xilinx/bin/p16f84.prj (revision 21)
+++ trunk/syn/xilinx/bin/p16f84.prj (nonexistent)
@@ -1,10 +0,0 @@
-../../../rtl/vhdl/PPX_Pack.vhd
-../../../rtl/vhdl/PPX_ALU.vhd
-../../../rtl/vhdl/PPX_Ctrl.vhd
-../../../rtl/vhdl/PPX_PCS.vhd
-../../../rtl/vhdl/PPX16.vhd
-../../../rtl/vhdl/PPX_RAM.vhd
-../../../rtl/vhdl/PPX_Port.vhd
-../../../rtl/vhdl/PPX_TMR.vhd
-../src/ROM84_Test.vhd
-../../../rtl/vhdl/P16F84.vhd
Index: trunk/syn/xilinx/bin/p16c55.tcl
===================================================================
--- trunk/syn/xilinx/bin/p16c55.tcl (revision 21)
+++ trunk/syn/xilinx/bin/p16c55.tcl (nonexistent)
@@ -1,44 +0,0 @@
-set process "5"
-set part "2s200pq208"
-set tristate_map "FALSE"
-set opt_auto_mode "TRUE"
-set opt_best_result "29223.458000"
-set dont_lock_lcells "auto"
-set input2output "20.000000"
-set input2register "20.000000"
-set register2output "20.000000"
-set register2register "20.000000"
-set wire_table "xis215-5_avg"
-set encoding "auto"
-set edifin_ground_port_names "GND"
-set edifin_power_port_names "VCC"
-set edif_array_range_extraction_style "%s\[%d:%d\]"
-
-set_xilinx_eqn
-
-load_library xis2
-
-read -technology xis2 {
-../../../rtl/vhdl/PPX_Pack.vhd
-../../../rtl/vhdl/PPX_ALU.vhd
-../../../rtl/vhdl/PPX_Ctrl.vhd
-../../../rtl/vhdl/PPX_PCS.vhd
-../../../rtl/vhdl/PPX16.vhd
-../../../rtl/vhdl/PPX_RAM.vhd
-../../../rtl/vhdl/PPX_Port.vhd
-../../../rtl/vhdl/PPX_TMR.vhd
-../src/ROM55_Test_leo.vhd
-../../../rtl/vhdl/P16C55.vhd
-}
-
-pre_optimize
-
-optimize -hierarchy=auto -delay -pass 1 -pass 2 -pass 3 -pass 4
-
-optimize_timing
-
-report_area
-
-report_delay
-
-write p16c55_leo.edf
Index: trunk/bench/vhdl/TestBench55.vhd
===================================================================
--- trunk/bench/vhdl/TestBench55.vhd (revision 21)
+++ trunk/bench/vhdl/TestBench55.vhd (nonexistent)
@@ -1,30 +0,0 @@
-library IEEE;
-use IEEE.std_logic_1164.all;
-use work.StimLog.all;
-
-entity TestBench55 is
-end TestBench55;
-
-architecture behaviour of TestBench55 is
-
- signal Clk : std_logic := '0';
- signal Reset_n : std_logic := '0';
- signal T0CKI : std_logic := '0';
- signal Port_A : std_logic_vector(7 downto 0);
- signal Port_B : std_logic_vector(7 downto 0);
- signal Port_C : std_logic_vector(7 downto 0);
-
-begin
-
- p1 : entity work.P16C55 port map (Clk, Reset_n, T0CKI, Port_A, Port_B, Port_C);
-
- as : AsyncStim generic map(FileName => "../../../rtl/vhdl/PPX16.vhd", InterCharDelay => 300 us, Baud => 48000, Bits => 8)
- port map(Port_A(1));
-
- al : AsyncLog generic map(FileName => "RX_Log.txt", Baud => 48000, Bits => 8)
- port map(Port_A(0));
-
- Clk <= not Clk after 50 ns;
- Reset_n <= '1' after 200 ns;
-
-end;
Index: trunk/bench/vhdl/AsyncStim.vhd
===================================================================
--- trunk/bench/vhdl/AsyncStim.vhd (revision 21)
+++ trunk/bench/vhdl/AsyncStim.vhd (nonexistent)
@@ -1,115 +0,0 @@
---
--- Asynchronous serial generator with input from binary file
---
--- Version : 0146
---
--- Copyright (c) 2001 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity AsyncStim is
- generic(
- FileName : string;
- Baud : integer;
- InterCharDelay : time := 0 ns;
- Bits : integer := 8; -- Data bits
- Parity : boolean := false; -- Enable Parity
- P_Odd_Even_n : boolean := false -- false => Even Parity, true => Odd Parity
- );
- port(
- TXD : out std_logic
- );
-end AsyncStim;
-
-architecture behaviour of AsyncStim is
-
- signal TX_ShiftReg : std_logic_vector(Bits - 1 downto 0);
- signal TX_Bit_Cnt : integer range 0 to 15 := 0;
- signal ParTmp : boolean;
-
-begin
-
- process
- type ChFile is file of character;
- file InFile : ChFile open read_mode is FileName;
- variable Inited : boolean := false;
- variable CharTmp : character;
- variable IntTmp : integer;
- begin
- if not Inited then
- Inited := true;
- TXD <= '1';
- end if;
- wait for 1000000000 ns / Baud;
- TX_Bit_Cnt <= TX_Bit_Cnt + 1;
- case TX_Bit_Cnt is
- when 0 =>
- TXD <= '1';
- wait for InterCharDelay;
- when 1 => -- Start bit
- read(InFile, CharTmp);
- IntTmp := character'pos(CharTmp);
- TX_ShiftReg(Bits - 1 downto 0) <= std_logic_vector(to_unsigned(IntTmp, Bits));
- TXD <= '0';
- ParTmp <= P_Odd_Even_n;
- when others =>
- TXD <= TX_ShiftReg(0);
- ParTmp <= ParTmp xor (TX_ShiftReg(0) = '1');
- TX_ShiftReg(Bits - 2 downto 0) <= TX_ShiftReg(Bits - 1 downto 1);
- if (TX_Bit_Cnt = Bits + 1 and not Parity) or
- (TX_Bit_Cnt = Bits + 2 and Parity) then -- Stop bit
- TX_Bit_Cnt <= 0;
- end if;
- if Parity and TX_Bit_Cnt = Bits + 2 then
- if ParTmp then
- TXD <= '1';
- else
- TXD <= '0';
- end if;
- end if;
- end case;
- end process;
-
-end;
Index: trunk/bench/vhdl/TestBench84.vhd
===================================================================
--- trunk/bench/vhdl/TestBench84.vhd (revision 21)
+++ trunk/bench/vhdl/TestBench84.vhd (nonexistent)
@@ -1,24 +0,0 @@
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity TestBench84 is
-end TestBench84;
-
-architecture behaviour of TestBench84 is
-
- signal Clk : std_logic := '0';
- signal Reset_n : std_logic := '0';
- signal T0CKI : std_logic := '0';
- signal INT : std_logic := '0';
- signal Port_A : std_logic_vector(7 downto 0);
- signal Port_B : std_logic_vector(7 downto 0);
-
-begin
-
- p1 : entity work.P16F84 port map (Clk, Reset_n, T0CKI, INT, Port_A, Port_B);
-
- Clk <= not Clk after 50 ns;
- Reset_n <= '1' after 200 ns;
- INT <= not INT after 20 us;
-
-end;
Index: trunk/bench/vhdl/StimLog.vhd
===================================================================
--- trunk/bench/vhdl/StimLog.vhd (revision 21)
+++ trunk/bench/vhdl/StimLog.vhd (nonexistent)
@@ -1,142 +0,0 @@
---
--- File I/O test-bench utilities
---
--- Version : 0146
---
--- Copyright (c) 2001 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package StimLog is
-
- component AsyncStim
- generic(
- FileName : string;
- Baud : integer;
- InterCharDelay : time := 0 ns;
- Bits : integer := 8; -- Data bits
- Parity : boolean := false; -- Enable Parity
- P_Odd_Even_n : boolean := false -- false => Even Parity, true => Odd Parity
- );
- port(
- TXD : out std_logic
- );
- end component;
-
- component AsyncLog
- generic(
- FileName : string;
- Baud : integer;
- Bits : integer := 8; -- Data bits
- Parity : boolean := false; -- Enable Parity
- P_Odd_Even_n : boolean := false -- false => Even Parity, true => Odd Parity
- );
- port(
- RXD : in std_logic
- );
- end component;
-
- component BinaryStim
- generic(
- FileName : string;
- Bytes : integer := 1; -- Number of bytes per word
- LittleEndian : boolean := true -- Byte order
- );
- port(
- Rd : in std_logic;
- Data : out std_logic_vector(Bytes * 8 - 1 downto 0)
- );
- end component;
-
- component BinaryLog
- generic(
- FileName : string;
- Bytes : integer := 1; -- Number of bytes per word
- LittleEndian : boolean := true -- Byte order
- );
- port(
- Clk : in std_logic;
- En : in std_logic;
- Data : in std_logic_vector(Bytes * 8 - 1 downto 0)
- );
- end component;
-
- component I2SStim is
- generic(
- FileName : string;
- Bytes : integer := 2; -- Number of bytes per word (1 to 4)
- LittleEndian : boolean := true -- Byte order
- );
- port(
- BClk : in std_logic;
- FSync : in std_logic;
- SData : out std_logic
- );
- end component;
-
- component I2SLog is
- generic(
- FileName : string;
- Bytes : integer := 2; -- Number of bytes per word
- LittleEndian : boolean := true -- Byte order
- );
- port(
- BClk : in std_logic;
- FSync : in std_logic;
- SData : in std_logic
- );
- end component;
-
- component IntegerLog is
- generic(
- FileName : string
- );
- port(
- Clk : in std_logic;
- En : in std_logic;
- Data : in integer
- );
- end component;
-
-end;
Index: trunk/bench/vhdl/AsyncLog.vhd
===================================================================
--- trunk/bench/vhdl/AsyncLog.vhd (revision 21)
+++ trunk/bench/vhdl/AsyncLog.vhd (nonexistent)
@@ -1,124 +0,0 @@
---
--- Asynchronous serial input with binary file log
---
--- Version : 0146
---
--- Copyright (c) 2001 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity AsyncLog is
- generic(
- FileName : string;
- Baud : integer;
- Bits : integer := 8; -- Data bits
- Parity : boolean := false; -- Enable Parity
- P_Odd_Even_n : boolean := false -- false => Even Parity, true => Odd Parity
- );
- port(
- RXD : in std_logic
- );
-end AsyncLog;
-
-architecture behaviour of AsyncLog is
-
- function to_char(
- constant Byte : std_logic_vector(7 downto 0)
- ) return character is
- begin
- return character'val(to_integer(unsigned(Byte)));
- end function;
-
- signal Baud16 : std_logic := '0';
-
- -- Receive signals
- signal Bit_Phase : unsigned(3 downto 0) := "0000";
- signal RX_ShiftReg : std_logic_vector(Bits - 1 downto 0) := (others => '0');
- signal RX_Bit_Cnt : integer := 0;
- signal ParTmp : boolean;
-
-begin
-
- Baud16 <= not Baud16 after 1000000000 ns / 32 / Baud;
-
- process (Baud16)
- type ChFile is file of character;
- file OutFile : ChFile open write_mode is FileName;
- begin
- if Baud16'event and Baud16 = '1' then
- if RX_Bit_Cnt = 0 and (RXD = '1' or Bit_Phase = "0111") then
- Bit_Phase <= "0000";
- else
- Bit_Phase <= Bit_Phase + 1;
- end if;
- if RX_Bit_Cnt = 0 then
- if Bit_Phase = "0111" then
- RX_Bit_Cnt <= RX_Bit_Cnt + 1;
- end if;
- ParTmp <= false;
- elsif Bit_Phase = "1111" then
- RX_Bit_Cnt <= RX_Bit_Cnt + 1;
- if (RX_Bit_Cnt = Bits + 1 and not Parity) or
- (RX_Bit_Cnt = Bits + 2 and Parity) then -- Stop bit
- RX_Bit_Cnt <= 0;
- assert RXD = '1'
- report "Framing error"
- severity error;
- write(OutFile, to_char(RX_ShiftReg(7 downto 0)));
- elsif RX_Bit_Cnt = Bits + 1 and Parity then -- Parity bit
- assert ParTmp xor (RXD = '1') = P_Odd_Even_n
- report "Parity error"
- severity error;
- else
- ParTmp <= ParTmp xor (RXD = '1');
- RX_ShiftReg(Bits - 2 downto 0) <= RX_ShiftReg(Bits - 1 downto 1);
- RX_ShiftReg(Bits - 1) <= RXD;
- end if;
- end if;
- end if;
- end process;
-
-end;
-
Index: trunk/rtl/vhdl/PPX_RAM.vhd
===================================================================
--- trunk/rtl/vhdl/PPX_RAM.vhd (revision 21)
+++ trunk/rtl/vhdl/PPX_RAM.vhd (nonexistent)
@@ -1,96 +0,0 @@
---
--- PIC16xx compatible microcontroller core
---
--- Version : 0221
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
--- Registers implemented in this entity are INDF, PCL, STATUS, FSR, (PCLATH)
--- other registers must be implemented externally including GPR
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity PPX_RAM is
- generic(
- Bottom : integer;
- Top : integer;
- AddrWidth : integer
- );
- port(
- Clk : in std_logic;
- CS : in std_logic;
- Wr : in std_logic;
- Addr : in std_logic_vector(AddrWidth - 1 downto 0);
- Data_In : in std_logic_vector(7 downto 0);
- Data_Out : out std_logic_vector(7 downto 0)
- );
-end PPX_RAM;
-
-architecture rtl of PPX_RAM is
-
- type RAM_Image is array (Top downto 0) of std_logic_vector(7 downto 0);
- signal RAM : RAM_Image;
- signal AddrRd : std_logic_vector(AddrWidth - 1 downto 0);
- signal AddrWr : std_logic_vector(AddrWidth - 1 downto 0);
-
-begin
-
- process (Clk)
- begin
- if Clk'event and Clk = '1' then
- AddrRd <= Addr;
- AddrWr <= Addr;
- if CS = '1' and Wr = '1' then
- RAM(to_integer(unsigned(AddrWr))) <= Data_In;
- end if;
- end if;
- end process;
-
- Data_Out <= RAM(to_integer(unsigned(AddrRd)))
--- pragma translate_off
- when to_integer(unsigned(AddrRd)) >= Bottom and to_integer(unsigned(AddrRd)) <= Top else "--------"
--- pragma translate_on
- ;
-
-end;
Index: trunk/rtl/vhdl/P16F84.vhd
===================================================================
--- trunk/rtl/vhdl/P16F84.vhd (revision 21)
+++ trunk/rtl/vhdl/P16F84.vhd (nonexistent)
@@ -1,311 +0,0 @@
---
--- PIC16F84 compatible microcontroller core
---
--- Version : 0222
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
--- No port B pullup
--- No EEPROM
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.PPX_Pack.all;
-
-entity P16F84 is
- generic(
- SyncReset : boolean := true);
- port(
- Clk : in std_logic;
- Reset_n : in std_logic;
- T0CKI : in std_logic;
- INT : in std_logic;
- Port_A : inout std_logic_vector(7 downto 0);
- Port_B : inout std_logic_vector(7 downto 0)
- );
-end P16F84;
-
-architecture rtl of P16F84 is
-
- constant InstructionLength : integer := 14;
- constant ROMAddressWidth : integer := 10;
- constant StackAddrWidth : integer := 3;
- constant TopBoot : boolean := false;
-
- component ROM84
- port(
- Clk : in std_logic;
- A : in std_logic_vector(9 downto 0);
- D : out std_logic_vector(13 downto 0)
- );
- end component;
-
- signal Reset_s_n : std_logic;
- signal ROM_Addr : std_logic_vector(9 downto 0);
- signal ROM_Data : std_logic_vector(InstructionLength - 1 downto 0);
- signal Instruction : std_logic_vector(InstructionLength - 1 downto 0);
- signal File_Addr : std_logic_vector(InstructionLength - 6 downto 0);
- signal File_Addr_r : std_logic_vector(InstructionLength - 6 downto 0);
- signal TMR_CS : std_logic;
- signal RAM_CS : std_logic;
- signal File_Wr : std_logic;
- signal W_Wr : std_logic;
- signal Port_A_Wr : std_logic;
- signal Tris_A_Wr : std_logic;
- signal Port_B_Wr : std_logic;
- signal Tris_B_Wr : std_logic;
- signal RAM_Data : std_logic_vector(7 downto 0);
- signal Op_Bus : std_logic_vector(7 downto 0);
- signal Op_Mux : std_logic_vector(7 downto 0);
- signal Res_Bus : std_logic_vector(7 downto 0);
- signal OPTION : std_logic_vector(7 downto 0);
- signal INTCON : std_logic_vector(7 downto 0);
- signal PortA : std_logic_vector(7 downto 0);
- signal TrisA : std_logic_vector(7 downto 0);
- signal PortB : std_logic_vector(7 downto 0);
- signal TrisB : std_logic_vector(7 downto 0);
- signal TMR : std_logic_vector(7 downto 0);
- signal W : std_logic_vector(7 downto 0);
- signal STATUS : std_logic_vector(7 downto 0);
- signal FSR : std_logic_vector(7 downto 0);
- signal PCLATH : std_logic_vector(4 downto 0);
- signal Int_Trig : std_logic;
- signal Int_Acc : std_logic;
- signal Int_Ret : std_logic;
- signal TOF : std_logic;
- signal Old_B : std_logic_vector(7 downto 4);
- signal Old_INT : std_logic;
-
-begin
-
- -- Synchronise reset
- process (Reset_n, Clk)
- variable Reset_v : std_logic;
- begin
- if Reset_n = '0' then
- if SyncReset then
- Reset_s_n <= '0';
- Reset_v := '0';
- end if;
- elsif Clk'event and Clk = '1' then
- if SyncReset then
- Reset_s_n <= Reset_v;
- Reset_v := '1';
- end if;
- end if;
- end process;
-
- g_reset : if not SyncReset generate
- Reset_s_n <= Reset_n;
- end generate;
-
- -- Address decoder
- Port_A_Wr <= '1' when to_integer(unsigned(File_Addr_r(7 downto 0))) = 5 and File_Wr = '1' else '0';
- Port_B_Wr <= '1' when to_integer(unsigned(File_Addr_r(7 downto 0))) = 6 and File_Wr = '1' else '0';
- Tris_A_Wr <= '1' when (to_integer(unsigned(File_Addr_r(7 downto 0))) = 133 and File_Wr = '1') or
- Instruction(13 downto 0) = "00000001100101" else '0';
- Tris_B_Wr <= '1' when (to_integer(unsigned(File_Addr_r(7 downto 0))) = 134 and File_Wr = '1') or
- Instruction(13 downto 0) = "00000001100110" else '0';
- TMR_CS <= '1' when to_integer(unsigned(File_Addr_r(7 downto 0))) = 1 else '0';
-
- -- Register selector
- process (Clk)
- begin
- if Clk'event and Clk = '1' then
- case to_integer(unsigned(File_Addr(7 downto 0))) is
- when 1 => Op_Bus <= TMR;
- when 129 => Op_Bus <= OPTION;
- when 2 | 130 => Op_Bus <= ROM_Addr(7 downto 0);
- when 3 | 131 => Op_Bus <= STATUS;
- when 4 | 132 => Op_Bus <= FSR;
- when 5 => Op_Bus <= PortA;
- when 133 => Op_Bus <= TrisA;
- when 6 => Op_Bus <= PortB;
- when 134 => Op_Bus <= TrisB;
- when 10 | 138 => Op_Bus(4 downto 0) <= PCLATH;
- when 11 | 139 => Op_Bus <= INTCON;
- when others => Op_Bus <= "--------";
- end case;
- if File_Wr = '1' and File_Addr_r = File_Addr then
- -- Write through
- Op_Bus <= Res_Bus;
- end if;
- RAM_CS <= '0';
- if ROM_Data(InstructionLength - 1) = '1' then
- Op_Bus <= W;
- -- Write through
- if W_Wr = '1' then
- Op_Bus <= Res_Bus;
- end if;
- elsif File_Addr(6 downto 4) /= "000" or File_Addr(3 downto 2) = "11" then
- RAM_CS <= '1';
- end if;
- end if;
- end process;
-
- -- Register File
- Op_Mux <= RAM_Data when RAM_CS = '1' else Op_Bus;
- pr : PPX_RAM
- generic map(Bottom => 12, Top => 79, AddrWidth => 7)
- port map(
- Clk => Clk,
- CS => RAM_CS,
- Wr => File_Wr,
- Addr => File_Addr(6 downto 0),
- Data_In => Res_Bus,
- Data_Out => RAM_Data);
-
- -- Option Register
- process (Clk)
- begin
- if Clk'event and Clk = '1' then
- if Instruction(13 downto 0) = "00000001100010" or
- to_integer(unsigned(File_Addr_r(7 downto 0))) = 129 then
- OPTION <= Res_Bus;
- end if;
- Old_B <= Port_B(7 downto 4);
- Old_INT <= INT;
- end if;
- end process;
-
- -- Interrupt Register
- Int_Trig <= (INTCON(0) and INTCON(3)) or
- (INTCON(1) and INTCON(4)) or
- (INTCON(2) and INTCON(5));
- process (Reset_s_n, Clk)
- begin
- if Reset_s_n = '0' then
- INTCON <= (others => '0');
- elsif Clk'event and Clk = '1' then
- if to_integer(unsigned(File_Addr_r(6 downto 0))) = 11 then
- INTCON <= Res_Bus;
- end if;
- if Int_Acc = '1' then
- INTCON(7) <= '0';
- end if;
- if Int_Ret = '1' then
- INTCON(7) <= '1';
- end if;
- if TOF = '1' then
- INTCON(2) <= '1';
- end if;
- if (OPTION(6) = '1' and INT = '1' and Old_INT = '0') or
- (OPTION(6) = '0' and INT = '0' and Old_INT = '1') then
- INTCON(1) <= '1';
- end if;
- if Old_B /= Port_B(7 downto 4) then
- INTCON(0) <= '1';
- end if;
- end if;
- end process;
-
- rom : ROM84 port map(
- Clk => Clk,
- A => ROM_Addr,
- D => ROM_Data);
-
- ppx : PPX16
- generic map(
- InstructionLength => InstructionLength,
- ROMAddressWidth => ROMAddressWidth,
- StackAddrWidth => StackAddrWidth,
- TopBoot => TopBoot)
- port map(
- Clk => Clk,
- Reset_n => Reset_s_n,
- ROM_Addr => ROM_Addr,
- ROM_Data => ROM_Data,
- Int_Trig => Int_Trig,
- GIE => INTCON(7),
- Int_Acc => Int_Acc,
- Int_Ret => Int_Ret,
- File_Addr => File_Addr,
- File_Addr_r => File_Addr_r,
- File_Wr => File_Wr,
- W_Wr => W_Wr,
- Instruction => Instruction,
- Op_Bus => Op_Mux,
- W => W,
- PCLATH => PCLATH,
- STATUS => STATUS,
- FSR => FSR,
- Res_Bus => Res_Bus);
-
- tmr0 : PPX_TMR
- port map(
- Clk => Clk,
- Reset_n => Reset_s_n,
- CKI => T0CKI,
- SE => OPTION(4),
- CS => OPTION(5),
- PS => OPTION(2 downto 0),
- PSA => OPTION(3),
- TMR_Sel => TMR_CS,
- Wr => File_Wr,
- Data_In => Res_Bus,
- Data_Out => TMR,
- TOF => TOF);
-
- aport : PPX_Port
- port map(
- Clk => Clk,
- Reset_n => Reset_s_n,
- Port_Wr => Port_A_Wr,
- Tris_Wr => Tris_A_Wr,
- Data_In => Res_Bus,
- Port_In => PortA,
- Tris => TrisA,
- IOPort => Port_A);
-
- bport : PPX_Port
- port map(
- Clk => Clk,
- Reset_n => Reset_s_n,
- Port_Wr => Port_B_Wr,
- Tris_Wr => Tris_B_Wr,
- Data_In => Res_Bus,
- Port_In => PortB,
- Tris => TrisB,
- IOPort => Port_B);
-
-end;
Index: trunk/rtl/vhdl/PPX_ALU.vhd
===================================================================
--- trunk/rtl/vhdl/PPX_ALU.vhd (revision 21)
+++ trunk/rtl/vhdl/PPX_ALU.vhd (nonexistent)
@@ -1,344 +0,0 @@
---
--- PIC16xx compatible microcontroller core
---
--- Version : 0222
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity PPX_ALU is
- generic(
- InstructionLength : integer;
- TriState : boolean := false
- );
- port (
- Clk : in std_logic;
- ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
- A : in std_logic_vector(7 downto 0);
- B : in std_logic_vector(7 downto 0);
- Q : out std_logic_vector(7 downto 0);
- Skip : in std_logic;
- Carry : in std_logic;
- Z_Skip : out std_logic;
- STATUS_d : out std_logic_vector(2 downto 0);
- STATUS_Wr : out std_logic_vector(2 downto 0)
- );
-end PPX_ALU;
-
-architecture rtl of PPX_ALU is
-
- procedure AddSub(A : std_logic_vector(3 downto 0);
- B : std_logic_vector(3 downto 0);
- Sub : std_logic;
- Carry_In : std_logic;
- signal Res : out std_logic_vector(3 downto 0);
- signal Carry : out std_logic) is
- variable B_i : unsigned(4 downto 0);
- variable Full_Carry : unsigned(4 downto 0);
- variable Res_i : unsigned(4 downto 0);
- begin
- if Sub = '1' then
- B_i := "0" & not unsigned(B);
- else
- B_i := "0" & unsigned(B);
- end if;
- if (Sub = '1' and Carry_In = '1') or (Sub = '0' and Carry_In = '1') then
- Full_Carry := "00001";
- else
- Full_Carry := "00000";
- end if;
- Res_i := unsigned("0" & A) + B_i + Full_Carry;
- Carry <= Res_i(4);
- Res <= std_logic_vector(Res_i(3 downto 0));
- end;
-
- signal Do_IDTEST : std_logic;
- signal Do_ADD : std_logic;
- signal Do_SUB : std_logic;
- signal Do_DEC : std_logic;
- signal Do_INC : std_logic;
- signal Do_AND : std_logic;
- signal Do_OR : std_logic;
- signal Do_XOR : std_logic;
- signal Do_COM : std_logic;
- signal Do_RRF : std_logic;
- signal Do_RLF : std_logic;
- signal Do_SWAP : std_logic;
- signal Do_BITCLR : std_logic;
- signal Do_BITSET : std_logic;
- signal Do_BITTESTCLR : std_logic;
- signal Do_BITTESTSET : std_logic;
- signal Do_CLR : std_logic;
-
- signal Inst_Top : std_logic_vector(11 downto 0);
-
- signal Bit_Pattern : std_logic_vector(7 downto 0);
- signal Bit_Test : std_logic_vector(7 downto 0);
-
- signal Q_ID : std_logic_vector(7 downto 0);
- signal Q_L : std_logic_vector(7 downto 0);
- signal Q_C : std_logic_vector(7 downto 0);
- signal Q_RR : std_logic_vector(7 downto 0);
- signal Q_RL : std_logic_vector(7 downto 0);
- signal Q_S : std_logic_vector(7 downto 0);
- signal Q_BC : std_logic_vector(7 downto 0);
- signal Q_BS : std_logic_vector(7 downto 0);
-
- signal DC_i : std_logic;
- signal AddSubRes : std_logic_vector(8 downto 0);
-
- signal Q_i : std_logic_vector(7 downto 0);
-
-begin
-
- Q <= Q_i;
-
- Inst_Top <= ROM_Data(InstructionLength - 1 downto InstructionLength - 12);
-
- gNoTri : if not TriState generate
- Q_i <= Q_ID when Do_INC = '1' or Do_DEC = '1' else
- AddSubRes(7 downto 0) when Do_ADD = '1' OR Do_SUB = '1' else
- Q_L when Do_AND = '1' or Do_OR = '1' or Do_XOR = '1' else
- Q_C when Do_COM = '1' else
- Q_RR when Do_RRF = '1' else
- Q_RL when Do_RLF = '1' else
- Q_S when Do_SWAP = '1' else
- Q_BC when Do_BITCLR = '1' else
- Q_BS when Do_BITSET = '1' else
- "00000000";
- end generate;
-
- gTri : if TriState generate
- Q_i <= Q_ID when Do_INC = '1' or Do_DEC = '1' else "ZZZZZZZZ";
- Q_i <= AddSubRes(7 downto 0) when Do_ADD = '1' OR Do_SUB = '1' else "ZZZZZZZZ";
- Q_i <= Q_L when Do_AND = '1' or Do_OR = '1' or Do_XOR = '1' else "ZZZZZZZZ";
- Q_i <= Q_C when Do_COM = '1' else "ZZZZZZZZ";
- Q_i <= Q_RR when Do_RRF = '1' else "ZZZZZZZZ";
- Q_i <= Q_RL when Do_RLF = '1' else "ZZZZZZZZ";
- Q_i <= Q_S when Do_SWAP = '1' else "ZZZZZZZZ";
- Q_i <= Q_BC when Do_BITCLR = '1' else "ZZZZZZZZ";
- Q_i <= Q_BS when Do_BITSET = '1' else "ZZZZZZZZ";
- Q_i <= "00000000" when Do_CLR = '1' else "ZZZZZZZZ";
- end generate;
-
- process (Clk)
- begin
- if Clk'event and Clk = '1' then
- Do_ADD <= '0';
- Do_SUB <= '0';
- Do_AND <= '0';
- Do_OR <= '0';
- Do_XOR <= '0';
- Do_IDTEST <= '0';
- Do_INC <= '0';
- Do_DEC <= '0';
- Do_COM <= '0';
- Do_RRF <= '0';
- Do_RLF <= '0';
- Do_SWAP <= '0';
- Do_BITCLR <= '0';
- Do_BITSET <= '0';
- Do_BITTESTCLR <= '0';
- Do_BITTESTSET <= '0';
- Do_CLR <= '0';
- if Skip = '0' then
- if InstructionLength = 12 then
- if Inst_Top(11 downto 6) = "000111" then
- -- ADDWF
- Do_ADD <= '1';
- end if;
- if Inst_Top(11 downto 6) = "000010" then
- -- SUBWF
- Do_SUB <= '1';
- end if;
- if Inst_Top(11 downto 6) = "000101" or Inst_Top(11 downto 8) = "1110" then
- -- ANDWF, ANDLW
- Do_AND <= '1';
- end if;
- if Inst_Top(11 downto 6) = "000100" or Inst_Top(11 downto 8) = "1101" then
- -- IORWF, IORLW
- Do_OR <= '1';
- end if;
- if Inst_Top(11 downto 6) = "000110" or Inst_Top(11 downto 8) = "1111" then
- -- XORWF, XORLW
- Do_XOR <= '1';
- end if;
- else
- if Inst_Top(11 downto 6) = "000111" or Inst_Top(11 downto 7) = "11111" then
- -- ADDWF, ADDLW
- Do_ADD <= '1';
- end if;
- if Inst_Top(11 downto 6) = "000010" or Inst_Top(11 downto 7) = "11110" then
- -- SUBWF, SUBLW
- Do_SUB <= '1';
- end if;
- if Inst_Top(11 downto 6) = "000101" or Inst_Top(11 downto 6) = "111001" then
- -- ANDWF, ANDLW
- Do_AND <= '1';
- end if;
- if Inst_Top(11 downto 6) = "000100" or Inst_Top(11 downto 6) = "111000" then
- -- IORWF, IORLW
- Do_OR <= '1';
- end if;
- if Inst_Top(11 downto 6) = "000110" or Inst_Top(11 downto 6) = "111010" then
- -- XORWF, XORLW
- Do_XOR <= '1';
- end if;
- end if;
-
- if Inst_Top(11 downto 9) = "001" and Inst_Top(7 downto 6) = "11" then
- -- INC/DEC w conditional skip
- Do_IDTEST <= '1';
- end if;
- if Inst_Top(11 downto 6) = "001010" or Inst_Top(11 downto 6) = "001111" then
- -- INCF, INCFSZ
- Do_INC <= '1';
- end if;
- if Inst_Top(11 downto 6) = "000011" or Inst_Top(11 downto 6) = "001011" then
- -- DECF, DECFSZ,
- Do_DEC <= '1';
- end if;
- if Inst_Top(11 downto 6) = "001001" then
- -- COMF
- Do_COM <= '1';
- end if;
- if Inst_Top(11 downto 6) = "001100" then
- -- RRF
- Do_RRF <= '1';
- end if;
- if Inst_Top(11 downto 6) = "001101" then
- -- RLF
- Do_RLF <= '1';
- end if;
- if Inst_Top(11 downto 6) = "001110" then
- -- SWAPF
- Do_SWAP <= '1';
- end if;
- if Inst_Top(11 downto 8) = "0100" then
- -- BCF
- Do_BITCLR <= '1';
- end if;
- if Inst_Top(11 downto 8) = "0101" then
- -- BSF
- Do_BITSET <= '1';
- end if;
- if Inst_Top(11 downto 8) = "0110" then
- -- BTFSC
- Do_BITTESTCLR <= '1';
- end if;
- if Inst_Top(11 downto 8) = "0111" then
- -- BTFSS
- Do_BITTESTSET <= '1';
- end if;
- if Inst_Top(11 downto 6) = "000001" then
- -- CLRF, CLRW
- Do_CLR <= '1';
- end if;
- end if;
-
- case Inst_Top(7 downto 5) is
- when "000" =>
- Bit_Pattern <= "00000001";
- when "001" =>
- Bit_Pattern <= "00000010";
- when "010" =>
- Bit_Pattern <= "00000100";
- when "011" =>
- Bit_Pattern <= "00001000";
- when "100" =>
- Bit_Pattern <= "00010000";
- when "101" =>
- Bit_Pattern <= "00100000";
- when "110" =>
- Bit_Pattern <= "01000000";
- when others =>
- Bit_Pattern <= "10000000";
- end case;
- end if;
- end process;
-
- Q_ID <= std_logic_vector(unsigned(A) + 1) when Do_INC = '1' else
- std_logic_vector(unsigned(A) - 1);
-
- AddSub(A(3 downto 0), B(3 downto 0), Do_SUB, Do_SUB, AddSubRes(3 downto 0), DC_i);
- AddSub(A(7 downto 4), B(7 downto 4), Do_SUB, DC_i, AddSubRes(7 downto 4), AddSubRes(8));
-
- Q_L <= (A and B) when Do_AND = '1' else
- (A or B) when Do_OR = '1' else
- (A xor B);
- Q_C <= (not A);
-
- Q_RR <= Carry & A(7 downto 1);
- Q_RL <= A(6 downto 0) & Carry;
-
- Q_S <= A(3 downto 0) & A(7 downto 4);
-
- Q_BC <= ((not Bit_Pattern) and A);
- Q_BS <= (Bit_Pattern or A);
-
- Bit_Test <= Bit_Pattern and A;
-
- Z_Skip <= '1' when (Do_IDTEST = '1' and Q_ID = "00000000") or
- (Bit_Test /= "00000000" and Do_BITTESTSET = '1') or
- (Bit_Test = "00000000" and Do_BITTESTCLR = '1') else '0';
-
- STATUS_d(2) <= '1' when Q_i(7 downto 0) = "00000000" else '0';
- STATUS_d(1) <= DC_i;
- STATUS_d(0) <= A(0) when Do_RRF = '1' else
- A(7) when Do_RLF = '1' else
- AddSubRes(8);
-
- -- Z
- STATUS_Wr(2) <= '1' when Do_SUB = '1' or Do_ADD = '1' or
- ((Do_DEC = '1' or Do_INC = '1') and Do_IDTEST = '0') or
- Do_AND = '1' or Do_OR = '1' or Do_XOR = '1' or
- Do_CLR = '1' or Do_COM = '1' else '0';
- -- DC
- STATUS_Wr(1) <= '1' when Do_SUB = '1' or Do_ADD = '1' else '0';
- -- C
- STATUS_Wr(0) <= '1' when Do_SUB = '1' or Do_ADD = '1' or Do_RRF = '1' or Do_RLF = '1' else '0';
-
-end;
Index: trunk/rtl/vhdl/PPX_TMR.vhd
===================================================================
--- trunk/rtl/vhdl/PPX_TMR.vhd (revision 21)
+++ trunk/rtl/vhdl/PPX_TMR.vhd (nonexistent)
@@ -1,157 +0,0 @@
---
--- PIC16xx compatible microcontroller core
---
--- Version : 0221
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
--- Registers implemented in this entity are INDF, PCL, STATUS, FSR, (PCLATH)
--- other registers must be implemented externally including GPR
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity PPX_TMR is
- port(
- Clk : in std_logic;
- Reset_n : in std_logic;
- CKI : in std_logic;
- SE : in std_logic;
- CS : in std_logic;
- PS : in std_logic_vector(2 downto 0);
- PSA : in std_logic;
- TMR_Sel : in std_logic;
- Wr : in std_logic;
- Data_In : in std_logic_vector(7 downto 0);
- Data_Out : out std_logic_vector(7 downto 0);
- TOF : out std_logic
- );
-end PPX_TMR;
-
-architecture rtl of PPX_TMR is
-
- signal TMR : std_logic_vector(7 downto 0);
-
- signal Tick : std_logic;
-
-begin
-
- Data_Out <= TMR;
-
- -- Registers and counter
- process (Reset_n, Clk)
- begin
- if Reset_n = '0' then
- TMR <= "00000000";
- TOF <= '0';
- elsif Clk'event and Clk = '1' then
- TOF <= '0';
- if Tick = '1' then
- TMR <= std_logic_vector(unsigned(TMR) + 1);
- if TMR = "11111111" then
- TOF <= '1';
- end if;
- end if;
- if TMR_Sel = '1' and Wr = '1' then
- TMR <= Data_In;
- TOF <= '0';
- end if;
- end if;
- end process;
-
- -- Tick generator
- process (Clk, Reset_n)
- variable Prescaler : unsigned(7 downto 0);
- variable CKI_r : std_logic_vector(1 downto 0);
- variable P_r : std_logic_vector(1 downto 0);
- variable Tick0 : std_logic;
- begin
- if Reset_n = '0' then
- Prescaler := (others => '0');
- Tick <= '0';
- Tick0 := '0';
- CKI_r := "00";
- P_r := "00";
- elsif Clk'event and Clk='1' then
- P_r(1) := P_r(0);
- case PS is
- when "000" => P_r(0) := Prescaler(0);
- when "001" => P_r(0) := Prescaler(1);
- when "010" => P_r(0) := Prescaler(2);
- when "011" => P_r(0) := Prescaler(3);
- when "100" => P_r(0) := Prescaler(4);
- when "101" => P_r(0) := Prescaler(5);
- when "110" => P_r(0) := Prescaler(6);
- when others => P_r(0) := Prescaler(7);
- end case;
-
- Tick0 := '0';
- if SE = '0' then -- low-to-high
- if CKI_r(1) = '1' and CKI_r(0) = '0' then
- Tick0 := '1';
- end if;
- else
- if CKI_r(1) = '0' and CKI_r(0) = '1' then
- Tick0 := '1';
- end if;
- end if;
- if CS = '0' then
- Tick0 := '1';
- end if;
- CKI_r(1) := CKI_r(0);
- CKI_r(0) := CKI;
-
- Tick <= '0';
- if PSA = '1' then
- Tick <= Tick0;
- elsif P_r(1) = '1' and P_r(0) = '0' then
- Tick <= '1';
- end if;
-
- if Tick0 = '1' then
- Prescaler := Prescaler + 1;
- end if;
- end if;
- end process;
-
-end;
Index: trunk/rtl/vhdl/PPX_Port.vhd
===================================================================
--- trunk/rtl/vhdl/PPX_Port.vhd (revision 21)
+++ trunk/rtl/vhdl/PPX_Port.vhd (nonexistent)
@@ -1,108 +0,0 @@
---
--- PIC16xx compatible microcontroller core
---
--- Version : 0221
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
--- Registers implemented in this entity are INDF, PCL, STATUS, FSR, (PCLATH)
--- other registers must be implemented externally including GPR
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PPX_Port is
- port(
- Clk : in std_logic;
- Reset_n : in std_logic;
- Port_Wr : in std_logic;
- Tris_Wr : in std_logic;
- Data_In : in std_logic_vector(7 downto 0);
- Port_In : out std_logic_vector(7 downto 0);
- Tris : out std_logic_vector(7 downto 0);
- IOPort : inout std_logic_vector(7 downto 0)
- );
-end PPX_Port;
-
-architecture rtl of PPX_Port is
-
- signal Tris_i : std_logic_vector(7 downto 0);
- signal Port_Output : std_logic_vector(7 downto 0);
- signal Port_Input : std_logic_vector(7 downto 0);
-
-begin
-
- Port_In <= Port_Input;
- Tris <= Tris_i;
-
- IOPort(0) <= Port_Output(0) when Tris_i(0) = '0' else 'Z';
- IOPort(1) <= Port_Output(1) when Tris_i(1) = '0' else 'Z';
- IOPort(2) <= Port_Output(2) when Tris_i(2) = '0' else 'Z';
- IOPort(3) <= Port_Output(3) when Tris_i(3) = '0' else 'Z';
- IOPort(4) <= Port_Output(4) when Tris_i(4) = '0' else 'Z';
- IOPort(5) <= Port_Output(5) when Tris_i(5) = '0' else 'Z';
- IOPort(6) <= Port_Output(6) when Tris_i(6) = '0' else 'Z';
- IOPort(7) <= Port_Output(7) when Tris_i(7) = '0' else 'Z';
-
- process (Clk)
- begin
- if Clk'event and Clk = '1' then
- Port_Input <= IOPort; -- Synchronise input
- if Port_Wr = '1' then
- Port_Output <= Data_In;
- Port_Input <= Data_In;
- end if;
- end if;
- end process;
-
- process (Reset_n, Clk)
- begin
- if Reset_n = '0' then
- Tris_i <= "11111111";
- elsif Clk'event and Clk = '1' then
- if Tris_Wr = '1' then
- Tris_i <= Data_In;
- end if;
- end if;
- end process;
-
-end;
Index: trunk/rtl/vhdl/PPX_Ctrl.vhd
===================================================================
--- trunk/rtl/vhdl/PPX_Ctrl.vhd (revision 21)
+++ trunk/rtl/vhdl/PPX_Ctrl.vhd (nonexistent)
@@ -1,188 +0,0 @@
---
--- PIC16xx compatible microcontroller core
---
--- Version : 0224
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/ppx16/
---
--- Limitations :
--- Registers implemented in this entity are INDF, PCL, STATUS, FSR, (PCLATH)
--- other registers must be implemented externally including GPR
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PPX_Ctrl is
- generic(
- InstructionLength : integer
- );
- port(
- Clk : in std_logic;
- Reset_n : in std_logic;
- ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
- Inst : in std_logic_vector(InstructionLength - 1 downto 0);
- Skip : in std_logic;
- File_Wr : out std_logic;
- W_Wr : out std_logic;
- Imm_Op : out std_logic;
- A2Res : out std_logic;
- B2Res : out std_logic;
- Push : out std_logic;
- Pop : out std_logic;
- Goto : out std_logic;
- IRet : out std_logic;
- B_Skip : out std_logic;
- Sleep : out std_logic
- );
-end PPX_Ctrl;
-
-architecture rtl of PPX_Ctrl is
-
-begin
-
- Imm_Op <= Inst(InstructionLength - 1);
-
- i12 : if InstructionLength = 12 generate
- B_Skip <= '1' when Inst(11 downto 10) = "10" else '0';
- Sleep <= '1' when ROM_Data(11 downto 0) = "000000000011" else '0';
- W_Wr <= '1' when Inst(11 downto 8) = "1000" or
- Inst(11 downto 10) = "11" or
- (Inst(11 downto 10) = "00" and Inst(5) = '0' and Inst(9 downto 6) /= "0000") else '0';
- IRet <= '0';
- process (Reset_n, Clk)
- begin
- if Reset_n = '0' then
- File_Wr <= '0';
- Goto <= '0';
- Push <= '0';
- Pop <= '0';
- A2Res <= '0';
- B2Res <= '0';
- elsif Clk'event and Clk = '1' then
- File_Wr <= '0';
- Goto <= '0';
- Push <= '0';
- Pop <= '0';
- A2Res <= '0';
- B2Res <= '0';
- if Skip = '0' then
- if (ROM_Data(InstructionLength - 1 downto InstructionLength - 2) = "00" and
- ROM_Data(InstructionLength - 7) = '1') or
- ROM_Data(InstructionLength - 1 downto InstructionLength - 3) = "010" then
- File_Wr <= '1';
- end if;
- if ROM_Data(InstructionLength - 1 downto InstructionLength - 3) = "101" then
- Goto <= '1';
- end if;
- if ROM_Data(11 downto 8) = "1001" then -- CALL
- Push <= '1';
- end if;
- if ROM_Data(11 downto 8) = "1000" then -- RETLW
- Pop <= '1';
- end if;
- if ROM_Data(11 downto 6) = "001000" then
- -- MOVF
- A2Res <= '1';
- end if;
- if ROM_Data(11 downto 8) = "1100" or -- MOVLW
- ROM_Data(11 downto 8) = "1000" or -- RETLW
- ROM_Data(11 downto 6) = "000000" then -- MOVWF/TRIS/OPTION and some others
- B2Res <= '1';
- end if;
- end if;
- end if;
- end process;
- end generate;
-
- i14 : if InstructionLength = 14 generate
- B_Skip <= '1' when Inst(13 downto 12) = "10" or Inst(13 downto 10) = "1101" or
- Inst(13 downto 1) = "0000000000100" else '0';
- Sleep <= '1' when ROM_Data(13 downto 0) = "00000001100011" else '0';
- W_Wr <= '1' when Inst(13 downto 12) = "11" or
- (Inst(13 downto 12) = "00" and Inst(7) = '0' and Inst(11 downto 8) /= "0000") else '0';
- IRet <= '1' when Inst(13 downto 0) = "00000000001001" else '0'; -- RETFIE
- process (Reset_n, Clk)
- begin
- if Reset_n = '0' then
- File_Wr <= '0';
- Goto <= '0';
- Push <= '0';
- Pop <= '0';
- A2Res <= '0';
- B2Res <= '0';
- elsif Clk'event and Clk = '1' then
- File_Wr <= '0';
- Goto <= '0';
- Push <= '0';
- Pop <= '0';
- A2Res <= '0';
- B2Res <= '0';
- if Skip = '0' then
- if (ROM_Data(InstructionLength - 1 downto InstructionLength - 2) = "00" and
- ROM_Data(InstructionLength - 7) = '1') or
- ROM_Data(InstructionLength - 1 downto InstructionLength - 3) = "010" then
- File_Wr <= '1';
- end if;
- if ROM_Data(InstructionLength - 1 downto InstructionLength - 3) = "101" then
- Goto <= '1';
- end if;
- if ROM_Data(13 downto 11) = "100" then
- Push <= '1'; -- CALL
- end if;
- if ROM_Data(13 downto 10) = "1101" or -- RETLW
- ROM_Data(13 downto 1) = "0000000000100" then -- RETURN, RETFIE
- Pop <= '1';
- end if;
- if ROM_Data(13 downto 8) = "001000" then
- -- MOVF
- A2Res <= '1';
- end if;
- if ROM_Data(13 downto 10) = "1100" or -- MOVLW
- ROM_Data(13 downto 10) = "1101" or -- RETLW
- ROM_Data(13 downto 8) = "000000" then -- MOVWF/TRIS/OPTION and some others
- B2Res <= '1';
- end if;
- end if;
- end if;
- end process;
- end generate;
-
-end;
Index: trunk/rtl/vhdl/PPX_PCS.vhd
===================================================================
--- trunk/rtl/vhdl/PPX_PCS.vhd (revision 21)
+++ trunk/rtl/vhdl/PPX_PCS.vhd (nonexistent)
@@ -1,171 +0,0 @@
---
--- PIC16xx compatible microcontroller core
---
--- Version : 0222
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity PPX_PCS is
- generic(
- PC_Width : integer;
- StackAddrWidth : integer;
- TopBoot : boolean
- );
- port(
- Clk : in std_logic;
- Reset_n : in std_logic;
- CS : in std_logic;
- Wr : in std_logic;
- Data_In : in std_logic_vector(7 downto 0);
- Addr_In : in std_logic_vector(PC_Width - 3 downto 0);
- PCLATH : in std_logic_vector(4 downto 0);
- STATUS : in std_logic_vector(6 downto 5);
- NPC : out std_logic_vector(PC_Width - 1 downto 0);
- Int : in std_logic;
- Sleep : in std_logic;
- Push : in std_logic;
- Pop : in std_logic;
- Goto : in std_logic
- );
-end PPX_PCS;
-
-architecture rtl of PPX_PCS is
-
- signal PC_i : unsigned(PC_Width - 1 downto 0);
- signal NPC_i : unsigned(PC_Width - 1 downto 0);
-
- type Stack_Image is array (2 ** StackAddrWidth - 1 downto 0) of unsigned(PC_Width - 1 downto 0);
- signal Stack : Stack_Image;
-
- signal StackPtr : unsigned(StackAddrWidth -1 downto 0);
-
-begin
-
- NPC <= std_logic_vector(NPC_i);
-
- process (Clk)
- begin
- if Clk'event and Clk = '1' then
- if Push = '1' then
- Stack(to_integer(StackPtr)) <= PC_i;
- end if;
- if Int = '1' then
- Stack(to_integer(StackPtr)) <= PC_i - 1;
- end if;
- end if;
- end process;
-
- process (PC_i, Sleep, CS, Wr, PCLATH, STATUS, Push, Pop, Goto, Data_In, Addr_In, Int, Stack, StackPtr)
- begin
- NPC_i <= PC_i;
- if Sleep = '0' then
- NPC_i <= PC_i + 1;
- end if;
- if CS = '1' and Wr = '1' then
- if PC_Width = 13 then
- NPC_i(7 downto 0) <= unsigned(Data_In);
- NPC_i(PC_Width - 1 downto PC_Width - 5) <= unsigned(PCLATH);
- end if;
- if PC_Width = 11 then
- NPC_i(7 downto 0) <= unsigned(Data_In);
- NPC_i(8) <= '0';
- NPC_i(10 downto 9) <= unsigned(STATUS);
- end if;
- end if;
- if Push = '1' then
- if PC_Width = 13 then
- NPC_i(10 downto 0) <= unsigned(Addr_In);
- NPC_i(PC_Width - 1 downto PC_Width - 2) <= unsigned(PCLATH(4 downto 3));
- end if;
- if PC_Width = 11 then
- NPC_i(7 downto 0) <= unsigned(Addr_In(7 downto 0));
- NPC_i(8) <= '0';
- NPC_i(10 downto 9) <= unsigned(STATUS);
- end if;
- end if;
- if Pop = '1' then
- NPC_i <= Stack(to_integer(StackPtr - 1));
- end if;
- if Goto = '1' then
- if PC_Width = 13 then
- NPC_i(10 downto 0) <= unsigned(Addr_In);
- NPC_i(PC_Width - 1 downto PC_Width - 2) <= unsigned(PCLATH(4 downto 3));
- end if;
- if PC_Width = 11 then
- NPC_i(8 downto 0) <= unsigned(Addr_In);
- NPC_i(10 downto 9) <= unsigned(STATUS);
- end if;
- end if;
- if Int = '1' then
- NPC_i <= (others => '0');
- NPC_i(2) <= '1';
- end if;
- end process;
-
- process (Reset_n, Clk)
- begin
- if Reset_n = '0' then
- PC_i <= (others => '1');
- if TopBoot then
- PC_i(0) <= '0';
- end if;
- StackPtr <= (others => '0');
- elsif Clk'event and Clk = '1' then
- PC_i <= NPC_i;
- if Push = '1' then
- StackPtr <= StackPtr + 1;
- end if;
- if Pop = '1' then
- StackPtr <= StackPtr - 1;
- end if;
- if Int = '1' then
- StackPtr <= StackPtr + 1;
- end if;
- end if;
- end process;
-
-end;
Index: trunk/rtl/vhdl/PPX16.vhd
===================================================================
--- trunk/rtl/vhdl/PPX16.vhd (revision 21)
+++ trunk/rtl/vhdl/PPX16.vhd (nonexistent)
@@ -1,343 +0,0 @@
---
--- PIC16xx compatible microcontroller core
---
--- Version : 0232
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/ppx16/
---
--- Limitations :
--- Registers implemented in this entity are INDF, PCL, STATUS, FSR, (PCLATH)
--- other registers must be implemented externally including GPR
---
--- File history :
---
--- 0232 : Fixed bank decoding and FSR/PCLATH register access
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.PPX_Pack.all;
-
-entity PPX16 is
- generic(
- InstructionLength : integer;
- ROMAddressWidth : integer;
- StackAddrWidth : integer;
- TopBoot : boolean
- );
- port(
- Clk : in std_logic;
- Reset_n : in std_logic;
- ROM_Addr : out std_logic_vector(ROMAddressWidth - 1 downto 0);
- ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
- Int_Trig : in std_logic;
- GIE : in std_logic;
- Int_Acc : out std_logic;
- Int_Ret : out std_logic;
- File_Addr : out std_logic_vector(InstructionLength - 6 downto 0);
- File_Addr_r : out std_logic_vector(InstructionLength - 6 downto 0);
- File_Wr : out std_logic;
- W_Wr : out std_logic;
- Instruction : out std_logic_vector(InstructionLength - 1 downto 0);
- Op_Bus : in std_logic_vector(7 downto 0);
- W : out std_logic_vector(7 downto 0);
- STATUS : out std_logic_vector(7 downto 0);
- FSR : out std_logic_vector(7 downto 0);
- PCLATH : out std_logic_vector(4 downto 0);
- Res_Bus : out std_logic_vector(7 downto 0)
- );
-end PPX16;
-
-architecture rtl of PPX16 is
-
- -- File control
- signal File_Addr_i : std_logic_vector(InstructionLength - 6 downto 0);
- signal File_Addr_i_r : std_logic_vector(InstructionLength - 6 downto 0);
- signal File_Wr_i : std_logic;
- signal PC_CS : std_logic;
-
- -- Registers
- signal W_i : std_logic_vector(7 downto 0);
- signal PCLATH_d : std_logic_vector(4 downto 0);
- signal PCLATH_i : std_logic_vector(4 downto 0);
- signal STATUS_i : std_logic_vector(7 downto 0);
- signal FSR_d : std_logic_vector(7 downto 0);
- signal FSR_i : std_logic_vector(7 downto 0);
- signal NPC : std_logic_vector(InstructionLength - 2 downto 0);
-
- -- Registered instruction word
- signal Inst : std_logic_vector(InstructionLength - 1 downto 0);
-
- -- Control signals
- signal Res_Bus_i : std_logic_vector(7 downto 0);
- signal Q : std_logic_vector(7 downto 0);
- signal Op_Mux : std_logic_vector(7 downto 0);
- signal STATUS_d_i : std_logic_vector(7 downto 0);
- signal STATUS_d : std_logic_vector(2 downto 0);
- signal STATUS_Wr : std_logic_vector(2 downto 0);
- signal Z_Skip : std_logic;
- signal B_Skip : std_logic;
- signal Inst_Skip : std_logic;
- signal W_Wr_i : std_logic;
- signal Imm_Op : std_logic;
- signal Push : std_logic;
- signal Pop : std_logic;
- signal Goto : std_logic;
- signal IRet : std_logic;
- signal A2Res : std_logic;
- signal B2Res : std_logic;
- signal Sleep : std_logic;
- signal Sleep_r : std_logic;
- signal Int : std_logic;
- signal Int_Pending : std_logic;
-
-begin
-
- Int_Acc <= Int;
- W_Wr <= W_Wr_i;
- W <= W_i;
- STATUS <= STATUS_d_i;
- PCLATH <= PCLATH_d;
- FSR <= FSR_d;
-
- -- Instruction register
- Instruction <= Inst;
- process (Reset_n, Clk)
- begin
- if Reset_n = '0' then
- Inst <= (others => '0'); -- Force NOP at reset.
- elsif Clk'event and Clk = '1' then
- if Inst_Skip = '1' then
- Inst <= (others => '0'); -- Flush (Force NOP)
- else
- Inst <= ROM_Data;
- end if;
- end if;
- end process;
-
- -- File address
- File_Addr <= File_Addr_i;
- i12 : if InstructionLength = 12 generate
- File_Addr_i <= FSR_d(6 downto 0) when
--- pragma translate_off
- is_x(ROM_Data) or
--- pragma translate_on
- unsigned(ROM_Data(4 downto 0)) = 0 else
- FSR_d(6 downto 5) & ROM_Data(4 downto 0);
- end generate;
- i14 : if InstructionLength = 14 generate
- File_Addr_i <= STATUS_d_i(7) & FSR_d(7 downto 0) when
--- pragma translate_off
- is_x(ROM_Data) or
--- pragma translate_on
- unsigned(ROM_Data(6 downto 0)) = 0 else
- STATUS_d_i(6 downto 5) & ROM_Data(6 downto 0);
- end generate;
- process (Clk)
- begin
- if Clk'event and Clk = '1' then
- File_Addr_r <= File_Addr_i;
- File_Addr_i_r <= File_Addr_i;
- end if;
- end process;
-
- -- PCLATH Register
- PCLATH_d <= Res_Bus_i(4 downto 0) when
- to_integer(unsigned(File_Addr_i_r(6 downto 0))) = 10 and File_Wr_i = '1'
- else PCLATH_i;
- process (Reset_n, Clk)
- begin
- if Reset_n = '0' then
- PCLATH_i <= "00000";
- elsif Clk'event and Clk = '1' then
- PCLATH_i <= PCLATH_d;
- end if;
- end process;
-
- -- Working register
- process (Clk)
- begin
- if Clk'event and Clk = '1' then
- if W_Wr_i = '1' then
- W_i <= Res_Bus_i;
- end if;
- end if;
- end process;
-
- -- Status register
- process (STATUS_Wr, STATUS_d, STATUS_i, A2Res, Op_Bus, File_Addr_i_r, File_Wr_i, Res_Bus_i)
- begin
- STATUS_d_i <= STATUS_i;
- if STATUS_Wr(0) = '1' then
- STATUS_d_i(0) <= STATUS_d(0);
- end if;
- if STATUS_Wr(1) = '1' then
- STATUS_d_i(1) <= STATUS_d(1);
- end if;
- if STATUS_Wr(2) = '1' then
- STATUS_d_i(2) <= STATUS_d(2);
- end if;
- if A2Res = '1' then
- STATUS_d_i(2) <= '0';
- if Op_Bus = "00000000" then
- STATUS_d_i(2) <= '1';
- end if;
- end if;
- if to_integer(unsigned(File_Addr_i_r(InstructionLength - 8 downto 0))) = 3 and File_Wr_i = '1' then
- STATUS_d_i <= Res_Bus_i;
- end if;
- end process;
- process (Reset_n, Clk)
- begin
- if Reset_n = '0' then
- STATUS_i <= "00011000";
- elsif Clk'event and Clk = '1' then
- STATUS_i <= STATUS_d_i;
- end if;
- end process;
-
- -- FSR Register
- FSR_d <= Res_Bus_i when
- to_integer(unsigned(File_Addr_i_r(InstructionLength - 8 downto 0))) = 4 and
- File_Wr_i = '1' else FSR_i;
- process (Reset_n, Clk)
- begin
- if Reset_n = '0' then
- FSR_i <= "11111111";
- elsif Clk'event and Clk = '1' then
- FSR_i <= FSR_d;
- end if;
- end process;
-
- -- Program counter
- PC_CS <= '1' when to_integer(unsigned(File_Addr_i_r(InstructionLength - 8 downto 0))) = 2 else '0';
- ROM_Addr <= NPC(ROMAddressWidth - 1 downto 0);
- pcs : PPX_PCS
- generic map(
- PC_Width => InstructionLength - 1,
- StackAddrWidth => StackAddrWidth,
- TopBoot => TopBoot)
- port map(
- Clk => Clk,
- Reset_n => Reset_n,
- CS => PC_CS,
- Wr => File_Wr_i,
- Data_In => Res_Bus_i,
- Addr_In => Inst(InstructionLength - 4 downto 0),
- PCLATH => PCLATH_i,
- STATUS => STATUS_i(6 downto 5),
- NPC => NPC,
- Int => Int,
- Sleep => Sleep_r,
- Push => Push,
- Pop => Pop,
- Goto => Goto);
-
- -- ALU
- Op_Mux <= Inst(7 downto 0) when Imm_Op = '1' else W_i;
- Res_Bus <= Res_Bus_i;
- Res_Bus_i <= Op_Bus when A2Res = '1' else Op_Mux when B2Res = '1' else Q;
- alu : PPX_ALU
- generic map(InstructionLength => InstructionLength)
- port map(
- Clk => Clk,
- ROM_Data => ROM_Data,
- A => Op_Bus,
- B => Op_Mux,
- Q => Q,
- Skip => Inst_Skip,
- Carry => STATUS_i(0),
- Z_Skip => Z_Skip,
- STATUS_d => STATUS_d,
- STATUS_Wr => STATUS_Wr);
-
- -- Instruction decoder
- File_Wr <= File_Wr_i;
- Inst_Skip <= Z_Skip or B_Skip or Sleep_r or Int_Pending;
- id : PPX_Ctrl
- generic map(InstructionLength => InstructionLength)
- port map(
- Clk => Clk,
- Reset_n => Reset_n,
- ROM_Data => ROM_Data,
- Inst => Inst,
- Skip => Inst_Skip,
- File_Wr => File_Wr_i,
- W_Wr => W_Wr_i,
- Imm_Op => Imm_Op,
- A2Res => A2Res,
- B2Res => B2Res,
- Push => Push,
- Pop => Pop,
- Goto => Goto,
- IRet => IRet,
- B_Skip => B_Skip,
- Sleep => Sleep);
-
- -- Interrupt
- process (Reset_n, Clk)
- begin
- if Reset_n = '0' then
- Sleep_r <= '0';
- Int <= '0';
- Int_Pending <= '0';
- Int_Ret <= '0';
- elsif Clk'event and Clk = '1' then
- if Sleep = '1' then
- Sleep_r <= '1';
- end if;
- if Int_Trig = '1' then
- Sleep_r <= '0';
- end if;
- Int_Pending <= '0';
- Int <= '0';
- if Int_Trig = '1' and GIE = '1' and Int = '0' then
- Int_Pending <= '1';
- end if;
- if Int_Pending = '1' and Int = '0' and (Z_Skip or B_Skip or Sleep_r) = '0' then
- Int <= '1';
- end if;
- if IRet = '1' then
- Int_Ret <= '1';
- else
- Int_Ret <= '0';
- end if;
- end if;
- end process;
-
-end;
Index: trunk/rtl/vhdl/P16C55.vhd
===================================================================
--- trunk/rtl/vhdl/P16C55.vhd (revision 21)
+++ trunk/rtl/vhdl/P16C55.vhd (nonexistent)
@@ -1,269 +0,0 @@
---
--- PIC16C55 compatible microcontroller core
---
--- Version : 0222
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.PPX_Pack.all;
-
-entity P16C55 is
- generic(
- SyncReset : boolean := true);
- port(
- Clk : in std_logic;
- Reset_n : in std_logic;
- T0CKI : in std_logic;
- Port_A : inout std_logic_vector(7 downto 0);
- Port_B : inout std_logic_vector(7 downto 0);
- Port_C : inout std_logic_vector(7 downto 0)
- );
-end P16C55;
-
-architecture rtl of P16C55 is
-
- constant InstructionLength : integer := 12;
- constant ROMAddressWidth : integer := 9;
- constant StackAddrWidth : integer := 1;
- constant TopBoot : boolean := true;
-
- component ROM55
- port(
- Clk : in std_logic;
- A : in std_logic_vector(ROMAddressWidth - 1 downto 0);
- D : out std_logic_vector(11 downto 0)
- );
- end component;
-
- signal Reset_s_n : std_logic;
- signal ROM_Addr : std_logic_vector(ROMAddressWidth - 1 downto 0);
- signal ROM_Data : std_logic_vector(InstructionLength - 1 downto 0);
- signal Instruction : std_logic_vector(InstructionLength - 1 downto 0);
- signal File_Addr : std_logic_vector(InstructionLength - 6 downto 0);
- signal File_Addr_r : std_logic_vector(InstructionLength - 6 downto 0);
- signal RAM_CS : std_logic;
- signal TMR_CS : std_logic;
- signal File_Wr : std_logic;
- signal W_Wr : std_logic;
- signal Tris_A_Wr : std_logic;
- signal Tris_B_Wr : std_logic;
- signal Tris_C_Wr : std_logic;
- signal Port_A_Wr : std_logic;
- signal Port_B_Wr : std_logic;
- signal Port_C_Wr : std_logic;
- signal Op_Bus : std_logic_vector(7 downto 0);
- signal Op_Mux : std_logic_vector(7 downto 0);
- signal Res_Bus : std_logic_vector(7 downto 0);
- signal RAM_Data : std_logic_vector(7 downto 0);
- signal OPTION : std_logic_vector(5 downto 0);
- signal PortA : std_logic_vector(7 downto 0);
- signal PortB : std_logic_vector(7 downto 0);
- signal PortC : std_logic_vector(7 downto 0);
- signal TMR : std_logic_vector(7 downto 0);
- signal W : std_logic_vector(7 downto 0);
- signal STATUS : std_logic_vector(7 downto 0);
- signal FSR : std_logic_vector(7 downto 0);
- signal Int_Trig : std_logic;
- signal GIE : std_logic;
-
-begin
-
- Int_Trig <= '0';
- GIE <= '0';
-
- -- Synchronise reset
- process (Reset_n, Clk)
- variable Reset_v : std_logic;
- begin
- if Reset_n = '0' then
- if SyncReset then
- Reset_s_n <= '0';
- Reset_v := '0';
- end if;
- elsif Clk'event and Clk = '1' then
- if SyncReset then
- Reset_s_n <= Reset_v;
- Reset_v := '1';
- end if;
- end if;
- end process;
-
- g_reset : if not SyncReset generate
- Reset_s_n <= Reset_n;
- end generate;
-
- -- Address decoder
- TMR_CS <= '1' when to_integer(unsigned(File_Addr_r(4 downto 0))) = 1 else '0';
- Tris_A_Wr <= '1' when Instruction(11 downto 0) = "000000000101" else '0';
- Tris_B_Wr <= '1' when Instruction(11 downto 0) = "000000000110" else '0';
- Tris_C_Wr <= '1' when Instruction(11 downto 0) = "000000000111" else '0';
- Port_A_Wr <= '1' when to_integer(unsigned(File_Addr_r(4 downto 0))) = 5 and File_Wr = '1' else '0';
- Port_B_Wr <= '1' when to_integer(unsigned(File_Addr_r(4 downto 0))) = 6 and File_Wr = '1' else '0';
- Port_C_Wr <= '1' when to_integer(unsigned(File_Addr_r(4 downto 0))) = 7 and File_Wr = '1' else '0';
-
- -- Register selector
- process (Clk)
- begin
- if Clk'event and Clk = '1' then
- case to_integer(unsigned(File_Addr(4 downto 0))) is
- when 1 => Op_Bus <= TMR;
- when 2 => Op_Bus <= ROM_Addr(7 downto 0);
- when 3 => Op_Bus <= STATUS;
- when 4 => Op_Bus <= FSR;
- when 5 => Op_Bus <= PortA;
- when 6 => Op_Bus <= PortB;
- when 7 => Op_Bus <= PortC;
- when others => Op_Bus <= "--------";
- end case;
- if File_Wr = '1' and File_Addr_r = File_Addr then
- -- Write through
- Op_Bus <= Res_Bus;
- end if;
- RAM_CS <= '0';
- if ROM_Data(InstructionLength - 1) = '1' then
- Op_Bus <= W;
- -- Write through
- if W_Wr = '1' then
- Op_Bus <= Res_Bus;
- end if;
- elsif File_Addr(4 downto 3) /= "00" then
- RAM_CS <= '1';
- end if;
- end if;
- end process;
-
- -- Register File
- Op_Mux <= RAM_Data when RAM_CS = '1' else Op_Bus;
- pr : PPX_RAM
- generic map(Bottom => 8, Top => 31, AddrWidth => 5)
- port map(
- Clk => Clk,
- CS => RAM_CS,
- Wr => File_Wr,
- Addr => File_Addr(4 downto 0),
- Data_In => Res_Bus,
- Data_Out => RAM_Data);
-
- -- Option Register
- process (Clk)
- begin
- if Clk'event and Clk = '1' then
- if Instruction(11 downto 0) = "000000000010" then
- OPTION <= Res_Bus(5 downto 0);
- end if;
- end if;
- end process;
-
- rom : ROM55 port map(
- Clk => Clk,
- A => ROM_Addr,
- D => ROM_Data);
-
- ppx : PPX16
- generic map(
- InstructionLength => InstructionLength,
- ROMAddressWidth => ROMAddressWidth,
- StackAddrWidth => StackAddrWidth,
- TopBoot => TopBoot)
- port map(
- Clk => Clk,
- Reset_n => Reset_s_n,
- ROM_Addr => ROM_Addr,
- ROM_Data => ROM_Data,
- Int_Trig => Int_Trig,
- GIE => GIE,
- File_Addr => File_Addr,
- File_Addr_r => File_Addr_r,
- File_Wr => File_Wr,
- W_Wr => W_Wr,
- Instruction => Instruction,
- Op_Bus => Op_Mux,
- W => W,
- STATUS => STATUS,
- FSR => FSR,
- Res_Bus => Res_Bus);
-
- tmr0 : PPX_TMR port map(
- Clk => Clk,
- Reset_n => Reset_s_n,
- CKI => T0CKI,
- SE => OPTION(4),
- CS => OPTION(5),
- PS => OPTION(2 downto 0),
- PSA => OPTION(3),
- TMR_Sel => TMR_CS,
- Wr => File_Wr,
- Data_In => Res_Bus,
- Data_Out => TMR);
-
- aport : PPX_Port port map(
- Clk => Clk,
- Reset_n => Reset_s_n,
- Port_Wr => Port_A_Wr,
- Tris_Wr => Tris_A_Wr,
- Data_In => Res_Bus,
- Port_In => PortA,
- IOPort => Port_A);
-
- bport : PPX_Port port map(
- Clk => Clk,
- Reset_n => Reset_s_n,
- Port_Wr => Port_B_Wr,
- Tris_Wr => Tris_B_Wr,
- Data_In => Res_Bus,
- Port_In => PortB,
- IOPort => Port_B);
-
- cport : PPX_Port port map(
- Clk => Clk,
- Reset_n => Reset_s_n,
- Port_Wr => Port_C_Wr,
- Tris_Wr => Tris_C_Wr,
- Data_In => Res_Bus,
- Port_In => PortC,
- IOPort => Port_C);
-
-end;
Index: trunk/rtl/vhdl/PPX_Pack.vhd
===================================================================
--- trunk/rtl/vhdl/PPX_Pack.vhd (revision 21)
+++ trunk/rtl/vhdl/PPX_Pack.vhd (nonexistent)
@@ -1,195 +0,0 @@
---
--- PIC16xx compatible microcontroller core
---
--- Version : 0224
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/ppx16/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package PPX_Pack is
-
- component PPX_ALU
- generic(
- InstructionLength : integer
- );
- port (
- Clk : in std_logic;
- ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
- A : in std_logic_vector(7 downto 0);
- B : in std_logic_vector(7 downto 0);
- Q : out std_logic_vector(7 downto 0);
- Skip : in std_logic;
- Carry : in std_logic;
- Z_Skip : out std_logic;
- STATUS_d : out std_logic_vector(2 downto 0);
- STATUS_Wr : out std_logic_vector(2 downto 0)
- );
- end component;
-
- component PPX_Ctrl
- generic(
- InstructionLength : integer
- );
- port(
- Clk : in std_logic;
- Reset_n : in std_logic;
- ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
- Inst : in std_logic_vector(InstructionLength - 1 downto 0);
- Skip : in std_logic;
- File_Wr : out std_logic;
- W_Wr : out std_logic;
- Imm_Op : out std_logic;
- A2Res : out std_logic;
- B2Res : out std_logic;
- Push : out std_logic;
- Pop : out std_logic;
- Goto : out std_logic;
- IRet : out std_logic;
- B_Skip : out std_logic;
- Sleep : out std_logic
- );
- end component;
-
- component PPX_PCS
- generic(
- PC_Width : integer;
- StackAddrWidth : integer;
- TopBoot : boolean
- );
- port(
- Clk : in std_logic;
- Reset_n : in std_logic;
- CS : in std_logic;
- Wr : in std_logic;
- Data_In : in std_logic_vector(7 downto 0);
- Addr_In : in std_logic_vector(PC_Width - 3 downto 0);
- PCLATH : in std_logic_vector(4 downto 0);
- STATUS : in std_logic_vector(6 downto 5);
- NPC : out std_logic_vector(PC_Width - 1 downto 0);
- Int : in std_logic;
- Sleep : in std_logic;
- Push : in std_logic;
- Pop : in std_logic;
- Goto : in std_logic
- );
- end component;
-
- component PPX16
- generic(
- InstructionLength : integer;
- ROMAddressWidth : integer;
- StackAddrWidth : integer;
- TopBoot : boolean
- );
- port(
- Clk : in std_logic;
- Reset_n : in std_logic;
- ROM_Addr : out std_logic_vector(ROMAddressWidth - 1 downto 0);
- ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
- Int_Trig : in std_logic;
- GIE : in std_logic;
- Int_Acc : out std_logic;
- Int_Ret : out std_logic;
- File_Addr : out std_logic_vector(InstructionLength - 6 downto 0);
- File_Addr_r : out std_logic_vector(InstructionLength - 6 downto 0);
- File_Wr : out std_logic;
- W_Wr : out std_logic;
- Instruction : out std_logic_vector(InstructionLength - 1 downto 0);
- Op_Bus : in std_logic_vector(7 downto 0);
- W : out std_logic_vector(7 downto 0);
- STATUS : out std_logic_vector(7 downto 0);
- FSR : out std_logic_vector(7 downto 0);
- PCLATH : out std_logic_vector(4 downto 0);
- Res_Bus : out std_logic_vector(7 downto 0)
- );
- end component;
-
- component PPX_RAM
- generic(
- Bottom : integer;
- Top : integer;
- AddrWidth : integer
- );
- port(
- Clk : in std_logic;
- CS : in std_logic;
- Wr : in std_logic;
- Addr : in std_logic_vector(AddrWidth - 1 downto 0);
- Data_In : in std_logic_vector(7 downto 0);
- Data_Out : out std_logic_vector(7 downto 0)
- );
- end component;
-
- component PPX_Port
- port(
- Clk : in std_logic;
- Reset_n : in std_logic;
- Port_Wr : in std_logic;
- Tris_Wr : in std_logic;
- Data_In : in std_logic_vector(7 downto 0);
- Port_In : out std_logic_vector(7 downto 0);
- Tris : out std_logic_vector(7 downto 0);
- IOPort : inout std_logic_vector(7 downto 0)
- );
- end component;
-
- component PPX_TMR
- port(
- Clk : in std_logic;
- Reset_n : in std_logic;
- CKI : in std_logic;
- SE : in std_logic;
- CS : in std_logic;
- PS : in std_logic_vector(2 downto 0);
- PSA : in std_logic;
- TMR_Sel : in std_logic;
- Wr : in std_logic;
- Data_In : in std_logic_vector(7 downto 0);
- Data_Out : out std_logic_vector(7 downto 0);
- TOF : out std_logic
- );
- end component;
-
-end PPX_Pack;
Index: ppx16/trunk/sw/xrom.cpp
===================================================================
--- ppx16/trunk/sw/xrom.cpp (nonexistent)
+++ ppx16/trunk/sw/xrom.cpp (revision 22)
@@ -0,0 +1,414 @@
+//
+// Xilinx VHDL ROM generator
+//
+// Version : 0244
+//
+// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+//
+// All rights reserved
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// Neither the name of the author nor the names of other contributors may
+// be used to endorse or promote products derived from this software without
+// specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// Please report bugs to the author, but before you do so, please
+// make sure that this is not a derivative work and that
+// you have the latest version of this file.
+//
+// The latest version of this file can be found at:
+// http://www.opencores.org/cvsweb.shtml/t51/
+//
+// Limitations :
+// Not all address/data widths produce working code
+// Requires stl to compile
+//
+// File history :
+//
+// 0220 : Initial release
+//
+// 0221 : Fixed block ROMs with partial bytes
+//
+// 0241 : Updated for WebPack 5.1
+//
+// 0244 : Added -n option and component declaration
+//
+
+#include
+#include
+#include
+#include
+
+using namespace std;
+
+#if !(defined(max)) && _MSC_VER
+ // VC fix
+ #define max __max
+#endif
+
+int main (int argc, char *argv[])
+{
+ cerr << "Xilinx VHDL ROM generator by Daniel Wallner. Version 0244\n";
+
+ try
+ {
+ unsigned long aWidth;
+ unsigned long dWidth;
+ unsigned long select = 0;
+ unsigned long length = 0;
+ char z = 0;
+
+ if (argc < 4)
+ {
+ cerr << "\nUsage: xrom \n";
+ cerr << "\nThe options can be:\n";
+ cerr << " -[decimal number] = SelectRAM usage in 1/16 parts\n";
+ cerr << " -z = use tri-state buses\n";
+ cerr << " -n [decimal size] = limit rom size\n";
+ cerr << "\nExample:\n";
+ cerr << " xrom Test_ROM 13 8 -6\n\n";
+ return -1;
+ }
+
+ int result;
+
+ result = sscanf(argv[2], "%lu", &aWidth);
+ if (result < 1)
+ {
+ throw "Error in address bits argument!\n";
+ }
+
+ result = sscanf(argv[3], "%lu", &dWidth);
+ if (result < 1)
+ {
+ throw "Error in data bits argument!\n";
+ }
+
+ int argument = 4;
+
+ while (argument < argc)
+ {
+ char tmpC = 0;
+ unsigned long tmpL = 0;
+
+ result = sscanf(argv[argument], "%c%lu", &tmpC, &tmpL);
+ if (result < 1 || tmpC != '-' )
+ {
+ throw "Error in options!\n";
+ }
+
+ if (result < 2)
+ {
+ sscanf(argv[argument], "%c%c", &tmpC, &tmpC);
+ if (tmpC != 'z' && tmpC != 'n')
+ {
+ throw "Unkown option!\n";
+ }
+ if (tmpC == 'z')
+ {
+ z = tmpC;
+ }
+ else
+ {
+ argument++;
+
+ if (argument == argc)
+ {
+ throw "No memory size argument!\n";
+ }
+
+ result = sscanf(argv[argument], "%lu", &tmpL);
+ if (!result)
+ {
+ throw "Memory size not a number!\n";
+ }
+ length = tmpL;
+ }
+ }
+ else
+ {
+ select = tmpL;
+ }
+ argument++;
+ }
+
+ unsigned long selectIter = 0;
+ unsigned long blockIter = 0;
+ unsigned long bytes = (dWidth + 7) / 8;
+
+ if (!select)
+ {
+ blockIter = ((1UL << aWidth) + 511) / 512;
+ if (length && length < blockIter * 512)
+ {
+ blockIter = (length + 511) / 512;
+ }
+ }
+ else if (select == 16)
+ {
+ selectIter = ((1UL << aWidth) + 15) / 16;
+ if (length && length < selectIter * 16)
+ {
+ selectIter = (length + 15) / 16;
+ }
+ }
+ else
+ {
+ blockIter = ((1UL << aWidth) * (16 - select) / 16 + 511) / 512;
+ selectIter = ((1UL << aWidth) - blockIter * 512 + 15) / 16;
+ }
+
+ unsigned long blockTotal = ((1UL << aWidth) + 511) / 512;
+ if (length && length < blockTotal * 512)
+ {
+ blockTotal = (length + 511) / 512;
+ }
+
+ if (length)
+ {
+ if (length > selectIter * 16)
+ {
+ blockIter -= ((1UL << aWidth) + 511) / 512 - blockTotal;
+ }
+ else
+ {
+ blockIter = 0;
+ }
+ }
+ if (length && !blockIter && length < selectIter * 16)
+ {
+ selectIter = (length + 15) / 16;
+ }
+
+ cerr << "Creating ROM with " << selectIter * bytes;
+ cerr << " RAM16X1S and " << blockIter * bytes << " RAMB4_S8\n";
+
+ printf("-- This file was generated with xrom written by Daniel Wallner\n");
+ printf("\nlibrary IEEE;");
+ printf("\nuse IEEE.std_logic_1164.all;");
+ printf("\nuse IEEE.numeric_std.all;");
+ printf("\n\nentity %s is", argv[1]);
+ printf("\n\tport(");
+ printf("\n\t\tClk\t: in std_logic;");
+ printf("\n\t\tA\t: in std_logic_vector(%d downto 0);", aWidth - 1);
+ printf("\n\t\tD\t: out std_logic_vector(%d downto 0)", dWidth - 1);
+ printf("\n\t);");
+ printf("\nend %s;", argv[1]);
+ printf("\n\narchitecture rtl of %s is", argv[1]);
+
+ if (selectIter)
+ {
+ printf("\n\tcomponent RAM16X1S");
+ printf("\n\t\tport(");
+ printf("\n\t\t\tO : out std_ulogic;");
+ printf("\n\t\t\tA0 : in std_ulogic;");
+ printf("\n\t\t\tA1 : in std_ulogic;");
+ printf("\n\t\t\tA2 : in std_ulogic;");
+ printf("\n\t\t\tA3 : in std_ulogic;");
+ printf("\n\t\t\tD : in std_ulogic;");
+ printf("\n\t\t\tWCLK : in std_ulogic;");
+ printf("\n\t\t\tWE : in std_ulogic);");
+ printf("\n\tend component;\n");
+ }
+ if (blockIter)
+ {
+ printf("\n\tcomponent RAMB4_S8");
+ printf("\n\t\tport(");
+ printf("\n\t\t\tDO : out std_logic_vector(7 downto 0);");
+ printf("\n\t\t\tADDR : in std_logic_vector(8 downto 0);");
+ printf("\n\t\t\tCLK : in std_ulogic;");
+ printf("\n\t\t\tDI : in std_logic_vector(7 downto 0);");
+ printf("\n\t\t\tEN : in std_ulogic;");
+ printf("\n\t\t\tRST : in std_ulogic;");
+ printf("\n\t\t\tWE : in std_ulogic);");
+ printf("\n\tend component;\n");
+ }
+
+ if (selectIter > 0)
+ {
+ printf("\n\tsignal A_r: unsigned(A'range);");
+ }
+ if (selectIter > 1)
+ {
+ printf("\n\ttype sRAMOut_a is array(0 to %d) of std_logic_vector(D'range);", selectIter - 1);
+ printf("\n\tsignal sRAMOut : sRAMOut_a;");
+ printf("\n\tsignal siA_r : integer;");
+ }
+ if (selectIter && blockIter)
+ {
+ printf("\n\tsignal sD : std_logic_vector(D'range);");
+ }
+ if (blockIter == 1)
+ {
+ printf("\n\tsignal bRAMOut : std_logic_vector(%d downto 0);", bytes * 8 - 1);
+ }
+ if (blockIter > 1)
+ {
+ printf("\n\ttype bRAMOut_a is array(%d to %d) of std_logic_vector(%d downto 0);", blockTotal - blockIter, blockTotal - 1, bytes * 8 - 1);
+ printf("\n\tsignal bRAMOut : bRAMOut_a;");
+ printf("\n\tsignal biA_r : integer;");
+ if (!selectIter)
+ {
+ printf("\n\tsignal A_r : unsigned(A'left downto 9);");
+ }
+ }
+ if (selectIter && blockIter)
+ {
+ printf("\n\tsignal bD : std_logic_vector(D'range);");
+ }
+
+ printf("\nbegin");
+
+ if (selectIter > 0 || blockIter > 1)
+ {
+ printf("\n\tprocess (Clk)");
+ printf("\n\tbegin");
+ printf("\n\t\tif Clk'event and Clk = '1' then");
+ if (!selectIter)
+ {
+ printf("\n\t\t\tA_r <= unsigned(A(A'left downto 9));");
+ }
+ else
+ {
+ printf("\n\t\t\tA_r <= unsigned(A);");
+ }
+ printf("\n\t\tend if;");
+ printf("\n\tend process;");
+ }
+
+ if (selectIter == 1)
+ {
+ printf("\n\n\tsG1: for I in 0 to %d generate", dWidth - 1);
+ printf("\n\t\tS%s : RAM16X1S\n\t\t\tport map (", argv[1]);
+ if (blockIter)
+ {
+ printf("s");
+ }
+ printf("WE => '0', WCLK => '0', D => '0', O => D(I), A0 => A_r(0), A1 => A_r(1), A2 => A_r(2), A3 => A_r(3));");
+ printf("\n\tend generate;");
+ }
+ if (selectIter > 1)
+ {
+ printf("\n\n\tsiA_r <= to_integer(A_r(A'left downto 4));");
+ printf("\n\n\tsG1: for I in 0 to %d generate", selectIter - 1);
+ printf("\n\t\tsG2: for J in 0 to %d generate", dWidth - 1);
+ printf("\n\t\t\tS%s : RAM16X1S\n\t\t\t\tport map (WE => '0', WCLK => '0', D => '0', O => sRAMOut(I)(J), A0 => A_r(0), A1 => A_r(1), A2 => A_r(2), A3 => A_r(3));", argv[1]);
+ printf("\n\t\tend generate;");
+ if (z == 'z')
+ {
+ printf("\n\t\t");
+ if (blockIter)
+ {
+ printf("s");
+ }
+ printf("D <= sRAMOut(I) when siA_r = I else (others => 'Z');");
+ }
+ printf("\n\tend generate;");
+ if (z != 'z')
+ {
+ printf("\n\n\tprocess (siA_r, sRAMOut)\n\tbegin\n\t\t");
+ if (blockIter)
+ {
+ printf("s");
+ }
+ printf("D <= sRAMOut(0);");
+ printf("\n\t\tfor I in 1 to %d loop", selectIter - 1);
+ printf("\n\t\t\tif siA_r = I then\n\t\t\t\t");
+ if (blockIter)
+ {
+ printf("s");
+ }
+ printf("D <= sRAMOut(I);\n\t\t\tend if;");
+ printf("\n\t\tend loop;\n\tend process;");
+ }
+ }
+
+ if (blockIter == 1)
+ {
+ printf("\n\n\tbG1: for J in 0 to %d generate", bytes - 1);
+ printf("\n\t\tB%s : RAMB4_S8", argv[1]);
+ printf("\n\t\t\tport map (DI => \"00000000\", EN => '1', RST => '0', WE => '0', CLK => Clk, ADDR => A(8 downto 0), DO => bRAMOut(7 + 8 * J downto 8 * J));", argv[1]);
+ printf("\n\tend generate;");
+ printf("\n\n\t");
+ if (selectIter)
+ {
+ printf("b");
+ }
+ printf("D <= bRAMOut(D'range);");
+ }
+ if (blockIter > 1)
+ {
+ printf("\n\n\tbiA_r <= to_integer(A_r(A'left downto 9));");
+ printf("\n\n\tbG1: for I in %d to %d generate", blockTotal - blockIter, blockTotal - 1);
+ printf("\n\t\tbG2: for J in 0 to %d generate", bytes - 1);
+ printf("\n\t\t\tB%s : RAMB4_S8\n\t\t\t\tport map (DI => \"00000000\", EN => '1', RST => '0', WE => '0', CLK => Clk, ADDR => A(8 downto 0), DO => bRAMOut(I)(7 + 8 * J downto 8 * J));", argv[1]);
+ printf("\n\t\tend generate;");
+ if (z == 'z')
+ {
+ printf("\n\t\t");
+ if (selectIter)
+ {
+ printf("b");
+ }
+ printf("D <= bRAMOut(I) when biA_r = I else (others => 'Z');");
+ }
+ printf("\n\tend generate;");
+ if (z != 'z')
+ {
+ printf("\n\n\tprocess (biA_r, bRAMOut)\n\tbegin\n\t\t");
+ if (selectIter)
+ {
+ printf("b");
+ }
+ printf("D <= bRAMOut(%d)(D'range);", blockTotal - blockIter);
+ printf("\n\t\tfor I in %d to %d loop", blockTotal - blockIter + 1, blockTotal - 1);
+ printf("\n\t\t\tif biA_r = I then\n\t\t\t\t");
+ if (selectIter)
+ {
+ printf("b");
+ }
+ printf("D <= bRAMOut(I)(D'range);\n\t\t\tend if;");
+ printf("\n\t\tend loop;\n\tend process;");
+ }
+ }
+
+ if (selectIter && blockIter)
+ {
+ printf("\n\n\tD <= bD when A_r(A'left downto 9) >= %d else sD;", blockTotal - blockIter);
+ }
+
+ printf("\nend;\n");
+
+ return 0;
+ }
+ catch (string error)
+ {
+ cerr << "Fatal: " << error;
+ }
+ catch (const char *error)
+ {
+ cerr << "Fatal: " << error;
+ }
+ return -1;
+}
Index: ppx16/trunk/sw/hex2rom.cpp
===================================================================
--- ppx16/trunk/sw/hex2rom.cpp (nonexistent)
+++ ppx16/trunk/sw/hex2rom.cpp (revision 22)
@@ -0,0 +1,962 @@
+//
+// Binary and intel/motorola hex to VHDL ROM converter
+//
+// Version : 0244
+//
+// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+//
+// All rights reserved
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// Neither the name of the author nor the names of other contributors may
+// be used to endorse or promote products derived from this software without
+// specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// Please report bugs to the author, but before you do so, please
+// make sure that this is not a derivative work and that
+// you have the latest version of this file.
+//
+// The latest version of this file can be found at:
+// http://www.opencores.org/cvsweb.shtml/t51/
+//
+// Limitations :
+// No support for wrapped intel segments
+// Requires stl to compile
+//
+// File history :
+//
+// 0146 : Initial release
+//
+// 0150 : Added binary read
+//
+// 0208 : Changed some errors to warnings
+//
+// 0215 : Added support for synchronous ROM
+//
+// 0220 : Changed array ROM format, added support for Xilinx .UCF generation
+//
+// 0221 : Fixed small .UCF generation for small ROMs
+//
+// 0244 : Added Leonardo .UCF option
+//
+
+#include
+#include
+#include
+#include
+
+using namespace std;
+
+#if !(defined(max)) && _MSC_VER
+ // VC fix
+ #define max __max
+#endif
+
+class MemBlock
+{
+public:
+ unsigned long m_startAddress;
+ vector m_bytes;
+};
+
+class File
+{
+public:
+ explicit File(const char *fileName, const char *mode)
+ {
+ m_file = fopen(fileName, mode);
+ if (m_file != NULL)
+ {
+ return;
+ }
+ string errorStr = "Error opening ";
+ errorStr += fileName;
+ errorStr += "\n";
+ throw errorStr;
+ }
+
+ ~File()
+ {
+ fclose(m_file);
+ }
+
+ // Read binary file
+ void ReadBin(unsigned long limit)
+ {
+ m_top = 0;
+
+ m_chunks.push_back(MemBlock());
+ m_chunks.back().m_startAddress = 0;
+
+ cerr << "Reading binary file\n";
+
+ int tmp = fgetc(m_file);
+
+ while (!feof(m_file))
+ {
+ m_chunks.back().m_bytes.push_back(tmp);
+
+ if (m_chunks.back().m_bytes.size() > limit + 1)
+ {
+ m_chunks.back().m_bytes.pop_back();
+ m_top = m_chunks.back().m_bytes.size() - 1;
+ cerr << "Ignoring data above address space!\n";
+ cerr << " Limit: " << limit << "\n";
+ return;
+ }
+
+ tmp = fgetc(m_file);
+ }
+
+ m_top = m_chunks.back().m_bytes.size() - 1;
+
+ if (!m_chunks.back().m_bytes.size())
+ {
+ cerr << "No data!\n";
+
+ m_chunks.pop_back();
+ }
+ }
+
+ // Read hex file
+ void ReadHex(unsigned long limit)
+ {
+ char szLine[1024];
+ bool formatDetected = false;
+ bool intel;
+ bool endSeen = false;
+ bool linear = true; // Only used for intel hex
+ unsigned long addressBase = 0; // Only used for intel hex
+ unsigned long dataRecords = 0; // Only used for s-record
+ while (!feof(m_file))
+ {
+ if (fgets(szLine, 1024, m_file) == 0)
+ {
+ if (ferror(m_file))
+ {
+ throw "Error reading input!\n";
+ }
+ continue;
+ }
+
+ if (szLine[strlen(szLine) - 1] == 0xA || szLine[strlen(szLine) - 1] == 0xD)
+ {
+ szLine[strlen(szLine) - 1] = 0;
+ }
+
+ if (szLine[strlen(szLine) - 1] == 0xA || szLine[strlen(szLine) - 1] == 0xD)
+ {
+ szLine[strlen(szLine) - 1] = 0;
+ }
+
+ if (strlen(szLine) == 1023)
+ {
+ throw "Hex file lines to long!\n";
+ }
+ // Ignore blank lines
+ if (szLine[0] == '\n')
+ {
+ continue;
+ }
+ // Detect format and warn if garbage lines are found
+ if (!formatDetected)
+ {
+ if (szLine[0] != ':' && szLine[0] != 'S')
+ {
+ cerr << "Ignoring garbage line!\n";
+ continue;
+ }
+ if (szLine[0] == 'S')
+ {
+ intel = false;
+ cerr << "Detected S-Record\n";
+ }
+ else
+ {
+ intel = true;
+ cerr << "Detected intel hex file\n";
+ }
+ formatDetected = true;
+ }
+ else if ((intel && szLine[0] != ':') ||
+ (!intel && szLine[0] != 'S'))
+ {
+ cerr << "Ignoring garbage line!\n";
+ continue;
+ }
+
+ if (endSeen)
+ {
+ throw "Hex line after end of file record!\n";
+ }
+
+ if (intel)
+ {
+ unsigned long dataBytes;
+ unsigned long startAddress;
+ unsigned long type;
+ if (sscanf(&szLine[1], "%2lx%4lx%2lx", &dataBytes, &startAddress, &type) != 3)
+ {
+ throw "Hex line beginning corrupt!\n";
+ }
+ // Check line length
+ if (szLine[11 + dataBytes * 2] != '\n' && szLine[11 + dataBytes * 2] != 0)
+ {
+ throw "Hex line length incorrect!\n";
+ }
+ // Check line checksum
+ unsigned char checkSum = 0;
+ unsigned long tmp;
+ for (unsigned int i = 0; i <= dataBytes + 4; ++i)
+ {
+ if (sscanf(&szLine[1 + i * 2], "%2lx", &tmp) != 1)
+ {
+ throw "Hex line data corrupt!\n";
+ }
+ checkSum += tmp;
+ }
+ if (checkSum != 0)
+ {
+ throw "Hex line checksum error!\n";
+ }
+
+ switch (type)
+ {
+ case 0:
+ // Data record
+ if (!linear)
+ {
+ // Segmented
+ unsigned long test = startAddress;
+ test += dataBytes;
+ if (test > 0xffff)
+ {
+ throw "Can't handle wrapped segments!\n";
+ }
+ }
+ if (!m_chunks.size() ||
+ m_chunks.back().m_startAddress + m_chunks.back().m_bytes.size() !=
+ addressBase + startAddress)
+ {
+ m_chunks.push_back(MemBlock());
+ m_chunks.back().m_startAddress = addressBase + startAddress;
+ }
+ {
+ unsigned char i = 0;
+ for (i = 0; i < dataBytes; ++i)
+ {
+ sscanf(&szLine[9 + i * 2], "%2lx", &tmp);
+ if (addressBase + startAddress + i > limit)
+ {
+ cerr << "Ignoring data above address space!\n";
+ cerr << "Data address: " << addressBase + startAddress + i;
+ cerr << " Limit: " << limit << "\n";
+ if (!m_chunks.back().m_bytes.size())
+ {
+ m_chunks.pop_back();
+ }
+ continue;
+ }
+ m_chunks.back().m_bytes.push_back(tmp);
+ }
+ }
+ break;
+
+ case 1:
+ // End-of-file record
+ if (dataBytes != 0)
+ {
+ cerr << "Warning: End of file record not zero length!\n";
+ }
+ if (startAddress != 0)
+ {
+ cerr << "Warning: End of file record address not zero!\n";
+ }
+ endSeen = true;
+ break;
+
+ case 2:
+ // Extended segment address record
+ if (dataBytes != 2)
+ {
+ throw "Length field must be 2 in extended segment address record!\n";
+ }
+ if (startAddress != 0)
+ {
+ throw "Address field must be zero in extended segment address record!\n";
+ }
+ sscanf(&szLine[9], "%4lx", &startAddress);
+ addressBase = startAddress << 4;
+ linear = false;
+ break;
+
+ case 3:
+ // Start segment address record
+ if (dataBytes != 4)
+ {
+ cerr << "Warning: Length field must be 4 in start segment address record!\n";
+ }
+ if (startAddress != 0)
+ {
+ cerr << "Warning: Address field must be zero in start segment address record!\n";
+ }
+ if (dataBytes == 4)
+ {
+ unsigned long ssa;
+ char ssaStr[16];
+ sscanf(&szLine[9], "%8lx", &ssa);
+ sprintf(ssaStr, "%08X\n", ssa);
+ cerr << "Segment start address (CS/IP): ";
+ cerr << ssaStr;
+ }
+ break;
+
+ case 4:
+ // Extended linear address record
+ if (dataBytes != 2)
+ {
+ throw "Length field must be 2 in extended linear address record!\n";
+ }
+ if (startAddress != 0)
+ {
+ throw "Address field must be zero in extended linear address record!\n";
+ }
+ sscanf(&szLine[9], "%4lx", &startAddress);
+ addressBase = ((unsigned long)startAddress) << 16;
+ linear = true;
+ break;
+
+ case 5:
+ // Start linear address record
+ if (dataBytes != 4)
+ {
+ cerr << "Warning: Length field must be 4 in start linear address record!\n";
+ }
+ if (startAddress != 0)
+ {
+ cerr << "Warning: Address field must be zero in start linear address record!\n";
+ }
+ if (dataBytes == 4)
+ {
+ unsigned long lsa;
+ char lsaStr[16];
+ sscanf(&szLine[9], "%8lx", &lsa);
+ sprintf(lsaStr, "%08X\n", lsa);
+ cerr << "Linear start address: ";
+ cerr << lsaStr;
+ }
+ break;
+
+ default:
+ cerr << "Waring: Unknown record found!\n";
+ }
+ }
+ else
+ {
+ // S-record
+ unsigned long count;
+ char type;
+ if (sscanf(&szLine[1], "%c%2lx", &type, &count) != 2)
+ {
+ throw "Hex line beginning corrupt!\n";
+ }
+ // Check line length
+ if (szLine[4 + count * 2] != '\n' && szLine[4 + count * 2] != 0)
+ {
+ throw "Hex line length incorrect!\n";
+ }
+ // Check line checksum
+ unsigned char checkSum = 0;
+ unsigned long tmp;
+ for (unsigned int i = 0; i < count + 1; ++i)
+ {
+ if (sscanf(&szLine[2 + i * 2], "%2lx", &tmp) != 1)
+ {
+ throw "Hex line data corrupt!\n";
+ }
+ checkSum += tmp;
+ }
+ if (checkSum != 255)
+ {
+ throw "Hex line checksum error!\n";
+ }
+
+ switch (type)
+ {
+ case '0':
+ // Header record
+ {
+ char header[256];
+ unsigned char i = 0;
+ for (i = 0; i + 3 < count; ++i)
+ {
+ sscanf(&szLine[8 + i * 2], "%2lx", &tmp);
+ header[i] = tmp;
+ }
+ header[i] = 0;
+ if (i > 0)
+ {
+ cerr << "Module name: " << header << "\n";
+ }
+ }
+ break;
+
+ case '1':
+ case '2':
+ case '3':
+ // Data record
+ {
+ dataRecords++;
+ unsigned long startAddress;
+ if (type == '1')
+ {
+ sscanf(&szLine[4], "%4lx", &startAddress);
+ }
+ else if (type == '2')
+ {
+ sscanf(&szLine[4], "%6lx", &startAddress);
+ }
+ else
+ {
+ sscanf(&szLine[4], "%8lx", &startAddress);
+ }
+
+ if (!m_chunks.size() ||
+ m_chunks.back().m_startAddress + m_chunks.back().m_bytes.size() !=
+ startAddress)
+ {
+ m_chunks.push_back(MemBlock());
+ m_chunks.back().m_startAddress = startAddress;
+ }
+ unsigned char i = 0;
+ for (i = (type - '1'); i + 3 < count; ++i)
+ {
+ sscanf(&szLine[8 + i * 2], "%2lx", &tmp);
+ if (startAddress + i > limit)
+ {
+ cerr << "Ignoring data above address space!\n";
+ cerr << "Data address: " << startAddress + i;
+ cerr << " Limit: " << limit << "\n";
+ if (!m_chunks.back().m_bytes.size())
+ {
+ m_chunks.pop_back();
+ }
+ continue;
+ }
+ m_chunks.back().m_bytes.push_back(tmp);
+ }
+ }
+ break;
+
+ case '5':
+ // Count record
+ {
+ unsigned long address;
+ sscanf(&szLine[4], "%4lx", &address);
+ if (address != dataRecords)
+ {
+ throw "Wrong number of data records!\n";
+ }
+ }
+ break;
+
+ case '7':
+ case '8':
+ case '9':
+ // Start address record
+ cerr << "Ignoring start address record!\n";
+ break;
+
+ default:
+ cerr << "Unknown record found!\n";
+ }
+ }
+ }
+ if (intel && !endSeen)
+ {
+ cerr << "No end of file record!\n";
+ }
+ if (!m_chunks.size())
+ {
+ throw "No data in file!\n";
+ }
+ vector::iterator vi;
+ m_top = 0;
+ for (vi = m_chunks.begin(); vi < m_chunks.end(); vi++)
+ {
+ m_top = max(m_top, vi->m_startAddress + vi->m_bytes.size() - 1);
+ }
+ }
+
+ // Rather inefficient this one, fix sometime
+ bool GetByte(const unsigned long address, unsigned char &chr)
+ {
+ vector::iterator vi;
+
+ for (vi = m_chunks.begin(); vi < m_chunks.end(); vi++)
+ {
+ if (vi->m_startAddress + vi->m_bytes.size() > address && vi->m_startAddress <= address)
+ {
+ break;
+ }
+ }
+ if (vi == m_chunks.end())
+ {
+ return false;
+ }
+ chr = vi->m_bytes[address - vi->m_startAddress];
+ return true;
+ }
+
+ bool BitString(const unsigned long address, const unsigned char bits, const bool lEndian, string &str)
+ {
+ bool ok = false;
+ long i;
+ unsigned char chr;
+ unsigned long data = 0;
+ unsigned long tmp;
+
+ if (lEndian)
+ {
+ for (i = 0; i < (bits + 7) / 8; ++i)
+ {
+ ok |= GetByte(address + i, chr);
+ tmp = chr;
+ data |= tmp << (8 * i);
+ }
+ }
+ else
+ {
+ for (i = 0; i < (bits + 7) / 8; ++i)
+ {
+ ok |= GetByte(address + i, chr);
+ tmp = chr;
+ data |= tmp << (8 * ((bits + 7) / 8 - i - 1));
+ }
+ }
+
+ if (!ok)
+ {
+ return false;
+ }
+
+ unsigned long mask = 1;
+
+ str = "";
+ for (i = 0; i < bits; i++)
+ {
+ if (data & mask)
+ {
+ str.insert(0,"1");
+ }
+ else
+ {
+ str.insert(0,"0");
+ }
+ mask <<= 1;
+ }
+ return true;
+ }
+
+ FILE *Handle() { return m_file; };
+ vector m_chunks;
+ unsigned long m_top;
+private:
+ FILE *m_file;
+};
+
+
+int main (int argc, char *argv[])
+{
+ cerr << "Hex to VHDL ROM converter by Daniel Wallner. Version 0244\n";
+
+ try
+ {
+ unsigned long aWidth;
+ unsigned long dWidth;
+ char endian;
+ char O = 0;
+
+ if (!(argc == 4 || argc == 5))
+ {
+ cerr << "\nUsage: hex2rom [-b] \n";
+ cerr << "\nIf the -b option is specified the file is read as a binary file\n";
+ cerr << "Hex input files must be intel hex or motorola s-record\n";
+ cerr << "\nThe format string has the format AEDOS where:\n";
+ cerr << " A = Address bits\n";
+ cerr << " E = Endianness, l or b\n";
+ cerr << " D = Data bits\n";
+ cerr << " O = ROM type: (one optional character)\n";
+ cerr << " z for tri-state output\n";
+ cerr << " a for array ROM\n";
+ cerr << " s for synchronous ROM\n";
+ cerr << " u for XST ucf\n";
+ cerr << " l for Leonardo ucf\n";
+ cerr << " S = SelectRAM usage in 1/16 parts (only used when O = u)\n";
+ cerr << "\nExample:\n";
+ cerr << " hex2rom test.hex Test_ROM 18b16z\n\n";
+ return -1;
+ }
+
+ string inFileName;
+ string outFileName;
+
+ unsigned long bytes;
+ unsigned long select = 0;
+
+ if (argc == 5)
+ {
+ if (strcmp(argv[1], "-b"))
+ {
+ throw "Error in arguments!\n";
+ }
+ }
+
+ int result;
+
+ result = sscanf(argv[argc - 1], "%lu%c%lu%c%lu", &aWidth, &endian, &dWidth, &O, &select);
+ if (result < 3)
+ {
+ throw "Error in output format argument!\n";
+ }
+
+ if (aWidth > 32 || (endian != 'l' && endian != 'b') || dWidth > 32 || (result > 3 && O != 'z' && O != 'a' && O != 's' && O != 'u' && O != 'l'))
+ {
+ throw "Error in output format argument!\n";
+ }
+ inFileName = argv[argc - 3];
+ outFileName = argv[argc - 2];
+
+ bytes = (dWidth + 7) / 8;
+
+ File inFile(inFileName.c_str(), "rb");
+
+ if (argc == 4)
+ {
+ inFile.ReadHex((1UL << aWidth) * bytes - 1);
+ }
+ else
+ {
+ inFile.ReadBin((1UL << aWidth) * bytes - 1);
+ }
+
+ string line;
+
+ unsigned long words = 1;
+ unsigned long i = inFile.m_top;
+ i /= bytes;
+
+ while (i != 0)
+ {
+ i >>= 1;
+ words <<= 1;
+ }
+
+ if (O != 'u' && O != 'l')
+ {
+ printf("-- This file was generated with hex2rom written by Daniel Wallner\n");
+ printf("\nlibrary IEEE;");
+ printf("\nuse IEEE.std_logic_1164.all;");
+ printf("\nuse IEEE.numeric_std.all;");
+ printf("\n\nentity %s is", outFileName.c_str());
+ printf("\n\tport(");
+ if (O == 'z')
+ {
+ printf("\n\t\tCE_n\t: in std_logic;", dWidth - 1);
+ printf("\n\t\tOE_n\t: in std_logic;", dWidth - 1);
+ }
+ if (O == 's')
+ {
+ printf("\n\t\tClk\t: in std_logic;", dWidth - 1);
+ }
+ printf("\n\t\tA\t: in std_logic_vector(%d downto 0);", aWidth - 1);
+ printf("\n\t\tD\t: out std_logic_vector(%d downto 0)", dWidth - 1);
+ printf("\n\t);");
+ printf("\nend %s;", outFileName.c_str());
+ printf("\n\narchitecture rtl of %s is", outFileName.c_str());
+ if (!O)
+ {
+ printf("\nbegin");
+ printf("\n\tprocess (A)");
+ printf("\n\tbegin");
+ printf("\n\t\tcase to_integer(unsigned(A)) is");
+ }
+ else if (O == 's')
+ {
+ printf("\n\tsignal A_r : std_logic_vector(%d downto 0);", aWidth - 1);
+ printf("\nbegin");
+ printf("\n\tprocess (Clk)");
+ printf("\n\tbegin");
+ printf("\n\t\tif Clk'event and Clk = '1' then");
+ printf("\n\t\t\tA_r <= A;");
+ printf("\n\t\tend if;");
+ printf("\n\tend process;");
+ printf("\n\tprocess (A_r)");
+ printf("\n\tbegin");
+ printf("\n\t\tcase to_integer(unsigned(A_r)) is");
+ }
+ else
+ {
+ printf("\n\tsubtype ROM_WORD is std_logic_vector(%d downto 0);", dWidth - 1);
+ printf("\n\ttype ROM_TABLE is array(0 to %d) of ROM_WORD;", words - 1);
+ printf("\n\tconstant ROM: ROM_TABLE := ROM_TABLE'(");
+ }
+
+ string str;
+ string strDC;
+ for (i = 0; i < dWidth; i++)
+ {
+ strDC.insert(0, "-");
+ }
+ for (i = 0; i < words; i++)
+ {
+ if (!inFile.BitString(i * bytes, dWidth, endian == 'l', str))
+ {
+ str = strDC;
+ }
+ if (!O || O == 's')
+ {
+ if (inFile.m_top / bytes >= i)
+ {
+ printf("\n\t\twhen %06d => D <= \"%s\";",i, str.c_str());
+ printf("\t-- 0x%04X", i * bytes);
+ }
+ }
+ else
+ {
+ printf("\n\t\t\"%s", str.c_str());
+ if (i != words - 1)
+ {
+ printf("\",");
+ }
+ else
+ {
+ printf("\");");
+ }
+ printf("\t-- 0x%04X", i * bytes);
+ }
+ }
+
+ if (!O || O == 's')
+ {
+ printf("\n\t\twhen others => D <= \"%s\";", strDC.c_str());
+ printf("\n\t\tend case;");
+ printf("\n\tend process;");
+ }
+ else
+ {
+ printf("\nbegin");
+ if (O == 'z')
+ {
+ printf("\n\tD <= ROM(to_integer(unsigned(A))) when CE_n = '0' and OE_n = '0' else (others => 'Z');");
+ }
+ else
+ {
+ printf("\n\tD <= ROM(to_integer(unsigned(A)));");
+ }
+ }
+ printf("\nend;\n");
+ }
+ else
+ {
+ unsigned long selectIter = 0;
+ unsigned long blockIter = 0;
+
+ if (!select)
+ {
+ blockIter = ((1UL << aWidth) + 511) / 512;
+ }
+ else if (select == 16)
+ {
+ selectIter = ((1UL << aWidth) + 15) / 16;
+ }
+ else
+ {
+ blockIter = ((1UL << aWidth) * (16 - select) / 16 + 511) / 512;
+ selectIter = ((1UL << aWidth) - blockIter * 512 + 15) / 16;
+ }
+
+ cerr << "Creating .ucf file with " << selectIter * bytes;
+ cerr << " LUTs and " << blockIter * bytes << " block RAMs\n";
+
+ unsigned long blockTotal = ((1UL << aWidth) + 511) / 512;
+
+ printf("# This file was generated with hex2rom written by Daniel Wallner\n");
+
+ for (i = 0; i < selectIter; i++)
+ {
+ unsigned long base = i * 16 * bytes;
+ unsigned long j;
+ unsigned char c;
+ unsigned long pos;
+
+ // Check that there is any actual data in segment
+ bool init = false;
+ for (pos = 0; pos < bytes * 16; pos++)
+ {
+ init = inFile.GetByte(base + pos, c);
+ if (init)
+ {
+ break;
+ }
+ }
+
+ if (init)
+ {
+ for (j = 0; j < dWidth; j++)
+ {
+ unsigned long bitMask = 1;
+ unsigned long bits = 0;
+
+ for (pos = 0; pos < 16; pos++)
+ {
+ unsigned long addr;
+
+ if (endian = 'l')
+ {
+ addr = base + bytes * pos + j / 8;
+ }
+ else
+ {
+ addr = base + bytes * pos + bytes - j / 8 - 1;
+ }
+
+ c = 0;
+ inFile.GetByte(addr, c);
+ if (c & (1 << (j % 8)))
+ {
+ bits |= bitMask;
+ }
+ bitMask <<= 1;
+ }
+
+ if (O == 'u')
+ {
+ if (selectIter == 1)
+ {
+ printf("\nINST *s%s%d INIT = %04X;", outFileName.c_str(), j, bits);
+ }
+ else
+ {
+ printf("\nINST *s%s%d%d INIT = %04X;", outFileName.c_str(), i, j, bits);
+ }
+ }
+ else
+ {
+ if (selectIter == 1)
+ {
+ printf("\nINST *sG1_%d_S%s INIT = %04X;", j, outFileName.c_str(), bits);
+ }
+ else
+ {
+ printf("\nINST *sG1_%d_sG2_%d_S%s INIT = %04X;", i, j, outFileName.c_str(), bits);
+ }
+ }
+ }
+ }
+ }
+
+ for (i = blockTotal - blockIter; i < blockTotal; i++)
+ {
+ unsigned long j;
+ for (j = 0; j < bytes; j++)
+ {
+ unsigned long k;
+ for (k = 0; k < 16; k++)
+ {
+ unsigned long base = i * 512 * bytes + k * 32 * bytes;
+ unsigned char c;
+ unsigned long pos;
+
+ // Check that there is any actual data in segment
+ bool init = false;
+ for (pos = 0; pos < 32; pos++)
+ {
+ init = inFile.GetByte(base + bytes * pos + j, c);
+ if (init)
+ {
+ break;
+ }
+ }
+
+ if (init)
+ {
+ if (O == 'u')
+ {
+ if (blockIter == 1)
+ {
+ printf("\nINST *b%s%d INIT_%02X = ", outFileName.c_str(), j, k);
+ }
+ else
+ {
+ printf("\nINST *b%s%d%d INIT_%02X = ", outFileName.c_str(), i, j, k);
+ }
+ }
+ else
+ {
+ if (blockIter == 1)
+ {
+ printf("\nINST *bG1_%d_B%s INIT_%02X = ", j, outFileName.c_str(), k);
+ }
+ else
+ {
+ printf("\nINST *bG1_%d_bG2_%d_B%s INIT_%02X = ", i, j, outFileName.c_str(), k);
+ }
+ }
+ for (pos = 0; pos < 32; pos++)
+ {
+ unsigned long addr;
+
+ if (endian = 'l')
+ {
+ addr = base + bytes * (31 - pos) + j;
+ }
+ else
+ {
+ addr = base + bytes * (31 - pos) + bytes - j - 1;
+ }
+
+ c = 0;
+ inFile.GetByte(addr, c);
+ printf("%02X", c);
+ }
+ printf(";");
+ }
+ }
+ }
+ }
+ printf("\n");
+ }
+ return 0;
+ }
+ catch (string error)
+ {
+ cerr << "Fatal: " << error;
+ }
+ catch (const char *error)
+ {
+ cerr << "Fatal: " << error;
+ }
+ return -1;
+}
Index: ppx16/trunk/syn/xilinx/run/p16c55_leo.bat
===================================================================
--- ppx16/trunk/syn/xilinx/run/p16c55_leo.bat (nonexistent)
+++ ppx16/trunk/syn/xilinx/run/p16c55_leo.bat (revision 22)
@@ -0,0 +1,10 @@
+cd ..\out
+
+hex2rom ..\..\..\sw\c55.hex ROM55 9l12s > ..\src\ROM55_Test_leo.vhd
+
+spectrum -file ..\bin\p16c55.tcl
+move exemplar.log ..\log\p16c55_leo.srp
+
+cd ..\run
+
+p16c55 p16c55_leo.edf xc2s200-pq208-5
ppx16/trunk/syn/xilinx/run/p16c55_leo.bat
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ppx16/trunk/syn/xilinx/run/p16c55.bat
===================================================================
--- ppx16/trunk/syn/xilinx/run/p16c55.bat (nonexistent)
+++ ppx16/trunk/syn/xilinx/run/p16c55.bat (revision 22)
@@ -0,0 +1,46 @@
+set name=p16c55
+rem set target=xc2v250-cs144-6
+rem set target=xcv300e-pq240-8
+set target=xc2s200-pq208-5
+
+if "%2" == "" goto default
+set target=%2
+:default
+
+cd ..\out
+
+if "%1" == "" goto xst
+
+set name=p16c55_leo
+
+copy ..\bin\%name%.pin %name%.ucf
+
+ngdbuild -p %target% %1 %name%.ngd
+
+goto builddone
+
+:xst
+
+xrom ROM55 9 12 > ..\src\ROM55_Test.vhd
+hex2rom ..\..\..\sw\c55.hex rom55 9l12u > rom55_test.ini
+copy ..\out\rom55_test.ini + ..\bin\%name%.pin %name%.ucf
+
+xst -ifn ../bin/%name%.scr -ofn ../log/%name%.srp
+ngdbuild -p %target% %name%.ngc
+
+:builddone
+
+move %name%.bld ..\log
+
+map -p %target% -cm speed -c 100 -timing -tx on -o %name%_map %name%
+move %name%_map.mrp ..\log\%name%.mrp
+
+par -ol 3 -t 1 -c 0 %name%_map -w %name%
+move %name%.par ..\log
+
+trce %name%.ncd -o ../log/%name%.twr %name%_map.pcf
+
+bitgen -w %name%
+move %name%.bgn ..\log
+
+cd ..\run
ppx16/trunk/syn/xilinx/run/p16c55.bat
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ppx16/trunk/syn/xilinx/run/p16f84_leo.bat
===================================================================
--- ppx16/trunk/syn/xilinx/run/p16f84_leo.bat (nonexistent)
+++ ppx16/trunk/syn/xilinx/run/p16f84_leo.bat (revision 22)
@@ -0,0 +1,10 @@
+cd ..\out
+
+hex2rom ..\..\..\sw\f84.hex ROM84 10l14s > ..\src\ROM84_Test_leo.vhd
+
+spectrum -file ..\bin\p16f84.tcl
+move exemplar.log ..\log\p16f84_leo.srp
+
+cd ..\run
+
+p16f84 p16f84_leo.edf xc2s200-pq208-5
ppx16/trunk/syn/xilinx/run/p16f84_leo.bat
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ppx16/trunk/syn/xilinx/run/p16f84.bat
===================================================================
--- ppx16/trunk/syn/xilinx/run/p16f84.bat (nonexistent)
+++ ppx16/trunk/syn/xilinx/run/p16f84.bat (revision 22)
@@ -0,0 +1,46 @@
+set name=p16f84
+rem set target=xc2v250-cs144-6
+rem set target=xcv300e-pq240-8
+set target=xc2s200-pq208-5
+
+if "%2" == "" goto default
+set target=%2
+:default
+
+cd ..\out
+
+if "%1" == "" goto xst
+
+set name=p16f84_leo
+
+copy ..\bin\%name%.pin %name%.ucf
+
+ngdbuild -p %target% %1 %name%.ngd
+
+goto builddone
+
+:xst
+
+xrom ROM84 10 14 > ..\src\ROM84_Test.vhd
+hex2rom ..\..\..\sw\f84.hex rom84 10b14u > rom84_test.ini
+copy ..\out\rom84_test.ini + ..\bin\%name%.pin %name%.ucf
+
+xst -ifn ../bin/%name%.scr -ofn ../log/%name%.srp
+ngdbuild -p %target% %name%.ngc
+
+:builddone
+
+move %name%.bld ..\log
+
+map -p %target% -cm speed -c 100 -timing -tx on -o %name%_map %name%
+move %name%_map.mrp ..\log\%name%.mrp
+
+par -ol 3 -t 1 -c 0 %name%_map -w %name%
+move %name%.par ..\log
+
+trce %name%.ncd -o ../log/%name%.twr %name%_map.pcf
+
+bitgen -w %name%
+move %name%.bgn ..\log
+
+cd ..\run
ppx16/trunk/syn/xilinx/run/p16f84.bat
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ppx16/trunk/syn/xilinx/bin/p16c55.tcl
===================================================================
--- ppx16/trunk/syn/xilinx/bin/p16c55.tcl (nonexistent)
+++ ppx16/trunk/syn/xilinx/bin/p16c55.tcl (revision 22)
@@ -0,0 +1,44 @@
+set process "5"
+set part "2s200pq208"
+set tristate_map "FALSE"
+set opt_auto_mode "TRUE"
+set opt_best_result "29223.458000"
+set dont_lock_lcells "auto"
+set input2output "20.000000"
+set input2register "20.000000"
+set register2output "20.000000"
+set register2register "20.000000"
+set wire_table "xis215-5_avg"
+set encoding "auto"
+set edifin_ground_port_names "GND"
+set edifin_power_port_names "VCC"
+set edif_array_range_extraction_style "%s\[%d:%d\]"
+
+set_xilinx_eqn
+
+load_library xis2
+
+read -technology xis2 {
+../../../rtl/vhdl/PPX_Pack.vhd
+../../../rtl/vhdl/PPX_ALU.vhd
+../../../rtl/vhdl/PPX_Ctrl.vhd
+../../../rtl/vhdl/PPX_PCS.vhd
+../../../rtl/vhdl/PPX16.vhd
+../../../rtl/vhdl/PPX_RAM.vhd
+../../../rtl/vhdl/PPX_Port.vhd
+../../../rtl/vhdl/PPX_TMR.vhd
+../src/ROM55_Test_leo.vhd
+../../../rtl/vhdl/P16C55.vhd
+}
+
+pre_optimize
+
+optimize -hierarchy=auto -delay -pass 1 -pass 2 -pass 3 -pass 4
+
+optimize_timing
+
+report_area
+
+report_delay
+
+write p16c55_leo.edf
Index: ppx16/trunk/syn/xilinx/bin/p16c55_leo.pin
===================================================================
--- ppx16/trunk/syn/xilinx/bin/p16c55_leo.pin (nonexistent)
+++ ppx16/trunk/syn/xilinx/bin/p16c55_leo.pin (revision 22)
@@ -0,0 +1,7 @@
+#NET "clk" TNM_NET = "clk";
+#TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50%;
+
+NET "Clk" LOC = "P77";
+NET "Reset_n" LOC = "P133";
+NET "Port_A(0)" LOC = "P96";
+NET "Port_A(1)" LOC = "P98";
Index: ppx16/trunk/syn/xilinx/bin/p16c55.pin
===================================================================
--- ppx16/trunk/syn/xilinx/bin/p16c55.pin (nonexistent)
+++ ppx16/trunk/syn/xilinx/bin/p16c55.pin (revision 22)
@@ -0,0 +1,7 @@
+#NET "clk" TNM_NET = "clk";
+#TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50%;
+
+NET "clk" LOC = "P77";
+NET "reset_n" LOC = "P133";
+NET "port_a<0>" LOC = "P96";
+NET "port_a<1>" LOC = "P98";
Index: ppx16/trunk/syn/xilinx/bin/p16f84.tcl
===================================================================
--- ppx16/trunk/syn/xilinx/bin/p16f84.tcl (nonexistent)
+++ ppx16/trunk/syn/xilinx/bin/p16f84.tcl (revision 22)
@@ -0,0 +1,44 @@
+set process "5"
+set part "2s200pq208"
+set tristate_map "FALSE"
+set opt_auto_mode "TRUE"
+set opt_best_result "29223.458000"
+set dont_lock_lcells "auto"
+set input2output "20.000000"
+set input2register "20.000000"
+set register2output "20.000000"
+set register2register "20.000000"
+set wire_table "xis215-5_avg"
+set encoding "auto"
+set edifin_ground_port_names "GND"
+set edifin_power_port_names "VCC"
+set edif_array_range_extraction_style "%s\[%d:%d\]"
+
+set_xilinx_eqn
+
+load_library xis2
+
+read -technology xis2 {
+../../../rtl/vhdl/PPX_Pack.vhd
+../../../rtl/vhdl/PPX_ALU.vhd
+../../../rtl/vhdl/PPX_Ctrl.vhd
+../../../rtl/vhdl/PPX_PCS.vhd
+../../../rtl/vhdl/PPX16.vhd
+../../../rtl/vhdl/PPX_RAM.vhd
+../../../rtl/vhdl/PPX_Port.vhd
+../../../rtl/vhdl/PPX_TMR.vhd
+../src/ROM84_Test_leo.vhd
+../../../rtl/vhdl/P16F84.vhd
+}
+
+pre_optimize
+
+optimize -hierarchy=auto -delay -pass 1 -pass 2 -pass 3 -pass 4
+
+optimize_timing
+
+report_area
+
+report_delay
+
+write p16f84_leo.edf
Index: ppx16/trunk/syn/xilinx/bin/p16f84_leo.pin
===================================================================
--- ppx16/trunk/syn/xilinx/bin/p16f84_leo.pin (nonexistent)
+++ ppx16/trunk/syn/xilinx/bin/p16f84_leo.pin (revision 22)
@@ -0,0 +1,13 @@
+NET "clk" TNM_NET = "clk";
+TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50%;
+
+NET "Clk" LOC = "P77";
+NET "Reset_n" LOC = "P133";
+NET "Port_B(0)" LOC = "P29";
+NET "Port_B(1)" LOC = "P31";
+NET "Port_B(2)" LOC = "P34";
+NET "Port_B(3)" LOC = "P36";
+NET "Port_B(4)" LOC = "P41";
+NET "Port_B(5)" LOC = "P43";
+NET "Port_B(6)" LOC = "P45";
+NET "Port_B(7)" LOC = "P47";
Index: ppx16/trunk/syn/xilinx/bin/p16f84.pin
===================================================================
--- ppx16/trunk/syn/xilinx/bin/p16f84.pin (nonexistent)
+++ ppx16/trunk/syn/xilinx/bin/p16f84.pin (revision 22)
@@ -0,0 +1,13 @@
+NET "clk" TNM_NET = "clk";
+TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50%;
+
+NET "clk" LOC = "P77";
+NET "reset_n" LOC = "P133";
+NET "port_b<0>" LOC = "P29";
+NET "port_b<1>" LOC = "P31";
+NET "port_b<2>" LOC = "P34";
+NET "port_b<3>" LOC = "P36";
+NET "port_b<4>" LOC = "P41";
+NET "port_b<5>" LOC = "P43";
+NET "port_b<6>" LOC = "P45";
+NET "port_b<7>" LOC = "P47";
Index: ppx16/trunk/syn/xilinx/bin/p16f84.prj
===================================================================
--- ppx16/trunk/syn/xilinx/bin/p16f84.prj (nonexistent)
+++ ppx16/trunk/syn/xilinx/bin/p16f84.prj (revision 22)
@@ -0,0 +1,10 @@
+../../../rtl/vhdl/PPX_Pack.vhd
+../../../rtl/vhdl/PPX_ALU.vhd
+../../../rtl/vhdl/PPX_Ctrl.vhd
+../../../rtl/vhdl/PPX_PCS.vhd
+../../../rtl/vhdl/PPX16.vhd
+../../../rtl/vhdl/PPX_RAM.vhd
+../../../rtl/vhdl/PPX_Port.vhd
+../../../rtl/vhdl/PPX_TMR.vhd
+../src/ROM84_Test.vhd
+../../../rtl/vhdl/P16F84.vhd
Index: ppx16/trunk/syn/xilinx/bin/p16c55.scr
===================================================================
--- ppx16/trunk/syn/xilinx/bin/p16c55.scr (nonexistent)
+++ ppx16/trunk/syn/xilinx/bin/p16c55.scr (revision 22)
@@ -0,0 +1,7 @@
+run
+-ifn ../bin/p16c55.prj
+-ifmt VHDL
+-ofn ../out/p16c55.ngc
+-ofmt NGC -p xc2s200-pq208-5
+-opt_mode Speed
+-opt_level 2
Index: ppx16/trunk/syn/xilinx/bin/p16c55.prj
===================================================================
--- ppx16/trunk/syn/xilinx/bin/p16c55.prj (nonexistent)
+++ ppx16/trunk/syn/xilinx/bin/p16c55.prj (revision 22)
@@ -0,0 +1,10 @@
+../../../rtl/vhdl/PPX_Pack.vhd
+../../../rtl/vhdl/PPX_ALU.vhd
+../../../rtl/vhdl/PPX_Ctrl.vhd
+../../../rtl/vhdl/PPX_PCS.vhd
+../../../rtl/vhdl/PPX16.vhd
+../../../rtl/vhdl/PPX_RAM.vhd
+../../../rtl/vhdl/PPX_Port.vhd
+../../../rtl/vhdl/PPX_TMR.vhd
+../src/ROM55_Test.vhd
+../../../rtl/vhdl/P16C55.vhd
Index: ppx16/trunk/syn/xilinx/bin/p16f84.scr
===================================================================
--- ppx16/trunk/syn/xilinx/bin/p16f84.scr (nonexistent)
+++ ppx16/trunk/syn/xilinx/bin/p16f84.scr (revision 22)
@@ -0,0 +1,7 @@
+run
+-ifn ../bin/p16f84.prj
+-ifmt VHDL
+-ofn ../out/p16f84.ngc
+-ofmt NGC -p xc2s200-pq208-5
+-opt_mode Speed
+-opt_level 2
Index: ppx16/trunk/syn/xilinx/log/.keepme
===================================================================
Index: ppx16/trunk/syn/xilinx/out/.keepme
===================================================================
Index: ppx16/trunk/syn/xilinx/src/.keepme
===================================================================
Index: ppx16/trunk/rtl/vhdl/PPX16.vhd
===================================================================
--- ppx16/trunk/rtl/vhdl/PPX16.vhd (nonexistent)
+++ ppx16/trunk/rtl/vhdl/PPX16.vhd (revision 22)
@@ -0,0 +1,343 @@
+--
+-- PIC16xx compatible microcontroller core
+--
+-- Version : 0232
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/ppx16/
+--
+-- Limitations :
+-- Registers implemented in this entity are INDF, PCL, STATUS, FSR, (PCLATH)
+-- other registers must be implemented externally including GPR
+--
+-- File history :
+--
+-- 0232 : Fixed bank decoding and FSR/PCLATH register access
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.PPX_Pack.all;
+
+entity PPX16 is
+ generic(
+ InstructionLength : integer;
+ ROMAddressWidth : integer;
+ StackAddrWidth : integer;
+ TopBoot : boolean
+ );
+ port(
+ Clk : in std_logic;
+ Reset_n : in std_logic;
+ ROM_Addr : out std_logic_vector(ROMAddressWidth - 1 downto 0);
+ ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
+ Int_Trig : in std_logic;
+ GIE : in std_logic;
+ Int_Acc : out std_logic;
+ Int_Ret : out std_logic;
+ File_Addr : out std_logic_vector(InstructionLength - 6 downto 0);
+ File_Addr_r : out std_logic_vector(InstructionLength - 6 downto 0);
+ File_Wr : out std_logic;
+ W_Wr : out std_logic;
+ Instruction : out std_logic_vector(InstructionLength - 1 downto 0);
+ Op_Bus : in std_logic_vector(7 downto 0);
+ W : out std_logic_vector(7 downto 0);
+ STATUS : out std_logic_vector(7 downto 0);
+ FSR : out std_logic_vector(7 downto 0);
+ PCLATH : out std_logic_vector(4 downto 0);
+ Res_Bus : out std_logic_vector(7 downto 0)
+ );
+end PPX16;
+
+architecture rtl of PPX16 is
+
+ -- File control
+ signal File_Addr_i : std_logic_vector(InstructionLength - 6 downto 0);
+ signal File_Addr_i_r : std_logic_vector(InstructionLength - 6 downto 0);
+ signal File_Wr_i : std_logic;
+ signal PC_CS : std_logic;
+
+ -- Registers
+ signal W_i : std_logic_vector(7 downto 0);
+ signal PCLATH_d : std_logic_vector(4 downto 0);
+ signal PCLATH_i : std_logic_vector(4 downto 0);
+ signal STATUS_i : std_logic_vector(7 downto 0);
+ signal FSR_d : std_logic_vector(7 downto 0);
+ signal FSR_i : std_logic_vector(7 downto 0);
+ signal NPC : std_logic_vector(InstructionLength - 2 downto 0);
+
+ -- Registered instruction word
+ signal Inst : std_logic_vector(InstructionLength - 1 downto 0);
+
+ -- Control signals
+ signal Res_Bus_i : std_logic_vector(7 downto 0);
+ signal Q : std_logic_vector(7 downto 0);
+ signal Op_Mux : std_logic_vector(7 downto 0);
+ signal STATUS_d_i : std_logic_vector(7 downto 0);
+ signal STATUS_d : std_logic_vector(2 downto 0);
+ signal STATUS_Wr : std_logic_vector(2 downto 0);
+ signal Z_Skip : std_logic;
+ signal B_Skip : std_logic;
+ signal Inst_Skip : std_logic;
+ signal W_Wr_i : std_logic;
+ signal Imm_Op : std_logic;
+ signal Push : std_logic;
+ signal Pop : std_logic;
+ signal Goto : std_logic;
+ signal IRet : std_logic;
+ signal A2Res : std_logic;
+ signal B2Res : std_logic;
+ signal Sleep : std_logic;
+ signal Sleep_r : std_logic;
+ signal Int : std_logic;
+ signal Int_Pending : std_logic;
+
+begin
+
+ Int_Acc <= Int;
+ W_Wr <= W_Wr_i;
+ W <= W_i;
+ STATUS <= STATUS_d_i;
+ PCLATH <= PCLATH_d;
+ FSR <= FSR_d;
+
+ -- Instruction register
+ Instruction <= Inst;
+ process (Reset_n, Clk)
+ begin
+ if Reset_n = '0' then
+ Inst <= (others => '0'); -- Force NOP at reset.
+ elsif Clk'event and Clk = '1' then
+ if Inst_Skip = '1' then
+ Inst <= (others => '0'); -- Flush (Force NOP)
+ else
+ Inst <= ROM_Data;
+ end if;
+ end if;
+ end process;
+
+ -- File address
+ File_Addr <= File_Addr_i;
+ i12 : if InstructionLength = 12 generate
+ File_Addr_i <= FSR_d(6 downto 0) when
+-- pragma translate_off
+ is_x(ROM_Data) or
+-- pragma translate_on
+ unsigned(ROM_Data(4 downto 0)) = 0 else
+ FSR_d(6 downto 5) & ROM_Data(4 downto 0);
+ end generate;
+ i14 : if InstructionLength = 14 generate
+ File_Addr_i <= STATUS_d_i(7) & FSR_d(7 downto 0) when
+-- pragma translate_off
+ is_x(ROM_Data) or
+-- pragma translate_on
+ unsigned(ROM_Data(6 downto 0)) = 0 else
+ STATUS_d_i(6 downto 5) & ROM_Data(6 downto 0);
+ end generate;
+ process (Clk)
+ begin
+ if Clk'event and Clk = '1' then
+ File_Addr_r <= File_Addr_i;
+ File_Addr_i_r <= File_Addr_i;
+ end if;
+ end process;
+
+ -- PCLATH Register
+ PCLATH_d <= Res_Bus_i(4 downto 0) when
+ to_integer(unsigned(File_Addr_i_r(6 downto 0))) = 10 and File_Wr_i = '1'
+ else PCLATH_i;
+ process (Reset_n, Clk)
+ begin
+ if Reset_n = '0' then
+ PCLATH_i <= "00000";
+ elsif Clk'event and Clk = '1' then
+ PCLATH_i <= PCLATH_d;
+ end if;
+ end process;
+
+ -- Working register
+ process (Clk)
+ begin
+ if Clk'event and Clk = '1' then
+ if W_Wr_i = '1' then
+ W_i <= Res_Bus_i;
+ end if;
+ end if;
+ end process;
+
+ -- Status register
+ process (STATUS_Wr, STATUS_d, STATUS_i, A2Res, Op_Bus, File_Addr_i_r, File_Wr_i, Res_Bus_i)
+ begin
+ STATUS_d_i <= STATUS_i;
+ if STATUS_Wr(0) = '1' then
+ STATUS_d_i(0) <= STATUS_d(0);
+ end if;
+ if STATUS_Wr(1) = '1' then
+ STATUS_d_i(1) <= STATUS_d(1);
+ end if;
+ if STATUS_Wr(2) = '1' then
+ STATUS_d_i(2) <= STATUS_d(2);
+ end if;
+ if A2Res = '1' then
+ STATUS_d_i(2) <= '0';
+ if Op_Bus = "00000000" then
+ STATUS_d_i(2) <= '1';
+ end if;
+ end if;
+ if to_integer(unsigned(File_Addr_i_r(InstructionLength - 8 downto 0))) = 3 and File_Wr_i = '1' then
+ STATUS_d_i <= Res_Bus_i;
+ end if;
+ end process;
+ process (Reset_n, Clk)
+ begin
+ if Reset_n = '0' then
+ STATUS_i <= "00011000";
+ elsif Clk'event and Clk = '1' then
+ STATUS_i <= STATUS_d_i;
+ end if;
+ end process;
+
+ -- FSR Register
+ FSR_d <= Res_Bus_i when
+ to_integer(unsigned(File_Addr_i_r(InstructionLength - 8 downto 0))) = 4 and
+ File_Wr_i = '1' else FSR_i;
+ process (Reset_n, Clk)
+ begin
+ if Reset_n = '0' then
+ FSR_i <= "11111111";
+ elsif Clk'event and Clk = '1' then
+ FSR_i <= FSR_d;
+ end if;
+ end process;
+
+ -- Program counter
+ PC_CS <= '1' when to_integer(unsigned(File_Addr_i_r(InstructionLength - 8 downto 0))) = 2 else '0';
+ ROM_Addr <= NPC(ROMAddressWidth - 1 downto 0);
+ pcs : PPX_PCS
+ generic map(
+ PC_Width => InstructionLength - 1,
+ StackAddrWidth => StackAddrWidth,
+ TopBoot => TopBoot)
+ port map(
+ Clk => Clk,
+ Reset_n => Reset_n,
+ CS => PC_CS,
+ Wr => File_Wr_i,
+ Data_In => Res_Bus_i,
+ Addr_In => Inst(InstructionLength - 4 downto 0),
+ PCLATH => PCLATH_i,
+ STATUS => STATUS_i(6 downto 5),
+ NPC => NPC,
+ Int => Int,
+ Sleep => Sleep_r,
+ Push => Push,
+ Pop => Pop,
+ Goto => Goto);
+
+ -- ALU
+ Op_Mux <= Inst(7 downto 0) when Imm_Op = '1' else W_i;
+ Res_Bus <= Res_Bus_i;
+ Res_Bus_i <= Op_Bus when A2Res = '1' else Op_Mux when B2Res = '1' else Q;
+ alu : PPX_ALU
+ generic map(InstructionLength => InstructionLength)
+ port map(
+ Clk => Clk,
+ ROM_Data => ROM_Data,
+ A => Op_Bus,
+ B => Op_Mux,
+ Q => Q,
+ Skip => Inst_Skip,
+ Carry => STATUS_i(0),
+ Z_Skip => Z_Skip,
+ STATUS_d => STATUS_d,
+ STATUS_Wr => STATUS_Wr);
+
+ -- Instruction decoder
+ File_Wr <= File_Wr_i;
+ Inst_Skip <= Z_Skip or B_Skip or Sleep_r or Int_Pending;
+ id : PPX_Ctrl
+ generic map(InstructionLength => InstructionLength)
+ port map(
+ Clk => Clk,
+ Reset_n => Reset_n,
+ ROM_Data => ROM_Data,
+ Inst => Inst,
+ Skip => Inst_Skip,
+ File_Wr => File_Wr_i,
+ W_Wr => W_Wr_i,
+ Imm_Op => Imm_Op,
+ A2Res => A2Res,
+ B2Res => B2Res,
+ Push => Push,
+ Pop => Pop,
+ Goto => Goto,
+ IRet => IRet,
+ B_Skip => B_Skip,
+ Sleep => Sleep);
+
+ -- Interrupt
+ process (Reset_n, Clk)
+ begin
+ if Reset_n = '0' then
+ Sleep_r <= '0';
+ Int <= '0';
+ Int_Pending <= '0';
+ Int_Ret <= '0';
+ elsif Clk'event and Clk = '1' then
+ if Sleep = '1' then
+ Sleep_r <= '1';
+ end if;
+ if Int_Trig = '1' then
+ Sleep_r <= '0';
+ end if;
+ Int_Pending <= '0';
+ Int <= '0';
+ if Int_Trig = '1' and GIE = '1' and Int = '0' then
+ Int_Pending <= '1';
+ end if;
+ if Int_Pending = '1' and Int = '0' and (Z_Skip or B_Skip or Sleep_r) = '0' then
+ Int <= '1';
+ end if;
+ if IRet = '1' then
+ Int_Ret <= '1';
+ else
+ Int_Ret <= '0';
+ end if;
+ end if;
+ end process;
+
+end;
Index: ppx16/trunk/rtl/vhdl/PPX_Pack.vhd
===================================================================
--- ppx16/trunk/rtl/vhdl/PPX_Pack.vhd (nonexistent)
+++ ppx16/trunk/rtl/vhdl/PPX_Pack.vhd (revision 22)
@@ -0,0 +1,195 @@
+--
+-- PIC16xx compatible microcontroller core
+--
+-- Version : 0224
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/ppx16/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package PPX_Pack is
+
+ component PPX_ALU
+ generic(
+ InstructionLength : integer
+ );
+ port (
+ Clk : in std_logic;
+ ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
+ A : in std_logic_vector(7 downto 0);
+ B : in std_logic_vector(7 downto 0);
+ Q : out std_logic_vector(7 downto 0);
+ Skip : in std_logic;
+ Carry : in std_logic;
+ Z_Skip : out std_logic;
+ STATUS_d : out std_logic_vector(2 downto 0);
+ STATUS_Wr : out std_logic_vector(2 downto 0)
+ );
+ end component;
+
+ component PPX_Ctrl
+ generic(
+ InstructionLength : integer
+ );
+ port(
+ Clk : in std_logic;
+ Reset_n : in std_logic;
+ ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
+ Inst : in std_logic_vector(InstructionLength - 1 downto 0);
+ Skip : in std_logic;
+ File_Wr : out std_logic;
+ W_Wr : out std_logic;
+ Imm_Op : out std_logic;
+ A2Res : out std_logic;
+ B2Res : out std_logic;
+ Push : out std_logic;
+ Pop : out std_logic;
+ Goto : out std_logic;
+ IRet : out std_logic;
+ B_Skip : out std_logic;
+ Sleep : out std_logic
+ );
+ end component;
+
+ component PPX_PCS
+ generic(
+ PC_Width : integer;
+ StackAddrWidth : integer;
+ TopBoot : boolean
+ );
+ port(
+ Clk : in std_logic;
+ Reset_n : in std_logic;
+ CS : in std_logic;
+ Wr : in std_logic;
+ Data_In : in std_logic_vector(7 downto 0);
+ Addr_In : in std_logic_vector(PC_Width - 3 downto 0);
+ PCLATH : in std_logic_vector(4 downto 0);
+ STATUS : in std_logic_vector(6 downto 5);
+ NPC : out std_logic_vector(PC_Width - 1 downto 0);
+ Int : in std_logic;
+ Sleep : in std_logic;
+ Push : in std_logic;
+ Pop : in std_logic;
+ Goto : in std_logic
+ );
+ end component;
+
+ component PPX16
+ generic(
+ InstructionLength : integer;
+ ROMAddressWidth : integer;
+ StackAddrWidth : integer;
+ TopBoot : boolean
+ );
+ port(
+ Clk : in std_logic;
+ Reset_n : in std_logic;
+ ROM_Addr : out std_logic_vector(ROMAddressWidth - 1 downto 0);
+ ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
+ Int_Trig : in std_logic;
+ GIE : in std_logic;
+ Int_Acc : out std_logic;
+ Int_Ret : out std_logic;
+ File_Addr : out std_logic_vector(InstructionLength - 6 downto 0);
+ File_Addr_r : out std_logic_vector(InstructionLength - 6 downto 0);
+ File_Wr : out std_logic;
+ W_Wr : out std_logic;
+ Instruction : out std_logic_vector(InstructionLength - 1 downto 0);
+ Op_Bus : in std_logic_vector(7 downto 0);
+ W : out std_logic_vector(7 downto 0);
+ STATUS : out std_logic_vector(7 downto 0);
+ FSR : out std_logic_vector(7 downto 0);
+ PCLATH : out std_logic_vector(4 downto 0);
+ Res_Bus : out std_logic_vector(7 downto 0)
+ );
+ end component;
+
+ component PPX_RAM
+ generic(
+ Bottom : integer;
+ Top : integer;
+ AddrWidth : integer
+ );
+ port(
+ Clk : in std_logic;
+ CS : in std_logic;
+ Wr : in std_logic;
+ Addr : in std_logic_vector(AddrWidth - 1 downto 0);
+ Data_In : in std_logic_vector(7 downto 0);
+ Data_Out : out std_logic_vector(7 downto 0)
+ );
+ end component;
+
+ component PPX_Port
+ port(
+ Clk : in std_logic;
+ Reset_n : in std_logic;
+ Port_Wr : in std_logic;
+ Tris_Wr : in std_logic;
+ Data_In : in std_logic_vector(7 downto 0);
+ Port_In : out std_logic_vector(7 downto 0);
+ Tris : out std_logic_vector(7 downto 0);
+ IOPort : inout std_logic_vector(7 downto 0)
+ );
+ end component;
+
+ component PPX_TMR
+ port(
+ Clk : in std_logic;
+ Reset_n : in std_logic;
+ CKI : in std_logic;
+ SE : in std_logic;
+ CS : in std_logic;
+ PS : in std_logic_vector(2 downto 0);
+ PSA : in std_logic;
+ TMR_Sel : in std_logic;
+ Wr : in std_logic;
+ Data_In : in std_logic_vector(7 downto 0);
+ Data_Out : out std_logic_vector(7 downto 0);
+ TOF : out std_logic
+ );
+ end component;
+
+end PPX_Pack;
Index: ppx16/trunk/rtl/vhdl/PPX_Ctrl.vhd
===================================================================
--- ppx16/trunk/rtl/vhdl/PPX_Ctrl.vhd (nonexistent)
+++ ppx16/trunk/rtl/vhdl/PPX_Ctrl.vhd (revision 22)
@@ -0,0 +1,188 @@
+--
+-- PIC16xx compatible microcontroller core
+--
+-- Version : 0224
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/ppx16/
+--
+-- Limitations :
+-- Registers implemented in this entity are INDF, PCL, STATUS, FSR, (PCLATH)
+-- other registers must be implemented externally including GPR
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PPX_Ctrl is
+ generic(
+ InstructionLength : integer
+ );
+ port(
+ Clk : in std_logic;
+ Reset_n : in std_logic;
+ ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
+ Inst : in std_logic_vector(InstructionLength - 1 downto 0);
+ Skip : in std_logic;
+ File_Wr : out std_logic;
+ W_Wr : out std_logic;
+ Imm_Op : out std_logic;
+ A2Res : out std_logic;
+ B2Res : out std_logic;
+ Push : out std_logic;
+ Pop : out std_logic;
+ Goto : out std_logic;
+ IRet : out std_logic;
+ B_Skip : out std_logic;
+ Sleep : out std_logic
+ );
+end PPX_Ctrl;
+
+architecture rtl of PPX_Ctrl is
+
+begin
+
+ Imm_Op <= Inst(InstructionLength - 1);
+
+ i12 : if InstructionLength = 12 generate
+ B_Skip <= '1' when Inst(11 downto 10) = "10" else '0';
+ Sleep <= '1' when ROM_Data(11 downto 0) = "000000000011" else '0';
+ W_Wr <= '1' when Inst(11 downto 8) = "1000" or
+ Inst(11 downto 10) = "11" or
+ (Inst(11 downto 10) = "00" and Inst(5) = '0' and Inst(9 downto 6) /= "0000") else '0';
+ IRet <= '0';
+ process (Reset_n, Clk)
+ begin
+ if Reset_n = '0' then
+ File_Wr <= '0';
+ Goto <= '0';
+ Push <= '0';
+ Pop <= '0';
+ A2Res <= '0';
+ B2Res <= '0';
+ elsif Clk'event and Clk = '1' then
+ File_Wr <= '0';
+ Goto <= '0';
+ Push <= '0';
+ Pop <= '0';
+ A2Res <= '0';
+ B2Res <= '0';
+ if Skip = '0' then
+ if (ROM_Data(InstructionLength - 1 downto InstructionLength - 2) = "00" and
+ ROM_Data(InstructionLength - 7) = '1') or
+ ROM_Data(InstructionLength - 1 downto InstructionLength - 3) = "010" then
+ File_Wr <= '1';
+ end if;
+ if ROM_Data(InstructionLength - 1 downto InstructionLength - 3) = "101" then
+ Goto <= '1';
+ end if;
+ if ROM_Data(11 downto 8) = "1001" then -- CALL
+ Push <= '1';
+ end if;
+ if ROM_Data(11 downto 8) = "1000" then -- RETLW
+ Pop <= '1';
+ end if;
+ if ROM_Data(11 downto 6) = "001000" then
+ -- MOVF
+ A2Res <= '1';
+ end if;
+ if ROM_Data(11 downto 8) = "1100" or -- MOVLW
+ ROM_Data(11 downto 8) = "1000" or -- RETLW
+ ROM_Data(11 downto 6) = "000000" then -- MOVWF/TRIS/OPTION and some others
+ B2Res <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+ end generate;
+
+ i14 : if InstructionLength = 14 generate
+ B_Skip <= '1' when Inst(13 downto 12) = "10" or Inst(13 downto 10) = "1101" or
+ Inst(13 downto 1) = "0000000000100" else '0';
+ Sleep <= '1' when ROM_Data(13 downto 0) = "00000001100011" else '0';
+ W_Wr <= '1' when Inst(13 downto 12) = "11" or
+ (Inst(13 downto 12) = "00" and Inst(7) = '0' and Inst(11 downto 8) /= "0000") else '0';
+ IRet <= '1' when Inst(13 downto 0) = "00000000001001" else '0'; -- RETFIE
+ process (Reset_n, Clk)
+ begin
+ if Reset_n = '0' then
+ File_Wr <= '0';
+ Goto <= '0';
+ Push <= '0';
+ Pop <= '0';
+ A2Res <= '0';
+ B2Res <= '0';
+ elsif Clk'event and Clk = '1' then
+ File_Wr <= '0';
+ Goto <= '0';
+ Push <= '0';
+ Pop <= '0';
+ A2Res <= '0';
+ B2Res <= '0';
+ if Skip = '0' then
+ if (ROM_Data(InstructionLength - 1 downto InstructionLength - 2) = "00" and
+ ROM_Data(InstructionLength - 7) = '1') or
+ ROM_Data(InstructionLength - 1 downto InstructionLength - 3) = "010" then
+ File_Wr <= '1';
+ end if;
+ if ROM_Data(InstructionLength - 1 downto InstructionLength - 3) = "101" then
+ Goto <= '1';
+ end if;
+ if ROM_Data(13 downto 11) = "100" then
+ Push <= '1'; -- CALL
+ end if;
+ if ROM_Data(13 downto 10) = "1101" or -- RETLW
+ ROM_Data(13 downto 1) = "0000000000100" then -- RETURN, RETFIE
+ Pop <= '1';
+ end if;
+ if ROM_Data(13 downto 8) = "001000" then
+ -- MOVF
+ A2Res <= '1';
+ end if;
+ if ROM_Data(13 downto 10) = "1100" or -- MOVLW
+ ROM_Data(13 downto 10) = "1101" or -- RETLW
+ ROM_Data(13 downto 8) = "000000" then -- MOVWF/TRIS/OPTION and some others
+ B2Res <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+ end generate;
+
+end;
Index: ppx16/trunk/rtl/vhdl/P16C55.vhd
===================================================================
--- ppx16/trunk/rtl/vhdl/P16C55.vhd (nonexistent)
+++ ppx16/trunk/rtl/vhdl/P16C55.vhd (revision 22)
@@ -0,0 +1,269 @@
+--
+-- PIC16C55 compatible microcontroller core
+--
+-- Version : 0222
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.PPX_Pack.all;
+
+entity P16C55 is
+ generic(
+ SyncReset : boolean := true);
+ port(
+ Clk : in std_logic;
+ Reset_n : in std_logic;
+ T0CKI : in std_logic;
+ Port_A : inout std_logic_vector(7 downto 0);
+ Port_B : inout std_logic_vector(7 downto 0);
+ Port_C : inout std_logic_vector(7 downto 0)
+ );
+end P16C55;
+
+architecture rtl of P16C55 is
+
+ constant InstructionLength : integer := 12;
+ constant ROMAddressWidth : integer := 9;
+ constant StackAddrWidth : integer := 1;
+ constant TopBoot : boolean := true;
+
+ component ROM55
+ port(
+ Clk : in std_logic;
+ A : in std_logic_vector(ROMAddressWidth - 1 downto 0);
+ D : out std_logic_vector(11 downto 0)
+ );
+ end component;
+
+ signal Reset_s_n : std_logic;
+ signal ROM_Addr : std_logic_vector(ROMAddressWidth - 1 downto 0);
+ signal ROM_Data : std_logic_vector(InstructionLength - 1 downto 0);
+ signal Instruction : std_logic_vector(InstructionLength - 1 downto 0);
+ signal File_Addr : std_logic_vector(InstructionLength - 6 downto 0);
+ signal File_Addr_r : std_logic_vector(InstructionLength - 6 downto 0);
+ signal RAM_CS : std_logic;
+ signal TMR_CS : std_logic;
+ signal File_Wr : std_logic;
+ signal W_Wr : std_logic;
+ signal Tris_A_Wr : std_logic;
+ signal Tris_B_Wr : std_logic;
+ signal Tris_C_Wr : std_logic;
+ signal Port_A_Wr : std_logic;
+ signal Port_B_Wr : std_logic;
+ signal Port_C_Wr : std_logic;
+ signal Op_Bus : std_logic_vector(7 downto 0);
+ signal Op_Mux : std_logic_vector(7 downto 0);
+ signal Res_Bus : std_logic_vector(7 downto 0);
+ signal RAM_Data : std_logic_vector(7 downto 0);
+ signal OPTION : std_logic_vector(5 downto 0);
+ signal PortA : std_logic_vector(7 downto 0);
+ signal PortB : std_logic_vector(7 downto 0);
+ signal PortC : std_logic_vector(7 downto 0);
+ signal TMR : std_logic_vector(7 downto 0);
+ signal W : std_logic_vector(7 downto 0);
+ signal STATUS : std_logic_vector(7 downto 0);
+ signal FSR : std_logic_vector(7 downto 0);
+ signal Int_Trig : std_logic;
+ signal GIE : std_logic;
+
+begin
+
+ Int_Trig <= '0';
+ GIE <= '0';
+
+ -- Synchronise reset
+ process (Reset_n, Clk)
+ variable Reset_v : std_logic;
+ begin
+ if Reset_n = '0' then
+ if SyncReset then
+ Reset_s_n <= '0';
+ Reset_v := '0';
+ end if;
+ elsif Clk'event and Clk = '1' then
+ if SyncReset then
+ Reset_s_n <= Reset_v;
+ Reset_v := '1';
+ end if;
+ end if;
+ end process;
+
+ g_reset : if not SyncReset generate
+ Reset_s_n <= Reset_n;
+ end generate;
+
+ -- Address decoder
+ TMR_CS <= '1' when to_integer(unsigned(File_Addr_r(4 downto 0))) = 1 else '0';
+ Tris_A_Wr <= '1' when Instruction(11 downto 0) = "000000000101" else '0';
+ Tris_B_Wr <= '1' when Instruction(11 downto 0) = "000000000110" else '0';
+ Tris_C_Wr <= '1' when Instruction(11 downto 0) = "000000000111" else '0';
+ Port_A_Wr <= '1' when to_integer(unsigned(File_Addr_r(4 downto 0))) = 5 and File_Wr = '1' else '0';
+ Port_B_Wr <= '1' when to_integer(unsigned(File_Addr_r(4 downto 0))) = 6 and File_Wr = '1' else '0';
+ Port_C_Wr <= '1' when to_integer(unsigned(File_Addr_r(4 downto 0))) = 7 and File_Wr = '1' else '0';
+
+ -- Register selector
+ process (Clk)
+ begin
+ if Clk'event and Clk = '1' then
+ case to_integer(unsigned(File_Addr(4 downto 0))) is
+ when 1 => Op_Bus <= TMR;
+ when 2 => Op_Bus <= ROM_Addr(7 downto 0);
+ when 3 => Op_Bus <= STATUS;
+ when 4 => Op_Bus <= FSR;
+ when 5 => Op_Bus <= PortA;
+ when 6 => Op_Bus <= PortB;
+ when 7 => Op_Bus <= PortC;
+ when others => Op_Bus <= "--------";
+ end case;
+ if File_Wr = '1' and File_Addr_r = File_Addr then
+ -- Write through
+ Op_Bus <= Res_Bus;
+ end if;
+ RAM_CS <= '0';
+ if ROM_Data(InstructionLength - 1) = '1' then
+ Op_Bus <= W;
+ -- Write through
+ if W_Wr = '1' then
+ Op_Bus <= Res_Bus;
+ end if;
+ elsif File_Addr(4 downto 3) /= "00" then
+ RAM_CS <= '1';
+ end if;
+ end if;
+ end process;
+
+ -- Register File
+ Op_Mux <= RAM_Data when RAM_CS = '1' else Op_Bus;
+ pr : PPX_RAM
+ generic map(Bottom => 8, Top => 31, AddrWidth => 5)
+ port map(
+ Clk => Clk,
+ CS => RAM_CS,
+ Wr => File_Wr,
+ Addr => File_Addr(4 downto 0),
+ Data_In => Res_Bus,
+ Data_Out => RAM_Data);
+
+ -- Option Register
+ process (Clk)
+ begin
+ if Clk'event and Clk = '1' then
+ if Instruction(11 downto 0) = "000000000010" then
+ OPTION <= Res_Bus(5 downto 0);
+ end if;
+ end if;
+ end process;
+
+ rom : ROM55 port map(
+ Clk => Clk,
+ A => ROM_Addr,
+ D => ROM_Data);
+
+ ppx : PPX16
+ generic map(
+ InstructionLength => InstructionLength,
+ ROMAddressWidth => ROMAddressWidth,
+ StackAddrWidth => StackAddrWidth,
+ TopBoot => TopBoot)
+ port map(
+ Clk => Clk,
+ Reset_n => Reset_s_n,
+ ROM_Addr => ROM_Addr,
+ ROM_Data => ROM_Data,
+ Int_Trig => Int_Trig,
+ GIE => GIE,
+ File_Addr => File_Addr,
+ File_Addr_r => File_Addr_r,
+ File_Wr => File_Wr,
+ W_Wr => W_Wr,
+ Instruction => Instruction,
+ Op_Bus => Op_Mux,
+ W => W,
+ STATUS => STATUS,
+ FSR => FSR,
+ Res_Bus => Res_Bus);
+
+ tmr0 : PPX_TMR port map(
+ Clk => Clk,
+ Reset_n => Reset_s_n,
+ CKI => T0CKI,
+ SE => OPTION(4),
+ CS => OPTION(5),
+ PS => OPTION(2 downto 0),
+ PSA => OPTION(3),
+ TMR_Sel => TMR_CS,
+ Wr => File_Wr,
+ Data_In => Res_Bus,
+ Data_Out => TMR);
+
+ aport : PPX_Port port map(
+ Clk => Clk,
+ Reset_n => Reset_s_n,
+ Port_Wr => Port_A_Wr,
+ Tris_Wr => Tris_A_Wr,
+ Data_In => Res_Bus,
+ Port_In => PortA,
+ IOPort => Port_A);
+
+ bport : PPX_Port port map(
+ Clk => Clk,
+ Reset_n => Reset_s_n,
+ Port_Wr => Port_B_Wr,
+ Tris_Wr => Tris_B_Wr,
+ Data_In => Res_Bus,
+ Port_In => PortB,
+ IOPort => Port_B);
+
+ cport : PPX_Port port map(
+ Clk => Clk,
+ Reset_n => Reset_s_n,
+ Port_Wr => Port_C_Wr,
+ Tris_Wr => Tris_C_Wr,
+ Data_In => Res_Bus,
+ Port_In => PortC,
+ IOPort => Port_C);
+
+end;
Index: ppx16/trunk/rtl/vhdl/PPX_RAM.vhd
===================================================================
--- ppx16/trunk/rtl/vhdl/PPX_RAM.vhd (nonexistent)
+++ ppx16/trunk/rtl/vhdl/PPX_RAM.vhd (revision 22)
@@ -0,0 +1,96 @@
+--
+-- PIC16xx compatible microcontroller core
+--
+-- Version : 0221
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+-- Registers implemented in this entity are INDF, PCL, STATUS, FSR, (PCLATH)
+-- other registers must be implemented externally including GPR
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity PPX_RAM is
+ generic(
+ Bottom : integer;
+ Top : integer;
+ AddrWidth : integer
+ );
+ port(
+ Clk : in std_logic;
+ CS : in std_logic;
+ Wr : in std_logic;
+ Addr : in std_logic_vector(AddrWidth - 1 downto 0);
+ Data_In : in std_logic_vector(7 downto 0);
+ Data_Out : out std_logic_vector(7 downto 0)
+ );
+end PPX_RAM;
+
+architecture rtl of PPX_RAM is
+
+ type RAM_Image is array (Top downto 0) of std_logic_vector(7 downto 0);
+ signal RAM : RAM_Image;
+ signal AddrRd : std_logic_vector(AddrWidth - 1 downto 0);
+ signal AddrWr : std_logic_vector(AddrWidth - 1 downto 0);
+
+begin
+
+ process (Clk)
+ begin
+ if Clk'event and Clk = '1' then
+ AddrRd <= Addr;
+ AddrWr <= Addr;
+ if CS = '1' and Wr = '1' then
+ RAM(to_integer(unsigned(AddrWr))) <= Data_In;
+ end if;
+ end if;
+ end process;
+
+ Data_Out <= RAM(to_integer(unsigned(AddrRd)))
+-- pragma translate_off
+ when to_integer(unsigned(AddrRd)) >= Bottom and to_integer(unsigned(AddrRd)) <= Top else "--------"
+-- pragma translate_on
+ ;
+
+end;
Index: ppx16/trunk/rtl/vhdl/P16F84.vhd
===================================================================
--- ppx16/trunk/rtl/vhdl/P16F84.vhd (nonexistent)
+++ ppx16/trunk/rtl/vhdl/P16F84.vhd (revision 22)
@@ -0,0 +1,311 @@
+--
+-- PIC16F84 compatible microcontroller core
+--
+-- Version : 0222
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+-- No port B pullup
+-- No EEPROM
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.PPX_Pack.all;
+
+entity P16F84 is
+ generic(
+ SyncReset : boolean := true);
+ port(
+ Clk : in std_logic;
+ Reset_n : in std_logic;
+ T0CKI : in std_logic;
+ INT : in std_logic;
+ Port_A : inout std_logic_vector(7 downto 0);
+ Port_B : inout std_logic_vector(7 downto 0)
+ );
+end P16F84;
+
+architecture rtl of P16F84 is
+
+ constant InstructionLength : integer := 14;
+ constant ROMAddressWidth : integer := 10;
+ constant StackAddrWidth : integer := 3;
+ constant TopBoot : boolean := false;
+
+ component ROM84
+ port(
+ Clk : in std_logic;
+ A : in std_logic_vector(9 downto 0);
+ D : out std_logic_vector(13 downto 0)
+ );
+ end component;
+
+ signal Reset_s_n : std_logic;
+ signal ROM_Addr : std_logic_vector(9 downto 0);
+ signal ROM_Data : std_logic_vector(InstructionLength - 1 downto 0);
+ signal Instruction : std_logic_vector(InstructionLength - 1 downto 0);
+ signal File_Addr : std_logic_vector(InstructionLength - 6 downto 0);
+ signal File_Addr_r : std_logic_vector(InstructionLength - 6 downto 0);
+ signal TMR_CS : std_logic;
+ signal RAM_CS : std_logic;
+ signal File_Wr : std_logic;
+ signal W_Wr : std_logic;
+ signal Port_A_Wr : std_logic;
+ signal Tris_A_Wr : std_logic;
+ signal Port_B_Wr : std_logic;
+ signal Tris_B_Wr : std_logic;
+ signal RAM_Data : std_logic_vector(7 downto 0);
+ signal Op_Bus : std_logic_vector(7 downto 0);
+ signal Op_Mux : std_logic_vector(7 downto 0);
+ signal Res_Bus : std_logic_vector(7 downto 0);
+ signal OPTION : std_logic_vector(7 downto 0);
+ signal INTCON : std_logic_vector(7 downto 0);
+ signal PortA : std_logic_vector(7 downto 0);
+ signal TrisA : std_logic_vector(7 downto 0);
+ signal PortB : std_logic_vector(7 downto 0);
+ signal TrisB : std_logic_vector(7 downto 0);
+ signal TMR : std_logic_vector(7 downto 0);
+ signal W : std_logic_vector(7 downto 0);
+ signal STATUS : std_logic_vector(7 downto 0);
+ signal FSR : std_logic_vector(7 downto 0);
+ signal PCLATH : std_logic_vector(4 downto 0);
+ signal Int_Trig : std_logic;
+ signal Int_Acc : std_logic;
+ signal Int_Ret : std_logic;
+ signal TOF : std_logic;
+ signal Old_B : std_logic_vector(7 downto 4);
+ signal Old_INT : std_logic;
+
+begin
+
+ -- Synchronise reset
+ process (Reset_n, Clk)
+ variable Reset_v : std_logic;
+ begin
+ if Reset_n = '0' then
+ if SyncReset then
+ Reset_s_n <= '0';
+ Reset_v := '0';
+ end if;
+ elsif Clk'event and Clk = '1' then
+ if SyncReset then
+ Reset_s_n <= Reset_v;
+ Reset_v := '1';
+ end if;
+ end if;
+ end process;
+
+ g_reset : if not SyncReset generate
+ Reset_s_n <= Reset_n;
+ end generate;
+
+ -- Address decoder
+ Port_A_Wr <= '1' when to_integer(unsigned(File_Addr_r(7 downto 0))) = 5 and File_Wr = '1' else '0';
+ Port_B_Wr <= '1' when to_integer(unsigned(File_Addr_r(7 downto 0))) = 6 and File_Wr = '1' else '0';
+ Tris_A_Wr <= '1' when (to_integer(unsigned(File_Addr_r(7 downto 0))) = 133 and File_Wr = '1') or
+ Instruction(13 downto 0) = "00000001100101" else '0';
+ Tris_B_Wr <= '1' when (to_integer(unsigned(File_Addr_r(7 downto 0))) = 134 and File_Wr = '1') or
+ Instruction(13 downto 0) = "00000001100110" else '0';
+ TMR_CS <= '1' when to_integer(unsigned(File_Addr_r(7 downto 0))) = 1 else '0';
+
+ -- Register selector
+ process (Clk)
+ begin
+ if Clk'event and Clk = '1' then
+ case to_integer(unsigned(File_Addr(7 downto 0))) is
+ when 1 => Op_Bus <= TMR;
+ when 129 => Op_Bus <= OPTION;
+ when 2 | 130 => Op_Bus <= ROM_Addr(7 downto 0);
+ when 3 | 131 => Op_Bus <= STATUS;
+ when 4 | 132 => Op_Bus <= FSR;
+ when 5 => Op_Bus <= PortA;
+ when 133 => Op_Bus <= TrisA;
+ when 6 => Op_Bus <= PortB;
+ when 134 => Op_Bus <= TrisB;
+ when 10 | 138 => Op_Bus(4 downto 0) <= PCLATH;
+ when 11 | 139 => Op_Bus <= INTCON;
+ when others => Op_Bus <= "--------";
+ end case;
+ if File_Wr = '1' and File_Addr_r = File_Addr then
+ -- Write through
+ Op_Bus <= Res_Bus;
+ end if;
+ RAM_CS <= '0';
+ if ROM_Data(InstructionLength - 1) = '1' then
+ Op_Bus <= W;
+ -- Write through
+ if W_Wr = '1' then
+ Op_Bus <= Res_Bus;
+ end if;
+ elsif File_Addr(6 downto 4) /= "000" or File_Addr(3 downto 2) = "11" then
+ RAM_CS <= '1';
+ end if;
+ end if;
+ end process;
+
+ -- Register File
+ Op_Mux <= RAM_Data when RAM_CS = '1' else Op_Bus;
+ pr : PPX_RAM
+ generic map(Bottom => 12, Top => 79, AddrWidth => 7)
+ port map(
+ Clk => Clk,
+ CS => RAM_CS,
+ Wr => File_Wr,
+ Addr => File_Addr(6 downto 0),
+ Data_In => Res_Bus,
+ Data_Out => RAM_Data);
+
+ -- Option Register
+ process (Clk)
+ begin
+ if Clk'event and Clk = '1' then
+ if Instruction(13 downto 0) = "00000001100010" or
+ to_integer(unsigned(File_Addr_r(7 downto 0))) = 129 then
+ OPTION <= Res_Bus;
+ end if;
+ Old_B <= Port_B(7 downto 4);
+ Old_INT <= INT;
+ end if;
+ end process;
+
+ -- Interrupt Register
+ Int_Trig <= (INTCON(0) and INTCON(3)) or
+ (INTCON(1) and INTCON(4)) or
+ (INTCON(2) and INTCON(5));
+ process (Reset_s_n, Clk)
+ begin
+ if Reset_s_n = '0' then
+ INTCON <= (others => '0');
+ elsif Clk'event and Clk = '1' then
+ if to_integer(unsigned(File_Addr_r(6 downto 0))) = 11 then
+ INTCON <= Res_Bus;
+ end if;
+ if Int_Acc = '1' then
+ INTCON(7) <= '0';
+ end if;
+ if Int_Ret = '1' then
+ INTCON(7) <= '1';
+ end if;
+ if TOF = '1' then
+ INTCON(2) <= '1';
+ end if;
+ if (OPTION(6) = '1' and INT = '1' and Old_INT = '0') or
+ (OPTION(6) = '0' and INT = '0' and Old_INT = '1') then
+ INTCON(1) <= '1';
+ end if;
+ if Old_B /= Port_B(7 downto 4) then
+ INTCON(0) <= '1';
+ end if;
+ end if;
+ end process;
+
+ rom : ROM84 port map(
+ Clk => Clk,
+ A => ROM_Addr,
+ D => ROM_Data);
+
+ ppx : PPX16
+ generic map(
+ InstructionLength => InstructionLength,
+ ROMAddressWidth => ROMAddressWidth,
+ StackAddrWidth => StackAddrWidth,
+ TopBoot => TopBoot)
+ port map(
+ Clk => Clk,
+ Reset_n => Reset_s_n,
+ ROM_Addr => ROM_Addr,
+ ROM_Data => ROM_Data,
+ Int_Trig => Int_Trig,
+ GIE => INTCON(7),
+ Int_Acc => Int_Acc,
+ Int_Ret => Int_Ret,
+ File_Addr => File_Addr,
+ File_Addr_r => File_Addr_r,
+ File_Wr => File_Wr,
+ W_Wr => W_Wr,
+ Instruction => Instruction,
+ Op_Bus => Op_Mux,
+ W => W,
+ PCLATH => PCLATH,
+ STATUS => STATUS,
+ FSR => FSR,
+ Res_Bus => Res_Bus);
+
+ tmr0 : PPX_TMR
+ port map(
+ Clk => Clk,
+ Reset_n => Reset_s_n,
+ CKI => T0CKI,
+ SE => OPTION(4),
+ CS => OPTION(5),
+ PS => OPTION(2 downto 0),
+ PSA => OPTION(3),
+ TMR_Sel => TMR_CS,
+ Wr => File_Wr,
+ Data_In => Res_Bus,
+ Data_Out => TMR,
+ TOF => TOF);
+
+ aport : PPX_Port
+ port map(
+ Clk => Clk,
+ Reset_n => Reset_s_n,
+ Port_Wr => Port_A_Wr,
+ Tris_Wr => Tris_A_Wr,
+ Data_In => Res_Bus,
+ Port_In => PortA,
+ Tris => TrisA,
+ IOPort => Port_A);
+
+ bport : PPX_Port
+ port map(
+ Clk => Clk,
+ Reset_n => Reset_s_n,
+ Port_Wr => Port_B_Wr,
+ Tris_Wr => Tris_B_Wr,
+ Data_In => Res_Bus,
+ Port_In => PortB,
+ Tris => TrisB,
+ IOPort => Port_B);
+
+end;
Index: ppx16/trunk/rtl/vhdl/PPX_ALU.vhd
===================================================================
--- ppx16/trunk/rtl/vhdl/PPX_ALU.vhd (nonexistent)
+++ ppx16/trunk/rtl/vhdl/PPX_ALU.vhd (revision 22)
@@ -0,0 +1,344 @@
+--
+-- PIC16xx compatible microcontroller core
+--
+-- Version : 0222
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity PPX_ALU is
+ generic(
+ InstructionLength : integer;
+ TriState : boolean := false
+ );
+ port (
+ Clk : in std_logic;
+ ROM_Data : in std_logic_vector(InstructionLength - 1 downto 0);
+ A : in std_logic_vector(7 downto 0);
+ B : in std_logic_vector(7 downto 0);
+ Q : out std_logic_vector(7 downto 0);
+ Skip : in std_logic;
+ Carry : in std_logic;
+ Z_Skip : out std_logic;
+ STATUS_d : out std_logic_vector(2 downto 0);
+ STATUS_Wr : out std_logic_vector(2 downto 0)
+ );
+end PPX_ALU;
+
+architecture rtl of PPX_ALU is
+
+ procedure AddSub(A : std_logic_vector(3 downto 0);
+ B : std_logic_vector(3 downto 0);
+ Sub : std_logic;
+ Carry_In : std_logic;
+ signal Res : out std_logic_vector(3 downto 0);
+ signal Carry : out std_logic) is
+ variable B_i : unsigned(4 downto 0);
+ variable Full_Carry : unsigned(4 downto 0);
+ variable Res_i : unsigned(4 downto 0);
+ begin
+ if Sub = '1' then
+ B_i := "0" & not unsigned(B);
+ else
+ B_i := "0" & unsigned(B);
+ end if;
+ if (Sub = '1' and Carry_In = '1') or (Sub = '0' and Carry_In = '1') then
+ Full_Carry := "00001";
+ else
+ Full_Carry := "00000";
+ end if;
+ Res_i := unsigned("0" & A) + B_i + Full_Carry;
+ Carry <= Res_i(4);
+ Res <= std_logic_vector(Res_i(3 downto 0));
+ end;
+
+ signal Do_IDTEST : std_logic;
+ signal Do_ADD : std_logic;
+ signal Do_SUB : std_logic;
+ signal Do_DEC : std_logic;
+ signal Do_INC : std_logic;
+ signal Do_AND : std_logic;
+ signal Do_OR : std_logic;
+ signal Do_XOR : std_logic;
+ signal Do_COM : std_logic;
+ signal Do_RRF : std_logic;
+ signal Do_RLF : std_logic;
+ signal Do_SWAP : std_logic;
+ signal Do_BITCLR : std_logic;
+ signal Do_BITSET : std_logic;
+ signal Do_BITTESTCLR : std_logic;
+ signal Do_BITTESTSET : std_logic;
+ signal Do_CLR : std_logic;
+
+ signal Inst_Top : std_logic_vector(11 downto 0);
+
+ signal Bit_Pattern : std_logic_vector(7 downto 0);
+ signal Bit_Test : std_logic_vector(7 downto 0);
+
+ signal Q_ID : std_logic_vector(7 downto 0);
+ signal Q_L : std_logic_vector(7 downto 0);
+ signal Q_C : std_logic_vector(7 downto 0);
+ signal Q_RR : std_logic_vector(7 downto 0);
+ signal Q_RL : std_logic_vector(7 downto 0);
+ signal Q_S : std_logic_vector(7 downto 0);
+ signal Q_BC : std_logic_vector(7 downto 0);
+ signal Q_BS : std_logic_vector(7 downto 0);
+
+ signal DC_i : std_logic;
+ signal AddSubRes : std_logic_vector(8 downto 0);
+
+ signal Q_i : std_logic_vector(7 downto 0);
+
+begin
+
+ Q <= Q_i;
+
+ Inst_Top <= ROM_Data(InstructionLength - 1 downto InstructionLength - 12);
+
+ gNoTri : if not TriState generate
+ Q_i <= Q_ID when Do_INC = '1' or Do_DEC = '1' else
+ AddSubRes(7 downto 0) when Do_ADD = '1' OR Do_SUB = '1' else
+ Q_L when Do_AND = '1' or Do_OR = '1' or Do_XOR = '1' else
+ Q_C when Do_COM = '1' else
+ Q_RR when Do_RRF = '1' else
+ Q_RL when Do_RLF = '1' else
+ Q_S when Do_SWAP = '1' else
+ Q_BC when Do_BITCLR = '1' else
+ Q_BS when Do_BITSET = '1' else
+ "00000000";
+ end generate;
+
+ gTri : if TriState generate
+ Q_i <= Q_ID when Do_INC = '1' or Do_DEC = '1' else "ZZZZZZZZ";
+ Q_i <= AddSubRes(7 downto 0) when Do_ADD = '1' OR Do_SUB = '1' else "ZZZZZZZZ";
+ Q_i <= Q_L when Do_AND = '1' or Do_OR = '1' or Do_XOR = '1' else "ZZZZZZZZ";
+ Q_i <= Q_C when Do_COM = '1' else "ZZZZZZZZ";
+ Q_i <= Q_RR when Do_RRF = '1' else "ZZZZZZZZ";
+ Q_i <= Q_RL when Do_RLF = '1' else "ZZZZZZZZ";
+ Q_i <= Q_S when Do_SWAP = '1' else "ZZZZZZZZ";
+ Q_i <= Q_BC when Do_BITCLR = '1' else "ZZZZZZZZ";
+ Q_i <= Q_BS when Do_BITSET = '1' else "ZZZZZZZZ";
+ Q_i <= "00000000" when Do_CLR = '1' else "ZZZZZZZZ";
+ end generate;
+
+ process (Clk)
+ begin
+ if Clk'event and Clk = '1' then
+ Do_ADD <= '0';
+ Do_SUB <= '0';
+ Do_AND <= '0';
+ Do_OR <= '0';
+ Do_XOR <= '0';
+ Do_IDTEST <= '0';
+ Do_INC <= '0';
+ Do_DEC <= '0';
+ Do_COM <= '0';
+ Do_RRF <= '0';
+ Do_RLF <= '0';
+ Do_SWAP <= '0';
+ Do_BITCLR <= '0';
+ Do_BITSET <= '0';
+ Do_BITTESTCLR <= '0';
+ Do_BITTESTSET <= '0';
+ Do_CLR <= '0';
+ if Skip = '0' then
+ if InstructionLength = 12 then
+ if Inst_Top(11 downto 6) = "000111" then
+ -- ADDWF
+ Do_ADD <= '1';
+ end if;
+ if Inst_Top(11 downto 6) = "000010" then
+ -- SUBWF
+ Do_SUB <= '1';
+ end if;
+ if Inst_Top(11 downto 6) = "000101" or Inst_Top(11 downto 8) = "1110" then
+ -- ANDWF, ANDLW
+ Do_AND <= '1';
+ end if;
+ if Inst_Top(11 downto 6) = "000100" or Inst_Top(11 downto 8) = "1101" then
+ -- IORWF, IORLW
+ Do_OR <= '1';
+ end if;
+ if Inst_Top(11 downto 6) = "000110" or Inst_Top(11 downto 8) = "1111" then
+ -- XORWF, XORLW
+ Do_XOR <= '1';
+ end if;
+ else
+ if Inst_Top(11 downto 6) = "000111" or Inst_Top(11 downto 7) = "11111" then
+ -- ADDWF, ADDLW
+ Do_ADD <= '1';
+ end if;
+ if Inst_Top(11 downto 6) = "000010" or Inst_Top(11 downto 7) = "11110" then
+ -- SUBWF, SUBLW
+ Do_SUB <= '1';
+ end if;
+ if Inst_Top(11 downto 6) = "000101" or Inst_Top(11 downto 6) = "111001" then
+ -- ANDWF, ANDLW
+ Do_AND <= '1';
+ end if;
+ if Inst_Top(11 downto 6) = "000100" or Inst_Top(11 downto 6) = "111000" then
+ -- IORWF, IORLW
+ Do_OR <= '1';
+ end if;
+ if Inst_Top(11 downto 6) = "000110" or Inst_Top(11 downto 6) = "111010" then
+ -- XORWF, XORLW
+ Do_XOR <= '1';
+ end if;
+ end if;
+
+ if Inst_Top(11 downto 9) = "001" and Inst_Top(7 downto 6) = "11" then
+ -- INC/DEC w conditional skip
+ Do_IDTEST <= '1';
+ end if;
+ if Inst_Top(11 downto 6) = "001010" or Inst_Top(11 downto 6) = "001111" then
+ -- INCF, INCFSZ
+ Do_INC <= '1';
+ end if;
+ if Inst_Top(11 downto 6) = "000011" or Inst_Top(11 downto 6) = "001011" then
+ -- DECF, DECFSZ,
+ Do_DEC <= '1';
+ end if;
+ if Inst_Top(11 downto 6) = "001001" then
+ -- COMF
+ Do_COM <= '1';
+ end if;
+ if Inst_Top(11 downto 6) = "001100" then
+ -- RRF
+ Do_RRF <= '1';
+ end if;
+ if Inst_Top(11 downto 6) = "001101" then
+ -- RLF
+ Do_RLF <= '1';
+ end if;
+ if Inst_Top(11 downto 6) = "001110" then
+ -- SWAPF
+ Do_SWAP <= '1';
+ end if;
+ if Inst_Top(11 downto 8) = "0100" then
+ -- BCF
+ Do_BITCLR <= '1';
+ end if;
+ if Inst_Top(11 downto 8) = "0101" then
+ -- BSF
+ Do_BITSET <= '1';
+ end if;
+ if Inst_Top(11 downto 8) = "0110" then
+ -- BTFSC
+ Do_BITTESTCLR <= '1';
+ end if;
+ if Inst_Top(11 downto 8) = "0111" then
+ -- BTFSS
+ Do_BITTESTSET <= '1';
+ end if;
+ if Inst_Top(11 downto 6) = "000001" then
+ -- CLRF, CLRW
+ Do_CLR <= '1';
+ end if;
+ end if;
+
+ case Inst_Top(7 downto 5) is
+ when "000" =>
+ Bit_Pattern <= "00000001";
+ when "001" =>
+ Bit_Pattern <= "00000010";
+ when "010" =>
+ Bit_Pattern <= "00000100";
+ when "011" =>
+ Bit_Pattern <= "00001000";
+ when "100" =>
+ Bit_Pattern <= "00010000";
+ when "101" =>
+ Bit_Pattern <= "00100000";
+ when "110" =>
+ Bit_Pattern <= "01000000";
+ when others =>
+ Bit_Pattern <= "10000000";
+ end case;
+ end if;
+ end process;
+
+ Q_ID <= std_logic_vector(unsigned(A) + 1) when Do_INC = '1' else
+ std_logic_vector(unsigned(A) - 1);
+
+ AddSub(A(3 downto 0), B(3 downto 0), Do_SUB, Do_SUB, AddSubRes(3 downto 0), DC_i);
+ AddSub(A(7 downto 4), B(7 downto 4), Do_SUB, DC_i, AddSubRes(7 downto 4), AddSubRes(8));
+
+ Q_L <= (A and B) when Do_AND = '1' else
+ (A or B) when Do_OR = '1' else
+ (A xor B);
+ Q_C <= (not A);
+
+ Q_RR <= Carry & A(7 downto 1);
+ Q_RL <= A(6 downto 0) & Carry;
+
+ Q_S <= A(3 downto 0) & A(7 downto 4);
+
+ Q_BC <= ((not Bit_Pattern) and A);
+ Q_BS <= (Bit_Pattern or A);
+
+ Bit_Test <= Bit_Pattern and A;
+
+ Z_Skip <= '1' when (Do_IDTEST = '1' and Q_ID = "00000000") or
+ (Bit_Test /= "00000000" and Do_BITTESTSET = '1') or
+ (Bit_Test = "00000000" and Do_BITTESTCLR = '1') else '0';
+
+ STATUS_d(2) <= '1' when Q_i(7 downto 0) = "00000000" else '0';
+ STATUS_d(1) <= DC_i;
+ STATUS_d(0) <= A(0) when Do_RRF = '1' else
+ A(7) when Do_RLF = '1' else
+ AddSubRes(8);
+
+ -- Z
+ STATUS_Wr(2) <= '1' when Do_SUB = '1' or Do_ADD = '1' or
+ ((Do_DEC = '1' or Do_INC = '1') and Do_IDTEST = '0') or
+ Do_AND = '1' or Do_OR = '1' or Do_XOR = '1' or
+ Do_CLR = '1' or Do_COM = '1' else '0';
+ -- DC
+ STATUS_Wr(1) <= '1' when Do_SUB = '1' or Do_ADD = '1' else '0';
+ -- C
+ STATUS_Wr(0) <= '1' when Do_SUB = '1' or Do_ADD = '1' or Do_RRF = '1' or Do_RLF = '1' else '0';
+
+end;
Index: ppx16/trunk/rtl/vhdl/PPX_TMR.vhd
===================================================================
--- ppx16/trunk/rtl/vhdl/PPX_TMR.vhd (nonexistent)
+++ ppx16/trunk/rtl/vhdl/PPX_TMR.vhd (revision 22)
@@ -0,0 +1,157 @@
+--
+-- PIC16xx compatible microcontroller core
+--
+-- Version : 0221
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+-- Registers implemented in this entity are INDF, PCL, STATUS, FSR, (PCLATH)
+-- other registers must be implemented externally including GPR
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity PPX_TMR is
+ port(
+ Clk : in std_logic;
+ Reset_n : in std_logic;
+ CKI : in std_logic;
+ SE : in std_logic;
+ CS : in std_logic;
+ PS : in std_logic_vector(2 downto 0);
+ PSA : in std_logic;
+ TMR_Sel : in std_logic;
+ Wr : in std_logic;
+ Data_In : in std_logic_vector(7 downto 0);
+ Data_Out : out std_logic_vector(7 downto 0);
+ TOF : out std_logic
+ );
+end PPX_TMR;
+
+architecture rtl of PPX_TMR is
+
+ signal TMR : std_logic_vector(7 downto 0);
+
+ signal Tick : std_logic;
+
+begin
+
+ Data_Out <= TMR;
+
+ -- Registers and counter
+ process (Reset_n, Clk)
+ begin
+ if Reset_n = '0' then
+ TMR <= "00000000";
+ TOF <= '0';
+ elsif Clk'event and Clk = '1' then
+ TOF <= '0';
+ if Tick = '1' then
+ TMR <= std_logic_vector(unsigned(TMR) + 1);
+ if TMR = "11111111" then
+ TOF <= '1';
+ end if;
+ end if;
+ if TMR_Sel = '1' and Wr = '1' then
+ TMR <= Data_In;
+ TOF <= '0';
+ end if;
+ end if;
+ end process;
+
+ -- Tick generator
+ process (Clk, Reset_n)
+ variable Prescaler : unsigned(7 downto 0);
+ variable CKI_r : std_logic_vector(1 downto 0);
+ variable P_r : std_logic_vector(1 downto 0);
+ variable Tick0 : std_logic;
+ begin
+ if Reset_n = '0' then
+ Prescaler := (others => '0');
+ Tick <= '0';
+ Tick0 := '0';
+ CKI_r := "00";
+ P_r := "00";
+ elsif Clk'event and Clk='1' then
+ P_r(1) := P_r(0);
+ case PS is
+ when "000" => P_r(0) := Prescaler(0);
+ when "001" => P_r(0) := Prescaler(1);
+ when "010" => P_r(0) := Prescaler(2);
+ when "011" => P_r(0) := Prescaler(3);
+ when "100" => P_r(0) := Prescaler(4);
+ when "101" => P_r(0) := Prescaler(5);
+ when "110" => P_r(0) := Prescaler(6);
+ when others => P_r(0) := Prescaler(7);
+ end case;
+
+ Tick0 := '0';
+ if SE = '0' then -- low-to-high
+ if CKI_r(1) = '1' and CKI_r(0) = '0' then
+ Tick0 := '1';
+ end if;
+ else
+ if CKI_r(1) = '0' and CKI_r(0) = '1' then
+ Tick0 := '1';
+ end if;
+ end if;
+ if CS = '0' then
+ Tick0 := '1';
+ end if;
+ CKI_r(1) := CKI_r(0);
+ CKI_r(0) := CKI;
+
+ Tick <= '0';
+ if PSA = '1' then
+ Tick <= Tick0;
+ elsif P_r(1) = '1' and P_r(0) = '0' then
+ Tick <= '1';
+ end if;
+
+ if Tick0 = '1' then
+ Prescaler := Prescaler + 1;
+ end if;
+ end if;
+ end process;
+
+end;
Index: ppx16/trunk/rtl/vhdl/PPX_Port.vhd
===================================================================
--- ppx16/trunk/rtl/vhdl/PPX_Port.vhd (nonexistent)
+++ ppx16/trunk/rtl/vhdl/PPX_Port.vhd (revision 22)
@@ -0,0 +1,108 @@
+--
+-- PIC16xx compatible microcontroller core
+--
+-- Version : 0221
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+-- Registers implemented in this entity are INDF, PCL, STATUS, FSR, (PCLATH)
+-- other registers must be implemented externally including GPR
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PPX_Port is
+ port(
+ Clk : in std_logic;
+ Reset_n : in std_logic;
+ Port_Wr : in std_logic;
+ Tris_Wr : in std_logic;
+ Data_In : in std_logic_vector(7 downto 0);
+ Port_In : out std_logic_vector(7 downto 0);
+ Tris : out std_logic_vector(7 downto 0);
+ IOPort : inout std_logic_vector(7 downto 0)
+ );
+end PPX_Port;
+
+architecture rtl of PPX_Port is
+
+ signal Tris_i : std_logic_vector(7 downto 0);
+ signal Port_Output : std_logic_vector(7 downto 0);
+ signal Port_Input : std_logic_vector(7 downto 0);
+
+begin
+
+ Port_In <= Port_Input;
+ Tris <= Tris_i;
+
+ IOPort(0) <= Port_Output(0) when Tris_i(0) = '0' else 'Z';
+ IOPort(1) <= Port_Output(1) when Tris_i(1) = '0' else 'Z';
+ IOPort(2) <= Port_Output(2) when Tris_i(2) = '0' else 'Z';
+ IOPort(3) <= Port_Output(3) when Tris_i(3) = '0' else 'Z';
+ IOPort(4) <= Port_Output(4) when Tris_i(4) = '0' else 'Z';
+ IOPort(5) <= Port_Output(5) when Tris_i(5) = '0' else 'Z';
+ IOPort(6) <= Port_Output(6) when Tris_i(6) = '0' else 'Z';
+ IOPort(7) <= Port_Output(7) when Tris_i(7) = '0' else 'Z';
+
+ process (Clk)
+ begin
+ if Clk'event and Clk = '1' then
+ Port_Input <= IOPort; -- Synchronise input
+ if Port_Wr = '1' then
+ Port_Output <= Data_In;
+ Port_Input <= Data_In;
+ end if;
+ end if;
+ end process;
+
+ process (Reset_n, Clk)
+ begin
+ if Reset_n = '0' then
+ Tris_i <= "11111111";
+ elsif Clk'event and Clk = '1' then
+ if Tris_Wr = '1' then
+ Tris_i <= Data_In;
+ end if;
+ end if;
+ end process;
+
+end;
Index: ppx16/trunk/rtl/vhdl/PPX_PCS.vhd
===================================================================
--- ppx16/trunk/rtl/vhdl/PPX_PCS.vhd (nonexistent)
+++ ppx16/trunk/rtl/vhdl/PPX_PCS.vhd (revision 22)
@@ -0,0 +1,171 @@
+--
+-- PIC16xx compatible microcontroller core
+--
+-- Version : 0222
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity PPX_PCS is
+ generic(
+ PC_Width : integer;
+ StackAddrWidth : integer;
+ TopBoot : boolean
+ );
+ port(
+ Clk : in std_logic;
+ Reset_n : in std_logic;
+ CS : in std_logic;
+ Wr : in std_logic;
+ Data_In : in std_logic_vector(7 downto 0);
+ Addr_In : in std_logic_vector(PC_Width - 3 downto 0);
+ PCLATH : in std_logic_vector(4 downto 0);
+ STATUS : in std_logic_vector(6 downto 5);
+ NPC : out std_logic_vector(PC_Width - 1 downto 0);
+ Int : in std_logic;
+ Sleep : in std_logic;
+ Push : in std_logic;
+ Pop : in std_logic;
+ Goto : in std_logic
+ );
+end PPX_PCS;
+
+architecture rtl of PPX_PCS is
+
+ signal PC_i : unsigned(PC_Width - 1 downto 0);
+ signal NPC_i : unsigned(PC_Width - 1 downto 0);
+
+ type Stack_Image is array (2 ** StackAddrWidth - 1 downto 0) of unsigned(PC_Width - 1 downto 0);
+ signal Stack : Stack_Image;
+
+ signal StackPtr : unsigned(StackAddrWidth -1 downto 0);
+
+begin
+
+ NPC <= std_logic_vector(NPC_i);
+
+ process (Clk)
+ begin
+ if Clk'event and Clk = '1' then
+ if Push = '1' then
+ Stack(to_integer(StackPtr)) <= PC_i;
+ end if;
+ if Int = '1' then
+ Stack(to_integer(StackPtr)) <= PC_i - 1;
+ end if;
+ end if;
+ end process;
+
+ process (PC_i, Sleep, CS, Wr, PCLATH, STATUS, Push, Pop, Goto, Data_In, Addr_In, Int, Stack, StackPtr)
+ begin
+ NPC_i <= PC_i;
+ if Sleep = '0' then
+ NPC_i <= PC_i + 1;
+ end if;
+ if CS = '1' and Wr = '1' then
+ if PC_Width = 13 then
+ NPC_i(7 downto 0) <= unsigned(Data_In);
+ NPC_i(PC_Width - 1 downto PC_Width - 5) <= unsigned(PCLATH);
+ end if;
+ if PC_Width = 11 then
+ NPC_i(7 downto 0) <= unsigned(Data_In);
+ NPC_i(8) <= '0';
+ NPC_i(10 downto 9) <= unsigned(STATUS);
+ end if;
+ end if;
+ if Push = '1' then
+ if PC_Width = 13 then
+ NPC_i(10 downto 0) <= unsigned(Addr_In);
+ NPC_i(PC_Width - 1 downto PC_Width - 2) <= unsigned(PCLATH(4 downto 3));
+ end if;
+ if PC_Width = 11 then
+ NPC_i(7 downto 0) <= unsigned(Addr_In(7 downto 0));
+ NPC_i(8) <= '0';
+ NPC_i(10 downto 9) <= unsigned(STATUS);
+ end if;
+ end if;
+ if Pop = '1' then
+ NPC_i <= Stack(to_integer(StackPtr - 1));
+ end if;
+ if Goto = '1' then
+ if PC_Width = 13 then
+ NPC_i(10 downto 0) <= unsigned(Addr_In);
+ NPC_i(PC_Width - 1 downto PC_Width - 2) <= unsigned(PCLATH(4 downto 3));
+ end if;
+ if PC_Width = 11 then
+ NPC_i(8 downto 0) <= unsigned(Addr_In);
+ NPC_i(10 downto 9) <= unsigned(STATUS);
+ end if;
+ end if;
+ if Int = '1' then
+ NPC_i <= (others => '0');
+ NPC_i(2) <= '1';
+ end if;
+ end process;
+
+ process (Reset_n, Clk)
+ begin
+ if Reset_n = '0' then
+ PC_i <= (others => '1');
+ if TopBoot then
+ PC_i(0) <= '0';
+ end if;
+ StackPtr <= (others => '0');
+ elsif Clk'event and Clk = '1' then
+ PC_i <= NPC_i;
+ if Push = '1' then
+ StackPtr <= StackPtr + 1;
+ end if;
+ if Pop = '1' then
+ StackPtr <= StackPtr - 1;
+ end if;
+ if Int = '1' then
+ StackPtr <= StackPtr + 1;
+ end if;
+ end if;
+ end process;
+
+end;
Index: ppx16/trunk/sim/rtl_sim/bin/compile.do
===================================================================
--- ppx16/trunk/sim/rtl_sim/bin/compile.do (nonexistent)
+++ ppx16/trunk/sim/rtl_sim/bin/compile.do (revision 22)
@@ -0,0 +1,17 @@
+vcom ../../../rtl/vhdl/PPX_Pack.vhd
+vcom ../../../rtl/vhdl/PPX_ALU.vhd
+vcom ../../../rtl/vhdl/PPX_Ctrl.vhd
+vcom ../../../rtl/vhdl/PPX_PCS.vhd
+vcom ../../../rtl/vhdl/PPX16.vhd
+vcom ../../../rtl/vhdl/PPX_RAM.vhd
+vcom ../../../rtl/vhdl/PPX_Port.vhd
+vcom ../../../rtl/vhdl/PPX_TMR.vhd
+vcom ../../../syn/xilinx/src/ROM55_Test_leo.vhd
+vcom ../../../syn/xilinx/src/ROM84_Test_leo.vhd
+vcom ../../../rtl/vhdl/P16C55.vhd
+vcom ../../../rtl/vhdl/P16F84.vhd
+vcom ../../../bench/vhdl/StimLog.vhd -93
+vcom ../../../bench/vhdl/AsyncLog.vhd -93
+vcom ../../../bench/vhdl/AsyncStim.vhd -93
+vcom ../../../bench/vhdl/TestBench55.vhd -93
+vcom ../../../bench/vhdl/TestBench84.vhd -93
Index: ppx16/trunk/bench/vhdl/TestBench55.vhd
===================================================================
--- ppx16/trunk/bench/vhdl/TestBench55.vhd (nonexistent)
+++ ppx16/trunk/bench/vhdl/TestBench55.vhd (revision 22)
@@ -0,0 +1,30 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use work.StimLog.all;
+
+entity TestBench55 is
+end TestBench55;
+
+architecture behaviour of TestBench55 is
+
+ signal Clk : std_logic := '0';
+ signal Reset_n : std_logic := '0';
+ signal T0CKI : std_logic := '0';
+ signal Port_A : std_logic_vector(7 downto 0);
+ signal Port_B : std_logic_vector(7 downto 0);
+ signal Port_C : std_logic_vector(7 downto 0);
+
+begin
+
+ p1 : entity work.P16C55 port map (Clk, Reset_n, T0CKI, Port_A, Port_B, Port_C);
+
+ as : AsyncStim generic map(FileName => "../../../rtl/vhdl/PPX16.vhd", InterCharDelay => 300 us, Baud => 48000, Bits => 8)
+ port map(Port_A(1));
+
+ al : AsyncLog generic map(FileName => "RX_Log.txt", Baud => 48000, Bits => 8)
+ port map(Port_A(0));
+
+ Clk <= not Clk after 50 ns;
+ Reset_n <= '1' after 200 ns;
+
+end;
Index: ppx16/trunk/bench/vhdl/TestBench84.vhd
===================================================================
--- ppx16/trunk/bench/vhdl/TestBench84.vhd (nonexistent)
+++ ppx16/trunk/bench/vhdl/TestBench84.vhd (revision 22)
@@ -0,0 +1,24 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity TestBench84 is
+end TestBench84;
+
+architecture behaviour of TestBench84 is
+
+ signal Clk : std_logic := '0';
+ signal Reset_n : std_logic := '0';
+ signal T0CKI : std_logic := '0';
+ signal INT : std_logic := '0';
+ signal Port_A : std_logic_vector(7 downto 0);
+ signal Port_B : std_logic_vector(7 downto 0);
+
+begin
+
+ p1 : entity work.P16F84 port map (Clk, Reset_n, T0CKI, INT, Port_A, Port_B);
+
+ Clk <= not Clk after 50 ns;
+ Reset_n <= '1' after 200 ns;
+ INT <= not INT after 20 us;
+
+end;
Index: ppx16/trunk/bench/vhdl/AsyncLog.vhd
===================================================================
--- ppx16/trunk/bench/vhdl/AsyncLog.vhd (nonexistent)
+++ ppx16/trunk/bench/vhdl/AsyncLog.vhd (revision 22)
@@ -0,0 +1,124 @@
+--
+-- Asynchronous serial input with binary file log
+--
+-- Version : 0146
+--
+-- Copyright (c) 2001 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity AsyncLog is
+ generic(
+ FileName : string;
+ Baud : integer;
+ Bits : integer := 8; -- Data bits
+ Parity : boolean := false; -- Enable Parity
+ P_Odd_Even_n : boolean := false -- false => Even Parity, true => Odd Parity
+ );
+ port(
+ RXD : in std_logic
+ );
+end AsyncLog;
+
+architecture behaviour of AsyncLog is
+
+ function to_char(
+ constant Byte : std_logic_vector(7 downto 0)
+ ) return character is
+ begin
+ return character'val(to_integer(unsigned(Byte)));
+ end function;
+
+ signal Baud16 : std_logic := '0';
+
+ -- Receive signals
+ signal Bit_Phase : unsigned(3 downto 0) := "0000";
+ signal RX_ShiftReg : std_logic_vector(Bits - 1 downto 0) := (others => '0');
+ signal RX_Bit_Cnt : integer := 0;
+ signal ParTmp : boolean;
+
+begin
+
+ Baud16 <= not Baud16 after 1000000000 ns / 32 / Baud;
+
+ process (Baud16)
+ type ChFile is file of character;
+ file OutFile : ChFile open write_mode is FileName;
+ begin
+ if Baud16'event and Baud16 = '1' then
+ if RX_Bit_Cnt = 0 and (RXD = '1' or Bit_Phase = "0111") then
+ Bit_Phase <= "0000";
+ else
+ Bit_Phase <= Bit_Phase + 1;
+ end if;
+ if RX_Bit_Cnt = 0 then
+ if Bit_Phase = "0111" then
+ RX_Bit_Cnt <= RX_Bit_Cnt + 1;
+ end if;
+ ParTmp <= false;
+ elsif Bit_Phase = "1111" then
+ RX_Bit_Cnt <= RX_Bit_Cnt + 1;
+ if (RX_Bit_Cnt = Bits + 1 and not Parity) or
+ (RX_Bit_Cnt = Bits + 2 and Parity) then -- Stop bit
+ RX_Bit_Cnt <= 0;
+ assert RXD = '1'
+ report "Framing error"
+ severity error;
+ write(OutFile, to_char(RX_ShiftReg(7 downto 0)));
+ elsif RX_Bit_Cnt = Bits + 1 and Parity then -- Parity bit
+ assert ParTmp xor (RXD = '1') = P_Odd_Even_n
+ report "Parity error"
+ severity error;
+ else
+ ParTmp <= ParTmp xor (RXD = '1');
+ RX_ShiftReg(Bits - 2 downto 0) <= RX_ShiftReg(Bits - 1 downto 1);
+ RX_ShiftReg(Bits - 1) <= RXD;
+ end if;
+ end if;
+ end if;
+ end process;
+
+end;
+
Index: ppx16/trunk/bench/vhdl/AsyncStim.vhd
===================================================================
--- ppx16/trunk/bench/vhdl/AsyncStim.vhd (nonexistent)
+++ ppx16/trunk/bench/vhdl/AsyncStim.vhd (revision 22)
@@ -0,0 +1,115 @@
+--
+-- Asynchronous serial generator with input from binary file
+--
+-- Version : 0146
+--
+-- Copyright (c) 2001 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity AsyncStim is
+ generic(
+ FileName : string;
+ Baud : integer;
+ InterCharDelay : time := 0 ns;
+ Bits : integer := 8; -- Data bits
+ Parity : boolean := false; -- Enable Parity
+ P_Odd_Even_n : boolean := false -- false => Even Parity, true => Odd Parity
+ );
+ port(
+ TXD : out std_logic
+ );
+end AsyncStim;
+
+architecture behaviour of AsyncStim is
+
+ signal TX_ShiftReg : std_logic_vector(Bits - 1 downto 0);
+ signal TX_Bit_Cnt : integer range 0 to 15 := 0;
+ signal ParTmp : boolean;
+
+begin
+
+ process
+ type ChFile is file of character;
+ file InFile : ChFile open read_mode is FileName;
+ variable Inited : boolean := false;
+ variable CharTmp : character;
+ variable IntTmp : integer;
+ begin
+ if not Inited then
+ Inited := true;
+ TXD <= '1';
+ end if;
+ wait for 1000000000 ns / Baud;
+ TX_Bit_Cnt <= TX_Bit_Cnt + 1;
+ case TX_Bit_Cnt is
+ when 0 =>
+ TXD <= '1';
+ wait for InterCharDelay;
+ when 1 => -- Start bit
+ read(InFile, CharTmp);
+ IntTmp := character'pos(CharTmp);
+ TX_ShiftReg(Bits - 1 downto 0) <= std_logic_vector(to_unsigned(IntTmp, Bits));
+ TXD <= '0';
+ ParTmp <= P_Odd_Even_n;
+ when others =>
+ TXD <= TX_ShiftReg(0);
+ ParTmp <= ParTmp xor (TX_ShiftReg(0) = '1');
+ TX_ShiftReg(Bits - 2 downto 0) <= TX_ShiftReg(Bits - 1 downto 1);
+ if (TX_Bit_Cnt = Bits + 1 and not Parity) or
+ (TX_Bit_Cnt = Bits + 2 and Parity) then -- Stop bit
+ TX_Bit_Cnt <= 0;
+ end if;
+ if Parity and TX_Bit_Cnt = Bits + 2 then
+ if ParTmp then
+ TXD <= '1';
+ else
+ TXD <= '0';
+ end if;
+ end if;
+ end case;
+ end process;
+
+end;
Index: ppx16/trunk/bench/vhdl/StimLog.vhd
===================================================================
--- ppx16/trunk/bench/vhdl/StimLog.vhd (nonexistent)
+++ ppx16/trunk/bench/vhdl/StimLog.vhd (revision 22)
@@ -0,0 +1,142 @@
+--
+-- File I/O test-bench utilities
+--
+-- Version : 0146
+--
+-- Copyright (c) 2001 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+-- http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package StimLog is
+
+ component AsyncStim
+ generic(
+ FileName : string;
+ Baud : integer;
+ InterCharDelay : time := 0 ns;
+ Bits : integer := 8; -- Data bits
+ Parity : boolean := false; -- Enable Parity
+ P_Odd_Even_n : boolean := false -- false => Even Parity, true => Odd Parity
+ );
+ port(
+ TXD : out std_logic
+ );
+ end component;
+
+ component AsyncLog
+ generic(
+ FileName : string;
+ Baud : integer;
+ Bits : integer := 8; -- Data bits
+ Parity : boolean := false; -- Enable Parity
+ P_Odd_Even_n : boolean := false -- false => Even Parity, true => Odd Parity
+ );
+ port(
+ RXD : in std_logic
+ );
+ end component;
+
+ component BinaryStim
+ generic(
+ FileName : string;
+ Bytes : integer := 1; -- Number of bytes per word
+ LittleEndian : boolean := true -- Byte order
+ );
+ port(
+ Rd : in std_logic;
+ Data : out std_logic_vector(Bytes * 8 - 1 downto 0)
+ );
+ end component;
+
+ component BinaryLog
+ generic(
+ FileName : string;
+ Bytes : integer := 1; -- Number of bytes per word
+ LittleEndian : boolean := true -- Byte order
+ );
+ port(
+ Clk : in std_logic;
+ En : in std_logic;
+ Data : in std_logic_vector(Bytes * 8 - 1 downto 0)
+ );
+ end component;
+
+ component I2SStim is
+ generic(
+ FileName : string;
+ Bytes : integer := 2; -- Number of bytes per word (1 to 4)
+ LittleEndian : boolean := true -- Byte order
+ );
+ port(
+ BClk : in std_logic;
+ FSync : in std_logic;
+ SData : out std_logic
+ );
+ end component;
+
+ component I2SLog is
+ generic(
+ FileName : string;
+ Bytes : integer := 2; -- Number of bytes per word
+ LittleEndian : boolean := true -- Byte order
+ );
+ port(
+ BClk : in std_logic;
+ FSync : in std_logic;
+ SData : in std_logic
+ );
+ end component;
+
+ component IntegerLog is
+ generic(
+ FileName : string
+ );
+ port(
+ Clk : in std_logic;
+ En : in std_logic;
+ Data : in integer
+ );
+ end component;
+
+end;
Index: ppx16/trunk
===================================================================
--- ppx16/trunk (nonexistent)
+++ ppx16/trunk (revision 22)
ppx16/trunk
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: ppx16/web_uploads
===================================================================
--- ppx16/web_uploads (nonexistent)
+++ ppx16/web_uploads (revision 22)
ppx16/web_uploads
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: ppx16/branches
===================================================================
--- ppx16/branches (nonexistent)
+++ ppx16/branches (revision 22)
ppx16/branches
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: ppx16/tags
===================================================================
--- ppx16/tags (nonexistent)
+++ ppx16/tags (revision 22)
ppx16/tags
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##