URL
https://opencores.org/ocsvn/dmt_tx/dmt_tx/trunk
Subversion Repositories dmt_tx
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/tags/import/bench/vhdl/tb_dmt_mod.vhd
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/tags/import/rtl/vhdl/dmt_mod.vhd
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/tags/import/doc/src/dmt_tx_part1_modem_spec.sxw
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Index: tags/import/doc/dmt_tx_part1_modem_spec.pdf
===================================================================
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Index: tags/import/doc/dmt_tx_part1_modem_spec.pdf
===================================================================
--- tags/import/doc/dmt_tx_part1_modem_spec.pdf (revision 22)
+++ tags/import/doc/dmt_tx_part1_modem_spec.pdf (nonexistent)
tags/import/doc/dmt_tx_part1_modem_spec.pdf
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Index: trunk/const_encoder/Makefile
===================================================================
--- trunk/const_encoder/Makefile (revision 22)
+++ trunk/const_encoder/Makefile (nonexistent)
@@ -1,45 +0,0 @@
-CC = iverilog
-SIM = vvp
-
-CFLAGS =-Wall -Irtl/
-
-vpath %.v rtl tb
-vpath %.vh rtl
-
-FIFO = fifo.v \
- generic_dpram.v
-CONST_ENC = $(FIFO) \
- const_enc.v
-
-
-
-.PHONY: all sim doc clean
-
-all: sim
-
-
-sim: fifo const_enc
-
-
-const_enc: const_enc.vvp
- @echo -e "\n--> Simulating $@"
- $(SIM) $^
-
-const_enc.vvp: tb_const_enc.v const_map_data.v $(CONST_ENC)
- $(CC) $(CFLAGS) $^ -s tb_const_encoder -o $@
-
-fifo: fifo.vvp
- @echo -e "\n--> Simulating $@"
- $(SIM) $^
-
-fifo.vvp: tb_fifo.v $(FIFO)
- @echo -e "\n--> Compiling $@"
- $(CC) $(CFLAGS) $^ -s tb_fifo -o $@
-
-doc:
- $(MAKE) -C doc/
-
-
-clean:
- rm -f *.vvp
- $(MAKE) -C doc/ cleantex
Index: trunk/const_encoder/rtl/defs.vh
===================================================================
--- trunk/const_encoder/rtl/defs.vh (revision 22)
+++ trunk/const_encoder/rtl/defs.vh (nonexistent)
@@ -1,6 +0,0 @@
-
-
-`define VENDOR_FPGA
-
-
-
Index: trunk/const_encoder/rtl/parameters.vh
===================================================================
--- trunk/const_encoder/rtl/parameters.vh (revision 22)
+++ trunk/const_encoder/rtl/parameters.vh (nonexistent)
@@ -1,25 +0,0 @@
-
-//
-// parameter
-//
-parameter DW = 8;
-parameter AW = 4;
-parameter CONFAW = 10;
-parameter CONFDW = 8;
-parameter CNUMW = 4; // Width of the carrier number output
-parameter CONSTW = 9;
-
-parameter SHIFTW = 23; // Width of the shift registers
-parameter MAXBITNUM = 15; // Maximum bit number per carrier
-
-parameter USED_C_REG_W = 8; // Used carrier register width
-parameter F_BITS_W = 8;
-parameter REG_MEM_LEN = 256;
-
-//
-// register addresses
-//
-parameter BIT_LOAD_ST_ADR = 12'h000;
-parameter C_NUM_ST_ADR = 12'h100;
-parameter USED_C_ADR = 12'h200;
-parameter F_BITS_ADR = 12'h201;
Index: trunk/const_encoder/rtl/const_enc.v
===================================================================
--- trunk/const_encoder/rtl/const_enc.v (revision 22)
+++ trunk/const_encoder/rtl/const_enc.v (nonexistent)
@@ -1,302 +0,0 @@
-/* *****************************************************************
- *
- * This file is part of the
- *
- * Tone Order and Constellation Encoder Core.
- *
- * Description:
- *
- * The conste_enc module implements the tone ordering and
- * constellation encoding as described in ITU G.992.1
- *
- *********************************************************************
- * Copyright (C) 2007 Guenter Dannoritzer
- *
- * This source is free software; you can redistribute it
- * and/or modify it under the terms of the
- * GNU General Public License
- * as published by the Free Software Foundation;
- * either version 3 of the License,
- * or (at your option) any later version.
- *
- * This source is distributed in the hope
- * that it will be useful, but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the
- * GNU General Public License along with this source.
- * If not, see .
- *
- * *****************************************************************/
-
-module const_encoder(
- clk,
- reset,
- fast_ready_o,
- we_fast_data_i,
- fast_data_i,
- inter_ready_o,
- we_inter_data_i,
- inter_data_i,
- addr_i,
- we_conf_i,
- conf_data_i,
- xy_ready_o,
- carrier_num_o,
- x_o,
- y_o);
-
-
-`include "parameters.vh"
-
-//
-// parameter
-//
-
-input clk;
-input reset;
-output fast_ready_o;
-input we_fast_data_i;
-input [DW-1:0] fast_data_i;
-output inter_ready_o;
-input we_inter_data_i;
-input [DW-1:0] inter_data_i;
-input [CONFAW-1:0] addr_i;
-input we_conf_i;
-input [CONFDW-1:0] conf_data_i;
-output xy_ready_o;
-output [CNUMW-1:0] carrier_num_o;
-output [CONSTW-1:0] x_o; reg signed [CONSTW-1:0] x_o;
-output [CONSTW-1:0] y_o; reg signed [CONSTW-1:0] y_o;
-
-
-
-//
-// local wire/regs
-//
-wire [DW-1:0] fast_data_o;
-wire [DW-1:0] inter_data_o;
-
-reg [SHIFTW-1:0] fast_shift_reg;
-reg [SHIFTW-1:0] inter_shift_reg;
-reg [MAXBITNUM-1:0] cin;
-reg [CONFDW-1:0] bit_load;
-
-reg [4:0] msb;
-reg [1:0] msb_x;
-reg [1:0] msb_y;
-
-reg [CONFDW-1:0] BitLoading [0:REG_MEM_LEN-1];
-reg [CONFDW-1:0] CarrierNumber [0:REG_MEM_LEN-1];
-reg [USED_C_REG_W-1:0] UsedCarrier;
-reg [F_BITS_W-1:0] FastBits;
-
-//
-// intantiate the fast path and interleaved path FIFOs
-//
-fifo #(.AWIDTH(AW), .DWIDTH(DW))
- fifo_fast ( .clk(clk),
- .reset(reset),
- .empty_o(fast_empty_o),
- .full_o(fast_full_o),
- .one_available_o(fast_one_available_o),
- .two_available_o(fast_two_available_o),
- .we_i(we_fast_i),
- .data_i(fast_data_i),
- .re_i(re_fast_i),
- .data_o(fast_data_o)
- );
-
-fifo #(.AWIDTH(AW), .DWIDTH(DW))
- fifo_inter ( .clk(clk),
- .reset(reset),
- .empty_o(inter_empty_o),
- .full_o(inter_full_o),
- .one_available_o(inter_one_available_o),
- .two_available_o(inter_two_available_o),
- .we_i(we_inter_i),
- .data_i(inter_data_i),
- .re_i(re_inter_i),
- .data_o(inter_data_o)
- );
-
-
-//
-// configuration register access
-//
-always @(posedge clk or posedge reset) begin
-
- if(reset) begin
- UsedCarrier <= 0;
- FastBits <= 0;
-
- end
- else begin
- if(we_conf_i) begin
- if(addr_i >= 0 && addr_i < C_NUM_ST_ADR) begin
- BitLoading[addr_i] <= conf_data_i;
- end
- else if(addr_i >= C_NUM_ST_ADR && addr_i < USED_C_ADR) begin
- CarrierNumber[addr_i - C_NUM_ST_ADR] <= conf_data_i;
- end
- else if(addr_i == USED_C_ADR) begin
- UsedCarrier <= conf_data_i;
- end
- else if(addr_i == F_BITS_ADR) begin
- FastBits <= conf_data_i;
- end
- end
- end
-
-end
-
-
-//
-// constellation mapping
-//
-always @(posedge reset or posedge clk) begin
-
- if(reset) begin
- x_o <= 9'b0;
- y_o <= 9'b0;
- end
- else begin
- case (bit_load)
- 4'b0010: begin // #2
- x_o <= {cin[1], cin[1], cin[1], cin[1], cin[1], cin[1], cin[1], cin[1], 1'b1};
- y_o <= {cin[0], cin[0], cin[0], cin[0], cin[0], cin[0], cin[0], cin[0], 1'b1};
- end
-
- 4'b0011: begin // #3
- case (cin[2:0])
- 3'b000: begin x_o <= 9'b000000001; y_o <= 9'b000000001; end
- 3'b001: begin x_o <= 9'b000000001; y_o <= 9'b111111111; end
- 3'b010: begin x_o <= 9'b111111111; y_o <= 9'b000000001; end
- 3'b011: begin x_o <= 9'b111111111; y_o <= 9'b111111111; end
-
- 3'b100: begin x_o <= 9'b111111101; y_o <= 9'b000000001; end
- 3'b101: begin x_o <= 9'b000000001; y_o <= 9'b000000011; end
- 3'b110: begin x_o <= 9'b111111111; y_o <= 9'b111111101; end
- 3'b111: begin x_o <= 9'b000000011; y_o <= 9'b111111111; end
- endcase
- end
-
- 4'b0100: begin // #4
- x_o <= {cin[3], cin[3], cin[3], cin[3], cin[3], cin[3], cin[3], cin[1], 1'b1};
- y_o <= {cin[2], cin[2], cin[2], cin[2], cin[2], cin[2], cin[2], cin[0], 1'b1};
- end
-
- 4'b0101: begin // #5
- map_msb(cin[4:0], msb_x, msb_y);
- x_o <= {msb_x[1], msb_x[1], msb_x[1], msb_x[1], msb_x[1], msb_x[1], msb_x[0], cin[1], 1'b1};
- y_o <= {msb_y[1], msb_y[1], msb_y[1], msb_y[1], msb_y[1], msb_y[1], msb_y[0], cin[0], 1'b1};
- end
-
- 4'b0110: begin // #6
- x_o <= {cin[4], cin[4], cin[4], cin[4], cin[4], cin[4], cin[2], cin[0], 1'b1};
- y_o <= {cin[5], cin[5], cin[5], cin[5], cin[5], cin[5], cin[3], cin[1], 1'b1};
- end
-
- 4'b0111: begin // #7
- map_msb(cin[6:2], msb_x, msb_y);
- x_o <= {msb_x[1], msb_x[1], msb_x[1], msb_x[1], msb_x[1], msb_x[0], cin[2], cin[0], 1'b1};
- y_o <= {msb_y[1], msb_y[1], msb_y[1], msb_y[1], msb_y[1], msb_y[0], cin[3], cin[1], 1'b1};
- end
- 4'b1000: begin // #8
- x_o <= {cin[6], cin[6], cin[6], cin[6], cin[6], cin[4], cin[2], cin[0], 1'b1};
- y_o <= {cin[7], cin[7], cin[7], cin[7], cin[7], cin[5], cin[3], cin[1], 1'b1};
- end
-
- 4'b1001: begin // #9
- map_msb(cin[7:3], msb_x, msb_y);
- x_o <= {msb_x[1], msb_x[1], msb_x[1], msb_x[1], msb_x[0], cin[4], cin[2], cin[0], 1'b1};
- y_o <= {msb_y[1], msb_y[1], msb_y[1], msb_y[1], msb_y[0], cin[5], cin[3], cin[1], 1'b1};
- end
- 4'b1010: begin // #10
- x_o <= {cin[8], cin[8], cin[8], cin[8], cin[6], cin[4], cin[2], cin[0], 1'b1};
- y_o <= {cin[9], cin[9], cin[9], cin[9], cin[7], cin[5], cin[3], cin[1], 1'b1};
- end
-
- 4'b1011: begin // #11
- map_msb(cin[8:4], msb_x, msb_y);
- x_o <= {msb_x[1], msb_x[1], msb_x[1], msb_x[0], cin[6], cin[4], cin[2], cin[0], 1'b1};
- y_o <= {msb_y[1], msb_y[1], msb_y[1], msb_y[0], cin[7], cin[5], cin[3], cin[1], 1'b1};
- end
- 4'b1100: begin // #12
- x_o <= {cin[10], cin[10], cin[10], cin[8], cin[6], cin[4], cin[2], cin[0], 1'b1};
- y_o <= {cin[11], cin[11], cin[11], cin[9], cin[7], cin[5], cin[3], cin[1], 1'b1};
- end
-
- 4'b1101: begin // #13
- map_msb(cin[9:5], msb_x, msb_y);
- x_o <= {msb_x[1], msb_x[1], msb_x[0], cin[8], cin[6], cin[4], cin[2], cin[0], 1'b1};
- y_o <= {msb_y[1], msb_y[1], msb_y[0], cin[9], cin[7], cin[5], cin[3], cin[1], 1'b1};
- end
- 4'b1110: begin // #14
- x_o <= {cin[12], cin[12], cin[10], cin[8], cin[6], cin[4], cin[2], cin[0], 1'b1};
- y_o <= {cin[13], cin[13], cin[11], cin[9], cin[7], cin[5], cin[3], cin[1], 1'b1};
- end
-
- 4'b1111: begin // #15 TODO
- map_msb(cin[10:6], msb_x, msb_y);
- x_o <= {msb_x[1], msb_x[0], cin[10], cin[8], cin[6], cin[4], cin[2], cin[0], 1'b1};
- y_o <= {msb_y[1], msb_y[0], cin[11], cin[9], cin[7], cin[5], cin[3], cin[1], 1'b1};
- end
-
- endcase
- end
-end
-
-//
-// determine the top two bits of X and Y based on table 7-12 in G.992.1
-//
-task map_msb(input [4:0] t_msb, output [1:0] t_msb_x, output [1:0] t_msb_y );
- begin
- case (t_msb)
- 5'b00000: begin t_msb_x <= 2'b00; t_msb_y <= 2'b00; end
- 5'b00001: begin t_msb_x <= 2'b00; t_msb_y <= 2'b00; end
- 5'b00010: begin t_msb_x <= 2'b00; t_msb_y <= 2'b00; end
- 5'b00011: begin t_msb_x <= 2'b00; t_msb_y <= 2'b00; end
-
- 5'b00100: begin t_msb_x <= 2'b00; t_msb_y <= 2'b11; end
- 5'b00101: begin t_msb_x <= 2'b00; t_msb_y <= 2'b11; end
- 5'b00110: begin t_msb_x <= 2'b00; t_msb_y <= 2'b11; end
- 5'b00111: begin t_msb_x <= 2'b00; t_msb_y <= 2'b11; end
-
- 5'b01000: begin t_msb_x <= 2'b11; t_msb_y <= 2'b00; end
- 5'b01001: begin t_msb_x <= 2'b11; t_msb_y <= 2'b00; end
- 5'b01010: begin t_msb_x <= 2'b11; t_msb_y <= 2'b00; end
- 5'b01011: begin t_msb_x <= 2'b11; t_msb_y <= 2'b00; end
-
- 5'b01100: begin t_msb_x <= 2'b11; t_msb_y <= 2'b11; end
- 5'b01101: begin t_msb_x <= 2'b11; t_msb_y <= 2'b11; end
- 5'b01110: begin t_msb_x <= 2'b11; t_msb_y <= 2'b11; end
- 5'b01111: begin t_msb_x <= 2'b11; t_msb_y <= 2'b11; end
-
- 5'b10000: begin t_msb_x <= 2'b01; t_msb_y <= 2'b00; end
- 5'b10001: begin t_msb_x <= 2'b01; t_msb_y <= 2'b00; end
- 5'b10010: begin t_msb_x <= 2'b10; t_msb_y <= 2'b00; end
- 5'b10011: begin t_msb_x <= 2'b10; t_msb_y <= 2'b00; end
-
- 5'b10100: begin t_msb_x <= 2'b00; t_msb_y <= 2'b01; end
- 5'b10101: begin t_msb_x <= 2'b00; t_msb_y <= 2'b10; end
- 5'b10110: begin t_msb_x <= 2'b00; t_msb_y <= 2'b01; end
- 5'b10111: begin t_msb_x <= 2'b00; t_msb_y <= 2'b10; end
-
- 5'b11000: begin t_msb_x <= 2'b11; t_msb_y <= 2'b01; end
- 5'b11001: begin t_msb_x <= 2'b11; t_msb_y <= 2'b10; end
- 5'b11010: begin t_msb_x <= 2'b11; t_msb_y <= 2'b01; end
- 5'b11011: begin t_msb_x <= 2'b11; t_msb_y <= 2'b10; end
-
- 5'b11100: begin t_msb_x <= 2'b01; t_msb_y <= 2'b11; end
- 5'b11101: begin t_msb_x <= 2'b01; t_msb_y <= 2'b11; end
- 5'b11110: begin t_msb_x <= 2'b10; t_msb_y <= 2'b11; end
- 5'b11111: begin t_msb_x <= 2'b10; t_msb_y <= 2'b11; end
-
- endcase
-end
-endtask
-
-endmodule
Index: trunk/const_encoder/rtl/generic_dpram.v
===================================================================
--- trunk/const_encoder/rtl/generic_dpram.v (revision 22)
+++ trunk/const_encoder/rtl/generic_dpram.v (nonexistent)
@@ -1,507 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Generic Dual-Port Synchronous RAM ////
-//// ////
-//// This file is part of memory library available from ////
-//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
-//// ////
-//// Description ////
-//// This block is a wrapper with common dual-port ////
-//// synchronous memory interface for different ////
-//// types of ASIC and FPGA RAMs. Beside universal memory ////
-//// interface it also provides behavioral model of generic ////
-//// dual-port synchronous RAM. ////
-//// It also contains a fully synthesizeable model for FPGAs. ////
-//// It should be used in all OPENCORES designs that want to be ////
-//// portable accross different target technologies and ////
-//// independent of target memory. ////
-//// ////
-//// Supported ASIC RAMs are: ////
-//// - Artisan Dual-Port Sync RAM ////
-//// - Avant! Two-Port Sync RAM (*) ////
-//// - Virage 2-port Sync RAM ////
-//// ////
-//// Supported FPGA RAMs are: ////
-//// - Generic FPGA (VENDOR_FPGA) ////
-//// Tested RAMs: Altera, Xilinx ////
-//// Synthesis tools: LeonardoSpectrum, Synplicity ////
-//// - Xilinx (VENDOR_XILINX) ////
-//// - Altera (VENDOR_ALTERA) ////
-//// ////
-//// To Do: ////
-//// - fix Avant! ////
-//// - add additional RAMs (VS etc) ////
-//// ////
-//// Author(s): ////
-//// - Richard Herveille, richard@asics.ws ////
-//// - Damjan Lampret, lampret@opencores.org ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.4 2002/09/28 08:18:52 rherveille
-// Changed synthesizeable FPGA memory implementation.
-// Fixed some issues with Xilinx BlockRAM
-//
-// Revision 1.3 2001/11/09 00:34:18 samg
-// minor changes: unified with all common rams
-//
-// Revision 1.2 2001/11/08 19:11:31 samg
-// added valid checks to behvioral model
-//
-// Revision 1.1.1.1 2001/09/14 09:57:10 rherveille
-// Major cleanup.
-// Files are now compliant to Altera & Xilinx memories.
-// Memories are now compatible, i.e. drop-in replacements.
-// Added synthesizeable generic FPGA description.
-// Created "generic_memories" cvs entry.
-//
-// Revision 1.1.1.2 2001/08/21 13:09:27 damjan
-// *** empty log message ***
-//
-// Revision 1.1 2001/08/20 18:23:20 damjan
-// Initial revision
-//
-// Revision 1.1 2001/08/09 13:39:33 lampret
-// Major clean-up.
-//
-// Revision 1.2 2001/07/30 05:38:02 lampret
-// Adding empty directories required by HDL coding guidelines
-//
-//
-
-//`include "timescale.v"
-//
-`include "defs.vh"
-
-//`define VENDOR_FPGA
-//`define VENDOR_XILINX
-//`define VENDOR_ALTERA
-
-module generic_dpram(
- // Generic synchronous dual-port RAM interface
- rclk, rrst, rce, oe, raddr, do,
- wclk, wrst, wce, we, waddr, di
-);
-
- //
- // Default address and data buses width
- //
- parameter aw = 5; // number of bits in address-bus
- parameter dw = 16; // number of bits in data-bus
-
- //
- // Generic synchronous double-port RAM interface
- //
- // read port
- input rclk; // read clock, rising edge trigger
- input rrst; // read port reset, active high
- input rce; // read port chip enable, active high
- input oe; // output enable, active high
- input [aw-1:0] raddr; // read address
- output [dw-1:0] do; // data output
-
- // write port
- input wclk; // write clock, rising edge trigger
- input wrst; // write port reset, active high
- input wce; // write port chip enable, active high
- input we; // write enable, active high
- input [aw-1:0] waddr; // write address
- input [dw-1:0] di; // data input
-
- //
- // Module body
- //
-
-`ifdef VENDOR_FPGA
- //
- // Instantiation synthesizeable FPGA memory
- //
- // This code has been tested using LeonardoSpectrum and Synplicity.
- // The code correctly instantiates Altera EABs and Xilinx BlockRAMs.
- //
- reg [dw-1:0] mem [(1< .
- *
- * *****************************************************************/
-module fifo(
- clk,
- reset,
- empty_o,
- full_o,
- one_available_o,
- two_available_o,
- we_i,
- data_i,
- re_i,
- data_o);
-
-parameter DWIDTH = 8;
-parameter AWIDTH = 4;
-
-input clk;
-input reset;
-output empty_o;
-output full_o;
-output one_available_o;
-output two_available_o;
-input we_i;
-input [DWIDTH-1:0] data_i;
-input re_i;
-output [DWIDTH-1:0] data_o;
-
-
-
-
-//
-// local reg/wires
-//
-reg [AWIDTH-1:0] read_ptr;
-reg [AWIDTH-1:0] write_ptr;
-reg [AWIDTH:0] fill_ctr;
-
-wire dp_we_i;
-wire dp_re_i;
-
-//
-// instantiate the dual port ram
-//
-generic_dpram #(.aw(AWIDTH),
- .dw(DWIDTH)
- )
- dpram ( .rclk(clk),
- .rrst(reset),
- .rce(ce),
- .oe(dp_re_i),
- .raddr(read_ptr),
- .do(data_o),
-
- .wclk(clk),
- .wrst(reset),
- .wce(ce),
- .we(dp_we_i),
- .waddr(write_ptr),
- .di(data_i));
-
-
-//
-// control logic
-//
-assign ce = 1'b1;
-
-assign one_available_o = (fill_ctr > 1'b0) ? 1'b1 : 1'b0;
-assign two_available_o = (fill_ctr > 1'b1) ? 1'b1 : 1'b0;
-assign empty_o = |fill_ctr ? 1'b0 : 1'b1;
-assign full_o = fill_ctr[AWIDTH] ? 1'b1 : 1'b0;
-
-// make sure a write only happens to dp_ram when not full
-assign dp_we_i = ~full_o ? we_i : 1'b0;
-// make sure a read only happens to the dp_ram when not empty
-assign dp_re_i = ~empty_o ? re_i : 1'b0;
-
-//
-// fill counter
-//
-always @(posedge clk or posedge reset) begin
- if(reset) begin
- fill_ctr <= 0;
- end
- else begin
-
- if(dp_we_i & ~ dp_re_i) begin
- fill_ctr <= fill_ctr + 1;
- end
- else if(dp_re_i & ~ dp_we_i) begin
- fill_ctr <= fill_ctr - 1;
- end
- end
-end
-
-//
-// read pointer
-//
-always @(posedge clk or posedge reset) begin
- if(reset) begin
- read_ptr <= 0;
- end
- else begin
- if(dp_re_i) begin
- read_ptr <= read_ptr + 1;
- end
- end
-end
-
-//
-// write pointer
-//
-always @(posedge clk or posedge reset) begin
- if(reset) begin
- write_ptr <= 0;
- end
- else begin
- if(dp_we_i) begin
- write_ptr <= write_ptr + 1;
- end
- end
-end
-
-
-endmodule
Index: trunk/const_encoder/doc/ConstSpec.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/const_encoder/doc/ConstSpec.pdf
===================================================================
--- trunk/const_encoder/doc/ConstSpec.pdf (revision 22)
+++ trunk/const_encoder/doc/ConstSpec.pdf (nonexistent)
trunk/const_encoder/doc/ConstSpec.pdf
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: trunk/const_encoder/tb/const_map_data.v
===================================================================
--- trunk/const_encoder/tb/const_map_data.v (revision 22)
+++ trunk/const_encoder/tb/const_map_data.v (nonexistent)
@@ -1,133 +0,0 @@
-
-// ///////////////////////////////////////////////////////////////////
-//
-// 2 -bit constellation map
-//
-// ///////////////////////////////////////////////////////////////////
-module const_map_2bit;
-
-`include "parameters.vh"
-
-reg signed [CONSTW-1:0] re [0:3];
-reg signed [CONSTW-1:0] im [0:3];
-
-
-initial begin : init_2bit
- re[0] = 1; im[0] = 1;
- re[1] = 1; im[1] = -1;
- re[2] = -1; im[2] = 1;
- re[3] = -1; im[3] = -1;
-end
-
-endmodule
-
-
-// ///////////////////////////////////////////////////////////////////
-//
-// 3 -bit constellation map
-//
-// ///////////////////////////////////////////////////////////////////
-module const_map_3bit;
-
-`include "parameters.vh"
-
-reg signed [CONSTW-1:0] re [0:7];
-reg signed [CONSTW-1:0] im [0:7];
-
-
-initial begin
- re[0] = 1; im[0] = 1;
- re[1] = 1; im[1] = -1;
- re[2] = -1; im[2] = 1;
- re[3] = -1; im[3] = -1;
- re[4] = -3; im[4] = 1;
- re[5] = 1; im[5] = 3;
- re[6] = -1; im[6] = -3;
- re[7] = 3; im[7] = -1;
-end
-
-endmodule
-
-// ///////////////////////////////////////////////////////////////////
-//
-// 4 -bit constellation map
-//
-// ///////////////////////////////////////////////////////////////////
-module const_map_4bit;
-
-`include "parameters.vh"
-
-reg signed [CONSTW-1:0] re [0:15];
-reg signed [CONSTW-1:0] im [0:15];
-
-
-initial begin
- re[0] = 1; im[0] = 1;
- re[1] = 1; im[1] = 3;
- re[2] = 3; im[2] = 1;
- re[3] = 3; im[3] = 3;
- re[4] = 1; im[4] = -3;
- re[5] = 1; im[5] = -1;
- re[6] = 3; im[6] = -3;
- re[7] = 3; im[7] = -1;
- re[8] = -3; im[8] = 1;
- re[9] = -3; im[9] = 3;
- re[10] = -1; im[10] = 1;
- re[11] = -1; im[11] = 3;
- re[12] = -3; im[12] = -3;
- re[13] = -3; im[13] = -1;
- re[14] = -1; im[14] = -3;
- re[15] = -1; im[15] = -1;
-end
-
-endmodule
-
-// ///////////////////////////////////////////////////////////////////
-//
-// 5 -bit constellation map
-//
-// ///////////////////////////////////////////////////////////////////
-module const_map_5bit;
-
-`include "parameters.vh"
-
-reg signed [CONSTW-1:0] re [0:31];
-reg signed [CONSTW-1:0] im [0:31];
-
-
-initial begin
- re[0] = 1; im[0] = 1;
- re[1] = 1; im[1] = 3;
- re[2] = 3; im[2] = 1;
- re[3] = 3; im[3] = 3;
- re[4] = 1; im[4] = -3;
- re[5] = 1; im[5] = -1;
- re[6] = 3; im[6] = -3;
- re[7] = 3; im[7] = -1;
- re[8] = -3; im[8] = 1;
- re[9] = -3; im[9] = 3;
- re[10] = -1; im[10] = 1;
- re[11] = -1; im[11] = 3;
- re[12] = -3; im[12] = -3;
- re[13] = -3; im[13] = -1;
- re[14] = -1; im[14] = -3;
- re[15] = -1; im[15] = -1;
- re[16] = 5; im[16] = 1;
- re[17] = 5; im[17] = 3;
- re[18] = -5; im[18] = 1;
- re[19] = -5; im[19] = 3;
- re[20] = 1; im[20] = 5;
- re[21] = 1; im[21] = -5;
- re[22] = 3; im[22] = 5;
- re[23] = 3; im[23] = -5;
- re[24] = -3; im[24] = 5;
- re[25] = -3; im[25] = -5;
- re[26] = -1; im[26] = 5;
- re[27] = -1; im[27] = -5;
- re[28] = 5; im[28] = -3;
- re[29] = 5; im[29] = -1;
- re[30] = -5; im[30] = -3;
- re[31] = -5; im[31] = -1;
-end
-
-endmodule
Index: trunk/const_encoder/tb/tb_const_enc.v
===================================================================
--- trunk/const_encoder/tb/tb_const_enc.v (revision 22)
+++ trunk/const_encoder/tb/tb_const_enc.v (nonexistent)
@@ -1,306 +0,0 @@
-/* *****************************************************************
- *
- * This file is part of the
- *
- * Tone Order and Constellation Encoder Core.
- *
- * Copyright (C) 2007 Guenter Dannoritzer
- *
- * This source is free software; you can redistribute it
- * and/or modify it under the terms of the
- * GNU General Public License
- * as published by the Free Software Foundation;
- * either version 3 of the License,
- * or (at your option) any later version.
- *
- * This source is distributed in the hope
- * that it will be useful, but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the
- * GNU General Public License along with this source.
- * If not, see .
- *
- * *****************************************************************/
-
-module tb_const_encoder();
-
-parameter TW = 10;
-
-`include "parameters.vh"
-
-
-reg clk;
-reg reset;
-wire fast_ready_o;
-reg we_fast_data_i;
-reg [DW-1:0] fast_data_i;
-wire inter_ready_o;
-reg we_inter_data_i;
-reg [DW-1:0] inter_data_i;
-
-reg we_conf_i;
-reg [CONFAW-1:0] addr_i;
-reg [CONFDW-1:0] conf_data_i;
-wire [CNUMW-1:0] carrier_num_o;
-wire signed [CONSTW-1:0] x_o;
-wire signed [CONSTW-1:0] y_o;
-
-//
-// instantiate the DUT
-//
-const_encoder dut ( .clk(clk),
- .reset(reset),
- .fast_ready_o(fast_ready_o),
- .we_fast_data_i(we_fast_data_i),
- .fast_data_i(fast_data_i),
- .inter_ready_o(inter_ready_o),
- .we_inter_data_i(we_inter_data_i),
- .inter_data_i(inter_data_i),
- .addr_i(addr_i),
- .we_conf_i(we_conf_i),
- .conf_data_i(conf_data_i),
- .xy_ready_o(xy_ready_o),
- .carrier_num_o(carrier_num_o),
- .x_o(x_o),
- .y_o(y_o));
-
-//
-// instantiate test data modules
-//
-const_map_2bit cm_2bit();
-const_map_3bit cm_3bit();
-const_map_4bit cm_4bit();
-const_map_5bit cm_5bit();
-
-
-initial begin
- clk = 0;
- we_fast_data_i = 0;
- we_inter_data_i = 0;
- we_conf_i = 0;
- reset = 0;
-end
-
-always begin
- #TW clk = ~clk;
-end
-
-//
-// dump signals
-//
-initial begin
- $dumpfile("tb_const_enc.vcd");
- $dumpvars;
-end
-
-
-//
-// main test
-//
-
-initial begin
-
- $monitor($time, " reset: ", reset);
-
- apply_reset;
-
- //
- // write configuration
- //
- write_config(BIT_LOAD_ST_ADR, 2);
- write_config(BIT_LOAD_ST_ADR+1, 3);
- write_config(BIT_LOAD_ST_ADR+2, 4);
- write_config(BIT_LOAD_ST_ADR+3, 5);
-
- write_config(C_NUM_ST_ADR, 48);
- write_config(C_NUM_ST_ADR+1, 49);
- write_config(C_NUM_ST_ADR+2, 50);
- write_config(C_NUM_ST_ADR+3, 51);
-
-
- write_config(USED_C_ADR, 4);
- write_config(F_BITS_ADR, 7);
-
- //
- // check written configuration
- //
- check_config(BIT_LOAD_ST_ADR, 2);
- check_config(BIT_LOAD_ST_ADR+1, 3);
- check_config(BIT_LOAD_ST_ADR+2, 4);
- check_config(BIT_LOAD_ST_ADR+3, 5);
-
- check_config(C_NUM_ST_ADR, 48);
- check_config(C_NUM_ST_ADR+1, 49);
- check_config(C_NUM_ST_ADR+2, 50);
- check_config(C_NUM_ST_ADR+3, 51);
-
- check_config(USED_C_ADR, 4);
- check_config(F_BITS_ADR, 7);
-
- //
- // checking the constellation map
- //
- check_const_map(2);
- check_const_map(3);
- check_const_map(4);
- check_const_map(5);
-
- #1000 $finish();
-
-end // main test
-
-
-// ////////////////////////////////////////////////////////////////////
-//
-// bus functional models
-//
-// ////////////////////////////////////////////////////////////////////
-
-task apply_reset;
- begin
- reset = 0;
- #20
- reset = 1;
- @(posedge clk);
- reset = 0;
- end
-endtask
-
-//
-// write data to the configuration registers
-//
-task write_config(input [CONFAW-1:0] addr, input[CONFDW-1:0] data);
- begin
-
- addr_i = addr;
- conf_data_i = data;
- @(negedge clk);
- we_conf_i = 1;
- @(negedge clk);
- we_conf_i = 0;
-
- end
-endtask
-
-//
-// check the written configuration
-//
-task check_config(input [CONFAW-1:0] addr, input [CONFDW-1:0] exp_data);
- begin
-
- if(addr >= 0 && addr < C_NUM_ST_ADR) begin
-
- if(dut.BitLoading[addr] !== exp_data) begin
- $display("ERROR! => BitLoading does not match @ %x!", addr);
- $display(" Got: %d expected: %d",
- dut.BitLoading[addr], exp_data);
- end
-
- end
- else if(addr >= C_NUM_ST_ADR && addr < USED_C_ADR) begin
-
- if(dut.CarrierNumber[addr-C_NUM_ST_ADR] !== exp_data) begin
- $display("ERROR! => CarrierNumber does not match @ %x!", addr);
- $display(" Got: %d expected: %d",
- dut.CarrierNumber[addr-C_NUM_ST_ADR], exp_data);
- end
-
- end
- else if(addr == USED_C_ADR) begin
-
- if(dut.UsedCarrier !== exp_data) begin
- $display("ERROR! => UsedCarrier does not match @ %x!", addr);
- $display(" Got: %d expected: %d",
- dut.UsedCarrier, exp_data);
- end
-
- end
- else if(addr == F_BITS_ADR) begin
-
- if(dut.FastBits !== exp_data) begin
- $display("ERROR! => FastBits does not match @ %x!", addr);
- $display(" Got: %d expected: %d",
- dut.FastBits, exp_data);
- end
-
- end
- end
-endtask
-
-
-//
-// check constellation map
-//
-// This task feeds in data direct to the constellation encoder module
-// and checks the expected outcome.
-//
-// Given parameter is the bit size of the constellation map.
-//
-task check_const_map(input [3:0] bit);
- integer len;
- integer i;
- begin
- len = 1 << bit;
- for(i=0; i x_o expected: %d got: %d", i, cm_2bit.re[i], x_o);
- end
- if(cm_2bit.im[i] !== y_o) begin
- $display("Input: %d --> y_o expected: %d got: %d", i, cm_2bit.im[i], y_o);
- end
- end
-
- 3: begin
- if(cm_3bit.re[i] !== x_o) begin
- $display("Input: %d --> x_o expected: %d got: %d", i, cm_3bit.re[i], x_o);
- end
- if(cm_3bit.im[i] !== y_o) begin
- $display("Input: %d --> y_o expected: %d got: %d", i, cm_3bit.im[i], y_o);
- end
- end
-
- 4: begin
- if(cm_4bit.re[i] !== x_o) begin
- $display("Input: %d --> x_o expected: %d got: %d", i, cm_4bit.re[i], x_o);
- end
- if(cm_4bit.im[i] !== y_o) begin
- $display("Input: %d --> y_o expected: %d got: %d", i, cm_4bit.im[i], y_o);
- end
- end
-
- 5: begin
- if(cm_5bit.re[i] !== x_o) begin
- $display($time, " Input: %d --> x_o expected: %d got: %d", i, cm_5bit.re[i], x_o);
- end
- if(cm_5bit.im[i] !== y_o) begin
- $display($time, " Input: %d --> y_o expected: %d got: %d", i, cm_5bit.im[i], y_o);
- end
- end
-
-
- default: $display("%d is not an implemented bit size", bit);
- endcase
-
- end
-
- end
-endtask
-
-
-endmodule
Index: trunk/const_encoder/tb/tb_fifo.v
===================================================================
--- trunk/const_encoder/tb/tb_fifo.v (revision 22)
+++ trunk/const_encoder/tb/tb_fifo.v (nonexistent)
@@ -1,336 +0,0 @@
-/* *****************************************************************
- *
- * This file is part of the
- *
- * Tone Order and Constellation Encoder Core.
- *
- * Copyright (C) 2007 Guenter Dannoritzer
- *
- * This source is free software; you can redistribute it
- * and/or modify it under the terms of the
- * GNU General Public License
- * as published by the Free Software Foundation;
- * either version 3 of the License,
- * or (at your option) any later version.
- *
- * This source is distributed in the hope
- * that it will be useful, but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the
- * GNU General Public License along with this source.
- * If not, see .
- *
- * *****************************************************************/
-module tb_fifo;
-
-parameter AWIDTH = 2;
-parameter DWIDTH = 8;
-parameter TW=10;
-
-
-
-//
-// to interface the dut
-//
-reg clk;
-reg reset;
-reg [DWIDTH-1:0] data_i;
-reg re_i;
-wire empty_o;
-wire full_o;
-wire one_available_o;
-wire two_available_o;
-reg we_i;
-reg [DWIDTH-1:0] data_i;
-reg re_i;
-wire [DWIDTH-1:0] data_o;
-
-
-
-//
-// instantiate the DUT
-//
-fifo #(.AWIDTH(AWIDTH), .DWIDTH(DWIDTH))
-
- dut ( .clk(clk),
- .reset(reset),
- .empty_o(empty_o),
- .full_o(full_o),
- .one_available_o(one_available_o),
- .two_available_o(two_available_o),
- .we_i(we_i),
- .data_i(data_i),
- .re_i(re_i),
- .data_o(data_o));
-
-
-//
-// local reg/wires
-//
-reg [DWIDTH-1:0] got_data;
-
-//
-// main tests
-//
-
-initial begin
- clk = 0;
- we_i = 0;
- re_i = 0;
- reset = 0;
-end
-
-always begin
- #TW clk = ~clk;
-end
-
-//
-// dump signals
-//
-initial begin
- $dumpfile("tb_fifo.vcd");
- $dumpvars;
-end
-
-
-initial begin
- $display("=== Verifing FIFO ===");
-
- $display("- reset test");
- test_reset;
- check_control(5'b0001);
-
- $display("- verify write followed by read");
- write_data(8'haa);
- check_control(5'b0100);
-
- read_data(got_data);
- check_result(got_data, 8'haa);
- check_control(5'b0001);
-
- // fifo is empty again
-
- // fill it and only expect after the 4th write a full signal
-
- $display("- fill FIFO up");
- // #1
- write_data(8'h70);
- check_control(5'b0100);
- // #2
- write_data(8'h71);
- check_control(5'b1100);
- // #3
- write_data(8'h72);
- check_control(5'b1100);
- // #4
- write_data(8'h73);
- check_control(5'b1110);
-
- $display("- FIFO is full, another write should not have an affect");
- write_data(8'hab);
- check_control(5'b1110);
-
- $display("- verify reading the data from the full FIFO back");
- // #1
- read_data(got_data);
- check_result(got_data, 8'h70);
- check_control(5'b1100);
- // #2
- read_data(got_data);
- check_result(got_data, 8'h71);
- check_control(5'b1100);
- // #3
- read_data(got_data);
- check_result(got_data, 8'h72);
- check_control(5'b0100);
- // #4
- read_data(got_data);
- check_result(got_data, 8'h73);
- check_control(5'b0001);
-
-
- $display("= Now test a read/write at the same clock =");
-
-
- $display("- First have an empty FIFO and do the read/write");
- // read should fail but write should succeed
- fork
- read_data(got_data);
- write_data(8'h80);
- join
- check_control(5'b0100);
- read_data(got_data);
- check_result(got_data, 8'h80);
-
-
- //
- $display("- Now have one entry in the FIFO and do a read/write");
- // read should bring the first value back and the written value
- // should stay
- write_data(8'h90);
- fork
- read_data(got_data);
- write_data(8'hA0);
- join
- check_control(5'b0100);
- check_result(got_data, 8'h90);
-
- read_data(got_data);
- check_result(got_data, 8'hA0);
- check_control(5'b0001);
-
-
-
- $display("- Finally fill up the FIFO and to the read/write");
- // #1
- write_data(8'h10);
- check_control(5'b0100);
- // #2
- write_data(8'h11);
- check_control(5'b1100);
- // #3
- write_data(8'h12);
- check_control(5'b1100);
- // #4
- write_data(8'h13);
- check_control(5'b1110);
-
- // doing the read/write, as the FIFO is full the written value should
- // not end up in the FIFO
- fork
- read_data(got_data);
- write_data(8'h20);
- join
-
- check_control(5'b1100);
- check_result(got_data, 8'h10);
-
- // doing a read/write with one empty spot, the read should return the
- // last but one value and the write should end up in the FIFO
- fork
- read_data(got_data);
- write_data(8'h21);
- join
-
- check_control(5'b1100);
- check_result(got_data, 8'h11);
-
-
- // so reading back the values, should return the 3 remaining values
- // #1
- read_data(got_data);
- check_result(got_data, 8'h12);
- check_control(5'b1100);
- // #2
- read_data(got_data);
- check_result(got_data, 8'h13);
- check_control(5'b0100);
- // #3
- read_data(got_data);
- check_result(got_data, 8'h21);
- check_control(5'b0001);
-
- $display("FIFO verification done!");
-
- $finish();
-
-end
-
-
-
-
-// ////////////////////////////////////////////////////////////////////
-//
-// bus functional models
-//
-// ////////////////////////////////////////////////////////////////////
-
-task test_reset;
- begin
- //$display("Testing reset");
- reset = 0;
- #10 reset = 1;
- #20 reset = 0;
-
-end
-endtask
-
-
-// =====================================================================
-// check the expected control line status
-//
-// exp_ctrl[4:0] == {two_available, one_available, full, empty}
-//
-task check_control(input [4:0]exp_ctrl);
- begin
-
- //$display("# %d expCtrl: %d", $time, exp_ctrl);
-
- if(empty_o !== exp_ctrl[0])
- $display("ERROR! => Expected empty_o == %d, got %d", exp_ctrl[0], empty_o);
-
- if(full_o !== exp_ctrl[1])
- $display("ERROR! => Expected full_o == %d, got %d", exp_ctrl[1], full_o);
-
- if(one_available_o !== exp_ctrl[2])
- $display("ERROR! => Expected one_available_o == %d, got %d", exp_ctrl[3], one_available_o);
-
- if(two_available_o !== exp_ctrl[3])
- $display("ERROR! => Expected two_available_o == %d, got %d", exp_ctrl[4], two_available_o);
-
- end
-endtask
-
-
-// =====================================================================
-//
-// write data to the fifo
-//
-task write_data(input [DWIDTH-1:0]data);
- begin
- //$display("# %d Writing data", $time);
- @(negedge clk);
- data_i = data;
- we_i = 1;
- @(negedge clk);
- we_i = 0;
-
- end
-endtask
-
-// =====================================================================
-//
-// read data from the fifo
-//
-//
-task read_data(output [DWIDTH-1:0]data);
- begin
-
- //$display("# %d Reading data", $time);
- @(negedge clk);
- re_i = 1;
- @(negedge clk);
- data = data_o;
- re_i = 0;
-
- end
-endtask
-
-
-// =====================================================================
-//
-// check result
-//
-//
-task check_result(input [DWIDTH-1:0]got, input [DWIDTH-1:0]expected);
- begin
- if(got !== expected)
- $display("ERROR! => Result does not match! Got: %d (%x) expected: %d (%x)", got, got, expected, expected);
- end
-endtask
-
-endmodule
-
Index: trunk/gpl.txt
===================================================================
--- trunk/gpl.txt (revision 22)
+++ trunk/gpl.txt (nonexistent)
@@ -1,674 +0,0 @@
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Index: dmt_tx/trunk/const_encoder/rtl/const_enc.v
===================================================================
--- dmt_tx/trunk/const_encoder/rtl/const_enc.v (nonexistent)
+++ dmt_tx/trunk/const_encoder/rtl/const_enc.v (revision 23)
@@ -0,0 +1,302 @@
+/* *****************************************************************
+ *
+ * This file is part of the
+ *
+ * Tone Order and Constellation Encoder Core.
+ *
+ * Description:
+ *
+ * The conste_enc module implements the tone ordering and
+ * constellation encoding as described in ITU G.992.1
+ *
+ *********************************************************************
+ * Copyright (C) 2007 Guenter Dannoritzer
+ *
+ * This source is free software; you can redistribute it
+ * and/or modify it under the terms of the
+ * GNU General Public License
+ * as published by the Free Software Foundation;
+ * either version 3 of the License,
+ * or (at your option) any later version.
+ *
+ * This source is distributed in the hope
+ * that it will be useful, but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the
+ * GNU General Public License along with this source.
+ * If not, see .
+ *
+ * *****************************************************************/
+
+module const_encoder(
+ clk,
+ reset,
+ fast_ready_o,
+ we_fast_data_i,
+ fast_data_i,
+ inter_ready_o,
+ we_inter_data_i,
+ inter_data_i,
+ addr_i,
+ we_conf_i,
+ conf_data_i,
+ xy_ready_o,
+ carrier_num_o,
+ x_o,
+ y_o);
+
+
+`include "parameters.vh"
+
+//
+// parameter
+//
+
+input clk;
+input reset;
+output fast_ready_o;
+input we_fast_data_i;
+input [DW-1:0] fast_data_i;
+output inter_ready_o;
+input we_inter_data_i;
+input [DW-1:0] inter_data_i;
+input [CONFAW-1:0] addr_i;
+input we_conf_i;
+input [CONFDW-1:0] conf_data_i;
+output xy_ready_o;
+output [CNUMW-1:0] carrier_num_o;
+output [CONSTW-1:0] x_o; reg signed [CONSTW-1:0] x_o;
+output [CONSTW-1:0] y_o; reg signed [CONSTW-1:0] y_o;
+
+
+
+//
+// local wire/regs
+//
+wire [DW-1:0] fast_data_o;
+wire [DW-1:0] inter_data_o;
+
+reg [SHIFTW-1:0] fast_shift_reg;
+reg [SHIFTW-1:0] inter_shift_reg;
+reg [MAXBITNUM-1:0] cin;
+reg [CONFDW-1:0] bit_load;
+
+reg [4:0] msb;
+reg [1:0] msb_x;
+reg [1:0] msb_y;
+
+reg [CONFDW-1:0] BitLoading [0:REG_MEM_LEN-1];
+reg [CONFDW-1:0] CarrierNumber [0:REG_MEM_LEN-1];
+reg [USED_C_REG_W-1:0] UsedCarrier;
+reg [F_BITS_W-1:0] FastBits;
+
+//
+// intantiate the fast path and interleaved path FIFOs
+//
+fifo #(.AWIDTH(AW), .DWIDTH(DW))
+ fifo_fast ( .clk(clk),
+ .reset(reset),
+ .empty_o(fast_empty_o),
+ .full_o(fast_full_o),
+ .one_available_o(fast_one_available_o),
+ .two_available_o(fast_two_available_o),
+ .we_i(we_fast_i),
+ .data_i(fast_data_i),
+ .re_i(re_fast_i),
+ .data_o(fast_data_o)
+ );
+
+fifo #(.AWIDTH(AW), .DWIDTH(DW))
+ fifo_inter ( .clk(clk),
+ .reset(reset),
+ .empty_o(inter_empty_o),
+ .full_o(inter_full_o),
+ .one_available_o(inter_one_available_o),
+ .two_available_o(inter_two_available_o),
+ .we_i(we_inter_i),
+ .data_i(inter_data_i),
+ .re_i(re_inter_i),
+ .data_o(inter_data_o)
+ );
+
+
+//
+// configuration register access
+//
+always @(posedge clk or posedge reset) begin
+
+ if(reset) begin
+ UsedCarrier <= 0;
+ FastBits <= 0;
+
+ end
+ else begin
+ if(we_conf_i) begin
+ if(addr_i >= 0 && addr_i < C_NUM_ST_ADR) begin
+ BitLoading[addr_i] <= conf_data_i;
+ end
+ else if(addr_i >= C_NUM_ST_ADR && addr_i < USED_C_ADR) begin
+ CarrierNumber[addr_i - C_NUM_ST_ADR] <= conf_data_i;
+ end
+ else if(addr_i == USED_C_ADR) begin
+ UsedCarrier <= conf_data_i;
+ end
+ else if(addr_i == F_BITS_ADR) begin
+ FastBits <= conf_data_i;
+ end
+ end
+ end
+
+end
+
+
+//
+// constellation mapping
+//
+always @(posedge reset or posedge clk) begin
+
+ if(reset) begin
+ x_o <= 9'b0;
+ y_o <= 9'b0;
+ end
+ else begin
+ case (bit_load)
+ 4'b0010: begin // #2
+ x_o <= {cin[1], cin[1], cin[1], cin[1], cin[1], cin[1], cin[1], cin[1], 1'b1};
+ y_o <= {cin[0], cin[0], cin[0], cin[0], cin[0], cin[0], cin[0], cin[0], 1'b1};
+ end
+
+ 4'b0011: begin // #3
+ case (cin[2:0])
+ 3'b000: begin x_o <= 9'b000000001; y_o <= 9'b000000001; end
+ 3'b001: begin x_o <= 9'b000000001; y_o <= 9'b111111111; end
+ 3'b010: begin x_o <= 9'b111111111; y_o <= 9'b000000001; end
+ 3'b011: begin x_o <= 9'b111111111; y_o <= 9'b111111111; end
+
+ 3'b100: begin x_o <= 9'b111111101; y_o <= 9'b000000001; end
+ 3'b101: begin x_o <= 9'b000000001; y_o <= 9'b000000011; end
+ 3'b110: begin x_o <= 9'b111111111; y_o <= 9'b111111101; end
+ 3'b111: begin x_o <= 9'b000000011; y_o <= 9'b111111111; end
+ endcase
+ end
+
+ 4'b0100: begin // #4
+ x_o <= {cin[3], cin[3], cin[3], cin[3], cin[3], cin[3], cin[3], cin[1], 1'b1};
+ y_o <= {cin[2], cin[2], cin[2], cin[2], cin[2], cin[2], cin[2], cin[0], 1'b1};
+ end
+
+ 4'b0101: begin // #5
+ map_msb(cin[4:0], msb_x, msb_y);
+ x_o <= {msb_x[1], msb_x[1], msb_x[1], msb_x[1], msb_x[1], msb_x[1], msb_x[0], cin[1], 1'b1};
+ y_o <= {msb_y[1], msb_y[1], msb_y[1], msb_y[1], msb_y[1], msb_y[1], msb_y[0], cin[0], 1'b1};
+ end
+
+ 4'b0110: begin // #6
+ x_o <= {cin[4], cin[4], cin[4], cin[4], cin[4], cin[4], cin[2], cin[0], 1'b1};
+ y_o <= {cin[5], cin[5], cin[5], cin[5], cin[5], cin[5], cin[3], cin[1], 1'b1};
+ end
+
+ 4'b0111: begin // #7
+ map_msb(cin[6:2], msb_x, msb_y);
+ x_o <= {msb_x[1], msb_x[1], msb_x[1], msb_x[1], msb_x[1], msb_x[0], cin[2], cin[0], 1'b1};
+ y_o <= {msb_y[1], msb_y[1], msb_y[1], msb_y[1], msb_y[1], msb_y[0], cin[3], cin[1], 1'b1};
+ end
+ 4'b1000: begin // #8
+ x_o <= {cin[6], cin[6], cin[6], cin[6], cin[6], cin[4], cin[2], cin[0], 1'b1};
+ y_o <= {cin[7], cin[7], cin[7], cin[7], cin[7], cin[5], cin[3], cin[1], 1'b1};
+ end
+
+ 4'b1001: begin // #9
+ map_msb(cin[7:3], msb_x, msb_y);
+ x_o <= {msb_x[1], msb_x[1], msb_x[1], msb_x[1], msb_x[0], cin[4], cin[2], cin[0], 1'b1};
+ y_o <= {msb_y[1], msb_y[1], msb_y[1], msb_y[1], msb_y[0], cin[5], cin[3], cin[1], 1'b1};
+ end
+ 4'b1010: begin // #10
+ x_o <= {cin[8], cin[8], cin[8], cin[8], cin[6], cin[4], cin[2], cin[0], 1'b1};
+ y_o <= {cin[9], cin[9], cin[9], cin[9], cin[7], cin[5], cin[3], cin[1], 1'b1};
+ end
+
+ 4'b1011: begin // #11
+ map_msb(cin[8:4], msb_x, msb_y);
+ x_o <= {msb_x[1], msb_x[1], msb_x[1], msb_x[0], cin[6], cin[4], cin[2], cin[0], 1'b1};
+ y_o <= {msb_y[1], msb_y[1], msb_y[1], msb_y[0], cin[7], cin[5], cin[3], cin[1], 1'b1};
+ end
+ 4'b1100: begin // #12
+ x_o <= {cin[10], cin[10], cin[10], cin[8], cin[6], cin[4], cin[2], cin[0], 1'b1};
+ y_o <= {cin[11], cin[11], cin[11], cin[9], cin[7], cin[5], cin[3], cin[1], 1'b1};
+ end
+
+ 4'b1101: begin // #13
+ map_msb(cin[9:5], msb_x, msb_y);
+ x_o <= {msb_x[1], msb_x[1], msb_x[0], cin[8], cin[6], cin[4], cin[2], cin[0], 1'b1};
+ y_o <= {msb_y[1], msb_y[1], msb_y[0], cin[9], cin[7], cin[5], cin[3], cin[1], 1'b1};
+ end
+ 4'b1110: begin // #14
+ x_o <= {cin[12], cin[12], cin[10], cin[8], cin[6], cin[4], cin[2], cin[0], 1'b1};
+ y_o <= {cin[13], cin[13], cin[11], cin[9], cin[7], cin[5], cin[3], cin[1], 1'b1};
+ end
+
+ 4'b1111: begin // #15 TODO
+ map_msb(cin[10:6], msb_x, msb_y);
+ x_o <= {msb_x[1], msb_x[0], cin[10], cin[8], cin[6], cin[4], cin[2], cin[0], 1'b1};
+ y_o <= {msb_y[1], msb_y[0], cin[11], cin[9], cin[7], cin[5], cin[3], cin[1], 1'b1};
+ end
+
+ endcase
+ end
+end
+
+//
+// determine the top two bits of X and Y based on table 7-12 in G.992.1
+//
+task map_msb(input [4:0] t_msb, output [1:0] t_msb_x, output [1:0] t_msb_y );
+ begin
+ case (t_msb)
+ 5'b00000: begin t_msb_x <= 2'b00; t_msb_y <= 2'b00; end
+ 5'b00001: begin t_msb_x <= 2'b00; t_msb_y <= 2'b00; end
+ 5'b00010: begin t_msb_x <= 2'b00; t_msb_y <= 2'b00; end
+ 5'b00011: begin t_msb_x <= 2'b00; t_msb_y <= 2'b00; end
+
+ 5'b00100: begin t_msb_x <= 2'b00; t_msb_y <= 2'b11; end
+ 5'b00101: begin t_msb_x <= 2'b00; t_msb_y <= 2'b11; end
+ 5'b00110: begin t_msb_x <= 2'b00; t_msb_y <= 2'b11; end
+ 5'b00111: begin t_msb_x <= 2'b00; t_msb_y <= 2'b11; end
+
+ 5'b01000: begin t_msb_x <= 2'b11; t_msb_y <= 2'b00; end
+ 5'b01001: begin t_msb_x <= 2'b11; t_msb_y <= 2'b00; end
+ 5'b01010: begin t_msb_x <= 2'b11; t_msb_y <= 2'b00; end
+ 5'b01011: begin t_msb_x <= 2'b11; t_msb_y <= 2'b00; end
+
+ 5'b01100: begin t_msb_x <= 2'b11; t_msb_y <= 2'b11; end
+ 5'b01101: begin t_msb_x <= 2'b11; t_msb_y <= 2'b11; end
+ 5'b01110: begin t_msb_x <= 2'b11; t_msb_y <= 2'b11; end
+ 5'b01111: begin t_msb_x <= 2'b11; t_msb_y <= 2'b11; end
+
+ 5'b10000: begin t_msb_x <= 2'b01; t_msb_y <= 2'b00; end
+ 5'b10001: begin t_msb_x <= 2'b01; t_msb_y <= 2'b00; end
+ 5'b10010: begin t_msb_x <= 2'b10; t_msb_y <= 2'b00; end
+ 5'b10011: begin t_msb_x <= 2'b10; t_msb_y <= 2'b00; end
+
+ 5'b10100: begin t_msb_x <= 2'b00; t_msb_y <= 2'b01; end
+ 5'b10101: begin t_msb_x <= 2'b00; t_msb_y <= 2'b10; end
+ 5'b10110: begin t_msb_x <= 2'b00; t_msb_y <= 2'b01; end
+ 5'b10111: begin t_msb_x <= 2'b00; t_msb_y <= 2'b10; end
+
+ 5'b11000: begin t_msb_x <= 2'b11; t_msb_y <= 2'b01; end
+ 5'b11001: begin t_msb_x <= 2'b11; t_msb_y <= 2'b10; end
+ 5'b11010: begin t_msb_x <= 2'b11; t_msb_y <= 2'b01; end
+ 5'b11011: begin t_msb_x <= 2'b11; t_msb_y <= 2'b10; end
+
+ 5'b11100: begin t_msb_x <= 2'b01; t_msb_y <= 2'b11; end
+ 5'b11101: begin t_msb_x <= 2'b01; t_msb_y <= 2'b11; end
+ 5'b11110: begin t_msb_x <= 2'b10; t_msb_y <= 2'b11; end
+ 5'b11111: begin t_msb_x <= 2'b10; t_msb_y <= 2'b11; end
+
+ endcase
+end
+endtask
+
+endmodule
Index: dmt_tx/trunk/const_encoder/rtl/parameters.vh
===================================================================
--- dmt_tx/trunk/const_encoder/rtl/parameters.vh (nonexistent)
+++ dmt_tx/trunk/const_encoder/rtl/parameters.vh (revision 23)
@@ -0,0 +1,25 @@
+
+//
+// parameter
+//
+parameter DW = 8;
+parameter AW = 4;
+parameter CONFAW = 10;
+parameter CONFDW = 8;
+parameter CNUMW = 4; // Width of the carrier number output
+parameter CONSTW = 9;
+
+parameter SHIFTW = 23; // Width of the shift registers
+parameter MAXBITNUM = 15; // Maximum bit number per carrier
+
+parameter USED_C_REG_W = 8; // Used carrier register width
+parameter F_BITS_W = 8;
+parameter REG_MEM_LEN = 256;
+
+//
+// register addresses
+//
+parameter BIT_LOAD_ST_ADR = 12'h000;
+parameter C_NUM_ST_ADR = 12'h100;
+parameter USED_C_ADR = 12'h200;
+parameter F_BITS_ADR = 12'h201;
Index: dmt_tx/trunk/const_encoder/rtl/fifo.v
===================================================================
--- dmt_tx/trunk/const_encoder/rtl/fifo.v (nonexistent)
+++ dmt_tx/trunk/const_encoder/rtl/fifo.v (revision 23)
@@ -0,0 +1,160 @@
+/* *****************************************************************
+ *
+ * This file is part of the
+ *
+ * Tone Order and Constellation Encoder Core.
+ *
+ *
+ * Description:
+ *
+ * fifo is a synchronouys FIFO without write through. The read
+ * and write operation happens with the positive edge of the clk
+ * signal. If the FIFO is empty and performing a read/write operation
+ * with at the same clock cycle only the write operation will succeed.
+ * The read operation will not return a valid value.
+ *
+ *
+ *********************************************************************
+ * Copyright (C) 2007 Guenter Dannoritzer
+ *
+ * This source is free software; you can redistribute it
+ * and/or modify it under the terms of the
+ * GNU General Public License
+ * as published by the Free Software Foundation;
+ * either version 3 of the License,
+ * or (at your option) any later version.
+ *
+ * This source is distributed in the hope
+ * that it will be useful, but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the
+ * GNU General Public License along with this source.
+ * If not, see .
+ *
+ * *****************************************************************/
+module fifo(
+ clk,
+ reset,
+ empty_o,
+ full_o,
+ one_available_o,
+ two_available_o,
+ we_i,
+ data_i,
+ re_i,
+ data_o);
+
+parameter DWIDTH = 8;
+parameter AWIDTH = 4;
+
+input clk;
+input reset;
+output empty_o;
+output full_o;
+output one_available_o;
+output two_available_o;
+input we_i;
+input [DWIDTH-1:0] data_i;
+input re_i;
+output [DWIDTH-1:0] data_o;
+
+
+
+
+//
+// local reg/wires
+//
+reg [AWIDTH-1:0] read_ptr;
+reg [AWIDTH-1:0] write_ptr;
+reg [AWIDTH:0] fill_ctr;
+
+wire dp_we_i;
+wire dp_re_i;
+
+//
+// instantiate the dual port ram
+//
+generic_dpram #(.aw(AWIDTH),
+ .dw(DWIDTH)
+ )
+ dpram ( .rclk(clk),
+ .rrst(reset),
+ .rce(ce),
+ .oe(dp_re_i),
+ .raddr(read_ptr),
+ .do(data_o),
+
+ .wclk(clk),
+ .wrst(reset),
+ .wce(ce),
+ .we(dp_we_i),
+ .waddr(write_ptr),
+ .di(data_i));
+
+
+//
+// control logic
+//
+assign ce = 1'b1;
+
+assign one_available_o = (fill_ctr > 1'b0) ? 1'b1 : 1'b0;
+assign two_available_o = (fill_ctr > 1'b1) ? 1'b1 : 1'b0;
+assign empty_o = |fill_ctr ? 1'b0 : 1'b1;
+assign full_o = fill_ctr[AWIDTH] ? 1'b1 : 1'b0;
+
+// make sure a write only happens to dp_ram when not full
+assign dp_we_i = ~full_o ? we_i : 1'b0;
+// make sure a read only happens to the dp_ram when not empty
+assign dp_re_i = ~empty_o ? re_i : 1'b0;
+
+//
+// fill counter
+//
+always @(posedge clk or posedge reset) begin
+ if(reset) begin
+ fill_ctr <= 0;
+ end
+ else begin
+
+ if(dp_we_i & ~ dp_re_i) begin
+ fill_ctr <= fill_ctr + 1;
+ end
+ else if(dp_re_i & ~ dp_we_i) begin
+ fill_ctr <= fill_ctr - 1;
+ end
+ end
+end
+
+//
+// read pointer
+//
+always @(posedge clk or posedge reset) begin
+ if(reset) begin
+ read_ptr <= 0;
+ end
+ else begin
+ if(dp_re_i) begin
+ read_ptr <= read_ptr + 1;
+ end
+ end
+end
+
+//
+// write pointer
+//
+always @(posedge clk or posedge reset) begin
+ if(reset) begin
+ write_ptr <= 0;
+ end
+ else begin
+ if(dp_we_i) begin
+ write_ptr <= write_ptr + 1;
+ end
+ end
+end
+
+
+endmodule
Index: dmt_tx/trunk/const_encoder/rtl/defs.vh
===================================================================
--- dmt_tx/trunk/const_encoder/rtl/defs.vh (nonexistent)
+++ dmt_tx/trunk/const_encoder/rtl/defs.vh (revision 23)
@@ -0,0 +1,6 @@
+
+
+`define VENDOR_FPGA
+
+
+
Index: dmt_tx/trunk/const_encoder/rtl/generic_dpram.v
===================================================================
--- dmt_tx/trunk/const_encoder/rtl/generic_dpram.v (nonexistent)
+++ dmt_tx/trunk/const_encoder/rtl/generic_dpram.v (revision 23)
@@ -0,0 +1,507 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Generic Dual-Port Synchronous RAM ////
+//// ////
+//// This file is part of memory library available from ////
+//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
+//// ////
+//// Description ////
+//// This block is a wrapper with common dual-port ////
+//// synchronous memory interface for different ////
+//// types of ASIC and FPGA RAMs. Beside universal memory ////
+//// interface it also provides behavioral model of generic ////
+//// dual-port synchronous RAM. ////
+//// It also contains a fully synthesizeable model for FPGAs. ////
+//// It should be used in all OPENCORES designs that want to be ////
+//// portable accross different target technologies and ////
+//// independent of target memory. ////
+//// ////
+//// Supported ASIC RAMs are: ////
+//// - Artisan Dual-Port Sync RAM ////
+//// - Avant! Two-Port Sync RAM (*) ////
+//// - Virage 2-port Sync RAM ////
+//// ////
+//// Supported FPGA RAMs are: ////
+//// - Generic FPGA (VENDOR_FPGA) ////
+//// Tested RAMs: Altera, Xilinx ////
+//// Synthesis tools: LeonardoSpectrum, Synplicity ////
+//// - Xilinx (VENDOR_XILINX) ////
+//// - Altera (VENDOR_ALTERA) ////
+//// ////
+//// To Do: ////
+//// - fix Avant! ////
+//// - add additional RAMs (VS etc) ////
+//// ////
+//// Author(s): ////
+//// - Richard Herveille, richard@asics.ws ////
+//// - Damjan Lampret, lampret@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.4 2002/09/28 08:18:52 rherveille
+// Changed synthesizeable FPGA memory implementation.
+// Fixed some issues with Xilinx BlockRAM
+//
+// Revision 1.3 2001/11/09 00:34:18 samg
+// minor changes: unified with all common rams
+//
+// Revision 1.2 2001/11/08 19:11:31 samg
+// added valid checks to behvioral model
+//
+// Revision 1.1.1.1 2001/09/14 09:57:10 rherveille
+// Major cleanup.
+// Files are now compliant to Altera & Xilinx memories.
+// Memories are now compatible, i.e. drop-in replacements.
+// Added synthesizeable generic FPGA description.
+// Created "generic_memories" cvs entry.
+//
+// Revision 1.1.1.2 2001/08/21 13:09:27 damjan
+// *** empty log message ***
+//
+// Revision 1.1 2001/08/20 18:23:20 damjan
+// Initial revision
+//
+// Revision 1.1 2001/08/09 13:39:33 lampret
+// Major clean-up.
+//
+// Revision 1.2 2001/07/30 05:38:02 lampret
+// Adding empty directories required by HDL coding guidelines
+//
+//
+
+//`include "timescale.v"
+//
+`include "defs.vh"
+
+//`define VENDOR_FPGA
+//`define VENDOR_XILINX
+//`define VENDOR_ALTERA
+
+module generic_dpram(
+ // Generic synchronous dual-port RAM interface
+ rclk, rrst, rce, oe, raddr, do,
+ wclk, wrst, wce, we, waddr, di
+);
+
+ //
+ // Default address and data buses width
+ //
+ parameter aw = 5; // number of bits in address-bus
+ parameter dw = 16; // number of bits in data-bus
+
+ //
+ // Generic synchronous double-port RAM interface
+ //
+ // read port
+ input rclk; // read clock, rising edge trigger
+ input rrst; // read port reset, active high
+ input rce; // read port chip enable, active high
+ input oe; // output enable, active high
+ input [aw-1:0] raddr; // read address
+ output [dw-1:0] do; // data output
+
+ // write port
+ input wclk; // write clock, rising edge trigger
+ input wrst; // write port reset, active high
+ input wce; // write port chip enable, active high
+ input we; // write enable, active high
+ input [aw-1:0] waddr; // write address
+ input [dw-1:0] di; // data input
+
+ //
+ // Module body
+ //
+
+`ifdef VENDOR_FPGA
+ //
+ // Instantiation synthesizeable FPGA memory
+ //
+ // This code has been tested using LeonardoSpectrum and Synplicity.
+ // The code correctly instantiates Altera EABs and Xilinx BlockRAMs.
+ //
+ reg [dw-1:0] mem [(1< .
+ *
+ * *****************************************************************/
+
+module tb_const_encoder();
+
+parameter TW = 10;
+
+`include "parameters.vh"
+
+
+reg clk;
+reg reset;
+wire fast_ready_o;
+reg we_fast_data_i;
+reg [DW-1:0] fast_data_i;
+wire inter_ready_o;
+reg we_inter_data_i;
+reg [DW-1:0] inter_data_i;
+
+reg we_conf_i;
+reg [CONFAW-1:0] addr_i;
+reg [CONFDW-1:0] conf_data_i;
+wire [CNUMW-1:0] carrier_num_o;
+wire signed [CONSTW-1:0] x_o;
+wire signed [CONSTW-1:0] y_o;
+
+//
+// instantiate the DUT
+//
+const_encoder dut ( .clk(clk),
+ .reset(reset),
+ .fast_ready_o(fast_ready_o),
+ .we_fast_data_i(we_fast_data_i),
+ .fast_data_i(fast_data_i),
+ .inter_ready_o(inter_ready_o),
+ .we_inter_data_i(we_inter_data_i),
+ .inter_data_i(inter_data_i),
+ .addr_i(addr_i),
+ .we_conf_i(we_conf_i),
+ .conf_data_i(conf_data_i),
+ .xy_ready_o(xy_ready_o),
+ .carrier_num_o(carrier_num_o),
+ .x_o(x_o),
+ .y_o(y_o));
+
+//
+// instantiate test data modules
+//
+const_map_2bit cm_2bit();
+const_map_3bit cm_3bit();
+const_map_4bit cm_4bit();
+const_map_5bit cm_5bit();
+
+
+initial begin
+ clk = 0;
+ we_fast_data_i = 0;
+ we_inter_data_i = 0;
+ we_conf_i = 0;
+ reset = 0;
+end
+
+always begin
+ #TW clk = ~clk;
+end
+
+//
+// dump signals
+//
+initial begin
+ $dumpfile("tb_const_enc.vcd");
+ $dumpvars;
+end
+
+
+//
+// main test
+//
+
+initial begin
+
+ $monitor($time, " reset: ", reset);
+
+ apply_reset;
+
+ //
+ // write configuration
+ //
+ write_config(BIT_LOAD_ST_ADR, 2);
+ write_config(BIT_LOAD_ST_ADR+1, 3);
+ write_config(BIT_LOAD_ST_ADR+2, 4);
+ write_config(BIT_LOAD_ST_ADR+3, 5);
+
+ write_config(C_NUM_ST_ADR, 48);
+ write_config(C_NUM_ST_ADR+1, 49);
+ write_config(C_NUM_ST_ADR+2, 50);
+ write_config(C_NUM_ST_ADR+3, 51);
+
+
+ write_config(USED_C_ADR, 4);
+ write_config(F_BITS_ADR, 7);
+
+ //
+ // check written configuration
+ //
+ check_config(BIT_LOAD_ST_ADR, 2);
+ check_config(BIT_LOAD_ST_ADR+1, 3);
+ check_config(BIT_LOAD_ST_ADR+2, 4);
+ check_config(BIT_LOAD_ST_ADR+3, 5);
+
+ check_config(C_NUM_ST_ADR, 48);
+ check_config(C_NUM_ST_ADR+1, 49);
+ check_config(C_NUM_ST_ADR+2, 50);
+ check_config(C_NUM_ST_ADR+3, 51);
+
+ check_config(USED_C_ADR, 4);
+ check_config(F_BITS_ADR, 7);
+
+ //
+ // checking the constellation map
+ //
+ check_const_map(2);
+ check_const_map(3);
+ check_const_map(4);
+ check_const_map(5);
+
+ #1000 $finish();
+
+end // main test
+
+
+// ////////////////////////////////////////////////////////////////////
+//
+// bus functional models
+//
+// ////////////////////////////////////////////////////////////////////
+
+task apply_reset;
+ begin
+ reset = 0;
+ #20
+ reset = 1;
+ @(posedge clk);
+ reset = 0;
+ end
+endtask
+
+//
+// write data to the configuration registers
+//
+task write_config(input [CONFAW-1:0] addr, input[CONFDW-1:0] data);
+ begin
+
+ addr_i = addr;
+ conf_data_i = data;
+ @(negedge clk);
+ we_conf_i = 1;
+ @(negedge clk);
+ we_conf_i = 0;
+
+ end
+endtask
+
+//
+// check the written configuration
+//
+task check_config(input [CONFAW-1:0] addr, input [CONFDW-1:0] exp_data);
+ begin
+
+ if(addr >= 0 && addr < C_NUM_ST_ADR) begin
+
+ if(dut.BitLoading[addr] !== exp_data) begin
+ $display("ERROR! => BitLoading does not match @ %x!", addr);
+ $display(" Got: %d expected: %d",
+ dut.BitLoading[addr], exp_data);
+ end
+
+ end
+ else if(addr >= C_NUM_ST_ADR && addr < USED_C_ADR) begin
+
+ if(dut.CarrierNumber[addr-C_NUM_ST_ADR] !== exp_data) begin
+ $display("ERROR! => CarrierNumber does not match @ %x!", addr);
+ $display(" Got: %d expected: %d",
+ dut.CarrierNumber[addr-C_NUM_ST_ADR], exp_data);
+ end
+
+ end
+ else if(addr == USED_C_ADR) begin
+
+ if(dut.UsedCarrier !== exp_data) begin
+ $display("ERROR! => UsedCarrier does not match @ %x!", addr);
+ $display(" Got: %d expected: %d",
+ dut.UsedCarrier, exp_data);
+ end
+
+ end
+ else if(addr == F_BITS_ADR) begin
+
+ if(dut.FastBits !== exp_data) begin
+ $display("ERROR! => FastBits does not match @ %x!", addr);
+ $display(" Got: %d expected: %d",
+ dut.FastBits, exp_data);
+ end
+
+ end
+ end
+endtask
+
+
+//
+// check constellation map
+//
+// This task feeds in data direct to the constellation encoder module
+// and checks the expected outcome.
+//
+// Given parameter is the bit size of the constellation map.
+//
+task check_const_map(input [3:0] bit);
+ integer len;
+ integer i;
+ begin
+ len = 1 << bit;
+ for(i=0; i x_o expected: %d got: %d", i, cm_2bit.re[i], x_o);
+ end
+ if(cm_2bit.im[i] !== y_o) begin
+ $display("Input: %d --> y_o expected: %d got: %d", i, cm_2bit.im[i], y_o);
+ end
+ end
+
+ 3: begin
+ if(cm_3bit.re[i] !== x_o) begin
+ $display("Input: %d --> x_o expected: %d got: %d", i, cm_3bit.re[i], x_o);
+ end
+ if(cm_3bit.im[i] !== y_o) begin
+ $display("Input: %d --> y_o expected: %d got: %d", i, cm_3bit.im[i], y_o);
+ end
+ end
+
+ 4: begin
+ if(cm_4bit.re[i] !== x_o) begin
+ $display("Input: %d --> x_o expected: %d got: %d", i, cm_4bit.re[i], x_o);
+ end
+ if(cm_4bit.im[i] !== y_o) begin
+ $display("Input: %d --> y_o expected: %d got: %d", i, cm_4bit.im[i], y_o);
+ end
+ end
+
+ 5: begin
+ if(cm_5bit.re[i] !== x_o) begin
+ $display($time, " Input: %d --> x_o expected: %d got: %d", i, cm_5bit.re[i], x_o);
+ end
+ if(cm_5bit.im[i] !== y_o) begin
+ $display($time, " Input: %d --> y_o expected: %d got: %d", i, cm_5bit.im[i], y_o);
+ end
+ end
+
+
+ default: $display("%d is not an implemented bit size", bit);
+ endcase
+
+ end
+
+ end
+endtask
+
+
+endmodule
Index: dmt_tx/trunk/const_encoder/tb/tb_fifo.v
===================================================================
--- dmt_tx/trunk/const_encoder/tb/tb_fifo.v (nonexistent)
+++ dmt_tx/trunk/const_encoder/tb/tb_fifo.v (revision 23)
@@ -0,0 +1,336 @@
+/* *****************************************************************
+ *
+ * This file is part of the
+ *
+ * Tone Order and Constellation Encoder Core.
+ *
+ * Copyright (C) 2007 Guenter Dannoritzer
+ *
+ * This source is free software; you can redistribute it
+ * and/or modify it under the terms of the
+ * GNU General Public License
+ * as published by the Free Software Foundation;
+ * either version 3 of the License,
+ * or (at your option) any later version.
+ *
+ * This source is distributed in the hope
+ * that it will be useful, but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the
+ * GNU General Public License along with this source.
+ * If not, see .
+ *
+ * *****************************************************************/
+module tb_fifo;
+
+parameter AWIDTH = 2;
+parameter DWIDTH = 8;
+parameter TW=10;
+
+
+
+//
+// to interface the dut
+//
+reg clk;
+reg reset;
+reg [DWIDTH-1:0] data_i;
+reg re_i;
+wire empty_o;
+wire full_o;
+wire one_available_o;
+wire two_available_o;
+reg we_i;
+reg [DWIDTH-1:0] data_i;
+reg re_i;
+wire [DWIDTH-1:0] data_o;
+
+
+
+//
+// instantiate the DUT
+//
+fifo #(.AWIDTH(AWIDTH), .DWIDTH(DWIDTH))
+
+ dut ( .clk(clk),
+ .reset(reset),
+ .empty_o(empty_o),
+ .full_o(full_o),
+ .one_available_o(one_available_o),
+ .two_available_o(two_available_o),
+ .we_i(we_i),
+ .data_i(data_i),
+ .re_i(re_i),
+ .data_o(data_o));
+
+
+//
+// local reg/wires
+//
+reg [DWIDTH-1:0] got_data;
+
+//
+// main tests
+//
+
+initial begin
+ clk = 0;
+ we_i = 0;
+ re_i = 0;
+ reset = 0;
+end
+
+always begin
+ #TW clk = ~clk;
+end
+
+//
+// dump signals
+//
+initial begin
+ $dumpfile("tb_fifo.vcd");
+ $dumpvars;
+end
+
+
+initial begin
+ $display("=== Verifing FIFO ===");
+
+ $display("- reset test");
+ test_reset;
+ check_control(5'b0001);
+
+ $display("- verify write followed by read");
+ write_data(8'haa);
+ check_control(5'b0100);
+
+ read_data(got_data);
+ check_result(got_data, 8'haa);
+ check_control(5'b0001);
+
+ // fifo is empty again
+
+ // fill it and only expect after the 4th write a full signal
+
+ $display("- fill FIFO up");
+ // #1
+ write_data(8'h70);
+ check_control(5'b0100);
+ // #2
+ write_data(8'h71);
+ check_control(5'b1100);
+ // #3
+ write_data(8'h72);
+ check_control(5'b1100);
+ // #4
+ write_data(8'h73);
+ check_control(5'b1110);
+
+ $display("- FIFO is full, another write should not have an affect");
+ write_data(8'hab);
+ check_control(5'b1110);
+
+ $display("- verify reading the data from the full FIFO back");
+ // #1
+ read_data(got_data);
+ check_result(got_data, 8'h70);
+ check_control(5'b1100);
+ // #2
+ read_data(got_data);
+ check_result(got_data, 8'h71);
+ check_control(5'b1100);
+ // #3
+ read_data(got_data);
+ check_result(got_data, 8'h72);
+ check_control(5'b0100);
+ // #4
+ read_data(got_data);
+ check_result(got_data, 8'h73);
+ check_control(5'b0001);
+
+
+ $display("= Now test a read/write at the same clock =");
+
+
+ $display("- First have an empty FIFO and do the read/write");
+ // read should fail but write should succeed
+ fork
+ read_data(got_data);
+ write_data(8'h80);
+ join
+ check_control(5'b0100);
+ read_data(got_data);
+ check_result(got_data, 8'h80);
+
+
+ //
+ $display("- Now have one entry in the FIFO and do a read/write");
+ // read should bring the first value back and the written value
+ // should stay
+ write_data(8'h90);
+ fork
+ read_data(got_data);
+ write_data(8'hA0);
+ join
+ check_control(5'b0100);
+ check_result(got_data, 8'h90);
+
+ read_data(got_data);
+ check_result(got_data, 8'hA0);
+ check_control(5'b0001);
+
+
+
+ $display("- Finally fill up the FIFO and to the read/write");
+ // #1
+ write_data(8'h10);
+ check_control(5'b0100);
+ // #2
+ write_data(8'h11);
+ check_control(5'b1100);
+ // #3
+ write_data(8'h12);
+ check_control(5'b1100);
+ // #4
+ write_data(8'h13);
+ check_control(5'b1110);
+
+ // doing the read/write, as the FIFO is full the written value should
+ // not end up in the FIFO
+ fork
+ read_data(got_data);
+ write_data(8'h20);
+ join
+
+ check_control(5'b1100);
+ check_result(got_data, 8'h10);
+
+ // doing a read/write with one empty spot, the read should return the
+ // last but one value and the write should end up in the FIFO
+ fork
+ read_data(got_data);
+ write_data(8'h21);
+ join
+
+ check_control(5'b1100);
+ check_result(got_data, 8'h11);
+
+
+ // so reading back the values, should return the 3 remaining values
+ // #1
+ read_data(got_data);
+ check_result(got_data, 8'h12);
+ check_control(5'b1100);
+ // #2
+ read_data(got_data);
+ check_result(got_data, 8'h13);
+ check_control(5'b0100);
+ // #3
+ read_data(got_data);
+ check_result(got_data, 8'h21);
+ check_control(5'b0001);
+
+ $display("FIFO verification done!");
+
+ $finish();
+
+end
+
+
+
+
+// ////////////////////////////////////////////////////////////////////
+//
+// bus functional models
+//
+// ////////////////////////////////////////////////////////////////////
+
+task test_reset;
+ begin
+ //$display("Testing reset");
+ reset = 0;
+ #10 reset = 1;
+ #20 reset = 0;
+
+end
+endtask
+
+
+// =====================================================================
+// check the expected control line status
+//
+// exp_ctrl[4:0] == {two_available, one_available, full, empty}
+//
+task check_control(input [4:0]exp_ctrl);
+ begin
+
+ //$display("# %d expCtrl: %d", $time, exp_ctrl);
+
+ if(empty_o !== exp_ctrl[0])
+ $display("ERROR! => Expected empty_o == %d, got %d", exp_ctrl[0], empty_o);
+
+ if(full_o !== exp_ctrl[1])
+ $display("ERROR! => Expected full_o == %d, got %d", exp_ctrl[1], full_o);
+
+ if(one_available_o !== exp_ctrl[2])
+ $display("ERROR! => Expected one_available_o == %d, got %d", exp_ctrl[3], one_available_o);
+
+ if(two_available_o !== exp_ctrl[3])
+ $display("ERROR! => Expected two_available_o == %d, got %d", exp_ctrl[4], two_available_o);
+
+ end
+endtask
+
+
+// =====================================================================
+//
+// write data to the fifo
+//
+task write_data(input [DWIDTH-1:0]data);
+ begin
+ //$display("# %d Writing data", $time);
+ @(negedge clk);
+ data_i = data;
+ we_i = 1;
+ @(negedge clk);
+ we_i = 0;
+
+ end
+endtask
+
+// =====================================================================
+//
+// read data from the fifo
+//
+//
+task read_data(output [DWIDTH-1:0]data);
+ begin
+
+ //$display("# %d Reading data", $time);
+ @(negedge clk);
+ re_i = 1;
+ @(negedge clk);
+ data = data_o;
+ re_i = 0;
+
+ end
+endtask
+
+
+// =====================================================================
+//
+// check result
+//
+//
+task check_result(input [DWIDTH-1:0]got, input [DWIDTH-1:0]expected);
+ begin
+ if(got !== expected)
+ $display("ERROR! => Result does not match! Got: %d (%x) expected: %d (%x)", got, got, expected, expected);
+ end
+endtask
+
+endmodule
+
Index: dmt_tx/trunk/const_encoder/Makefile
===================================================================
--- dmt_tx/trunk/const_encoder/Makefile (nonexistent)
+++ dmt_tx/trunk/const_encoder/Makefile (revision 23)
@@ -0,0 +1,45 @@
+CC = iverilog
+SIM = vvp
+
+CFLAGS =-Wall -Irtl/
+
+vpath %.v rtl tb
+vpath %.vh rtl
+
+FIFO = fifo.v \
+ generic_dpram.v
+CONST_ENC = $(FIFO) \
+ const_enc.v
+
+
+
+.PHONY: all sim doc clean
+
+all: sim
+
+
+sim: fifo const_enc
+
+
+const_enc: const_enc.vvp
+ @echo -e "\n--> Simulating $@"
+ $(SIM) $^
+
+const_enc.vvp: tb_const_enc.v const_map_data.v $(CONST_ENC)
+ $(CC) $(CFLAGS) $^ -s tb_const_encoder -o $@
+
+fifo: fifo.vvp
+ @echo -e "\n--> Simulating $@"
+ $(SIM) $^
+
+fifo.vvp: tb_fifo.v $(FIFO)
+ @echo -e "\n--> Compiling $@"
+ $(CC) $(CFLAGS) $^ -s tb_fifo -o $@
+
+doc:
+ $(MAKE) -C doc/
+
+
+clean:
+ rm -f *.vvp
+ $(MAKE) -C doc/ cleantex
Index: dmt_tx/trunk/const_encoder/doc/ConstSpec.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: dmt_tx/trunk/const_encoder/doc/ConstSpec.pdf
===================================================================
--- dmt_tx/trunk/const_encoder/doc/ConstSpec.pdf (nonexistent)
+++ dmt_tx/trunk/const_encoder/doc/ConstSpec.pdf (revision 23)
dmt_tx/trunk/const_encoder/doc/ConstSpec.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: dmt_tx/trunk/gpl.txt
===================================================================
--- dmt_tx/trunk/gpl.txt (nonexistent)
+++ dmt_tx/trunk/gpl.txt (revision 23)
@@ -0,0 +1,674 @@
+ GNU GENERAL PUBLIC LICENSE
+ Version 3, 29 June 2007
+
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+to choose that version for the Program.
+
+ Later license versions may give you additional or different
+permissions. However, no additional obligations are imposed on any
+author or copyright holder as a result of your choosing to follow a
+later version.
+
+ 15. Disclaimer of Warranty.
+
+ THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
+APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
+HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
+OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
+THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
+IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
+ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
+
+ 16. Limitation of Liability.
+
+ IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
+THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
+GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
+USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
+DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
+PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
+EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
+SUCH DAMAGES.
+
+ 17. Interpretation of Sections 15 and 16.
+
+ If the disclaimer of warranty and limitation of liability provided
+above cannot be given local legal effect according to their terms,
+reviewing courts shall apply local law that most closely approximates
+an absolute waiver of all civil liability in connection with the
+Program, unless a warranty or assumption of liability accompanies a
+copy of the Program in return for a fee.
+
+ END OF TERMS AND CONDITIONS
+
+ How to Apply These Terms to Your New Programs
+
+ If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+ To do so, attach the following notices to the program. It is safest
+to attach them to the start of each source file to most effectively
+state the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+
+ Copyright (C)
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+
+Also add information on how to contact you by electronic and paper mail.
+
+ If the program does terminal interaction, make it output a short
+notice like this when it starts in an interactive mode:
+
+ Copyright (C)
+ This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+ This is free software, and you are welcome to redistribute it
+ under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License. Of course, your program's commands
+might be different; for a GUI interface, you would use an "about box".
+
+ You should also get your employer (if you work as a programmer) or school,
+if any, to sign a "copyright disclaimer" for the program, if necessary.
+For more information on this, and how to apply and follow the GNU GPL, see
+ .
+
+ The GNU General Public License does not permit incorporating your program
+into proprietary programs. If your program is a subroutine library, you
+may consider it more useful to permit linking proprietary applications with
+the library. If this is what you want to do, use the GNU Lesser General
+Public License instead of this License. But first, please read
+.
Index: dmt_tx/trunk
===================================================================
--- dmt_tx/trunk (nonexistent)
+++ dmt_tx/trunk (revision 23)
dmt_tx/trunk
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Index: dmt_tx/web_uploads
===================================================================
--- dmt_tx/web_uploads (nonexistent)
+++ dmt_tx/web_uploads (revision 23)
dmt_tx/web_uploads
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## -0,0 +0,0 ##
Index: dmt_tx/branches
===================================================================
--- dmt_tx/branches (nonexistent)
+++ dmt_tx/branches (revision 23)
dmt_tx/branches
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Added: svn:mergeinfo
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Index: dmt_tx/tags/import/doc/src/dmt_tx_part1_modem_spec.sxw
===================================================================
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Index: dmt_tx/tags/import/doc/src/dmt_tx_part1_modem_spec.sxw
===================================================================
--- dmt_tx/tags/import/doc/src/dmt_tx_part1_modem_spec.sxw (nonexistent)
+++ dmt_tx/tags/import/doc/src/dmt_tx_part1_modem_spec.sxw (revision 23)
dmt_tx/tags/import/doc/src/dmt_tx_part1_modem_spec.sxw
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+application/octet-stream
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Index: dmt_tx/tags/import/doc/dmt_tx_part1_modem_spec.pdf
===================================================================
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svn:mime-type = application/octet-stream
Index: dmt_tx/tags/import/doc/dmt_tx_part1_modem_spec.pdf
===================================================================
--- dmt_tx/tags/import/doc/dmt_tx_part1_modem_spec.pdf (nonexistent)
+++ dmt_tx/tags/import/doc/dmt_tx_part1_modem_spec.pdf (revision 23)
dmt_tx/tags/import/doc/dmt_tx_part1_modem_spec.pdf
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Index: dmt_tx/tags/import/bench/vhdl/tb_dmt_mod.vhd
===================================================================
--- dmt_tx/tags/import/bench/vhdl/tb_dmt_mod.vhd (nonexistent)
+++ dmt_tx/tags/import/bench/vhdl/tb_dmt_mod.vhd (revision 23)
@@ -0,0 +1,96 @@
+-------------------------------------------------------------------------------
+-- Title : Testbench for DMT modulator
+-- Project :
+-------------------------------------------------------------------------------
+-- File : tb_dmt_mod.vhd
+-- Author :
+-- Company :
+-- Created : 2004-05-17
+-- Last update: 2004-05-17
+-- Platform :
+-------------------------------------------------------------------------------
+-- Description:
+-------------------------------------------------------------------------------
+-- Copyright (c) 2004
+-------------------------------------------------------------------------------
+-- Revisions : $Id: tb_dmt_mod.vhd,v 1.1.1.1 2004-05-17 19:58:40 dannori Exp $
+-- Date Version Author Description
+-- 2004-05-17 1.0 guenter Created
+-------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity tb_dmt_mod is
+
+ generic (Tpw_clk : time := 5 ns);
+
+end tb_dmt_mod;
+
+architecture arch of tb_dmt_mod is
+
+ component dmt_mod
+ port (
+ clk_i : in std_logic;
+ rst_i : in std_logic;
+ data_en_i : in std_logic;
+ data_i : in std_logic_vector(14 downto 0);
+ conf_we_i : in std_logic;
+ bin_addr_i : in std_logic_vector(7 downto 0);
+ const_size_i : in std_logic_vector(3 downto 0);
+ gain_i : in std_logic_vector(11 downto 0);
+ data_o : out std_logic_vector(15 downto 0));
+
+ end component;
+
+ -- Stimulus signals for DUT
+ signal sig_clk_i : std_logic;
+ signal sig_rst_i : std_logic;
+ signal sig_data_en_i : std_logic;
+ signal sig_data_i : std_logic_vector(14 downto 0);
+ signal sig_conf_we_i : std_logic;
+ signal sig_bin_addr_i : std_logic_vector(7 downto 0);
+ signal sig_const_size_i : std_logic_vector(3 downto 0);
+ signal sig_gain_i : std_logic_vector(11 downto 0);
+ signal sig_data_o : std_logic_vector(15 downto 0);
+
+
+
+begin -- arch
+
+ DUT : dmt_mod
+ port map(
+
+ clk_i => sig_clk_i,
+ rst_i => sig_rst_i,
+ data_en_i => sig_data_en_i,
+ data_i => sig_data_i,
+ conf_we_i => sig_conf_we_i,
+ bin_addr_i => sig_bin_addr_i,
+ const_size_i => sig_const_size_i,
+ gain_i => sig_gain_i,
+ data_o => sig_data_o);
+
+ -----------------------------------------------------------------------------
+ -- clock generator
+ clock_gen : process(sig_clk_i) is
+ begin
+ if sig_clk_i = '0' then
+ sig_clk_i <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
+ end if;
+ end process clock_gen;
+
+
+ -- purpose: ends the simulation after a specified number of clock cycles
+ sim_timing : process
+ begin -- process sim_timing
+ for count in 0 to 10 loop
+ wait until sig_clk_i'event and sig_clk_i = '1';
+ end loop; -- count
+
+ assert sig_clk_i /= '1' report "\n---> Finished simulation!" severity failure;
+ end process sim_timing;
+
+end arch;
Index: dmt_tx/tags/import/rtl/vhdl/dmt_mod.vhd
===================================================================
--- dmt_tx/tags/import/rtl/vhdl/dmt_mod.vhd (nonexistent)
+++ dmt_tx/tags/import/rtl/vhdl/dmt_mod.vhd (revision 23)
@@ -0,0 +1,45 @@
+-------------------------------------------------------------------------------
+-- Title : DMT modulator
+-- Project :
+-------------------------------------------------------------------------------
+-- File : dmt_mod.vhd
+-- Author :
+-- Company :
+-- Created : 2004-05-17
+-- Last update: 2004-05-17
+-- Platform :
+-------------------------------------------------------------------------------
+-- Description:
+-------------------------------------------------------------------------------
+-- Copyright (c) 2004
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2004-05-17 1.0 guenter Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dmt_mod is
+
+ port (
+ clk_i : in std_logic;
+ rst_i : in std_logic;
+ data_en_i : in std_logic; -- enables the data processing mode
+ data_i : in std_logic_vector(14 downto 0); -- input data to the modulator core
+ conf_we_i : in std_logic; -- enables the configuration mode
+ bin_addr_i : in std_logic_vector(7 downto 0); -- addresses the bin configuration
+ const_size_i : in std_logic_vector(3 downto 0); -- constellation size for the addressed bin
+ gain_i : in std_logic_vector(11 downto 0); -- gain value for the addressed bin
+ data_o : out std_logic_vector(15 downto 0)); -- output data from the modulator core
+
+end dmt_mod;
+
+architecture arch of dmt_mod is
+
+begin -- arch
+
+
+
+end arch;
Index: dmt_tx/tags
===================================================================
--- dmt_tx/tags (nonexistent)
+++ dmt_tx/tags (revision 23)
dmt_tx/tags
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##