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URL https://opencores.org/ocsvn/r2000/r2000/trunk

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Rev 22 → Rev 23

/trunk/r2000pl/bench/verilog/tb_r2000_soc.v
242,7 → 242,8
$readmemh("../../../bench/code/opcodes_sraml1.txt", SRAMl.mem1);
$readmemh("../../../bench/code/opcodes_sraml2.txt", SRAMl.mem2);
`else
$readmemh("../../../bench/code/opcodes_sraml.txt", SRAMl.mem);
// $readmemh("../../../bench/code/opcodes_sraml.txt", SRAMl.mem);
$readmemh("../../../bench/code/exception_sraml.txt", SRAMl.mem);
// $readmemh("../../../bench/code/dhry21_sraml.txt", SRAMl.mem);
// $readmemh("../../../bench/code/rtos_sraml.txt", SRAMl.mem);
// $readmemh("../../../bench/code/rs_tak_sraml.txt", SRAMl.mem);
256,7 → 257,8
$readmemh("../../../bench/code/opcodes_sramh1.txt", SRAMh.mem1);
$readmemh("../../../bench/code/opcodes_sramh2.txt", SRAMh.mem2);
`else
$readmemh("../../../bench/code/opcodes_sramh.txt", SRAMh.mem);
// $readmemh("../../../bench/code/opcodes_sramh.txt", SRAMh.mem);
$readmemh("../../../bench/code/exception_sramh.txt", SRAMh.mem);
// $readmemh("../../../bench/code/dhry21_sramh.txt", SRAMh.mem);
// $readmemh("../../../bench/code/rtos_sramh.txt", SRAMh.mem);
// $readmemh("../../../bench/code/rs_tak_sramh.txt", SRAMh.mem);
265,11 → 267,10
// $readmemh("../../../bench/code/torture_sramh.txt", SRAMh.mem);
`endif
clk = 1'b0; rst = 1'b1; sig_int = 6'b0; sig_si = 2'b0;
#1 rst = 1'b1;
#`PERIODE_CLK rst = 1'b0;
clk = `LOW; rst = `HIGH; sig_int = `LOW; sig_si = 2'b0;
#`PERIODE_CLK rst = `LOW;
#(0965*`PERIODE_CLK) sig_int = 1; #(2*`PERIODE_CLK) sig_int = 0;
#((0956-1)*`PERIODE_CLK+20) sig_int = `HIGH; #(1*`PERIODE_CLK) sig_int = `LOW;
end
 
277,9 → 278,9
initial begin
// $monitor("PC:%h ",UUT.wMem_code_addr);
// #(1220*`PERIODE_CLK) // 12.2 us
// #(550*`PERIODE_CLK) // 5.5 us
// #(2000*`PERIODE_CLK) // 20.0 us
#(7500*`PERIODE_CLK) // 75.0 us
// #(150*`PERIODE_CLK) // 1.5 us
#(1300*`PERIODE_CLK) // 13.0 us
// #(7500*`PERIODE_CLK) // 75.0 us
// #(44000*`PERIODE_CLK) // 0.44 ms
// #(100000*`PERIODE_CLK) // 10 ms
// #(20000000*`PERIODE_CLK) // 200 ms
/trunk/r2000pl/rtl/verilog/r2000/define.h
59,7 → 59,7
`define ICACHE // Use the Instruction Cache
`define DCACHE // Use the Data Cache
 
`define EXCEPTION // Co processor 0
`define EXCEPTION // Co processor 0
 
/* Length of memories */
`define TAILLE_CODE 100*1024
286,7 → 286,7
`define RST_VECTOR `dw'hBFC0_0000
`define INT_VECTOR_BEV `dw'hBFC0_0400
`define INT_VECTOR `dw'h0000_0ebc//`dw'h8000_0200
`define INT_VECTOR `dw'h0000_2000//`dw'h8000_0200
`define GRL_VECTOR_BEV `dw'hBFC0_0380
`define GRL_VECTOR `dw'h0000_0ec0//`dw'h8000_0180
/trunk/r2000pl/rtl/verilog/r2000/r2000_cpu_pipe.v
160,8 → 160,8
wire [3:0] ID_cmp_status ;
wire [`SELWIDTH-1:0]ID_mux_branch_sel
`ifdef EXCEPTION
, EX_mux_branch_sel , MEM_mux_branch_sel ;
reg MEM_branch_Slot // Detect branch slot when exception
, EX_mux_branch_sel , MEM_mux_branch_sel , WB_mux_branch_sel;
reg WB_branch_Slot // Detect branch slot when exception
`endif //EXCEPTION
;
241,13 → 241,13
wire IFID_stall , IDEX_stall , EXMEM_stall , MEMWB_stall ;
 
// co-processor 0
wire ID_sig_clt_sys , EX_sig_clt_sys , MEM_sig_clt_sys ;
wire ID_sig_clt_brk , EX_sig_clt_brk , MEM_sig_clt_brk ;
wire ID_sig_clt_sys , EX_sig_clt_sys , MEM_sig_clt_sys , WB_sig_clt_sys;
wire ID_sig_clt_brk , EX_sig_clt_brk , MEM_sig_clt_brk , WB_sig_clt_brk;
wire ID_clt_rfe , EX_clt_rfe , MEM_clt_rfe , WB_clt_rfe ;
wire ID_clt_CoMf ;
wire ID_clt_CoMt , EX_clt_CoMt , MEM_clt_CoMt , WB_clt_CoMt ;
`ifdef EXCEPTION
wire [`dw-1:0] IF_EPC , ID_EPC , EX_EPC , MEM_EPC ;
wire [`dw-1:0] IF_EPC , ID_EPC , EX_EPC , MEM_EPC , WB_EPC ;
reg [4:0] IF_EXC , ID_EXC , EX_EXC , MEM_EXC ;
wire [`dw-1:0] wEPC_Vector ;
255,9 → 255,9
EX_Carry ,
EX_Zero ,
EX_Neg ;
wire EX_sig_ovf , MEM_sig_ovf ;
wire [5:0] MEM_sig_int ;
wire [1:0] MEM_sig_si ;
wire EX_sig_ovf , MEM_sig_ovf , WB_sig_ovf;
wire [5:0] MEM_sig_int , WB_sig_int ;
wire [1:0] MEM_sig_si , WB_sig_si ;
wire wException ;
wire [`dw-1:0] WB_cp0_dout ;
340,12 → 340,12
/* ************** */
/* CONTROL */
/* DATAPATH */
r2000_pipe #(`dw) IFID_pc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IFID_stall) , .flush_i(IFID_flush) , .D_i(IF_PCplus4) , .Q_o(ID_PCplus4) );
r2000_pipe #(`dw) IFID_inst_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IFID_stall) , .flush_i(IFID_flush) , .D_i(mem_code_inst_i) , .Q_o(ID_inst) );
r2000_pipe #(`dw) IFID_pc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IFID_stall) , .flush_i(IFID_flush) , .D_i(IF_PCplus4) , .Q_o(ID_PCplus4) );
r2000_pipe #(`dw) IFID_inst_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IFID_stall) , .flush_i(IFID_flush) , .D_i(mem_code_inst_i) , .Q_o(ID_inst) );
 
`ifdef EXCEPTION
assign IF_EPC = wPC;
r2000_pipe #(`dw) IFID_epc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IFID_stall) , .flush_i(IFID_flush) , .D_i(IF_EPC) , .Q_o(ID_EPC) );
r2000_pipe #(`dw) IFID_epc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IFID_stall) , .flush_i(`CLEAR) , .D_i(IF_EPC) , .Q_o(ID_EPC) );
`endif //EXCEPTION
 
/*======================================================================================================================================================*/
576,25 → 576,25
r2000_pipe #( 1) IDEX_ctl_reg_src_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_clt_reg_src) , .Q_o(EX_clt_reg_src) );
/* DATAPATH */
r2000_pipe #(`dw) IDEX_pc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_PCplus8) , .Q_o(EX_PCplus8) );
r2000_pipe #(`dw) IDEX_pc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_PCplus8) , .Q_o(EX_PCplus8) );
r2000_pipe #(`dw) IDEX_inst_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_inst) , .Q_o(EX_inst) );
r2000_pipe #(`dw) IDEX_rs_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_reg_rs_forward) , .Q_o(EX_reg_rs) );
r2000_pipe #(`dw) IDEX_rt_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_reg_rt_forward) , .Q_o(EX_reg_rt) );
r2000_pipe #(`dw) IDEX_rs_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_reg_rs_forward) , .Q_o(EX_reg_rs) );
r2000_pipe #(`dw) IDEX_rt_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_reg_rt_forward) , .Q_o(EX_reg_rt) );
r2000_pipe #(`dw) IDEX_se_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_signextend) , .Q_o(EX_signextend) );
r2000_pipe #(`dw) IDEX_ze_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_zeroextend) , .Q_o(EX_zeroextend) );
r2000_pipe #(`dw) IDEX_up_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_imup) , .Q_o(EX_imup) );
r2000_pipe #(`iw) IDEX_rd_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_mux_rd_index_out) , .Q_o(EX_rd_index) );
r2000_pipe #(`dw) IDEX_se_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_signextend) , .Q_o(EX_signextend) );
r2000_pipe #(`dw) IDEX_ze_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_zeroextend) , .Q_o(EX_zeroextend) );
r2000_pipe #(`dw) IDEX_up_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_imup) , .Q_o(EX_imup) );
r2000_pipe #(`iw) IDEX_rd_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_mux_rd_index_out) , .Q_o(EX_rd_index) );
`ifdef EXCEPTION
r2000_pipe #( 1) IDEX_sig_brk_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_sig_clt_brk) , .Q_o(EX_sig_clt_brk) );
r2000_pipe #( 1) IDEX_sig_sys_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_sig_clt_sys) , .Q_o(EX_sig_clt_sys) );
r2000_pipe #( 1) IDEX_rfe_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_clt_rfe) , .Q_o(EX_clt_rfe) );
r2000_pipe #( 1) IDEX_comt_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_clt_CoMt) , .Q_o(EX_clt_CoMt) );
r2000_pipe #(`dw) IDEX_epc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_EPC) , .Q_o(EX_EPC) );
r2000_pipe #(`SELWIDTH) IDEX_brc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(IDEX_flush) , .D_i(ID_mux_branch_sel) , .Q_o(EX_mux_branch_sel) );
r2000_pipe #( 1) IDEX_rfe_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_clt_rfe) , .Q_o(EX_clt_rfe) );
r2000_pipe #( 1) IDEX_comt_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_clt_CoMt) , .Q_o(EX_clt_CoMt) );
r2000_pipe #(`dw) IDEX_epc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_EPC) , .Q_o(EX_EPC) );
r2000_pipe #(`SELWIDTH) IDEX_brc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(IDEX_stall) , .flush_i(`CLEAR) , .D_i(ID_mux_branch_sel) , .Q_o(EX_mux_branch_sel) );
`endif //EXCEPTION
/*======================================================================================================================================================*/
/* EX:Execution STAGE */
723,13 → 723,13
`ifdef EXCEPTION
r2000_pipe #( 1) EXMEM_sig_brk_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(EXMEM_stall) , .flush_i(EXMEM_flush) , .D_i(EX_sig_clt_brk) , .Q_o(MEM_sig_clt_brk) );
r2000_pipe #( 1) EXMEM_sig_sys_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(EXMEM_stall) , .flush_i(EXMEM_flush) , .D_i(EX_sig_clt_sys) , .Q_o(MEM_sig_clt_sys) );
r2000_pipe #( 6) EXMEM_sig_int_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(`CLEAR) , .flush_i(EXMEM_flush) , .D_i(sig_int_i) , .Q_o(MEM_sig_int) );
r2000_pipe #( 2) EXMEM_sig_si_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(`CLEAR) , .flush_i(EXMEM_flush) , .D_i(sig_si_i) , .Q_o(MEM_sig_si) );
r2000_pipe #( 6) EXMEM_sig_int_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(`CLEAR) , .flush_i(`CLEAR) , .D_i(sig_int_i) , .Q_o(MEM_sig_int) );
r2000_pipe #( 2) EXMEM_sig_si_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(`CLEAR) , .flush_i(`CLEAR) , .D_i(sig_si_i) , .Q_o(MEM_sig_si) );
r2000_pipe #( 1) EXMEM_sig_ovf_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(EXMEM_stall) , .flush_i(EXMEM_flush) , .D_i(EX_sig_ovf) , .Q_o(MEM_sig_ovf) );
 
r2000_pipe #( 1) EXMEM_comt_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(EXMEM_stall) , .flush_i(EXMEM_flush) , .D_i(EX_clt_CoMt) , .Q_o(MEM_clt_CoMt) );
r2000_pipe #( 1) EXMEM_rfe_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(EXMEM_stall) , .flush_i(EXMEM_flush) , .D_i(EX_clt_rfe) , .Q_o(MEM_clt_rfe) );
r2000_pipe #(`dw) EXMEM_epc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(EXMEM_stall) , .flush_i(EXMEM_flush) , .D_i(EX_EPC) , .Q_o(MEM_EPC) );
r2000_pipe #(`dw) EXMEM_epc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(EXMEM_stall) , .flush_i(`CLEAR) , .D_i(EX_EPC) , .Q_o(MEM_EPC) );
r2000_pipe #(`SELWIDTH) EXMEM_brc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(EXMEM_stall) , .flush_i(EXMEM_flush) , .D_i(EX_mux_branch_sel) , .Q_o(MEM_mux_branch_sel) );
`endif //EXCEPTION
/*======================================================================================================================================================*/
777,9 → 777,9
// Enable
assign mem_data_en_o = MEM_freeze;
// Read write
assign mem_data_wr_o = MEM_ctl_mem_write;
assign mem_data_rd_o = MEM_ctl_mem_read;
// Read write (when freeze or stall; don't let memory operations)
assign mem_data_wr_o = (MEM_freeze) ? MEM_ctl_mem_write : `LOW;
assign mem_data_rd_o = (MEM_freeze) ? MEM_ctl_mem_read : `LOW;
// Adress
assign MemDataAddrInt = MEM_alu_out;
809,16 → 809,46
.out_o (MEM_RegDatain) // the result write back to the registerfile
);
 
/* *************** */
/* MEM/WB PIPELINE */
/* *************** */
/* CONTROL */
// WB
r2000_pipe #( 1) MEMWB_ctl_reg_write_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_ctl_reg_write) , .Q_o(WB_ctl_reg_write) );
/* DATAPATH */
`ifdef DEBUG
r2000_pipe #(`dw) MEMWB_inst_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_inst) , .Q_o(WB_inst) );
`endif//DEBUG
r2000_pipe #(`dw) MEMWB_regdatain_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_RegDatain) , .Q_o(WB_RegDatain) );
r2000_pipe #(`iw) MEMWB_rd_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_rd_index) , .Q_o(WB_rd_index) );
`ifdef EXCEPTION
r2000_pipe #( 1) MEMWB_sig_brk_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_sig_clt_brk) , .Q_o(WB_sig_clt_brk) );
r2000_pipe #( 1) MEMWB_sig_sys_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_sig_clt_sys) , .Q_o(WB_sig_clt_sys) );
r2000_pipe #( 6) MEMWB_sig_int_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(`CLEAR) , .flush_i(`CLEAR) , .D_i(MEM_sig_int) , .Q_o(WB_sig_int) );
r2000_pipe #( 2) MEMWB_sig_si_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(`CLEAR) , .flush_i(`CLEAR) , .D_i(MEM_sig_si) , .Q_o(WB_sig_si) );
r2000_pipe #( 1) MEMWB_sig_ovf_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_sig_ovf) , .Q_o(WB_sig_ovf) );
 
r2000_pipe #( 1) MEMWB_comt_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_clt_CoMt) , .Q_o(WB_clt_CoMt) );
r2000_pipe #( 1) MEMWB_rfe_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_clt_rfe) , .Q_o(WB_clt_rfe) );
r2000_pipe #(`dw) MEMWB_epc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(`CLEAR) , .D_i(MEM_EPC) , .Q_o(WB_EPC) );
r2000_pipe #(`SELWIDTH) MEMWB_brc_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_mux_branch_sel) , .Q_o(WB_mux_branch_sel) );
`endif //EXCEPTION
/*======================================================================================================================================================*/
/* WB:Write Back STAGE */
/*======================================================================================================================================================*/
 
`ifdef EXCEPTION
always@(`CLOCK_EDGE clk_i, `RESET_EDGE rst_i)
begin
if (rst_i == `RESET_ON)
MEM_branch_Slot = `CLEAR;
WB_branch_Slot = `CLEAR;
else
// Branch Slot instruction in MEM stage (see mux_pc)
MEM_branch_Slot = ((MEM_mux_branch_sel == 1) ||
(MEM_mux_branch_sel == 2) ||
(MEM_mux_branch_sel == 3));
// Branch Slot instruction in WB stage (see mux_pc)
WB_branch_Slot = ((WB_mux_branch_sel == 1) ||
(WB_mux_branch_sel == 2) ||
(WB_mux_branch_sel == 3));
end
/*==================================================*/
837,17 → 867,19
.rfe_i (WB_clt_rfe) , // Signal of the rfe instruction
// Exception events signals
.brch_i (MEM_branch_Slot) , // Detect exception in Branch Slot
.brch_i (WB_branch_Slot) , // Detect exception in Branch Slot
.OVF_i (MEM_sig_ovf) , // Overflow exception
.SYS_i (MEM_sig_clt_sys) , // System exception
.INT_i (MEM_sig_int) , // Interrupt interrupt
.SI_i (MEM_sig_si) , //
.OVF_i (WB_sig_ovf) , // Overflow exception
.SYS_i (WB_sig_clt_sys) , // System exception
.INT_i (WB_sig_int) , // Interrupt interrupt
.SI_i (WB_sig_si) , //
// Exception control signals
.Exception_o (wException) , // Exception occured
.EPC_i (MEM_EPC) , // PC to EPC
.EPC_ctn_i (MEM_EPC) , // PC to EPC continue
.EPC_rpt_i (WB_EPC) , // PC to EPC repeat
.PC_vec_o (wEPC_Vector) , // Exception Vector
// System signals
857,27 → 889,6
);
`endif //EXCEPTION
 
/* *************** */
/* MEM/WB PIPELINE */
/* *************** */
/* CONTROL */
// WB
r2000_pipe #( 1) MEMWB_ctl_reg_write_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_ctl_reg_write) , .Q_o(WB_ctl_reg_write) );
/* DATAPATH */
`ifdef DEBUG
r2000_pipe #(`dw) MEMWB_inst_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_inst) , .Q_o(WB_inst) );
`endif//DEBUG
r2000_pipe #(`dw) MEMWB_regdatain_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_RegDatain) , .Q_o(WB_RegDatain) );
r2000_pipe #(`iw) MEMWB_rd_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_rd_index) , .Q_o(WB_rd_index) );
`ifdef EXCEPTION
r2000_pipe #( 1) MEMWB_comt_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_clt_CoMt) , .Q_o(WB_clt_CoMt) );
r2000_pipe #( 1) MEMWB_rfe_pipe (.clk_i(clk_i) , .rst_i(rst_i) , .stall_i(MEMWB_stall) , .flush_i(MEMWB_flush) , .D_i(MEM_clt_rfe) , .Q_o(WB_clt_rfe) );
`endif //EXCEPTION
/*======================================================================================================================================================*/
/* WB:Write Back STAGE */
/*======================================================================================================================================================*/
 
 
endmodule
/trunk/r2000pl/rtl/verilog/r2000/r2000_cp0.v
82,7 → 82,9
// Exception control signals
Exception_o , // Exception occured
EPC_i , // PC to EPC
EPC_rpt_i , // PC to EPC repeat
EPC_ctn_i , // PC to EPC continue
PC_vec_o , // Exception Vector
108,7 → 110,8
input[1:0] SI_i ; //
output Exception_o ;
input[`dw-1:0] EPC_i ;
input[`dw-1:0] EPC_rpt_i ;
input[`dw-1:0] EPC_ctn_i ;
output[`dw-1:0] PC_vec_o ;
input rfe_i ;
144,14 → 147,15
 
reg wStall ;
wire ExceptionP ; // Exception PreComputed
reg Exception ; // Exception occured signal
wire wExceptionDetect; // Exception Detection
reg rExceptionSave ; // Store the Exception signal while pipeline stall
wire ptrSTATUS
// , ptr_CAUSE
// , ptr_EPC
;
wire wException ; // Exception occured signal
 
wire wRepeat ; // Repeat or continue type of exception
wire ptrSTATUS ;
 
reg[`dw-1:0] rPC_vec = `ZERO;
158,29 → 162,32
/* -------------------------------------------------------------- */
/* instances, statements */
/* --------------------- */
 
assign wRepeat = `LOW;
 
// Set "Exception sign" active until all Stalls are completed.
always@(rst_i, stall_i, Exception)
if ((rst_i) || (!stall_i))
wStall = 0;
else if ((stall_i) && Exception )
wStall = 1;
always@(rst_i, stall_i, wException)
if (rst_i || !stall_i)
wStall = `LOW;
else if (stall_i && wException )
wStall = `HIGH;
 
assign {KUo, IEo, KUp, IEp, KUc, IEc} = rSTATUS[5:0];
 
// Exception if Interrupt pending AND Not Masked AND Current Interrupt Enable
// assign Exception = ((IP & IM) || OVF_i || SYS_i || SI_i) && IEc;
 
assign ExceptionP = ((rCAUSE[`IP] & rSTATUS[`IM]) || OVF_i || SYS_i || SI_i) && IEc;
assign wExceptionDetect = ((rCAUSE[`IP] & rSTATUS[`IM]) || OVF_i || SYS_i || SI_i) && IEc;
always@(`CLOCK_EDGE clk_i, `RESET_EDGE rst_i)
if (rst_i)
Exception = `CLEAR;
rExceptionSave = `CLEAR;
else if (wStall)
Exception = Exception;
rExceptionSave = rExceptionSave;
else
Exception = ExceptionP;
rExceptionSave = wExceptionDetect;
assign wException = wExceptionDetect;
// Used for "Stall the pipeline"
assign Exception_o = Exception;
assign Exception_o = wException || rExceptionSave;
/* ************************* */
/* STATUS Register statement */
197,7 → 204,7
rSTATUS = rSTATUS;
else if (ptrSTATUS && rw_i)
rSTATUS = data_i;
else if (Exception)
else if (wException)
rSTATUS[5:0] = {rSTATUS[3:0],2'b0};
else if (rfe_i)
rSTATUS[3:0] = rSTATUS[5:2];
206,9 → 213,8
/* ************************ */
/* CAUSE Register statement */
/* ************************ */
// assign ptr_CAUSE = (addr_rw_i == `CAUSE_adr);
 
always@(`CLOCK_EDGE clk_i, `RESET_EDGE rst_i)
// always@(`CLOCK_EDGE clk_i, `RESET_EDGE rst_i)
always@(rst_i, wStall, wException, INT_i, SI_i)// Asynchrone
begin
if (rst_i) begin
rCAUSE = `ZERO;
215,9 → 221,7
end
else if (wStall)
rCAUSE = rCAUSE;
// else if (ptr_CAUSE && rw_i)
// rCAUSE = data_i;
else if (Exception)
else if (wException)
begin
if (SYS_i) begin
rCAUSE[`ExcCode] = `SYS_MNE;
236,9 → 240,9
/* ************************ */
/* Vector statement: Gated */
/* ************************ */
always@(Exception)
always@(wException)
begin
if (Exception) begin
if (wException) begin
if (SYS_i) begin
if (BEV)
rPC_vec = `GRL_VECTOR_BEV;
260,8 → 264,6
/* ********************** */
/* EPC Register statement */
/* ********************** */
// assign ptr_EPC = (addr_rw_i == `EPC_adr);
always@(`CLOCK_EDGE clk_i, `RESET_EDGE rst_i)
begin
if (rst_i)
268,8 → 270,11
rEPC = `ZERO;
else if (wStall)
rEPC = rEPC;
else if (Exception)
rEPC = EPC_i;// + 4;
else if (wException)
if (wRepeat)
rEPC = EPC_rpt_i; // Repeat
else
rEPC = EPC_ctn_i; // Continue
end
// Ouput
/trunk/r2000pl/doc/spec/MipsR2000-Pipeline_controler.odg Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/r2000pl/sim/rtl_sim/bin/r2000pl.do
98,10 → 98,11
# Simulate #
# -------- #
# the soc processor
vsim -t 1ps tb_r2000_soc
vsim tb_r2000_soc
 
#do {r2000pl_d-cache.udo}
do {r2000pl_exception.udo}
#do {r2000pl_exception.udo}
do {r2000pl_stall-pipeline.udo}
 
# The viewer
view wave
/trunk/release.txt
455,3 → 455,18
 
11-02-2008
- Flush must be on all signals in the pipeline.
 
02-03-2008
- Add "WB_EPC" in the Write Back stage
10-03-2008
- when freeze or stall; don't let memory operations
-
16-03-2008
- Modification on the CP0
- The CP0 is deplaced in the WB stage
- The INT, SI event signals are treated asynchronously in the WB stage
- The rCAUSE register is asynchronous now
- The wException signal is asyncronous instantanously
- Add a repeat/continous treatement (not completed yet)
 
- *** The "INT EXCEPTION NO STALL" work correctly

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