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/sdram_controller/trunk/boards/Microblaze1600E/Microblaze1600E.ucf
0,0 → 1,101
# clocking stuff
NET "clk" IOSTANDARD = LVCMOS33 |LOC = "C9";
NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 20 ns HIGH 40%;
 
#NET "btn_east" IOSTANDARD = LVTTL | LOC = "H13" | PULLDOWN;
NET "rst" IOSTANDARD = LVTTL |LOC = "H13" |PULLDOWN;
#NET "btn_north" IOSTANDARD = LVTTL | LOC = "V4" | PULLDOWN;
#NET "btn_south" IOSTANDARD = LVTTL | LOC = "K17" | PULLDOWN;
#NET "btn_west" IOSTANDARD = LVTTL | LOC = "D18" | PULLDOWN;
#NET "sw<0>" IOSTANDARD = LVTTL | LOC = "L13" | PULLUP;
NET "clke" IOSTANDARD = LVTTL |LOC = "L13" |PULLUP;
#NET "sw<1>" IOSTANDARD = LVTTL | LOC = "L14" | PULLUP;
#NET "sw<2>" IOSTANDARD = LVTTL | LOC = "H18" | PULLUP;
#NET "sw<3>" IOSTANDARD = LVTTL | LOC = "N17" | PULLUP;
# led pinouts
#NET "led<7>" IOSTANDARD = LVTTL |LOC = "F9" |SLEW = SLOW |DRIVE = 8;
#NET "led<6>" IOSTANDARD = LVTTL |LOC = "E9" |SLEW = SLOW |DRIVE = 8;
#NET "led<5>" IOSTANDARD = LVTTL |LOC = "D11" |SLEW = SLOW |DRIVE = 8;
#NET "led<4>" IOSTANDARD = LVTTL |LOC = "C11" |SLEW = SLOW |DRIVE = 8;
#NET "led<3>" IOSTANDARD = LVTTL |LOC = "F11" |SLEW = SLOW |DRIVE = 8;
#NET "led<2>" IOSTANDARD = LVTTL |LOC = "E11" |SLEW = SLOW |DRIVE = 8;
#NET "led<1>" IOSTANDARD = LVTTL |LOC = "E12" |SLEW = SLOW |DRIVE = 8;
#NET "led<0>" IOSTANDARD = LVTTL |LOC = "F12" |SLEW = SLOW |DRIVE = 8;
 
NET LED<0> LOC=D4; # |IOSTANDARD=LVTTL |SLEW=SLOW |DRIVE=8;
NET LED<1> LOC=C3 |IOSTANDARD=LVTTL |SLEW=SLOW |DRIVE=8;
NET LED<2> LOC=D6 |IOSTANDARD=LVTTL |SLEW=SLOW |DRIVE=8;
NET LED<3> LOC=E6 |IOSTANDARD=LVTTL |SLEW=SLOW |DRIVE=8;
NET LED<4> LOC=D13 |IOSTANDARD=LVTTL |SLEW=SLOW |DRIVE=8;
NET LED<5> LOC=A7 |IOSTANDARD=LVTTL |SLEW=SLOW |DRIVE=8;
NET LED<6> LOC=G9 |IOSTANDARD=LVTTL |SLEW=SLOW |DRIVE=8;
NET LED<7> LOC=A8 |IOSTANDARD=LVTTL |SLEW=SLOW |DRIVE=8;
 
#
# sdram pinouts
#
# address lines
NET "dram_addr<12>" LOC = "P2" |IOSTANDARD = SSTL2_I;
NET "dram_addr<11>" LOC = "N5" |IOSTANDARD = SSTL2_I;
NET "dram_addr<10>" LOC = "T2" |IOSTANDARD = SSTL2_I;
NET "dram_addr<9>" LOC = "N4" |IOSTANDARD = SSTL2_I;
NET "dram_addr<8>" LOC = "H2" |IOSTANDARD = SSTL2_I;
NET "dram_addr<7>" LOC = "H1" |IOSTANDARD = SSTL2_I;
NET "dram_addr<6>" LOC = "H3" |IOSTANDARD = SSTL2_I;
NET "dram_addr<5>" LOC = "H4" |IOSTANDARD = SSTL2_I;
NET "dram_addr<4>" LOC = "E4" |IOSTANDARD = SSTL2_I; #F4
NET "dram_addr<3>" LOC = "P1" |IOSTANDARD = SSTL2_I;
NET "dram_addr<2>" LOC = "R2" |IOSTANDARD = SSTL2_I;
NET "dram_addr<1>" LOC = "R3" |IOSTANDARD = SSTL2_I;
NET "dram_addr<0>" LOC = "T1" |IOSTANDARD = SSTL2_I;
 
# data lines
NET "dram_dq<15>" LOC = "H5" |IOSTANDARD = SSTL2_I;
NET "dram_dq<14>" LOC = "H6" |IOSTANDARD = SSTL2_I;
NET "dram_dq<13>" LOC = "G5" |IOSTANDARD = SSTL2_I;
NET "dram_dq<12>" LOC = "G6" |IOSTANDARD = SSTL2_I;
NET "dram_dq<11>" LOC = "F2" |IOSTANDARD = SSTL2_I;
NET "dram_dq<10>" LOC = "F1" |IOSTANDARD = SSTL2_I;
NET "dram_dq<9>" LOC = "E1" |IOSTANDARD = SSTL2_I;
NET "dram_dq<8>" LOC = "E2" |IOSTANDARD = SSTL2_I;
NET "dram_dq<7>" LOC = "M6" |IOSTANDARD = SSTL2_I;
NET "dram_dq<6>" LOC = "M5" |IOSTANDARD = SSTL2_I;
NET "dram_dq<5>" LOC = "M4" |IOSTANDARD = SSTL2_I;
NET "dram_dq<4>" LOC = "M3" |IOSTANDARD = SSTL2_I;
NET "dram_dq<3>" LOC = "L4" |IOSTANDARD = SSTL2_I;
NET "dram_dq<2>" LOC = "L3" |IOSTANDARD = SSTL2_I;
NET "dram_dq<1>" LOC = "L1" |IOSTANDARD = SSTL2_I;
NET "dram_dq<0>" LOC = "L2" |IOSTANDARD = SSTL2_I;
 
# bank lines
NET "dram_bank<0>" LOC = "K5" |IOSTANDARD = SSTL2_I;
NET "dram_bank<1>" LOC = "K6" |IOSTANDARD = SSTL2_I;
 
# command lines
NET "dram_cs" LOC = "K4" |IOSTANDARD = SSTL2_I; #cs
NET "dram_cmd<0>" LOC = "C1" |IOSTANDARD = SSTL2_I; #ras
NET "dram_cmd<1>" LOC = "C2" |IOSTANDARD = SSTL2_I; #cas
NET "dram_cmd<2>" LOC = "D1" |IOSTANDARD = SSTL2_I; #we
# clocks
NET "dram_clkn" LOC = "J4" |IOSTANDARD = SSTL2_I;
NET "dram_clkp" LOC = "J5" |IOSTANDARD = SSTL2_I;
NET "dram_clke" LOC = "K3" |IOSTANDARD = SSTL2_I;
 
# U/D data masks and data strobes
NET "dram_dm<1>" LOC = "J1" |IOSTANDARD = SSTL2_I;
NET "dram_dm<0>" LOC = "J2" |IOSTANDARD = SSTL2_I;
NET "dram_dqs<1>" LOC = "G3" |IOSTANDARD = SSTL2_I;
NET "dram_dqs<0>" LOC = "L6" |IOSTANDARD = SSTL2_I;
 
# prohibited pins related to SDRAM
CONFIG PROHIBIT = D2;
CONFIG PROHIBIT = G4;
CONFIG PROHIBIT = J6;
CONFIG PROHIBIT = L5;
CONFIG PROHIBIT = R4;
 
#
#end sdram pinouts
#
 
/sdram_controller/trunk/boards/Microblaze1600E/Microblaze1600E.xise
0,0 → 1,90
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
 
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
</header>
 
<version xil_pn:ise_version="11.2" xil_pn:schema_version="2"/>
 
<files>
<file xil_pn:name="../../ddr.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../ddr_parameters.vh" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../scratch.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../scratch_isim_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
</file>
<file xil_pn:name="../../sdram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../sdram_init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../sdram_reader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../sdram_support.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../sdram_writer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="Microblaze1600E.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation"/>
</file>
</files>
 
<properties>
<property xil_pn:name="Constraints Entry" xil_pn:value="Constraints Editor"/>
<property xil_pn:name="Device" xil_pn:value="xc3s1600e"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3E"/>
<property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|scratch|impl"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/scratch"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="Microblaze1600E"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e"/>
<property xil_pn:name="Package" xil_pn:value="fg320"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL"/>
<property xil_pn:name="Project Description" xil_pn:value="Project to build a working minimal test application using the DDR controller on the Xilinx Microblaze Starter Kit FPGA developmnet board which includes a Spartan-3E 1600E device. "/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="Architecture|scratch|impl"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="Architecture|scratch_isim_tb|behavior"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="uut"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
<property xil_pn:name="Working Directory" xil_pn:value="C:/FPGA/sdram_controller/trunk/boards/Microblaze1600E"/>
</properties>
 
<bindings/>
 
<libraries/>
 
<partitions/>
 
</project>

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