URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
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/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ram/ram (copy).v
File deleted
an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ram/ram (copy).v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ram/general_dual_port_ram.v
===================================================================
--- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ram/general_dual_port_ram.v (revision 23)
+++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ram/general_dual_port_ram.v (revision 24)
@@ -226,4 +226,57 @@
+/****************
+*simple_dual_port_ram
+*
+*****************/
+
+
+// Quartus II Verilog Template
+// Simple Dual Port RAM with separate read/write addresses and
+// single read/write clock
+
+module simple_dual_port_ram #(
+ parameter Dw=8,
+ parameter Aw=6
+)
+(
+ data,
+ read_addr,
+ write_addr,
+ we,
+ clk,
+ q
+);
+
+ input [Dw-1 :0] data;
+ input [Aw-1 :0] read_addr;
+ input [Aw-1 :0] write_addr;
+ input we;
+ input clk;
+ output reg [Dw-1 :0] q;
+
+
+ // Declare the RAM variable
+ reg [Dw-1:0] ram [2**Aw-1:0];
+
+ always @ (posedge clk)
+ begin
+ // Write
+ if (we)
+ ram[write_addr] <= data;
+
+ // Read (if read_addr == write_addr, return OLD data). To return
+ // NEW data, use = (blocking write) rather than <= (non-blocking write)
+ // in the write assignment. NOTE: NEW data may require extra bypass
+ // logic around the RAM.
+ q <= ram[read_addr];
+ end
+
+endmodule
+
+
+
+
+
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/eth
0,0 → 1,189
#ifndef ${IP}_H |
#define ${IP}_H |
|
#ifndef ETH_BASIC_DEF |
#define ETH_BASIC_DEF |
|
//MODER BITS |
#define ETH_RECSMAL 0x00010000 |
#define ETH_PAD 0x00008000 |
#define ETH_HUGEN 0x00004000 |
#define ETH_CRCEN 0x00002000 |
#define ETH_DLYCRCEN 0x00001000 |
#define ETH_FULLD 0x00000400 |
#define ETH_EXDFREN 0x00000200 |
#define ETH_NOBCKOF 0x00000100 |
#define ETH_LOOPBCK 0x00000080 |
#define ETH_IFG 0x00000040 |
#define ETH_PRO 0x00000020 |
#define ETH_IAM 0x00000010 |
#define ETH_BRO 0x00000008 |
#define ETH_NOPRE 0x00000004 |
#define ETH_TXEN 0x00000002 |
#define ETH_RXEN 0x00000001 |
|
//INTERRUPTS BITS |
#define ETH_RXC 0x00000040 |
#define ETH_TXC 0x00000020 |
#define ETH_BUSY 0x00000010 |
#define ETH_RXE 0x00000008 |
#define ETH_RXB 0x00000004 |
#define ETH_TXE 0x00000002 |
#define ETH_TXB 0x00000001 |
|
//BUFFER DESCRIPTOR BITS |
#define ETH_RXBD_EMPTY 0x00008000 |
#define ETH_RXBD_IRQ 0x00004000 |
#define ETH_RXBD_WRAP 0x00002000 |
#define ETH_RXBD_CF 0x00000100 |
#define ETH_RXBD_MISS 0x00000080 |
#define ETH_RXBD_OR 0x00000040 |
#define ETH_RXBD_IS 0x00000020 |
#define ETH_RXBD_DN 0x00000010 |
#define ETH_RXBD_TL 0x00000008 |
#define ETH_RXBD_SF 0x00000004 |
#define ETH_RXBD_CRC 0x00000002 |
#define ETH_RXBD_LC 0x00000001 |
|
#define ETH_TXBD_READY 0x00008000 |
#define ETH_TXBD_IRQ 0x00004000 |
#define ETH_TXBD_WRAP 0x00002000 |
#define ETH_TXBD_PAD 0x00001000 |
#define ETH_TXBD_CRC 0x00000800 |
#define ETH_TXBD_UR 0x00000100 |
#define ETH_TXBD_RL 0x00000008 |
#define ETH_TXBD_LC 0x00000004 |
#define ETH_TXBD_DF 0x00000002 |
#define ETH_TXBD_CS 0x00000001 |
|
#define HDR_LEN 14 |
#define CRC_LEN 4 |
#define BD_SND ( ETH_TXBD_READY | ETH_TXBD_IRQ | ETH_TXBD_WRAP | ETH_TXBD_PAD | ETH_TXBD_CRC ) |
#define RX_READY ( ETH_RXBD_EMPTY | ETH_RXBD_IRQ | ETH_RXBD_WRAP ) |
#define TX_READY ( ETH_TXBD_IRQ | ETH_TXBD_WRAP | ETH_TXBD_PAD | ETH_TXBD_CRC ) |
|
|
#endif |
|
|
|
//user defines |
#define ${IP}_MAC_ADDR_5 0x55 |
#define ${IP}_MAC_ADDR_4 0x47 |
#define ${IP}_MAC_ADDR_3 0x34 |
#define ${IP}_MAC_ADDR_2 0x22 |
#define ${IP}_MAC_ADDR_1 0x88 |
#define ${IP}_MAC_ADDR_0 0x92 |
|
#define ${IP}_BROADCAST_ADDR_5 0xFF |
#define ${IP}_BROADCAST_ADDR_4 0xFF |
#define ${IP}_BROADCAST_ADDR_3 0xFF |
#define ${IP}_BROADCAST_ADDR_2 0xFF |
#define ${IP}_BROADCAST_ADDR_1 0xFF |
#define ${IP}_BROADCAST_ADDR_0 0xFF |
|
|
|
|
int ${IP}_tx_done; |
int ${IP}_rx_done; |
int ${IP}_rx_len; |
unsigned char ${IP}_tx_packet[1536]; //max length |
unsigned char ${IP}_rx_packet[1536]; |
unsigned char * ethmac_tx_data= & ethmac_tx_packet[HDR_LEN]; |
unsigned char * ethmac_rx_data= & ethmac_rx_packet[HDR_LEN]; |
|
void ${IP}_recv_ack(void) |
{ |
${IP}_rx_done = 0; |
${IP}_rx_len = 0; |
//accept further data (reset RXBD to empty) |
${IP}_RXBD0L = RX_READY; //len = 0 | IRQ & WR = 1 | EMPTY = 1 |
} |
|
void ${IP}_init() |
{ |
//TXEN & RXEN = 1; PAD & CRC = 1; FULLD = 1 |
${IP}_MODER = ETH_TXEN | ETH_RXEN | ETH_PAD | ETH_CRCEN | ETH_FULLD; |
//PHY ADDR = 0x001 |
${IP}_MIIADDR = 0x00000001; |
|
//enable all interrupts |
${IP}_INT_MASK = ETH_RXB | ETH_TXB; |
|
//set MAC ADDR |
${IP}_MAC_ADDR1 = (${IP}_MAC_ADDR_5 << 8) | ${IP}_MAC_ADDR_4; //low word = mac ADDR high word |
${IP}_MAC_ADDR0 = (${IP}_MAC_ADDR_3 << 24) | (${IP}_MAC_ADDR_2 << 16) |
| (${IP}_MAC_ADDR_1 << 8) | ${IP}_MAC_ADDR_0; //mac ADDR rest |
|
//configure TXBD0 |
${IP}_TXBD0H = (unsigned long) ${IP}_tx_packet; //ADDR used for tx_data |
${IP}_TXBD0L = TX_READY; //length = 0 | PAD & CRC = 1 | IRQ & WR = 1 |
|
//configure RXBD0 |
${IP}_RXBD0H = (unsigned long)${IP}_rx_packet; //ADDR used for tx_data |
${IP}_RXBD0L = RX_READY; //len = 0 | IRQ & WR = 1 | EMPTY = 1 |
|
//set txdata |
${IP}_tx_packet[0] = ${IP}_BROADCAST_ADDR_5; |
${IP}_tx_packet[1] = ${IP}_BROADCAST_ADDR_4; |
${IP}_tx_packet[2] = ${IP}_BROADCAST_ADDR_3; |
${IP}_tx_packet[3] = ${IP}_BROADCAST_ADDR_2; |
${IP}_tx_packet[4] = ${IP}_BROADCAST_ADDR_1; |
${IP}_tx_packet[5] = ${IP}_BROADCAST_ADDR_0; |
|
${IP}_tx_packet[6] = ${IP}_MAC_ADDR_5; |
${IP}_tx_packet[7] = ${IP}_MAC_ADDR_4; |
${IP}_tx_packet[8] = ${IP}_MAC_ADDR_3; |
${IP}_tx_packet[9] = ${IP}_MAC_ADDR_2; |
${IP}_tx_packet[10] = ${IP}_MAC_ADDR_1; |
${IP}_tx_packet[11] = ${IP}_MAC_ADDR_0; |
|
//erase interrupts |
${IP}_INT_SOURCE = ETH_RXC | ETH_TXC | ETH_BUSY | ETH_RXE | ETH_RXB | ETH_TXE | ETH_TXB; |
|
${IP}_tx_done = 1; |
${IP}_rx_done = 0; |
${IP}_rx_len = 0; |
${IP}_tx_data = & ${IP}_tx_packet[HDR_LEN]; |
${IP}_rx_data = & ${IP}_rx_packet[HDR_LEN]; |
} |
|
|
int ${IP}_send(int length) |
{ |
if (!${IP}_tx_done) //if previous command not fully processed, bail out |
return -1; |
|
${IP}_tx_done = 0; |
${IP}_tx_packet[12] = length >> 8; |
${IP}_tx_packet[13] = length; |
|
${IP}_TXBD0L = (( 0x0000FFFF & ( length + HDR_LEN ) ) << 16) | BD_SND; |
|
return length; |
} |
|
void ${IP}_interrupt() |
{ |
unsigned long source = ${IP}_INT_SOURCE; |
if ( source & ETH_TXB ) |
{ |
${IP}_tx_done = 1; |
//erase interrupt |
${IP}_INT_SOURCE |= ETH_TXB; |
} |
if ( source & ETH_RXB ) |
{ |
${IP}_rx_done = 1; |
${IP}_rx_len = (${IP}_RXBD0L >> 16) - HDR_LEN - CRC_LEN; |
//erase interrupt |
${IP}_INT_SOURCE |= ETH_RXB; |
} |
} |
|
|
|
|
|
#endif |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_rxethmac.v
0,0 → 1,437
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_rxethmac.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// - Novan Hartadi (novan@vlsi.itb.ac.id) //// |
//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) //// |
//// - Olof Kindgren (olof@opencores.org //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001, 2011 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// 2011-07-06 Olof Kindgren <olof@opencores.org> |
// Add ByteCntEq0 to rxaddrcheck |
// |
// CVS Revision History |
// |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.12 2004/04/26 15:26:23 igorm |
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the |
// previous update of the core. |
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register. |
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER |
// register. (thanks to Mathias and Torbjorn) |
// - Multicast reception was fixed. Thanks to Ulrich Gries |
// |
// Revision 1.11 2004/03/17 09:32:15 igorm |
// Multicast detection fixed. Only the LSB of the first byte is checked. |
// |
// Revision 1.10 2002/11/22 01:57:06 mohor |
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort |
// synchronized. |
// |
// Revision 1.9 2002/11/19 17:35:35 mohor |
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying |
// that a frame was received because of the promiscous mode. |
// |
// Revision 1.8 2002/02/16 07:15:27 mohor |
// Testbench fixed, code simplified, unused signals removed. |
// |
// Revision 1.7 2002/02/15 13:44:28 mohor |
// RxAbort is an output. No need to have is declared as wire. |
// |
// Revision 1.6 2002/02/15 11:17:48 mohor |
// File format changed. |
// |
// Revision 1.5 2002/02/14 20:48:43 billditt |
// Addition of new module eth_addrcheck.v |
// |
// Revision 1.4 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.3 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
// |
// Revision 1.2 2001/09/11 14:17:00 mohor |
// Few little NCSIM warnings fixed. |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// Revision 1.1 2001/06/27 21:26:19 mohor |
// Initial release of the RxEthMAC module. |
// |
// |
// |
// |
// |
|
`include "timescale.v" |
|
|
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, |
HugEn, DlyCrcEn, RxData, RxValid, RxStartFrm, RxEndFrm, |
ByteCnt, ByteCntEq0, ByteCntGreat2, ByteCntMaxFrame, |
CrcError, StateIdle, StatePreamble, StateSFD, StateData, |
MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, |
PassAll, ControlFrmAddressOK |
); |
|
input MRxClk; |
input MRxDV; |
input [3:0] MRxD; |
input Transmitting; |
input HugEn; |
input DlyCrcEn; |
input [15:0] MaxFL; |
input r_IFG; |
input Reset; |
input [47:0] MAC; // Station Address |
input r_Bro; // broadcast disable |
input r_Pro; // promiscuous enable |
input [31:0] r_HASH0; // lower 4 bytes Hash Table |
input [31:0] r_HASH1; // upper 4 bytes Hash Table |
input PassAll; |
input ControlFrmAddressOK; |
|
output [7:0] RxData; |
output RxValid; |
output RxStartFrm; |
output RxEndFrm; |
output [15:0] ByteCnt; |
output ByteCntEq0; |
output ByteCntGreat2; |
output ByteCntMaxFrame; |
output CrcError; |
output StateIdle; |
output StatePreamble; |
output StateSFD; |
output [1:0] StateData; |
output RxAbort; |
output AddressMiss; |
|
reg [7:0] RxData; |
reg RxValid; |
reg RxStartFrm; |
reg RxEndFrm; |
reg Broadcast; |
reg Multicast; |
reg [5:0] CrcHash; |
reg CrcHashGood; |
reg DelayData; |
reg [7:0] LatchedByte; |
reg [7:0] RxData_d; |
reg RxValid_d; |
reg RxStartFrm_d; |
reg RxEndFrm_d; |
|
wire MRxDEqD; |
wire MRxDEq5; |
wire StateDrop; |
wire ByteCntEq1; |
wire ByteCntEq2; |
wire ByteCntEq3; |
wire ByteCntEq4; |
wire ByteCntEq5; |
wire ByteCntEq6; |
wire ByteCntEq7; |
wire ByteCntSmall7; |
wire [31:0] Crc; |
wire Enable_Crc; |
wire Initialize_Crc; |
wire [3:0] Data_Crc; |
wire GenerateRxValid; |
wire GenerateRxStartFrm; |
wire GenerateRxEndFrm; |
wire DribbleRxEndFrm; |
wire [3:0] DlyCrcCnt; |
wire IFGCounterEq24; |
|
assign MRxDEqD = MRxD == 4'hd; |
assign MRxDEq5 = MRxD == 4'h5; |
|
|
// Rx State Machine module |
eth_rxstatem rxstatem1 |
(.MRxClk(MRxClk), |
.Reset(Reset), |
.MRxDV(MRxDV), |
.ByteCntEq0(ByteCntEq0), |
.ByteCntGreat2(ByteCntGreat2), |
.Transmitting(Transmitting), |
.MRxDEq5(MRxDEq5), |
.MRxDEqD(MRxDEqD), |
.IFGCounterEq24(IFGCounterEq24), |
.ByteCntMaxFrame(ByteCntMaxFrame), |
.StateData(StateData), |
.StateIdle(StateIdle), |
.StatePreamble(StatePreamble), |
.StateSFD(StateSFD), |
.StateDrop(StateDrop) |
); |
|
|
// Rx Counters module |
eth_rxcounters rxcounters1 |
(.MRxClk(MRxClk), |
.Reset(Reset), |
.MRxDV(MRxDV), |
.StateIdle(StateIdle), |
.StateSFD(StateSFD), |
.StateData(StateData), |
.StateDrop(StateDrop), |
.StatePreamble(StatePreamble), |
.MRxDEqD(MRxDEqD), |
.DlyCrcEn(DlyCrcEn), |
.DlyCrcCnt(DlyCrcCnt), |
.Transmitting(Transmitting), |
.MaxFL(MaxFL), |
.r_IFG(r_IFG), |
.HugEn(HugEn), |
.IFGCounterEq24(IFGCounterEq24), |
.ByteCntEq0(ByteCntEq0), |
.ByteCntEq1(ByteCntEq1), |
.ByteCntEq2(ByteCntEq2), |
.ByteCntEq3(ByteCntEq3), |
.ByteCntEq4(ByteCntEq4), |
.ByteCntEq5(ByteCntEq5), |
.ByteCntEq6(ByteCntEq6), |
.ByteCntEq7(ByteCntEq7), |
.ByteCntGreat2(ByteCntGreat2), |
.ByteCntSmall7(ByteCntSmall7), |
.ByteCntMaxFrame(ByteCntMaxFrame), |
.ByteCntOut(ByteCnt) |
); |
|
// Rx Address Check |
|
eth_rxaddrcheck rxaddrcheck1 |
(.MRxClk(MRxClk), |
.Reset( Reset), |
.RxData(RxData), |
.Broadcast (Broadcast), |
.r_Bro (r_Bro), |
.r_Pro(r_Pro), |
.ByteCntEq6(ByteCntEq6), |
.ByteCntEq7(ByteCntEq7), |
.ByteCntEq2(ByteCntEq2), |
.ByteCntEq3(ByteCntEq3), |
.ByteCntEq4(ByteCntEq4), |
.ByteCntEq5(ByteCntEq5), |
.HASH0(r_HASH0), |
.HASH1(r_HASH1), |
.ByteCntEq0(ByteCntEq0), |
.CrcHash(CrcHash), |
.CrcHashGood(CrcHashGood), |
.StateData(StateData), |
.Multicast(Multicast), |
.MAC(MAC), |
.RxAbort(RxAbort), |
.RxEndFrm(RxEndFrm), |
.AddressMiss(AddressMiss), |
.PassAll(PassAll), |
.ControlFrmAddressOK(ControlFrmAddressOK) |
); |
|
|
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame); |
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & |
DlyCrcCnt[3:0] < 4'h9; |
|
assign Data_Crc[0] = MRxD[3]; |
assign Data_Crc[1] = MRxD[2]; |
assign Data_Crc[2] = MRxD[1]; |
assign Data_Crc[3] = MRxD[0]; |
|
|
// Connecting module Crc |
eth_crc crcrx |
(.Clk(MRxClk), |
.Reset(Reset), |
.Data(Data_Crc), |
.Enable(Enable_Crc), |
.Initialize(Initialize_Crc), |
.Crc(Crc), |
.CrcError(CrcError) |
); |
|
|
// Latching CRC for use in the hash table |
always @ (posedge MRxClk) |
begin |
CrcHashGood <= StateData[0] & ByteCntEq6; |
end |
|
always @ (posedge MRxClk) |
begin |
if(Reset | StateIdle) |
CrcHash[5:0] <= 6'h0; |
else |
if(StateData[0] & ByteCntEq6) |
CrcHash[5:0] <= Crc[31:26]; |
end |
|
// Output byte stream |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
begin |
RxData_d[7:0] <= 8'h0; |
DelayData <= 1'b0; |
LatchedByte[7:0] <= 8'h0; |
RxData[7:0] <= 8'h0; |
end |
else |
begin |
// Latched byte |
LatchedByte[7:0] <= {MRxD[3:0], LatchedByte[7:4]}; |
DelayData <= StateData[0]; |
|
if(GenerateRxValid) |
// Data goes through only in data state |
RxData_d[7:0] <= LatchedByte[7:0] & {8{|StateData}}; |
else |
if(~DelayData) |
// Delaying data to be valid for two cycles. |
// Zero when not active. |
RxData_d[7:0] <= 8'h0; |
|
RxData[7:0] <= RxData_d[7:0]; // Output data byte |
end |
end |
|
|
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
Broadcast <= 1'b0; |
else |
begin |
if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7) |
Broadcast <= 1'b0; |
else |
if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1) |
Broadcast <= 1'b1; |
else |
if(RxAbort | RxEndFrm) |
Broadcast <= 1'b0; |
end |
end |
|
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
Multicast <= 1'b0; |
else |
begin |
if(StateData[0] & ByteCntEq1 & LatchedByte[0]) |
Multicast <= 1'b1; |
else if(RxAbort | RxEndFrm) |
Multicast <= 1'b0; |
end |
end |
|
|
assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3); |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
begin |
RxValid_d <= 1'b0; |
RxValid <= 1'b0; |
end |
else |
begin |
RxValid_d <= GenerateRxValid; |
RxValid <= RxValid_d; |
end |
end |
|
|
assign GenerateRxStartFrm = StateData[0] & |
((ByteCntEq1 & ~DlyCrcEn) | |
((DlyCrcCnt == 4'h3) & DlyCrcEn)); |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
begin |
RxStartFrm_d <= 1'b0; |
RxStartFrm <= 1'b0; |
end |
else |
begin |
RxStartFrm_d <= GenerateRxStartFrm; |
RxStartFrm <= RxStartFrm_d; |
end |
end |
|
|
assign GenerateRxEndFrm = StateData[0] & |
(~MRxDV & ByteCntGreat2 | ByteCntMaxFrame); |
assign DribbleRxEndFrm = StateData[1] & ~MRxDV & ByteCntGreat2; |
|
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
begin |
RxEndFrm_d <= 1'b0; |
RxEndFrm <= 1'b0; |
end |
else |
begin |
RxEndFrm_d <= GenerateRxEndFrm; |
RxEndFrm <= RxEndFrm_d | DribbleRxEndFrm; |
end |
end |
|
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_spram_256x32.v
0,0 → 1,384
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_spram_256x32.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is available in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001, 2002 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.9 2003/12/05 12:43:06 tadejm |
// Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. |
// |
// Revision 1.8 2003/12/04 14:59:13 simons |
// Lapsus fixed (!we -> ~we). |
// |
// Revision 1.7 2003/11/12 18:24:59 tadejm |
// WISHBONE slave changed and tested from only 32-bit accesss to byte access. |
// |
// Revision 1.6 2003/10/17 07:46:15 markom |
// mbist signals updated according to newest convention |
// |
// Revision 1.5 2003/08/14 16:42:58 simons |
// Artisan ram instance added. |
// |
// Revision 1.4 2002/10/18 17:04:20 tadejm |
// Changed BIST scan signals. |
// |
// Revision 1.3 2002/10/10 16:29:30 mohor |
// BIST added. |
// |
// Revision 1.2 2002/09/23 18:24:31 mohor |
// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). |
// |
// Revision 1.1 2002/07/23 16:36:09 mohor |
// ethernet spram added. So far a generic ram and xilinx RAMB4 are used. |
// |
// |
// |
|
`include "ethmac_defines.v" |
`include "timescale.v" |
|
module eth_spram_256x32( |
// Generic synchronous single-port RAM interface |
clk, rst, ce, we, oe, addr, di, dato |
|
`ifdef ETH_BIST |
, |
// debug chain signals |
mbist_si_i, // bist scan serial in |
mbist_so_o, // bist scan serial out |
mbist_ctrl_i // bist chain shift control |
`endif |
|
|
|
); |
|
// |
// Generic synchronous single-port RAM interface |
// |
input clk; // Clock, rising edge |
input rst; // Reset, active high |
input ce; // Chip enable input, active high |
input [3:0] we; // Write enable input, active high |
input oe; // Output enable input, active high |
input [7:0] addr; // address bus inputs |
input [31:0] di; // input data bus |
output [31:0] dato; // output data bus |
|
`ifdef ETH_BIST |
input mbist_si_i; // bist scan serial in |
output mbist_so_o; // bist scan serial out |
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control |
`endif |
|
`ifdef ETH_XILINX_RAMB4 |
|
/*RAMB4_S16 ram0 |
( |
.DO (do[15:0]), |
.ADDR (addr), |
.DI (di[15:0]), |
.EN (ce), |
.CLK (clk), |
.WE (we), |
.RST (rst) |
); |
|
RAMB4_S16 ram1 |
( |
.DO (do[31:16]), |
.ADDR (addr), |
.DI (di[31:16]), |
.EN (ce), |
.CLK (clk), |
.WE (we), |
.RST (rst) |
);*/ |
|
RAMB4_S8 ram0 |
( |
.DO (dato[7:0]), |
.ADDR ({1'b0, addr}), |
.DI (di[7:0]), |
.EN (ce), |
.CLK (clk), |
.WE (we[0]), |
.RST (rst) |
); |
|
RAMB4_S8 ram1 |
( |
.DO (dato[15:8]), |
.ADDR ({1'b0, addr}), |
.DI (di[15:8]), |
.EN (ce), |
.CLK (clk), |
.WE (we[1]), |
.RST (rst) |
); |
|
RAMB4_S8 ram2 |
( |
.DO (dato[23:16]), |
.ADDR ({1'b0, addr}), |
.DI (di[23:16]), |
.EN (ce), |
.CLK (clk), |
.WE (we[2]), |
.RST (rst) |
); |
|
RAMB4_S8 ram3 |
( |
.DO (dato[31:24]), |
.ADDR ({1'b0, addr}), |
.DI (di[31:24]), |
.EN (ce), |
.CLK (clk), |
.WE (we[3]), |
.RST (rst) |
); |
|
`else // !ETH_XILINX_RAMB4 |
`ifdef ETH_VIRTUAL_SILICON_RAM |
`ifdef ETH_BIST |
//vs_hdsp_256x32_bist ram0_bist |
vs_hdsp_256x32_bw_bist ram0_bist |
`else |
//vs_hdsp_256x32 ram0 |
vs_hdsp_256x32_bw ram0 |
`endif |
( |
.CK (clk), |
.CEN (!ce), |
.WEN (~we), |
.OEN (!oe), |
.ADR (addr), |
.DI (di), |
.DOUT (dato) |
|
`ifdef ETH_BIST |
, |
// debug chain signals |
.mbist_si_i (mbist_si_i), |
.mbist_so_o (mbist_so_o), |
.mbist_ctrl_i (mbist_ctrl_i) |
`endif |
); |
|
`else // !ETH_VIRTUAL_SILICON_RAM |
|
`ifdef ETH_ARTISAN_RAM |
`ifdef ETH_BIST |
//art_hssp_256x32_bist ram0_bist |
art_hssp_256x32_bw_bist ram0_bist |
`else |
//art_hssp_256x32 ram0 |
art_hssp_256x32_bw ram0 |
`endif |
( |
.CLK (clk), |
.CEN (!ce), |
.WEN (~we), |
.OEN (!oe), |
.A (addr), |
.D (di), |
.Q (dato) |
|
`ifdef ETH_BIST |
, |
// debug chain signals |
.mbist_si_i (mbist_si_i), |
.mbist_so_o (mbist_so_o), |
.mbist_ctrl_i (mbist_ctrl_i) |
`endif |
); |
|
`else // !ETH_ARTISAN_RAM |
`ifdef ETH_ALTERA_ALTSYNCRAM |
/* |
altera_spram_256x32 altera_spram_256x32_inst |
( |
.address (addr), |
.wren (ce & we), |
.clock (clk), |
.data (di), |
.q (dato) |
); //exemplar attribute altera_spram_256x32_inst NOOPT TRUE |
|
|
alt_spram_256x32 alt_spram_256x32_inst |
( |
.address (addr), |
.wren (ce & we), |
.clock (clk), |
.data (di), |
.q (dato) |
); |
|
|
single_port_ram #( |
.Dw(32), |
.Aw(8) |
) |
spram |
( |
.data(di), |
.addr(addr), |
.we(ce & we), |
.clk(clk), |
.q(dato) |
); |
|
*/ |
|
|
//localparam RAM_ID = {"ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=",RAM_TAG_STRING}; |
|
altsyncram #( |
.operation_mode("SINGLE_PORT"), |
.width_a(32), |
//.lpm_hint(RAM_ID), |
.read_during_write_mode_mixed_ports("DONT_CARE"), |
.widthad_a(8), |
.width_byteena_a(4) |
//.init_file(INIT_FILE) |
|
) ram_inst( |
.clock0 (clk), |
.address_a (addr), |
.wren_a (ce), |
.data_a (di), |
.q_a (dato), |
.byteena_a (we), |
|
.wren_b ( ), |
.rden_a ( ), |
.rden_b ( ), |
.data_b ( ), |
.address_b ( ), |
.clock1 ( ), |
.clocken0 ( ), |
.clocken1 ( ), |
.clocken2 ( ), |
.clocken3 ( ), |
.aclr0 ( ), |
.aclr1 ( ), |
.byteena_b ( ), |
.addressstall_a ( ), |
.addressstall_b ( ), |
.q_b ( ), |
.eccstatus ( ) |
); |
|
|
|
|
|
|
|
|
|
`else // !ETH_ALTERA_ALTSYNCRAM |
|
|
// |
// Generic single-port synchronous RAM model |
// |
|
// |
// Generic RAM's registers and wires |
// |
reg [ 7: 0] mem0 [255:0]; // RAM content |
reg [15: 8] mem1 [255:0]; // RAM content |
reg [23:16] mem2 [255:0]; // RAM content |
reg [31:24] mem3 [255:0]; // RAM content |
wire [31:0] q; // RAM output |
reg [7:0] raddr; // RAM read address |
// |
// Data output drivers |
// |
assign dato = (oe & ce) ? q : {32{1'bz}}; |
|
// |
// RAM read and write |
// |
|
// read operation |
always@(posedge clk) |
if (ce) |
raddr <= addr; // read address needs to be registered to read clock |
|
assign q = rst ? {32{1'b0}} : {mem3[raddr], |
mem2[raddr], |
mem1[raddr], |
mem0[raddr]}; |
|
// write operation |
always@(posedge clk) |
begin |
if (ce && we[3]) |
mem3[addr] <= di[31:24]; |
if (ce && we[2]) |
mem2[addr] <= di[23:16]; |
if (ce && we[1]) |
mem1[addr] <= di[15: 8]; |
if (ce && we[0]) |
mem0[addr] <= di[ 7: 0]; |
end |
|
// Task prints range of memory |
// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations. |
task print_ram; |
input [7:0] start; |
input [7:0] finish; |
integer rnum; |
begin |
for (rnum={24'd0,start};rnum<={24'd0,finish};rnum=rnum+1) |
$display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]); |
end |
endtask |
|
`endif // !ETH_ALTERA_ALTSYNCRAM |
`endif // !ETH_ARTISAN_RAM |
`endif // !ETH_VIRTUAL_SILICON_RAM |
`endif // !ETH_XILINX_RAMB4 |
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_rxcounters.v
0,0 → 1,217
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_rxcounters.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// - Novan Hartadi (novan@vlsi.itb.ac.id) //// |
//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2002/02/15 11:13:29 mohor |
// Format of the file changed a bit. |
// |
// Revision 1.4 2002/02/14 20:19:41 billditt |
// Modified for Address Checking, |
// addition of eth_addrcheck.v |
// |
// Revision 1.3 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.2 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// Revision 1.1 2001/06/27 21:26:19 mohor |
// Initial release of the RxEthMAC module. |
// |
// |
// |
// |
// |
// |
|
`include "timescale.v" |
|
|
module eth_rxcounters |
( |
MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble, |
MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24, |
ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6, |
ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut |
); |
|
input MRxClk; |
input Reset; |
input MRxDV; |
input StateSFD; |
input [1:0] StateData; |
input MRxDEqD; |
input StateIdle; |
input StateDrop; |
input DlyCrcEn; |
input StatePreamble; |
input Transmitting; |
input HugEn; |
input [15:0] MaxFL; |
input r_IFG; |
|
output IFGCounterEq24; // IFG counter reaches 9600 ns (960 ns) |
output [3:0] DlyCrcCnt; // Delayed CRC counter |
output ByteCntEq0; // Byte counter = 0 |
output ByteCntEq1; // Byte counter = 1 |
output ByteCntEq2; // Byte counter = 2 |
output ByteCntEq3; // Byte counter = 3 |
output ByteCntEq4; // Byte counter = 4 |
output ByteCntEq5; // Byte counter = 5 |
output ByteCntEq6; // Byte counter = 6 |
output ByteCntEq7; // Byte counter = 7 |
output ByteCntGreat2; // Byte counter > 2 |
output ByteCntSmall7; // Byte counter < 7 |
output ByteCntMaxFrame; // Byte counter = MaxFL |
output [15:0] ByteCntOut; // Byte counter |
|
wire ResetByteCounter; |
wire IncrementByteCounter; |
wire ResetIFGCounter; |
wire IncrementIFGCounter; |
wire ByteCntMax; |
|
reg [15:0] ByteCnt; |
reg [3:0] DlyCrcCnt; |
reg [4:0] IFGCounter; |
|
wire [15:0] ByteCntDelayed; |
|
|
|
assign ResetByteCounter = MRxDV & (StateSFD & MRxDEqD | StateData[0] & ByteCntMaxFrame); |
|
assign IncrementByteCounter = ~ResetByteCounter & MRxDV & |
(StatePreamble | StateSFD | StateIdle & ~Transmitting | |
StateData[1] & ~ByteCntMax & ~(DlyCrcEn & |DlyCrcCnt) |
); |
|
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ByteCnt[15:0] <= 16'd0; |
else |
begin |
if(ResetByteCounter) |
ByteCnt[15:0] <= 16'd0; |
else |
if(IncrementByteCounter) |
ByteCnt[15:0] <= ByteCnt[15:0] + 16'd1; |
end |
end |
|
assign ByteCntDelayed = ByteCnt + 16'd4; |
assign ByteCntOut = DlyCrcEn ? ByteCntDelayed : ByteCnt; |
|
assign ByteCntEq0 = ByteCnt == 16'd0; |
assign ByteCntEq1 = ByteCnt == 16'd1; |
assign ByteCntEq2 = ByteCnt == 16'd2; |
assign ByteCntEq3 = ByteCnt == 16'd3; |
assign ByteCntEq4 = ByteCnt == 16'd4; |
assign ByteCntEq5 = ByteCnt == 16'd5; |
assign ByteCntEq6 = ByteCnt == 16'd6; |
assign ByteCntEq7 = ByteCnt == 16'd7; |
assign ByteCntGreat2 = ByteCnt > 16'd2; |
assign ByteCntSmall7 = ByteCnt < 16'd7; |
assign ByteCntMax = ByteCnt == 16'hffff; |
assign ByteCntMaxFrame = ByteCnt == MaxFL[15:0] & ~HugEn; |
|
|
assign ResetIFGCounter = StateSFD & MRxDV & MRxDEqD | StateDrop; |
|
assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24; |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
IFGCounter[4:0] <= 5'h0; |
else |
begin |
if(ResetIFGCounter) |
IFGCounter[4:0] <= 5'h0; |
else |
if(IncrementIFGCounter) |
IFGCounter[4:0] <= IFGCounter[4:0] + 5'd1; |
end |
end |
|
|
|
assign IFGCounterEq24 = (IFGCounter[4:0] == 5'h18) | r_IFG; // 24*400 = 9600 ns or r_IFG is set to 1 |
|
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
DlyCrcCnt[3:0] <= 4'h0; |
else |
begin |
if(DlyCrcCnt[3:0] == 4'h9) |
DlyCrcCnt[3:0] <= 4'h0; |
else |
if(DlyCrcEn & StateSFD) |
DlyCrcCnt[3:0] <= 4'h1; |
else |
if(DlyCrcEn & (|DlyCrcCnt[3:0])) |
DlyCrcCnt[3:0] <= DlyCrcCnt[3:0] + 4'd1; |
end |
end |
|
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_txethmac.v
0,0 → 1,490
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_txethmac.v //// |
/// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// - Novan Hartadi (novan@vlsi.itb.ac.id) //// |
//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2003/01/30 13:33:24 mohor |
// When padding was enabled and crc disabled, frame was not ended correctly. |
// |
// Revision 1.7 2002/02/26 16:24:01 mohor |
// RetryCntLatched was unused and removed from design |
// |
// Revision 1.6 2002/02/22 12:56:35 mohor |
// Retry is not activated when a Tx Underrun occured |
// |
// Revision 1.5 2002/02/11 09:18:22 mohor |
// Tx status is written back to the BD. |
// |
// Revision 1.4 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.3 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
// |
// Revision 1.2 2001/09/11 14:17:00 mohor |
// Few little NCSIM warnings fixed. |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// Revision 1.3 2001/06/19 18:16:40 mohor |
// TxClk changed to MTxClk (as discribed in the documentation). |
// Crc changed so only one file can be used instead of two. |
// |
// Revision 1.2 2001/06/19 10:38:08 mohor |
// Minor changes in header. |
// |
// Revision 1.1 2001/06/19 10:27:58 mohor |
// TxEthMAC initial release. |
// |
// |
// |
|
`include "timescale.v" |
|
|
module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense, |
Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT, |
IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn, |
MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit, |
ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured, |
LateCollision, DeferIndication, StatePreamble, StateData |
|
); |
|
|
input MTxClk; // Transmit clock (from PHY) |
input Reset; // Reset |
input TxStartFrm; // Transmit packet start frame |
input TxEndFrm; // Transmit packet end frame |
input TxUnderRun; // Transmit packet under-run |
input [7:0] TxData; // Transmit packet data byte |
input CarrierSense; // Carrier sense (synchronized) |
input Collision; // Collision (synchronized) |
input Pad; // Pad enable (from register) |
input CrcEn; // Crc enable (from register) |
input FullD; // Full duplex (from register) |
input HugEn; // Huge packets enable (from register) |
input DlyCrcEn; // Delayed Crc enabled (from register) |
input [15:0] MinFL; // Minimum frame length (from register) |
input [15:0] MaxFL; // Maximum frame length (from register) |
input [6:0] IPGT; // Back to back transmit inter packet gap parameter (from register) |
input [6:0] IPGR1; // Non back to back transmit inter packet gap parameter IPGR1 (from register) |
input [6:0] IPGR2; // Non back to back transmit inter packet gap parameter IPGR2 (from register) |
input [5:0] CollValid; // Valid collision window (from register) |
input [3:0] MaxRet; // Maximum retry number (from register) |
input NoBckof; // No backoff (from register) |
input ExDfrEn; // Excessive defferal enable (from register) |
|
output [3:0] MTxD; // Transmit nibble (to PHY) |
output MTxEn; // Transmit enable (to PHY) |
output MTxErr; // Transmit error (to PHY) |
output TxDone; // Transmit packet done (to RISC) |
output TxRetry; // Transmit packet retry (to RISC) |
output TxAbort; // Transmit packet abort (to RISC) |
output TxUsedData; // Transmit packet used data (to RISC) |
output WillTransmit; // Will transmit (to RxEthMAC) |
output ResetCollision; // Reset Collision (for synchronizing collision) |
output [3:0] RetryCnt; // Latched Retry Counter for tx status purposes |
output StartTxDone; |
output StartTxAbort; |
output MaxCollisionOccured; |
output LateCollision; |
output DeferIndication; |
output StatePreamble; |
output [1:0] StateData; |
|
reg [3:0] MTxD; |
reg MTxEn; |
reg MTxErr; |
reg TxDone; |
reg TxRetry; |
reg TxAbort; |
reg TxUsedData; |
reg WillTransmit; |
reg ColWindow; |
reg StopExcessiveDeferOccured; |
reg [3:0] RetryCnt; |
reg [3:0] MTxD_d; |
reg StatusLatch; |
reg PacketFinished_q; |
reg PacketFinished; |
|
|
wire ExcessiveDeferOccured; |
wire StartIPG; |
wire StartPreamble; |
wire [1:0] StartData; |
wire StartFCS; |
wire StartJam; |
wire StartDefer; |
wire StartBackoff; |
wire StateDefer; |
wire StateIPG; |
wire StateIdle; |
wire StatePAD; |
wire StateFCS; |
wire StateJam; |
wire StateJam_q; |
wire StateBackOff; |
wire StateSFD; |
wire StartTxRetry; |
wire UnderRun; |
wire TooBig; |
wire [31:0] Crc; |
wire CrcError; |
wire [2:0] DlyCrcCnt; |
wire [15:0] NibCnt; |
wire NibCntEq7; |
wire NibCntEq15; |
wire NibbleMinFl; |
wire ExcessiveDefer; |
wire [15:0] ByteCnt; |
wire MaxFrame; |
wire RetryMax; |
wire RandomEq0; |
wire RandomEqByteCnt; |
wire PacketFinished_d; |
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|
|
assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS); |
|
assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured; |
|
assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & ~CrcEn); |
|
assign UnderRun = StateData[0] & TxUnderRun & ~Collision; |
|
assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS); |
|
// assign StartTxRetry = StartJam & (ColWindow & ~RetryMax); |
assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun; |
|
assign LateCollision = StartJam & ~ColWindow & ~UnderRun; |
|
assign MaxCollisionOccured = StartJam & ColWindow & RetryMax; |
|
assign StateSFD = StatePreamble & NibCntEq15; |
|
assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured; |
|
|
// StopExcessiveDeferOccured |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
StopExcessiveDeferOccured <= 1'b0; |
else |
begin |
if(~TxStartFrm) |
StopExcessiveDeferOccured <= 1'b0; |
else |
if(ExcessiveDeferOccured) |
StopExcessiveDeferOccured <= 1'b1; |
end |
end |
|
|
// Collision Window |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
ColWindow <= 1'b1; |
else |
begin |
if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0])) |
ColWindow <= 1'b0; |
else |
if(StateIdle | StateIPG) |
ColWindow <= 1'b1; |
end |
end |
|
|
// Start Window |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
StatusLatch <= 1'b0; |
else |
begin |
if(~TxStartFrm) |
StatusLatch <= 1'b0; |
else |
if(ExcessiveDeferOccured | StateIdle) |
StatusLatch <= 1'b1; |
end |
end |
|
|
// Transmit packet used data |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxUsedData <= 1'b0; |
else |
TxUsedData <= |StartData; |
end |
|
|
// Transmit packet done |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxDone <= 1'b0; |
else |
begin |
if(TxStartFrm & ~StatusLatch) |
TxDone <= 1'b0; |
else |
if(StartTxDone) |
TxDone <= 1'b1; |
end |
end |
|
|
// Transmit packet retry |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxRetry <= 1'b0; |
else |
begin |
if(TxStartFrm & ~StatusLatch) |
TxRetry <= 1'b0; |
else |
if(StartTxRetry) |
TxRetry <= 1'b1; |
end |
end |
|
|
// Transmit packet abort |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxAbort <= 1'b0; |
else |
begin |
if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured) |
TxAbort <= 1'b0; |
else |
if(StartTxAbort) |
TxAbort <= 1'b1; |
end |
end |
|
|
// Retry counter |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
RetryCnt[3:0] <= 4'h0; |
else |
begin |
if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun |
| StateJam & NibCntEq7 & (~ColWindow | RetryMax)) |
RetryCnt[3:0] <= 4'h0; |
else |
if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt) |
RetryCnt[3:0] <= RetryCnt[3:0] + 1; |
end |
end |
|
|
assign RetryMax = RetryCnt[3:0] == MaxRet[3:0]; |
|
|
// Transmit nibble |
always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or |
Crc or NibCntEq15) |
begin |
if(StateData[0]) |
MTxD_d[3:0] = TxData[3:0]; // Lower nibble |
else |
if(StateData[1]) |
MTxD_d[3:0] = TxData[7:4]; // Higher nibble |
else |
if(StateFCS) |
MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]}; // Crc |
else |
if(StateJam) |
MTxD_d[3:0] = 4'h9; // Jam pattern |
else |
if(StatePreamble) |
if(NibCntEq15) |
MTxD_d[3:0] = 4'hd; // SFD |
else |
MTxD_d[3:0] = 4'h5; // Preamble |
else |
MTxD_d[3:0] = 4'h0; |
end |
|
|
// Transmit Enable |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
MTxEn <= 1'b0; |
else |
MTxEn <= StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam; |
end |
|
|
// Transmit nibble |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
MTxD[3:0] <= 4'h0; |
else |
MTxD[3:0] <= MTxD_d[3:0]; |
end |
|
|
// Transmit error |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
MTxErr <= 1'b0; |
else |
MTxErr <= TooBig | UnderRun; |
end |
|
|
// WillTransmit |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
WillTransmit <= 1'b0; |
else |
WillTransmit <= StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam; |
end |
|
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assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured; |
|
|
// Packet finished |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
begin |
PacketFinished <= 1'b0; |
PacketFinished_q <= 1'b0; |
end |
else |
begin |
PacketFinished <= PacketFinished_d; |
PacketFinished_q <= PacketFinished; |
end |
end |
|
|
// Connecting module Counters |
eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData), |
.StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff), |
.StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG), |
.StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk), |
.Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn), |
.PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff), |
.StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer), |
.NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl), |
.DlyCrcCnt(DlyCrcCnt) |
); |
|
|
// Connecting module StateM |
eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense), |
.NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD), |
.TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision), |
.UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7), |
.NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn), |
.NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax), |
.NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle), |
.StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD), |
.StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff), |
.StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff), |
.StartDefer(StartDefer), .DeferIndication(DeferIndication), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG) |
); |
|
|
wire Enable_Crc; |
wire [3:0] Data_Crc; |
wire Initialize_Crc; |
|
assign Enable_Crc = ~StateFCS; |
|
assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0; |
assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0; |
assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0; |
assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0; |
|
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt); |
|
|
// Connecting module Crc |
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc), |
.Crc(Crc), .CrcError(CrcError) |
); |
|
|
// Connecting module Random |
eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt), |
.NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt)); |
|
|
|
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_wishbone.v
0,0 → 1,2698
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_wishbone.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is available in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001, 2002 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.57 2005/02/21 11:35:33 igorm |
// Defer indication fixed. |
// |
// Revision 1.56 2004/04/30 10:30:00 igorm |
// Accidently deleted line put back. |
// |
// Revision 1.55 2004/04/26 15:26:23 igorm |
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the |
// previous update of the core. |
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register. |
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER |
// register. (thanks to Mathias and Torbjorn) |
// - Multicast reception was fixed. Thanks to Ulrich Gries |
// |
// Revision 1.54 2003/11/12 18:24:59 tadejm |
// WISHBONE slave changed and tested from only 32-bit accesss to byte access. |
// |
// Revision 1.53 2003/10/17 07:46:17 markom |
// mbist signals updated according to newest convention |
// |
// Revision 1.52 2003/01/30 14:51:31 mohor |
// Reset has priority in some flipflops. |
// |
// Revision 1.51 2003/01/30 13:36:22 mohor |
// A new bug (entered with previous update) fixed. When abort occured sometimes |
// data transmission was blocked. |
// |
// Revision 1.50 2003/01/22 13:49:26 tadejm |
// When control packets were received, they were ignored in some cases. |
// |
// Revision 1.49 2003/01/21 12:09:40 mohor |
// When receiving normal data frame and RxFlow control was switched on, RXB |
// interrupt was not set. |
// |
// Revision 1.48 2003/01/20 12:05:26 mohor |
// When in full duplex, transmit was sometimes blocked. Fixed. |
// |
// Revision 1.47 2002/11/22 13:26:21 mohor |
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used |
// anywhere. Removed. |
// |
// Revision 1.46 2002/11/22 01:57:06 mohor |
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort |
// synchronized. |
// |
// Revision 1.45 2002/11/19 17:33:34 mohor |
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying |
// that a frame was received because of the promiscous mode. |
// |
// Revision 1.44 2002/11/13 22:21:40 tadejm |
// RxError is not generated when small frame reception is enabled and small |
// frames are received. |
// |
// Revision 1.43 2002/10/18 20:53:34 mohor |
// case changed to casex. |
// |
// Revision 1.42 2002/10/18 17:04:20 tadejm |
// Changed BIST scan signals. |
// |
// Revision 1.41 2002/10/18 15:42:09 tadejm |
// Igor added WB burst support and repaired BUG when handling TX under-run and retry. |
// |
// Revision 1.40 2002/10/14 16:07:02 mohor |
// TxStatus is written after last access to the TX fifo is finished (in case of abort |
// or retry). TxDone is fixed. |
// |
// Revision 1.39 2002/10/11 15:35:20 mohor |
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, |
// TxDone and TxRetry are generated after the current WISHBONE access is |
// finished. |
// |
// Revision 1.38 2002/10/10 16:29:30 mohor |
// BIST added. |
// |
// Revision 1.37 2002/09/11 14:18:46 mohor |
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. |
// |
// Revision 1.36 2002/09/10 13:48:46 mohor |
// Reception is possible after RxPointer is read and not after BD is read. For |
// that reason RxBDReady is changed to RxReady. |
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame |
// comes, interrupt is generated. |
// |
// Revision 1.35 2002/09/10 10:35:23 mohor |
// Ethernet debug registers removed. |
// |
// Revision 1.34 2002/09/08 16:31:49 mohor |
// Async reset for WB_ACK_O removed (when core was in reset, it was |
// impossible to access BDs). |
// RxPointers and TxPointers names changed to be more descriptive. |
// TxUnderRun synchronized. |
// |
// Revision 1.33 2002/09/04 18:47:57 mohor |
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals |
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal |
// was not used OK. |
// |
// Revision 1.32 2002/08/14 19:31:48 mohor |
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No |
// need to multiply or devide any more. |
// |
// Revision 1.31 2002/07/25 18:29:01 mohor |
// WriteRxDataToMemory signal changed so end of frame (when last word is |
// written to fifo) is changed. |
// |
// Revision 1.30 2002/07/23 15:28:31 mohor |
// Ram , used for BDs changed from generic_spram to eth_spram_256x32. |
// |
// Revision 1.29 2002/07/20 00:41:32 mohor |
// ShiftEnded synchronization changed. |
// |
// Revision 1.28 2002/07/18 16:11:46 mohor |
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. |
// |
// Revision 1.27 2002/07/11 02:53:20 mohor |
// RxPointer bug fixed. |
// |
// Revision 1.26 2002/07/10 13:12:38 mohor |
// Previous bug wasn't succesfully removed. Now fixed. |
// |
// Revision 1.25 2002/07/09 23:53:24 mohor |
// Master state machine had a bug when switching from master write to |
// master read. |
// |
// Revision 1.24 2002/07/09 20:44:41 mohor |
// m_wb_cyc_o signal released after every single transfer. |
// |
// Revision 1.23 2002/05/03 10:15:50 mohor |
// Outputs registered. Reset changed for eth_wishbone module. |
// |
// Revision 1.22 2002/04/24 08:52:19 mohor |
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision" |
// bug fixed. |
// |
// Revision 1.21 2002/03/29 16:18:11 lampret |
// Small typo fixed. |
// |
// Revision 1.20 2002/03/25 16:19:12 mohor |
// Any address can be used for Tx and Rx BD pointers. Address does not need |
// to be aligned. |
// |
// Revision 1.19 2002/03/19 12:51:50 mohor |
// Comments in Slovene language removed. |
// |
// Revision 1.18 2002/03/19 12:46:52 mohor |
// casex changed with case, fifo reset changed. |
// |
// Revision 1.17 2002/03/09 16:08:45 mohor |
// rx_fifo was not always cleared ok. Fixed. |
// |
// Revision 1.16 2002/03/09 13:51:20 mohor |
// Status was not latched correctly sometimes. Fixed. |
// |
// Revision 1.15 2002/03/08 06:56:46 mohor |
// Big Endian problem when sending frames fixed. |
// |
// Revision 1.14 2002/03/02 19:12:40 mohor |
// Byte ordering changed (Big Endian used). casex changed with case because |
// Xilinx Foundation had problems. Tested in HW. It WORKS. |
// |
// Revision 1.13 2002/02/26 16:59:55 mohor |
// Small fixes for external/internal DMA missmatches. |
// |
// Revision 1.12 2002/02/26 16:22:07 mohor |
// Interrupts changed |
// |
// Revision 1.11 2002/02/15 17:07:39 mohor |
// Status was not written correctly when frames were discarted because of |
// address mismatch. |
// |
// Revision 1.10 2002/02/15 12:17:39 mohor |
// RxStartFrm cleared when abort or retry comes. |
// |
// Revision 1.9 2002/02/15 11:59:10 mohor |
// Changes that were lost when updating from 1.5 to 1.8 fixed. |
// |
// Revision 1.8 2002/02/14 20:54:33 billditt |
// Addition of new module eth_addrcheck.v |
// |
// Revision 1.7 2002/02/12 17:03:47 mohor |
// RxOverRun added to statuses. |
// |
// Revision 1.6 2002/02/11 09:18:22 mohor |
// Tx status is written back to the BD. |
// |
// Revision 1.5 2002/02/08 16:21:54 mohor |
// Rx status is written back to the BD. |
// |
// Revision 1.4 2002/02/06 14:10:21 mohor |
// non-DMA host interface added. Select the right configutation in eth_defines. |
// |
// Revision 1.3 2002/02/05 16:44:39 mohor |
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 |
// MHz. Statuses, overrun, control frame transmission and reception still need |
// to be fixed. |
// |
// Revision 1.2 2002/02/01 12:46:51 mohor |
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be |
// added. |
// |
// Revision 1.1 2002/01/23 10:47:59 mohor |
// Initial version. Equals to eth_wishbonedma.v at this moment. |
// |
// |
// |
|
`include "ethmac_defines.v" |
`include "timescale.v" |
|
|
module eth_wishbone |
( |
|
// WISHBONE common |
WB_CLK_I, WB_DAT_I, WB_DAT_O, |
|
// WISHBONE slave |
WB_ADR_I, WB_WE_I, WB_ACK_O, |
BDCs, |
|
Reset, |
|
// WISHBONE master |
m_wb_adr_o, m_wb_sel_o, m_wb_we_o, |
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o, |
m_wb_stb_o, m_wb_ack_i, m_wb_err_i, |
|
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o, m_wb_bte_o, |
`endif |
|
//TX |
MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData, |
TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn, |
PerPacketPad, |
|
//RX |
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, |
RxStatusWriteLatched_sync2, |
|
// Register |
r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll, |
|
// Interrupts |
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, |
|
// Rx Status |
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble, |
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, |
AddressMiss, |
ReceivedPauseFrm, |
|
// Tx Status |
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched, |
CarrierSenseLost |
|
// Bist |
`ifdef ETH_BIST |
, |
// debug chain signals |
mbist_si_i, // bist scan serial in |
mbist_so_o, // bist scan serial out |
mbist_ctrl_i // bist chain shift control |
`endif |
|
`ifdef WISHBONE_DEBUG |
, |
dbg_dat0 |
`endif |
|
|
); |
|
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH; |
parameter TX_FIFO_DEPTH = `ETH_TX_FIFO_DEPTH; |
parameter TX_FIFO_CNT_WIDTH = `ETH_TX_FIFO_CNT_WIDTH; |
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH; |
parameter RX_FIFO_DEPTH = `ETH_RX_FIFO_DEPTH; |
parameter RX_FIFO_CNT_WIDTH = `ETH_RX_FIFO_CNT_WIDTH; |
|
// WISHBONE common |
input WB_CLK_I; // WISHBONE clock |
input [31:0] WB_DAT_I; // WISHBONE data input |
output [31:0] WB_DAT_O; // WISHBONE data output |
|
// WISHBONE slave |
input [9:2] WB_ADR_I; // WISHBONE address input |
input WB_WE_I; // WISHBONE write enable input |
input [3:0] BDCs; // Buffer descriptors are selected |
output WB_ACK_O; // WISHBONE acknowledge output |
|
// WISHBONE master |
output [29:0] m_wb_adr_o; // |
output [3:0] m_wb_sel_o; // |
output m_wb_we_o; // |
output [31:0] m_wb_dat_o; // |
output m_wb_cyc_o; // |
output m_wb_stb_o; // |
input [31:0] m_wb_dat_i; // |
input m_wb_ack_i; // |
input m_wb_err_i; // |
|
`ifdef ETH_WISHBONE_B3 |
output [2:0] m_wb_cti_o; // Cycle Type Identifier |
output [1:0] m_wb_bte_o; // Burst Type Extension |
reg [2:0] m_wb_cti_o; // Cycle Type Identifier |
`endif |
|
input Reset; // Reset signal |
|
// Rx Status signals |
input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode |
input LatchedCrcError; // CRC error |
input RxLateCollision; // Late collision occured while receiving frame |
input ShortFrame; // Frame shorter then the minimum size |
// (r_MinFL) was received while small |
// packets are enabled (r_RecSmall) |
input DribbleNibble; // Extra nibble received |
input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL |
input [15:0] RxLength; // Length of the incoming frame |
input LoadRxStatus; // Rx status was loaded |
input ReceivedPacketGood; // Received packet's length and CRC are |
// good |
input AddressMiss; // When a packet is received AddressMiss |
// status is written to the Rx BD |
input r_RxFlow; |
input r_PassAll; |
input ReceivedPauseFrm; |
|
// Tx Status signals |
input [3:0] RetryCntLatched; // Latched Retry Counter |
input RetryLimit; // Retry limit reached (Retry Max value +1 |
// attempts were made) |
input LateCollLatched; // Late collision occured |
input DeferLatched; // Defer indication (Frame was defered |
// before sucessfully sent) |
output RstDeferLatched; |
input CarrierSenseLost; // Carrier Sense was lost during the |
// frame transmission |
|
// Tx |
input MTxClk; // Transmit clock (from PHY) |
input TxUsedData; // Transmit packet used data |
input TxRetry; // Transmit packet retry |
input TxAbort; // Transmit packet abort |
input TxDone; // Transmission ended |
output TxStartFrm; // Transmit packet start frame |
output TxEndFrm; // Transmit packet end frame |
output [7:0] TxData; // Transmit packet data byte |
output TxUnderRun; // Transmit packet under-run |
output PerPacketCrcEn; // Per packet crc enable |
output PerPacketPad; // Per packet pading |
|
// Rx |
input MRxClk; // Receive clock (from PHY) |
input [7:0] RxData; // Received data byte (from PHY) |
input RxValid; // |
input RxStartFrm; // |
input RxEndFrm; // |
input RxAbort; // This signal is set when address doesn't |
// match. |
output RxStatusWriteLatched_sync2; |
|
//Register |
input r_TxEn; // Transmit enable |
input r_RxEn; // Receive enable |
input [7:0] r_TxBDNum; // Receive buffer descriptor number |
|
// Interrupts |
output TxB_IRQ; |
output TxE_IRQ; |
output RxB_IRQ; |
output RxE_IRQ; |
output Busy_IRQ; |
|
|
// Bist |
`ifdef ETH_BIST |
input mbist_si_i; // bist scan serial in |
output mbist_so_o; // bist scan serial out |
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control |
`endif |
|
`ifdef WISHBONE_DEBUG |
output [31:0] dbg_dat0; |
`endif |
|
|
reg TxB_IRQ; |
reg TxE_IRQ; |
reg RxB_IRQ; |
reg RxE_IRQ; |
|
reg TxStartFrm; |
reg TxEndFrm; |
reg [7:0] TxData; |
|
reg TxUnderRun; |
reg TxUnderRun_wb; |
|
reg TxBDRead; |
wire TxStatusWrite; |
|
reg [1:0] TxValidBytesLatched; |
|
reg [15:0] TxLength; |
reg [15:0] LatchedTxLength; |
reg [14:11] TxStatus; |
|
reg [14:13] RxStatus; |
|
reg TxStartFrm_wb; |
reg TxRetry_wb; |
reg TxAbort_wb; |
reg TxDone_wb; |
|
reg TxDone_wb_q; |
reg TxAbort_wb_q; |
reg TxRetry_wb_q; |
reg TxRetryPacket; |
reg TxRetryPacket_NotCleared; |
reg TxDonePacket; |
reg TxDonePacket_NotCleared; |
reg TxAbortPacket; |
reg TxAbortPacket_NotCleared; |
reg RxBDReady; |
reg RxReady; |
reg TxBDReady; |
|
reg RxBDRead; |
|
reg [31:0] TxDataLatched; |
reg [1:0] TxByteCnt; |
reg LastWord; |
reg ReadTxDataFromFifo_tck; |
|
reg BlockingTxStatusWrite; |
reg BlockingTxBDRead; |
|
reg Flop; |
|
reg [7:1] TxBDAddress; |
reg [7:1] RxBDAddress; |
|
reg TxRetrySync1; |
reg TxAbortSync1; |
reg TxDoneSync1; |
|
reg TxAbort_q; |
reg TxRetry_q; |
reg TxUsedData_q; |
|
reg [31:0] RxDataLatched2; |
|
reg [31:8] RxDataLatched1; // Big Endian Byte Ordering |
|
reg [1:0] RxValidBytes; |
reg [1:0] RxByteCnt; |
reg LastByteIn; |
reg ShiftWillEnd; |
|
reg WriteRxDataToFifo; |
reg [15:0] LatchedRxLength; |
reg RxAbortLatched; |
|
reg ShiftEnded; |
reg RxOverrun; |
|
reg [3:0] BDWrite; // BD Write Enable for access from WISHBONE side |
reg BDRead; // BD Read access from WISHBONE side |
wire [31:0] RxBDDataIn; // Rx BD data in |
wire [31:0] TxBDDataIn; // Tx BD data in |
|
reg TxEndFrm_wb; |
|
wire TxRetryPulse; |
wire TxDonePulse; |
wire TxAbortPulse; |
|
wire StartRxBDRead; |
|
wire StartTxBDRead; |
|
wire TxIRQEn; |
wire WrapTxStatusBit; |
|
wire RxIRQEn; |
wire WrapRxStatusBit; |
|
wire [1:0] TxValidBytes; |
|
wire [7:1] TempTxBDAddress; |
wire [7:1] TempRxBDAddress; |
|
wire RxStatusWrite; |
wire RxBufferFull; |
wire RxBufferAlmostEmpty; |
wire RxBufferEmpty; |
|
reg WB_ACK_O; |
|
wire [8:0] RxStatusIn; |
reg [8:0] RxStatusInLatched; |
|
reg WbEn, WbEn_q; |
reg RxEn, RxEn_q; |
reg TxEn, TxEn_q; |
reg r_TxEn_q; |
reg r_RxEn_q; |
|
wire ram_ce; |
wire [3:0] ram_we; |
wire ram_oe; |
reg [7:0] ram_addr; |
reg [31:0] ram_di; |
wire [31:0] ram_do; |
|
wire StartTxPointerRead; |
reg TxPointerRead; |
reg TxEn_needed; |
reg RxEn_needed; |
|
wire StartRxPointerRead; |
reg RxPointerRead; |
|
// RX shift ending signals |
reg ShiftEnded_rck; |
reg ShiftEndedSync1; |
reg ShiftEndedSync2; |
reg ShiftEndedSync3; |
reg ShiftEndedSync_c1; |
reg ShiftEndedSync_c2; |
|
wire StartShiftWillEnd; |
|
reg StartOccured; |
reg TxStartFrm_sync1; |
reg TxStartFrm_sync2; |
reg TxStartFrm_syncb1; |
reg TxStartFrm_syncb2; |
|
wire TxFifoClear; |
wire TxBufferAlmostFull; |
wire TxBufferFull; |
wire TxBufferEmpty; |
wire TxBufferAlmostEmpty; |
wire SetReadTxDataFromMemory; |
reg BlockReadTxDataFromMemory; |
|
reg tx_burst_en; |
reg rx_burst_en; |
reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt; |
|
wire ReadTxDataFromMemory_2; |
wire tx_burst; |
|
wire [31:0] TxData_wb; |
wire ReadTxDataFromFifo_wb; |
|
wire [TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt; |
wire [RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt; |
|
reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt; |
|
wire rx_burst; |
wire enough_data_in_rxfifo_for_burst; |
wire enough_data_in_rxfifo_for_burst_plus1; |
|
reg ReadTxDataFromMemory; |
wire WriteRxDataToMemory; |
|
reg MasterWbTX; |
reg MasterWbRX; |
|
reg [29:0] m_wb_adr_o; |
reg m_wb_cyc_o; |
reg [3:0] m_wb_sel_o; |
reg m_wb_we_o; |
|
wire TxLengthEq0; |
wire TxLengthLt4; |
|
reg BlockingIncrementTxPointer; |
reg [31:2] TxPointerMSB; |
reg [1:0] TxPointerLSB; |
reg [1:0] TxPointerLSB_rst; |
reg [31:2] RxPointerMSB; |
reg [1:0] RxPointerLSB_rst; |
|
wire RxBurstAcc; |
wire RxWordAcc; |
wire RxHalfAcc; |
wire RxByteAcc; |
|
wire ResetTxBDReady; |
reg BlockingTxStatusWrite_sync1; |
reg BlockingTxStatusWrite_sync2; |
reg BlockingTxStatusWrite_sync3; |
|
reg cyc_cleared; |
reg IncrTxPointer; |
|
reg [3:0] RxByteSel; |
wire MasterAccessFinished; |
|
reg LatchValidBytes; |
reg LatchValidBytes_q; |
|
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I |
reg ReadTxDataFromFifo_sync1; |
reg ReadTxDataFromFifo_sync2; |
reg ReadTxDataFromFifo_sync3; |
reg ReadTxDataFromFifo_syncb1; |
reg ReadTxDataFromFifo_syncb2; |
reg ReadTxDataFromFifo_syncb3; |
|
reg RxAbortSync1; |
reg RxAbortSync2; |
reg RxAbortSync3; |
reg RxAbortSync4; |
reg RxAbortSyncb1; |
reg RxAbortSyncb2; |
|
reg RxEnableWindow; |
|
wire SetWriteRxDataToFifo; |
|
reg WriteRxDataToFifoSync1; |
reg WriteRxDataToFifoSync2; |
reg WriteRxDataToFifoSync3; |
|
wire WriteRxDataToFifo_wb; |
|
reg LatchedRxStartFrm; |
reg SyncRxStartFrm; |
reg SyncRxStartFrm_q; |
reg SyncRxStartFrm_q2; |
wire RxFifoReset; |
|
wire TxError; |
wire RxError; |
|
reg RxStatusWriteLatched; |
reg RxStatusWriteLatched_sync1; |
reg RxStatusWriteLatched_sync2; |
reg RxStatusWriteLatched_syncb1; |
reg RxStatusWriteLatched_syncb2; |
|
`ifdef ETH_WISHBONE_B3 |
assign m_wb_bte_o = 2'b00; // Linear burst |
`endif |
|
assign m_wb_stb_o = m_wb_cyc_o; |
|
always @ (posedge WB_CLK_I) |
begin |
WB_ACK_O <= (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q; |
end |
|
assign WB_DAT_O = ram_do; |
|
// Generic synchronous single-port RAM interface |
eth_spram_256x32 |
bd_ram |
( |
.clk (WB_CLK_I), |
.rst (Reset), |
.ce (ram_ce), |
.we (ram_we), |
.oe (ram_oe), |
.addr (ram_addr), |
.di (ram_di), |
.dato (ram_do) |
`ifdef ETH_BIST |
, |
.mbist_si_i (mbist_si_i), |
.mbist_so_o (mbist_so_o), |
.mbist_ctrl_i (mbist_ctrl_i) |
`endif |
); |
|
assign ram_ce = 1'b1; |
assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) | |
{4{(TxStatusWrite | RxStatusWrite)}}; |
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & |
(TxBDRead | TxPointerRead) | RxEn & RxEn_q & |
(RxBDRead | RxPointerRead); |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxEn_needed <= 1'b0; |
else |
if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q) |
TxEn_needed <= 1'b1; |
else |
if(TxPointerRead & TxEn & TxEn_q) |
TxEn_needed <= 1'b0; |
end |
|
// Enabling access to the RAM for three devices. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
begin |
WbEn <= 1'b1; |
RxEn <= 1'b0; |
TxEn <= 1'b0; |
ram_addr <= 8'h0; |
ram_di <= 32'h0; |
BDRead <= 1'b0; |
BDWrite <= 0; |
end |
else |
begin |
// Switching between three stages depends on enable signals |
/* verilator lint_off CASEINCOMPLETE */ // JB |
case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case |
5'b100_10, 5'b100_11 : |
begin |
WbEn <= 1'b0; |
RxEn <= 1'b1; // wb access stage and r_RxEn is enabled |
TxEn <= 1'b0; |
ram_addr <= {RxBDAddress, RxPointerRead}; |
ram_di <= RxBDDataIn; |
end |
5'b100_01 : |
begin |
WbEn <= 1'b0; |
RxEn <= 1'b0; |
TxEn <= 1'b1; // wb access stage, r_RxEn is disabled but |
// r_TxEn is enabled |
ram_addr <= {TxBDAddress, TxPointerRead}; |
ram_di <= TxBDDataIn; |
end |
5'b010_00, 5'b010_10 : |
begin |
WbEn <= 1'b1; // RxEn access stage and r_TxEn is disabled |
RxEn <= 1'b0; |
TxEn <= 1'b0; |
ram_addr <= WB_ADR_I[9:2]; |
ram_di <= WB_DAT_I; |
BDWrite <= BDCs[3:0] & {4{WB_WE_I}}; |
BDRead <= (|BDCs) & ~WB_WE_I; |
end |
5'b010_01, 5'b010_11 : |
begin |
WbEn <= 1'b0; |
RxEn <= 1'b0; |
TxEn <= 1'b1; // RxEn access stage and r_TxEn is enabled |
ram_addr <= {TxBDAddress, TxPointerRead}; |
ram_di <= TxBDDataIn; |
end |
5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 : |
begin |
WbEn <= 1'b1; // TxEn access stage (we always go to wb |
// access stage) |
RxEn <= 1'b0; |
TxEn <= 1'b0; |
ram_addr <= WB_ADR_I[9:2]; |
ram_di <= WB_DAT_I; |
BDWrite <= BDCs[3:0] & {4{WB_WE_I}}; |
BDRead <= (|BDCs) & ~WB_WE_I; |
end |
5'b100_00 : |
begin |
WbEn <= 1'b0; // WbEn access stage and there is no need |
// for other stages. WbEn needs to be |
// switched off for a bit |
end |
5'b000_00 : |
begin |
WbEn <= 1'b1; // Idle state. We go to WbEn access stage. |
RxEn <= 1'b0; |
TxEn <= 1'b0; |
ram_addr <= WB_ADR_I[9:2]; |
ram_di <= WB_DAT_I; |
BDWrite <= BDCs[3:0] & {4{WB_WE_I}}; |
BDRead <= (|BDCs) & ~WB_WE_I; |
end |
endcase |
/* verilator lint_on CASEINCOMPLETE */ |
end |
end |
|
|
// Delayed stage signals |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
begin |
WbEn_q <= 1'b0; |
RxEn_q <= 1'b0; |
TxEn_q <= 1'b0; |
r_TxEn_q <= 1'b0; |
r_RxEn_q <= 1'b0; |
end |
else |
begin |
WbEn_q <= WbEn; |
RxEn_q <= RxEn; |
TxEn_q <= TxEn; |
r_TxEn_q <= r_TxEn; |
r_RxEn_q <= r_RxEn; |
end |
end |
|
// Changes for tx occur every second clock. Flop is used for this manner. |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
Flop <= 1'b0; |
else |
if(TxDone | TxAbort | TxRetry_q) |
Flop <= 1'b0; |
else |
if(TxUsedData) |
Flop <= ~Flop; |
end |
|
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse; |
|
// Latching READY status of the Tx buffer descriptor |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxBDReady <= 1'b0; |
else |
if(TxEn & TxEn_q & TxBDRead) |
// TxBDReady is sampled only once at the beginning. |
TxBDReady <= ram_do[15] & (ram_do[31:16] > 4); |
else |
// Only packets larger then 4 bytes are transmitted. |
if(ResetTxBDReady) |
TxBDReady <= 1'b0; |
end |
|
// Reading the Tx buffer descriptor |
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & |
~BlockingTxBDRead & ~TxBDReady; |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxBDRead <= 1'b1; |
else |
if(StartTxBDRead) |
TxBDRead <= 1'b1; |
else |
if(TxBDReady) |
TxBDRead <= 1'b0; |
end |
|
// Reading Tx BD pointer |
assign StartTxPointerRead = TxBDRead & TxBDReady; |
|
// Reading Tx BD Pointer |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxPointerRead <= 1'b0; |
else |
if(StartTxPointerRead) |
TxPointerRead <= 1'b1; |
else |
if(TxEn_q) |
TxPointerRead <= 1'b0; |
end |
|
|
// Writing status back to the Tx buffer descriptor |
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & |
TxEn & TxEn_q & ~BlockingTxStatusWrite; |
|
|
// Status writing must occur only once. Meanwhile it is blocked. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
BlockingTxStatusWrite <= 1'b0; |
else |
if(~TxDone_wb & ~TxAbort_wb) |
BlockingTxStatusWrite <= 1'b0; |
else |
if(TxStatusWrite) |
BlockingTxStatusWrite <= 1'b1; |
end |
|
|
// Synchronizing BlockingTxStatusWrite to MTxClk |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
BlockingTxStatusWrite_sync1 <= 1'b0; |
else |
BlockingTxStatusWrite_sync1 <= BlockingTxStatusWrite; |
end |
|
// Synchronizing BlockingTxStatusWrite to MTxClk |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
BlockingTxStatusWrite_sync2 <= 1'b0; |
else |
BlockingTxStatusWrite_sync2 <= BlockingTxStatusWrite_sync1; |
end |
|
// Synchronizing BlockingTxStatusWrite to MTxClk |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
BlockingTxStatusWrite_sync3 <= 1'b0; |
else |
BlockingTxStatusWrite_sync3 <= BlockingTxStatusWrite_sync2; |
end |
|
assign RstDeferLatched = BlockingTxStatusWrite_sync2 & |
~BlockingTxStatusWrite_sync3; |
|
// TxBDRead state is activated only once. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
BlockingTxBDRead <= 1'b0; |
else |
if(StartTxBDRead) |
BlockingTxBDRead <= 1'b1; |
else |
if(~StartTxBDRead & ~TxBDReady) |
BlockingTxBDRead <= 1'b0; |
end |
|
|
// Latching status from the tx buffer descriptor |
// Data is avaliable one cycle after the access is started (at that time |
// signal TxEn is not active) |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxStatus <= 4'h0; |
else |
if(TxEn & TxEn_q & TxBDRead) |
TxStatus <= ram_do[14:11]; |
end |
|
|
|
//Latching length from the buffer descriptor; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxLength <= 16'h0; |
else |
if(TxEn & TxEn_q & TxBDRead) |
TxLength <= ram_do[31:16]; |
else |
if(MasterWbTX & m_wb_ack_i) |
begin |
if(TxLengthLt4) |
TxLength <= 16'h0; |
else if(TxPointerLSB_rst==2'h0) |
TxLength <= TxLength - 16'd4; // Length is subtracted at |
// the data request |
else if(TxPointerLSB_rst==2'h1) |
TxLength <= TxLength - 16'd3; // Length is subtracted |
// at the data request |
else if(TxPointerLSB_rst==2'h2) |
TxLength <= TxLength - 16'd2; // Length is subtracted |
// at the data request |
else if(TxPointerLSB_rst==2'h3) |
TxLength <= TxLength - 16'd1; // Length is subtracted |
// at the data request |
end |
end |
|
//Latching length from the buffer descriptor; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
LatchedTxLength <= 16'h0; |
else |
if(TxEn & TxEn_q & TxBDRead) |
LatchedTxLength <= ram_do[31:16]; |
end |
|
assign TxLengthEq0 = TxLength == 0; |
assign TxLengthLt4 = TxLength < 4; |
|
|
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are |
// latched because TxPointerMSB is only used for word-aligned accesses. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxPointerMSB <= 30'h0; |
else |
if(TxEn & TxEn_q & TxPointerRead) |
TxPointerMSB <= ram_do[31:2]; |
else |
if(IncrTxPointer & ~BlockingIncrementTxPointer) |
// TxPointer is word-aligned |
TxPointerMSB <= TxPointerMSB + 1'b1; |
end |
|
|
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are |
// performed, valid data does not necesserly start at byte 0 (could be byte |
// 0, 1, 2 or 3). This signals are used for proper selection of the start |
// byte (TxData and TxByteCnt) are set by this two bits. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxPointerLSB[1:0] <= 0; |
else |
if(TxEn & TxEn_q & TxPointerRead) |
TxPointerLSB[1:0] <= ram_do[1:0]; |
end |
|
|
// Latching 2 MSB bits of the buffer descriptor. |
// After the read access, TxLength needs to be decremented for the number of |
// the valid bytes (1 to 4 bytes are valid in the first word). After the |
// first read all bytes are valid so this two bits are reset to zero. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxPointerLSB_rst[1:0] <= 0; |
else |
if(TxEn & TxEn_q & TxPointerRead) |
TxPointerLSB_rst[1:0] <= ram_do[1:0]; |
else |
// After first access pointer is word alligned |
if(MasterWbTX & m_wb_ack_i) |
TxPointerLSB_rst[1:0] <= 0; |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
BlockingIncrementTxPointer <= 0; |
else |
if(MasterAccessFinished) |
BlockingIncrementTxPointer <= 0; |
else |
if(IncrTxPointer) |
BlockingIncrementTxPointer <= 1'b1; |
end |
|
|
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead; |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromMemory <= 1'b0; |
else |
if(TxLengthEq0 | TxAbortPulse | TxRetryPulse) |
ReadTxDataFromMemory <= 1'b0; |
else |
if(SetReadTxDataFromMemory) |
ReadTxDataFromMemory <= 1'b1; |
end |
|
assign ReadTxDataFromMemory_2 = ReadTxDataFromMemory & |
~BlockReadTxDataFromMemory; |
|
assign tx_burst = ReadTxDataFromMemory_2 & tx_burst_en; |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
BlockReadTxDataFromMemory <= 1'b0; |
else |
if((TxBufferAlmostFull | TxLength <= 4) & MasterWbTX & (~cyc_cleared) & |
(!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared))) |
BlockReadTxDataFromMemory <= 1'b1; |
else |
if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket) |
BlockReadTxDataFromMemory <= 1'b0; |
end |
|
|
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i; |
|
// Enabling master wishbone access to the memory for two devices TX and RX. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
begin |
MasterWbTX <= 1'b0; |
MasterWbRX <= 1'b0; |
m_wb_adr_o <= 30'h0; |
m_wb_cyc_o <= 1'b0; |
m_wb_we_o <= 1'b0; |
m_wb_sel_o <= 4'h0; |
cyc_cleared<= 1'b0; |
tx_burst_cnt<= 0; |
rx_burst_cnt<= 0; |
IncrTxPointer<= 1'b0; |
tx_burst_en<= 1'b1; |
rx_burst_en<= 1'b0; |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <= 3'b0; |
`endif |
end |
else |
begin |
// Switching between two stages depends on enable signals |
casez ({MasterWbTX, |
MasterWbRX, |
ReadTxDataFromMemory_2, |
WriteRxDataToMemory, |
MasterAccessFinished, |
cyc_cleared, |
tx_burst, |
rx_burst}) // synopsys parallel_case |
|
8'b00_10_00_10, // Idle and MRB needed |
8'b10_1?_10_1?, // MRB continues |
8'b10_10_01_10, // Clear (previously MR) and MRB needed |
8'b01_1?_01_1?: // Clear (previously MW) and MRB needed |
begin |
MasterWbTX <= 1'b1; // tx burst |
MasterWbRX <= 1'b0; |
m_wb_cyc_o <= 1'b1; |
m_wb_we_o <= 1'b0; |
m_wb_sel_o <= 4'hf; |
cyc_cleared<= 1'b0; |
IncrTxPointer<= 1'b1; |
tx_burst_cnt <= tx_burst_cnt+3'h1; |
if(tx_burst_cnt==0) |
m_wb_adr_o <= TxPointerMSB; |
else |
m_wb_adr_o <= m_wb_adr_o + 1'b1; |
if(tx_burst_cnt==(`ETH_BURST_LENGTH-1)) |
begin |
tx_burst_en<= 1'b0; |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <= 3'b111; |
`endif |
end |
else |
begin |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <= 3'b010; |
`endif |
end |
end |
8'b00_?1_00_?1, // Idle and MWB needed |
8'b01_?1_10_?1, // MWB continues |
8'b01_01_01_01, // Clear (previously MW) and MWB needed |
8'b10_?1_01_?1 : // Clear (previously MR) and MWB needed |
begin |
MasterWbTX <= 1'b0; // rx burst |
MasterWbRX <= 1'b1; |
m_wb_cyc_o <= 1'b1; |
m_wb_we_o <= 1'b1; |
m_wb_sel_o <= RxByteSel; |
IncrTxPointer<= 1'b0; |
cyc_cleared<= 1'b0; |
rx_burst_cnt <= rx_burst_cnt+3'h1; |
|
if(rx_burst_cnt==0) |
m_wb_adr_o <= RxPointerMSB; |
else |
m_wb_adr_o <= m_wb_adr_o+1'b1; |
|
if(rx_burst_cnt==(`ETH_BURST_LENGTH-1)) |
begin |
rx_burst_en<= 1'b0; |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <= 3'b111; |
`endif |
end |
else |
begin |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <= 3'b010; |
`endif |
end |
end |
8'b00_?1_00_?0 :// idle and MW is needed (data write to rx buffer) |
begin |
MasterWbTX <= 1'b0; |
MasterWbRX <= 1'b1; |
m_wb_adr_o <= RxPointerMSB; |
m_wb_cyc_o <= 1'b1; |
m_wb_we_o <= 1'b1; |
m_wb_sel_o <= RxByteSel; |
IncrTxPointer<= 1'b0; |
end |
8'b00_10_00_00 : // idle and MR is needed (data read from tx buffer) |
begin |
MasterWbTX <= 1'b1; |
MasterWbRX <= 1'b0; |
m_wb_adr_o <= TxPointerMSB; |
m_wb_cyc_o <= 1'b1; |
m_wb_we_o <= 1'b0; |
m_wb_sel_o <= 4'hf; |
IncrTxPointer<= 1'b1; |
end |
8'b10_10_01_00,// MR and MR is needed (data read from tx buffer) |
8'b01_1?_01_0? :// MW and MR is needed (data read from tx buffer) |
begin |
MasterWbTX <= 1'b1; |
MasterWbRX <= 1'b0; |
m_wb_adr_o <= TxPointerMSB; |
m_wb_cyc_o <= 1'b1; |
m_wb_we_o <= 1'b0; |
m_wb_sel_o <= 4'hf; |
cyc_cleared<= 1'b0; |
IncrTxPointer<= 1'b1; |
end |
8'b01_01_01_00,// MW and MW needed (data write to rx buffer) |
8'b10_?1_01_?0 :// MR and MW is needed (data write to rx buffer) |
begin |
MasterWbTX <= 1'b0; |
MasterWbRX <= 1'b1; |
m_wb_adr_o <= RxPointerMSB; |
m_wb_cyc_o <= 1'b1; |
m_wb_we_o <= 1'b1; |
m_wb_sel_o <= RxByteSel; |
cyc_cleared<= 1'b0; |
IncrTxPointer<= 1'b0; |
end |
8'b01_01_10_00,// MW and MW needed (cycle is cleared between |
// previous and next access) |
8'b01_1?_10_?0,// MW and MW or MR or MRB needed (cycle is |
// cleared between previous and next access) |
8'b10_10_10_00,// MR and MR needed (cycle is cleared between |
// previous and next access) |
8'b10_?1_10_0? :// MR and MR or MW or MWB (cycle is cleared |
// between previous and next access) |
begin |
m_wb_cyc_o <= 1'b0;// whatever and master read or write is |
// needed. We need to clear m_wb_cyc_o |
// before next access is started |
cyc_cleared<= 1'b1; |
IncrTxPointer<= 1'b0; |
tx_burst_cnt<= 0; |
tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4)); |
rx_burst_cnt<= 0; |
rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used. |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <= 3'b0; |
`endif |
end |
8'b??_00_10_00,// whatever and no master read or write is needed |
// (ack or err comes finishing previous access) |
8'b??_00_01_00 : // Between cyc_cleared request was cleared |
begin |
MasterWbTX <= 1'b0; |
MasterWbRX <= 1'b0; |
m_wb_cyc_o <= 1'b0; |
cyc_cleared<= 1'b0; |
IncrTxPointer<= 1'b0; |
rx_burst_cnt<= 0; |
// Counter is not decremented, yet, so plus1 is used. |
rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : |
enough_data_in_rxfifo_for_burst; |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <= 3'b0; |
`endif |
end |
8'b00_00_00_00: // whatever and no master read or write is needed |
// (ack or err comes finishing previous access) |
begin |
tx_burst_cnt<= 0; |
tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4)); |
end |
default: // Don't touch |
begin |
MasterWbTX <= MasterWbTX; |
MasterWbRX <= MasterWbRX; |
m_wb_cyc_o <= m_wb_cyc_o; |
m_wb_sel_o <= m_wb_sel_o; |
IncrTxPointer<= IncrTxPointer; |
end |
endcase |
end |
end |
|
assign TxFifoClear = (TxAbortPacket | TxRetryPacket); |
|
eth_fifo |
#( |
.DATA_WIDTH(TX_FIFO_DATA_WIDTH), |
.DEPTH(TX_FIFO_DEPTH), |
.CNT_WIDTH(TX_FIFO_CNT_WIDTH)) |
tx_fifo ( |
.data_in(m_wb_dat_i), |
.data_out(TxData_wb), |
.clk(WB_CLK_I), |
.reset(Reset), |
.write(MasterWbTX & m_wb_ack_i), |
.read(ReadTxDataFromFifo_wb & ~TxBufferEmpty), |
.clear(TxFifoClear), |
.full(TxBufferFull), |
.almost_full(TxBufferAlmostFull), |
.almost_empty(TxBufferAlmostEmpty), |
.empty(TxBufferEmpty), |
.cnt(txfifo_cnt) |
); |
|
// Start: Generation of the TxStartFrm_wb which is then synchronized to the |
// MTxClk |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxStartFrm_wb <= 1'b0; |
else |
if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0)) |
TxStartFrm_wb <= 1'b1; |
else |
if(TxStartFrm_syncb2) |
TxStartFrm_wb <= 1'b0; |
end |
|
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's |
// blocked. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
StartOccured <= 1'b0; |
else |
if(TxStartFrm_wb) |
StartOccured <= 1'b1; |
else |
if(ResetTxBDReady) |
StartOccured <= 1'b0; |
end |
|
// Synchronizing TxStartFrm_wb to MTxClk |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxStartFrm_sync1 <= 1'b0; |
else |
TxStartFrm_sync1 <= TxStartFrm_wb; |
end |
|
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxStartFrm_sync2 <= 1'b0; |
else |
TxStartFrm_sync2 <= TxStartFrm_sync1; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxStartFrm_syncb1 <= 1'b0; |
else |
TxStartFrm_syncb1 <= TxStartFrm_sync2; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxStartFrm_syncb2 <= 1'b0; |
else |
TxStartFrm_syncb2 <= TxStartFrm_syncb1; |
end |
|
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxStartFrm <= 1'b0; |
else |
if(TxStartFrm_sync2) |
TxStartFrm <= 1'b1; |
else |
if(TxUsedData_q | ~TxStartFrm_sync2 & |
(TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q))) |
TxStartFrm <= 1'b0; |
end |
// End: Generation of the TxStartFrm_wb which is then synchronized to the |
// MTxClk |
|
|
// TxEndFrm_wb: indicator of the end of frame |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxEndFrm_wb <= 1'b0; |
else |
if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData) |
TxEndFrm_wb <= 1'b1; |
else |
if(TxRetryPulse | TxDonePulse | TxAbortPulse) |
TxEndFrm_wb <= 1'b0; |
end |
|
// Marks which bytes are valid within the word. |
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0; |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
LatchValidBytes <= 1'b0; |
else |
if(TxLengthLt4 & TxBDReady) |
LatchValidBytes <= 1'b1; |
else |
LatchValidBytes <= 1'b0; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
LatchValidBytes_q <= 1'b0; |
else |
LatchValidBytes_q <= LatchValidBytes; |
end |
|
|
// Latching valid bytes |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxValidBytesLatched <= 2'h0; |
else |
if(LatchValidBytes & ~LatchValidBytes_q) |
TxValidBytesLatched <= TxValidBytes; |
else |
if(TxRetryPulse | TxDonePulse | TxAbortPulse) |
TxValidBytesLatched <= 2'h0; |
end |
|
|
assign TxIRQEn = TxStatus[14]; |
assign WrapTxStatusBit = TxStatus[13]; |
assign PerPacketPad = TxStatus[12]; |
assign PerPacketCrcEn = TxStatus[11]; |
|
|
assign RxIRQEn = RxStatus[14]; |
assign WrapRxStatusBit = RxStatus[13]; |
|
|
// Temporary Tx and Rx buffer descriptor address |
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & |
(TxBDAddress + 1'b1); // Tx BD increment or wrap |
// (last BD) |
|
assign TempRxBDAddress[7:1] = |
{7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD |
{7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1); // Using next Rx BD |
// (increment address) |
|
// Latching Tx buffer descriptor address |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxBDAddress <= 7'h0; |
else if (r_TxEn & (~r_TxEn_q)) |
TxBDAddress <= 7'h0; |
else if (TxStatusWrite) |
TxBDAddress <= TempTxBDAddress; |
end |
|
// Latching Rx buffer descriptor address |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxBDAddress <= 7'h0; |
else if(r_RxEn & (~r_RxEn_q)) |
RxBDAddress <= r_TxBDNum[6:0]; |
else if(RxStatusWrite) |
RxBDAddress <= TempRxBDAddress; |
end |
|
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], |
RetryLimit, LateCollLatched, DeferLatched, |
CarrierSenseLost}; |
|
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched}; |
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched}; |
|
|
// Signals used for various purposes |
assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q; |
assign TxDonePulse = TxDone_wb & ~TxDone_wb_q; |
assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q; |
|
|
// Generating delayed signals |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
begin |
TxAbort_q <= 1'b0; |
TxRetry_q <= 1'b0; |
TxUsedData_q <= 1'b0; |
end |
else |
begin |
TxAbort_q <= TxAbort; |
TxRetry_q <= TxRetry; |
TxUsedData_q <= TxUsedData; |
end |
end |
|
// Generating delayed signals |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
begin |
TxDone_wb_q <= 1'b0; |
TxAbort_wb_q <= 1'b0; |
TxRetry_wb_q <= 1'b0; |
end |
else |
begin |
TxDone_wb_q <= TxDone_wb; |
TxAbort_wb_q <= TxAbort_wb; |
TxRetry_wb_q <= TxRetry_wb; |
end |
end |
|
|
reg TxAbortPacketBlocked; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxAbortPacket <= 1'b0; |
else |
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & |
(~TxAbortPacketBlocked) | TxAbort_wb & (~MasterWbTX) & |
(~TxAbortPacketBlocked)) |
TxAbortPacket <= 1'b1; |
else |
TxAbortPacket <= 1'b0; |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxAbortPacket_NotCleared <= 1'b0; |
else |
if(TxEn & TxEn_q & TxAbortPacket_NotCleared) |
TxAbortPacket_NotCleared <= 1'b0; |
else |
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & |
(~TxAbortPacketBlocked) | TxAbort_wb & (~MasterWbTX) & |
(~TxAbortPacketBlocked)) |
TxAbortPacket_NotCleared <= 1'b1; |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxAbortPacketBlocked <= 1'b0; |
else |
if(!TxAbort_wb & TxAbort_wb_q) |
TxAbortPacketBlocked <= 1'b0; |
else |
if(TxAbortPacket) |
TxAbortPacketBlocked <= 1'b1; |
end |
|
|
reg TxRetryPacketBlocked; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxRetryPacket <= 1'b0; |
else |
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & |
!TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked) |
TxRetryPacket <= 1'b1; |
else |
TxRetryPacket <= 1'b0; |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxRetryPacket_NotCleared <= 1'b0; |
else |
if(StartTxBDRead) |
TxRetryPacket_NotCleared <= 1'b0; |
else |
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & |
!TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked) |
TxRetryPacket_NotCleared <= 1'b1; |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxRetryPacketBlocked <= 1'b0; |
else |
if(!TxRetry_wb & TxRetry_wb_q) |
TxRetryPacketBlocked <= 1'b0; |
else |
if(TxRetryPacket) |
TxRetryPacketBlocked <= 1'b1; |
end |
|
|
reg TxDonePacketBlocked; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDonePacket <= 1'b0; |
else |
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & |
!TxDonePacketBlocked | TxDone_wb & !MasterWbTX & !TxDonePacketBlocked) |
TxDonePacket <= 1'b1; |
else |
TxDonePacket <= 1'b0; |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDonePacket_NotCleared <= 1'b0; |
else |
if(TxEn & TxEn_q & TxDonePacket_NotCleared) |
TxDonePacket_NotCleared <= 1'b0; |
else |
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & |
(~TxDonePacketBlocked) | TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked)) |
TxDonePacket_NotCleared <= 1'b1; |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDonePacketBlocked <= 1'b0; |
else |
if(!TxDone_wb & TxDone_wb_q) |
TxDonePacketBlocked <= 1'b0; |
else |
if(TxDonePacket) |
TxDonePacketBlocked <= 1'b1; |
end |
|
|
// Indication of the last word |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
LastWord <= 1'b0; |
else |
if((TxEndFrm | TxAbort | TxRetry) & Flop) |
LastWord <= 1'b0; |
else |
if(TxUsedData & Flop & TxByteCnt == 2'h3) |
LastWord <= TxEndFrm_wb; |
end |
|
|
// Tx end frame generation |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxEndFrm <= 1'b0; |
else |
if(Flop & TxEndFrm | TxAbort | TxRetry_q) |
TxEndFrm <= 1'b0; |
else |
if(Flop & LastWord) |
begin |
case (TxValidBytesLatched) // synopsys parallel_case |
1 : TxEndFrm <= TxByteCnt == 2'h0; |
2 : TxEndFrm <= TxByteCnt == 2'h1; |
3 : TxEndFrm <= TxByteCnt == 2'h2; |
0 : TxEndFrm <= TxByteCnt == 2'h3; |
default : TxEndFrm <= 1'b0; |
endcase |
end |
end |
|
|
// Tx data selection (latching) |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxData <= 0; |
else |
if(TxStartFrm_sync2 & ~TxStartFrm) |
case(TxPointerLSB) // synopsys parallel_case |
2'h0 : TxData <= TxData_wb[31:24];// Big Endian Byte Ordering |
2'h1 : TxData <= TxData_wb[23:16];// Big Endian Byte Ordering |
2'h2 : TxData <= TxData_wb[15:08];// Big Endian Byte Ordering |
2'h3 : TxData <= TxData_wb[07:00];// Big Endian Byte Ordering |
endcase |
else |
if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3) |
TxData <= TxData_wb[31:24];// Big Endian Byte Ordering |
else |
if(TxUsedData & Flop) |
begin |
case(TxByteCnt) // synopsys parallel_case |
0 : TxData <= TxDataLatched[31:24];// Big Endian Byte Ordering |
1 : TxData <= TxDataLatched[23:16]; |
2 : TxData <= TxDataLatched[15:8]; |
3 : TxData <= TxDataLatched[7:0]; |
endcase |
end |
end |
|
|
// Latching tx data |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxDataLatched[31:0] <= 32'h0; |
else |
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | |
TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0) |
TxDataLatched[31:0] <= TxData_wb[31:0]; |
end |
|
|
// Tx under run |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxUnderRun_wb <= 1'b0; |
else |
if(TxAbortPulse) |
TxUnderRun_wb <= 1'b0; |
else |
if(TxBufferEmpty & ReadTxDataFromFifo_wb) |
TxUnderRun_wb <= 1'b1; |
end |
|
|
reg TxUnderRun_sync1; |
|
// Tx under run |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxUnderRun_sync1 <= 1'b0; |
else |
if(TxUnderRun_wb) |
TxUnderRun_sync1 <= 1'b1; |
else |
if(BlockingTxStatusWrite_sync2) |
TxUnderRun_sync1 <= 1'b0; |
end |
|
// Tx under run |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxUnderRun <= 1'b0; |
else |
if(BlockingTxStatusWrite_sync2) |
TxUnderRun <= 1'b0; |
else |
if(TxUnderRun_sync1) |
TxUnderRun <= 1'b1; |
end |
|
|
// Tx Byte counter |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxByteCnt <= 2'h0; |
else |
if(TxAbort_q | TxRetry_q) |
TxByteCnt <= 2'h0; |
else |
if(TxStartFrm & ~TxUsedData) |
case(TxPointerLSB) // synopsys parallel_case |
2'h0 : TxByteCnt <= 2'h1; |
2'h1 : TxByteCnt <= 2'h2; |
2'h2 : TxByteCnt <= 2'h3; |
2'h3 : TxByteCnt <= 2'h0; |
endcase |
else |
if(TxUsedData & Flop) |
TxByteCnt <= TxByteCnt + 1'b1; |
end |
|
|
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_tck <= 1'b0; |
else |
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & |
~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0) |
ReadTxDataFromFifo_tck <= 1'b1; |
else |
if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3) |
ReadTxDataFromFifo_tck <= 1'b0; |
end |
|
// Synchronizing TxStartFrm_wb to MTxClk |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_sync1 <= 1'b0; |
else |
ReadTxDataFromFifo_sync1 <= ReadTxDataFromFifo_tck; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_sync2 <= 1'b0; |
else |
ReadTxDataFromFifo_sync2 <= ReadTxDataFromFifo_sync1; |
end |
|
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_syncb1 <= 1'b0; |
else |
ReadTxDataFromFifo_syncb1 <= ReadTxDataFromFifo_sync2; |
end |
|
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_syncb2 <= 1'b0; |
else |
ReadTxDataFromFifo_syncb2 <= ReadTxDataFromFifo_syncb1; |
end |
|
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_syncb3 <= 1'b0; |
else |
ReadTxDataFromFifo_syncb3 <= ReadTxDataFromFifo_syncb2; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_sync3 <= 1'b0; |
else |
ReadTxDataFromFifo_sync3 <= ReadTxDataFromFifo_sync2; |
end |
|
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & |
~ReadTxDataFromFifo_sync3; |
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization |
// to the WB_CLK_I |
|
|
// Synchronizing TxRetry signal (synchronized to WISHBONE clock) |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxRetrySync1 <= 1'b0; |
else |
TxRetrySync1 <= TxRetry; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxRetry_wb <= 1'b0; |
else |
TxRetry_wb <= TxRetrySync1; |
end |
|
|
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock) |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDoneSync1 <= 1'b0; |
else |
TxDoneSync1 <= TxDone; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDone_wb <= 1'b0; |
else |
TxDone_wb <= TxDoneSync1; |
end |
|
// Synchronizing TxAbort signal (synchronized to WISHBONE clock) |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxAbortSync1 <= 1'b0; |
else |
TxAbortSync1 <= TxAbort; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxAbort_wb <= 1'b0; |
else |
TxAbort_wb <= TxAbortSync1; |
end |
|
|
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 | |
r_RxEn & ~r_RxEn_q; |
|
// Reading the Rx buffer descriptor |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxBDRead <= 1'b0; |
else |
if(StartRxBDRead & ~RxReady) |
RxBDRead <= 1'b1; |
else |
if(RxBDReady) |
RxBDRead <= 1'b0; |
end |
|
|
// Reading of the next receive buffer descriptor starts after reception status |
// is written to the previous one. |
|
// Latching READY status of the Rx buffer descriptor |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxBDReady <= 1'b0; |
else |
if(RxPointerRead) |
RxBDReady <= 1'b0; |
else |
if(RxEn & RxEn_q & RxBDRead) |
RxBDReady <= ram_do[15];// RxBDReady is sampled only once at the beginning |
end |
|
// Latching Rx buffer descriptor status |
// Data is avaliable one cycle after the access is started (at that time |
// signal RxEn is not active) |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxStatus <= 2'h0; |
else |
if(RxEn & RxEn_q & RxBDRead) |
RxStatus <= ram_do[14:13]; |
end |
|
|
// RxReady generation |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxReady <= 1'b0; |
else if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~r_RxEn & r_RxEn_q) |
RxReady <= 1'b0; |
else if(RxEn & RxEn_q & RxPointerRead) |
RxReady <= 1'b1; |
end |
|
|
// Reading Rx BD pointer |
assign StartRxPointerRead = RxBDRead & RxBDReady; |
|
// Reading Tx BD Pointer |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxPointerRead <= 1'b0; |
else |
if(StartRxPointerRead) |
RxPointerRead <= 1'b1; |
else |
if(RxEn & RxEn_q) |
RxPointerRead <= 1'b0; |
end |
|
|
//Latching Rx buffer pointer from buffer descriptor; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxPointerMSB <= 30'h0; |
else |
if(RxEn & RxEn_q & RxPointerRead) |
RxPointerMSB <= ram_do[31:2]; |
else |
if(MasterWbRX & m_wb_ack_i) |
RxPointerMSB <= RxPointerMSB + 1'b1; // Word access (always word access. |
// m_wb_sel_o are used for |
// selecting bytes) |
end |
|
|
//Latching last addresses from buffer descriptor (used as byte-half-word |
//indicator); |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxPointerLSB_rst[1:0] <= 0; |
else |
if(MasterWbRX & m_wb_ack_i) // After first write all RxByteSel are active |
RxPointerLSB_rst[1:0] <= 0; |
else |
if(RxEn & RxEn_q & RxPointerRead) |
RxPointerLSB_rst[1:0] <= ram_do[1:0]; |
end |
|
|
always @ (RxPointerLSB_rst) |
begin |
case(RxPointerLSB_rst[1:0]) // synopsys parallel_case |
2'h0 : RxByteSel[3:0] = 4'hf; |
2'h1 : RxByteSel[3:0] = 4'h7; |
2'h2 : RxByteSel[3:0] = 4'h3; |
2'h3 : RxByteSel[3:0] = 4'h1; |
endcase |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxEn_needed <= 1'b0; |
else if(~RxReady & r_RxEn & WbEn & ~WbEn_q) |
RxEn_needed <= 1'b1; |
else if(RxPointerRead & RxEn & RxEn_q) |
RxEn_needed <= 1'b0; |
end |
|
|
// Reception status is written back to the buffer descriptor after the end |
// of frame is detected. |
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q; |
|
|
// Indicating that last byte is being reveived |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LastByteIn <= 1'b0; |
else |
if(ShiftWillEnd & (&RxByteCnt) | RxAbort) |
LastByteIn <= 1'b0; |
else |
if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow) |
LastByteIn <= 1'b1; |
end |
|
assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) & |
RxEnableWindow; |
|
// Indicating that data reception will end |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ShiftWillEnd <= 1'b0; |
else |
if(ShiftEnded_rck | RxAbort) |
ShiftWillEnd <= 1'b0; |
else |
if(StartShiftWillEnd) |
ShiftWillEnd <= 1'b1; |
end |
|
|
// Receive byte counter |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxByteCnt <= 2'h0; |
else |
if(ShiftEnded_rck | RxAbort) |
RxByteCnt <= 2'h0; |
else |
if(RxValid & RxStartFrm & RxReady) |
case(RxPointerLSB_rst) // synopsys parallel_case |
2'h0 : RxByteCnt <= 2'h1; |
2'h1 : RxByteCnt <= 2'h2; |
2'h2 : RxByteCnt <= 2'h3; |
2'h3 : RxByteCnt <= 2'h0; |
endcase |
else |
if(RxValid & RxEnableWindow & RxReady | LastByteIn) |
RxByteCnt <= RxByteCnt + 1'b1; |
end |
|
|
// Indicates how many bytes are valid within the last word |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxValidBytes <= 2'h1; |
else |
if(RxValid & RxStartFrm) |
case(RxPointerLSB_rst) // synopsys parallel_case |
2'h0 : RxValidBytes <= 2'h1; |
2'h1 : RxValidBytes <= 2'h2; |
2'h2 : RxValidBytes <= 2'h3; |
2'h3 : RxValidBytes <= 2'h0; |
endcase |
else |
if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow) |
RxValidBytes <= RxValidBytes + 1'b1; |
end |
|
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxDataLatched1 <= 24'h0; |
else |
if(RxValid & RxReady & ~LastByteIn) |
if(RxStartFrm) |
begin |
case(RxPointerLSB_rst) // synopsys parallel_case |
// Big Endian Byte Ordering |
2'h0: RxDataLatched1[31:24] <= RxData; |
2'h1: RxDataLatched1[23:16] <= RxData; |
2'h2: RxDataLatched1[15:8] <= RxData; |
2'h3: RxDataLatched1 <= RxDataLatched1; |
endcase |
end |
else if (RxEnableWindow) |
begin |
case(RxByteCnt) // synopsys parallel_case |
// Big Endian Byte Ordering |
2'h0: RxDataLatched1[31:24] <= RxData; |
2'h1: RxDataLatched1[23:16] <= RxData; |
2'h2: RxDataLatched1[15:8] <= RxData; |
2'h3: RxDataLatched1 <= RxDataLatched1; |
endcase |
end |
end |
|
// Assembling data that will be written to the rx_fifo |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxDataLatched2 <= 32'h0; |
else |
if(SetWriteRxDataToFifo & ~ShiftWillEnd) |
// Big Endian Byte Ordering |
RxDataLatched2 <= {RxDataLatched1[31:8], RxData}; |
else |
if(SetWriteRxDataToFifo & ShiftWillEnd) |
case(RxValidBytes) // synopsys parallel_case |
// Big Endian Byte Ordering |
0 : RxDataLatched2 <= {RxDataLatched1[31:8], RxData}; |
1 : RxDataLatched2 <= {RxDataLatched1[31:24], 24'h0}; |
2 : RxDataLatched2 <= {RxDataLatched1[31:16], 16'h0}; |
3 : RxDataLatched2 <= {RxDataLatched1[31:8], 8'h0}; |
endcase |
end |
|
|
// Indicating start of the reception process |
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & |
RxEnableWindow & (&RxByteCnt)) |
|(RxValid & RxReady & RxStartFrm & |
(&RxPointerLSB_rst)) |
|(ShiftWillEnd & LastByteIn & (&RxByteCnt)); |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
WriteRxDataToFifo <= 1'b0; |
else |
if(SetWriteRxDataToFifo & ~RxAbort) |
WriteRxDataToFifo <= 1'b1; |
else |
if(WriteRxDataToFifoSync2 | RxAbort) |
WriteRxDataToFifo <= 1'b0; |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
WriteRxDataToFifoSync1 <= 1'b0; |
else |
if(WriteRxDataToFifo) |
WriteRxDataToFifoSync1 <= 1'b1; |
else |
WriteRxDataToFifoSync1 <= 1'b0; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
WriteRxDataToFifoSync2 <= 1'b0; |
else |
WriteRxDataToFifoSync2 <= WriteRxDataToFifoSync1; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
WriteRxDataToFifoSync3 <= 1'b0; |
else |
WriteRxDataToFifoSync3 <= WriteRxDataToFifoSync2; |
end |
|
|
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & |
~WriteRxDataToFifoSync3; |
|
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LatchedRxStartFrm <= 0; |
else |
if(RxStartFrm & ~SyncRxStartFrm_q) |
LatchedRxStartFrm <= 1; |
else |
if(SyncRxStartFrm_q) |
LatchedRxStartFrm <= 0; |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
SyncRxStartFrm <= 0; |
else |
if(LatchedRxStartFrm) |
SyncRxStartFrm <= 1; |
else |
SyncRxStartFrm <= 0; |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
SyncRxStartFrm_q <= 0; |
else |
SyncRxStartFrm_q <= SyncRxStartFrm; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
SyncRxStartFrm_q2 <= 0; |
else |
SyncRxStartFrm_q2 <= SyncRxStartFrm_q; |
end |
|
|
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2; |
|
eth_fifo #( |
.DATA_WIDTH(RX_FIFO_DATA_WIDTH), |
.DEPTH(RX_FIFO_DEPTH), |
.CNT_WIDTH(RX_FIFO_CNT_WIDTH)) |
rx_fifo ( |
.clk (WB_CLK_I), |
.reset (Reset), |
// Inputs |
.data_in (RxDataLatched2), |
.write (WriteRxDataToFifo_wb & ~RxBufferFull), |
.read (MasterWbRX & m_wb_ack_i), |
.clear (RxFifoReset), |
// Outputs |
.data_out (m_wb_dat_o), |
.full (RxBufferFull), |
.almost_full (), |
.almost_empty (RxBufferAlmostEmpty), |
.empty (RxBufferEmpty), |
.cnt (rxfifo_cnt) |
); |
|
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH; |
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH; |
assign WriteRxDataToMemory = ~RxBufferEmpty; |
assign rx_burst = rx_burst_en & WriteRxDataToMemory; |
|
|
// Generation of the end-of-frame signal |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ShiftEnded_rck <= 1'b0; |
else |
if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd) |
ShiftEnded_rck <= 1'b1; |
else |
if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2) |
ShiftEnded_rck <= 1'b0; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ShiftEndedSync1 <= 1'b0; |
else |
ShiftEndedSync1 <= ShiftEnded_rck; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ShiftEndedSync2 <= 1'b0; |
else |
ShiftEndedSync2 <= ShiftEndedSync1; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ShiftEndedSync3 <= 1'b0; |
else |
if(ShiftEndedSync1 & ~ShiftEndedSync2) |
ShiftEndedSync3 <= 1'b1; |
else |
if(ShiftEnded) |
ShiftEndedSync3 <= 1'b0; |
end |
|
// Generation of the end-of-frame signal |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ShiftEnded <= 1'b0; |
else |
if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded) |
ShiftEnded <= 1'b1; |
else |
if(RxStatusWrite) |
ShiftEnded <= 1'b0; |
end |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ShiftEndedSync_c1 <= 1'b0; |
else |
ShiftEndedSync_c1 <= ShiftEndedSync2; |
end |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ShiftEndedSync_c2 <= 1'b0; |
else |
ShiftEndedSync_c2 <= ShiftEndedSync_c1; |
end |
|
// Generation of the end-of-frame signal |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxEnableWindow <= 1'b0; |
else if(RxStartFrm) |
RxEnableWindow <= 1'b1; |
else if(RxEndFrm | RxAbort) |
RxEnableWindow <= 1'b0; |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxAbortSync1 <= 1'b0; |
else |
RxAbortSync1 <= RxAbortLatched; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxAbortSync2 <= 1'b0; |
else |
RxAbortSync2 <= RxAbortSync1; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxAbortSync3 <= 1'b0; |
else |
RxAbortSync3 <= RxAbortSync2; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxAbortSync4 <= 1'b0; |
else |
RxAbortSync4 <= RxAbortSync3; |
end |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxAbortSyncb1 <= 1'b0; |
else |
RxAbortSyncb1 <= RxAbortSync2; |
end |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxAbortSyncb2 <= 1'b0; |
else |
RxAbortSyncb2 <= RxAbortSyncb1; |
end |
|
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxAbortLatched <= 1'b0; |
else |
if(RxAbortSyncb2) |
RxAbortLatched <= 1'b0; |
else |
if(RxAbort) |
RxAbortLatched <= 1'b1; |
end |
|
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LatchedRxLength[15:0] <= 16'h0; |
else |
if(LoadRxStatus) |
LatchedRxLength[15:0] <= RxLength[15:0]; |
end |
|
|
assign RxStatusIn = {ReceivedPauseFrm, |
AddressMiss, |
RxOverrun, |
InvalidSymbol, |
DribbleNibble, |
ReceivedPacketTooBig, |
ShortFrame, |
LatchedCrcError, |
RxLateCollision}; |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxStatusInLatched <= 'h0; |
else |
if(LoadRxStatus) |
RxStatusInLatched <= RxStatusIn; |
end |
|
|
// Rx overrun |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxOverrun <= 1'b0; |
else if(RxStatusWrite) |
RxOverrun <= 1'b0; |
else if(RxBufferFull & WriteRxDataToFifo_wb) |
RxOverrun <= 1'b1; |
end |
|
|
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost; |
|
|
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames |
// are aborted when signal r_RecSmall is set to 0 in MODER register. |
// AddressMiss is identifying that a frame was received because of the |
// promiscous mode and is not an error |
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]); |
|
|
// Latching and synchronizing RxStatusWrite signal. This signal is used for |
// clearing the ReceivedPauseFrm signal |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxStatusWriteLatched <= 1'b0; |
else |
if(RxStatusWriteLatched_syncb2) |
RxStatusWriteLatched <= 1'b0; |
else |
if(RxStatusWrite) |
RxStatusWriteLatched <= 1'b1; |
end |
|
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
begin |
RxStatusWriteLatched_sync1 <= 1'b0; |
RxStatusWriteLatched_sync2 <= 1'b0; |
end |
else |
begin |
RxStatusWriteLatched_sync1 <= RxStatusWriteLatched; |
RxStatusWriteLatched_sync2 <= RxStatusWriteLatched_sync1; |
end |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
begin |
RxStatusWriteLatched_syncb1 <= 1'b0; |
RxStatusWriteLatched_syncb2 <= 1'b0; |
end |
else |
begin |
RxStatusWriteLatched_syncb1 <= RxStatusWriteLatched_sync2; |
RxStatusWriteLatched_syncb2 <= RxStatusWriteLatched_syncb1; |
end |
end |
|
|
// Tx Done Interrupt |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxB_IRQ <= 1'b0; |
else |
if(TxStatusWrite & TxIRQEn) |
TxB_IRQ <= ~TxError; |
else |
TxB_IRQ <= 1'b0; |
end |
|
|
// Tx Error Interrupt |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxE_IRQ <= 1'b0; |
else |
if(TxStatusWrite & TxIRQEn) |
TxE_IRQ <= TxError; |
else |
TxE_IRQ <= 1'b0; |
end |
|
|
// Rx Done Interrupt |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxB_IRQ <= 1'b0; |
else |
if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & |
(~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow))) |
RxB_IRQ <= (~RxError); |
else |
RxB_IRQ <= 1'b0; |
end |
|
|
// Rx Error Interrupt |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxE_IRQ <= 1'b0; |
else |
if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm |
& r_PassAll & (~r_RxFlow))) |
RxE_IRQ <= RxError; |
else |
RxE_IRQ <= 1'b0; |
end |
|
|
// Busy Interrupt |
|
reg Busy_IRQ_rck; |
reg Busy_IRQ_sync1; |
reg Busy_IRQ_sync2; |
reg Busy_IRQ_sync3; |
reg Busy_IRQ_syncb1; |
reg Busy_IRQ_syncb2; |
|
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
Busy_IRQ_rck <= 1'b0; |
else |
if(RxValid & RxStartFrm & ~RxReady) |
Busy_IRQ_rck <= 1'b1; |
else |
if(Busy_IRQ_syncb2) |
Busy_IRQ_rck <= 1'b0; |
end |
|
always @ (posedge WB_CLK_I) |
begin |
Busy_IRQ_sync1 <= Busy_IRQ_rck; |
Busy_IRQ_sync2 <= Busy_IRQ_sync1; |
Busy_IRQ_sync3 <= Busy_IRQ_sync2; |
end |
|
always @ (posedge MRxClk) |
begin |
Busy_IRQ_syncb1 <= Busy_IRQ_sync2; |
Busy_IRQ_syncb2 <= Busy_IRQ_syncb1; |
end |
|
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3; |
|
|
// Assign the debug output |
`ifdef WISHBONE_DEBUG |
// Top byte, burst progress counters |
assign dbg_dat0[31] = 0; |
assign dbg_dat0[30:28] = rx_burst_cnt; |
assign dbg_dat0[27] = 0; |
assign dbg_dat0[26:24] = tx_burst_cnt; |
// Third byte |
assign dbg_dat0[23] = 0; //rx_ethside_fifo_sel; |
assign dbg_dat0[22] = 0; //rx_wbside_fifo_sel; |
assign dbg_dat0[21] = 0; //rx_fifo0_empty; |
assign dbg_dat0[20] = 0; //rx_fifo1_empty; |
assign dbg_dat0[19] = 0; //overflow_bug_reset; |
assign dbg_dat0[18] = 0; //RxBDOK; |
assign dbg_dat0[17] = 0; //write_rx_data_to_memory_go; |
assign dbg_dat0[16] = 0; //rx_wb_last_writes; |
// Second byte - TxBDAddress - or TX BD address pointer |
assign dbg_dat0[15:8] = { BlockingTxBDRead , TxBDAddress}; |
// Bottom byte - FSM controlling vector |
assign dbg_dat0[7:0] = {MasterWbTX, |
MasterWbRX, |
ReadTxDataFromMemory_2, |
WriteRxDataToMemory, |
MasterAccessFinished, |
cyc_cleared, |
tx_burst, |
rx_burst}; |
`else |
assign dbg_dat0 = 0; |
`endif |
|
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_txcounters.v
0,0 → 1,219
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_txcounters.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// - Novan Hartadi (novan@vlsi.itb.ac.id) //// |
//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2002/04/22 14:54:14 mohor |
// FCS should not be included in NibbleMinFl. |
// |
// Revision 1.4 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.3 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
// |
// Revision 1.2 2001/09/11 14:17:00 mohor |
// Few little NCSIM warnings fixed. |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// Revision 1.4 2001/06/27 21:27:45 mohor |
// Few typos fixed. |
// |
// Revision 1.2 2001/06/19 10:38:07 mohor |
// Minor changes in header. |
// |
// Revision 1.1 2001/06/19 10:27:57 mohor |
// TxEthMAC initial release. |
// |
// |
// |
|
|
`include "timescale.v" |
|
|
module eth_txcounters (StatePreamble, StateIPG, StateData, StatePAD, StateFCS, StateJam, |
StateBackOff, StateDefer, StateIdle, StartDefer, StartIPG, StartFCS, |
StartJam, StartBackoff, TxStartFrm, MTxClk, Reset, MinFL, MaxFL, HugEn, |
ExDfrEn, PacketFinished_q, DlyCrcEn, StateSFD, ByteCnt, NibCnt, |
ExcessiveDefer, NibCntEq7, NibCntEq15, MaxFrame, NibbleMinFl, DlyCrcCnt |
); |
|
input MTxClk; // Tx clock |
input Reset; // Reset |
input StatePreamble; // Preamble state |
input StateIPG; // IPG state |
input [1:0] StateData; // Data state |
input StatePAD; // PAD state |
input StateFCS; // FCS state |
input StateJam; // Jam state |
input StateBackOff; // Backoff state |
input StateDefer; // Defer state |
input StateIdle; // Idle state |
input StateSFD; // SFD state |
input StartDefer; // Defer state will be activated in next clock |
input StartIPG; // IPG state will be activated in next clock |
input StartFCS; // FCS state will be activated in next clock |
input StartJam; // Jam state will be activated in next clock |
input StartBackoff; // Backoff state will be activated in next clock |
input TxStartFrm; // Tx start frame |
input [15:0] MinFL; // Minimum frame length (in bytes) |
input [15:0] MaxFL; // Miximum frame length (in bytes) |
input HugEn; // Pakets bigger then MaxFL enabled |
input ExDfrEn; // Excessive deferral enabled |
input PacketFinished_q; |
input DlyCrcEn; // Delayed CRC enabled |
|
output [15:0] ByteCnt; // Byte counter |
output [15:0] NibCnt; // Nibble counter |
output ExcessiveDefer; // Excessive Deferral occuring |
output NibCntEq7; // Nibble counter is equal to 7 |
output NibCntEq15; // Nibble counter is equal to 15 |
output MaxFrame; // Maximum frame occured |
output NibbleMinFl; // Nibble counter is greater than the minimum frame length |
output [2:0] DlyCrcCnt; // Delayed CRC Count |
|
wire ExcessiveDeferCnt; |
wire ResetNibCnt; |
wire IncrementNibCnt; |
wire ResetByteCnt; |
wire IncrementByteCnt; |
wire ByteCntMax; |
|
reg [15:0] NibCnt; |
reg [15:0] ByteCnt; |
reg [2:0] DlyCrcCnt; |
|
|
|
assign IncrementNibCnt = StateIPG | StatePreamble | (|StateData) | StatePAD |
| StateFCS | StateJam | StateBackOff | StateDefer & ~ExcessiveDefer & TxStartFrm; |
|
|
assign ResetNibCnt = StateDefer & ExcessiveDefer & ~TxStartFrm | StatePreamble & NibCntEq15 |
| StateJam & NibCntEq7 | StateIdle | StartDefer | StartIPG | StartFCS | StartJam; |
|
// Nibble Counter |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
NibCnt <= 16'h0; |
else |
begin |
if(ResetNibCnt) |
NibCnt <= 16'h0; |
else |
if(IncrementNibCnt) |
NibCnt <= NibCnt + 16'd1; |
end |
end |
|
|
assign NibCntEq7 = &NibCnt[2:0]; |
assign NibCntEq15 = &NibCnt[3:0]; |
|
assign NibbleMinFl = NibCnt >= (((MinFL-16'd4)<<1) -1); // FCS should not be included in NibbleMinFl |
|
assign ExcessiveDeferCnt = NibCnt[13:0] == 14'h17b7; |
|
assign ExcessiveDefer = NibCnt[13:0] == 14'h17b7 & ~ExDfrEn; // 6071 nibbles |
|
assign IncrementByteCnt = StateData[1] & ~ByteCntMax |
| StateBackOff & (&NibCnt[6:0]) |
| (StatePAD | StateFCS) & NibCnt[0] & ~ByteCntMax; |
|
assign ResetByteCnt = StartBackoff | StateIdle & TxStartFrm | PacketFinished_q; |
|
|
// Transmit Byte Counter |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
ByteCnt[15:0] <= 16'h0; |
else |
begin |
if(ResetByteCnt) |
ByteCnt[15:0] <= 16'h0; |
else |
if(IncrementByteCnt) |
ByteCnt[15:0] <= ByteCnt[15:0] + 16'd1; |
end |
end |
|
|
assign MaxFrame = ByteCnt[15:0] == MaxFL[15:0] & ~HugEn; |
|
assign ByteCntMax = &ByteCnt[15:0]; |
|
|
// Delayed CRC counter |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
DlyCrcCnt <= 3'h0; |
else |
begin |
if(StateData[1] & DlyCrcCnt == 3'h4 | StartJam | PacketFinished_q) |
DlyCrcCnt <= 3'h0; |
else |
if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0]))) |
DlyCrcCnt <= DlyCrcCnt + 3'd1; |
end |
end |
|
|
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_fifo.v.bak
0,0 → 1,186
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_fifo.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/04/22 13:45:52 mohor |
// Generic ram or Xilinx ram can be used in fifo (selectable by setting |
// ETH_FIFO_XILINX in eth_defines.v). |
// |
// Revision 1.2 2002/03/25 13:33:04 mohor |
// When clear and read/write are active at the same time, cnt and pointers are |
// set to 1. |
// |
// Revision 1.1 2002/02/05 16:44:39 mohor |
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 |
// MHz. Statuses, overrun, control frame transmission and reception still need |
// to be fixed. |
// |
// |
|
`include "ethmac_defines.v" |
`include "timescale.v" |
|
module eth_fifo (data_in, data_out, clk, reset, write, read, clear, |
almost_full, full, almost_empty, empty, cnt); |
|
parameter DATA_WIDTH = 32; |
parameter DEPTH = 8; |
parameter CNT_WIDTH = 4; |
|
input clk; |
input reset; |
input write; |
input read; |
input clear; |
input [DATA_WIDTH-1:0] data_in; |
|
output [DATA_WIDTH-1:0] data_out; |
output almost_full; |
output full; |
output almost_empty; |
output empty; |
output [CNT_WIDTH-1:0] cnt; |
|
`ifdef ETH_FIFO_XILINX |
`else |
`ifdef ETH_ALTERA_ALTSYNCRAM |
`else |
reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1]; |
reg [DATA_WIDTH-1:0] data_out; |
`endif |
`endif |
|
reg [CNT_WIDTH-1:0] cnt; |
reg [CNT_WIDTH-2:0] read_pointer; |
reg [CNT_WIDTH-2:0] write_pointer; |
|
|
always @ (posedge clk or posedge reset) |
begin |
if(reset) |
cnt <= 0; |
else |
if(clear) |
cnt <= { {(CNT_WIDTH-1){1'b0}}, read^write}; |
else |
if(read ^ write) |
if(read) |
cnt <= cnt - 1; |
else |
cnt <= cnt + 1; |
end |
|
|
always @ (posedge clk or posedge reset) |
begin |
if(reset) |
read_pointer <= 0; |
else |
if(clear) |
read_pointer <= { {(CNT_WIDTH-2){1'b0}}, read}; |
else |
if(read & ~empty) |
read_pointer <= read_pointer + 1'b1; |
end |
|
always @ (posedge clk or posedge reset) |
begin |
if(reset) |
write_pointer <= 0; |
else |
if(clear) |
write_pointer <= { {(CNT_WIDTH-2){1'b0}}, write}; |
else |
if(write & ~full) |
write_pointer <= write_pointer + 1'b1; |
end |
|
assign empty = ~(|cnt); |
assign almost_empty = cnt == 1; |
assign full = cnt == DEPTH; |
assign almost_full = &cnt[CNT_WIDTH-2:0]; |
|
|
|
`ifdef ETH_FIFO_XILINX |
xilinx_dist_ram_16x32 fifo |
( .data_out(data_out), |
.we(write & ~full), |
.data_in(data_in), |
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer), |
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer), |
.wclk(clk) |
); |
`else // !ETH_FIFO_XILINX |
`ifdef ETH_ALTERA_ALTSYNCRAM |
altera_dpram_16x32 altera_dpram_16x32_inst |
( |
.data (data_in), |
.wren (write & ~full), |
.wraddress (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer), |
.rdaddress (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ), |
.clock (clk), |
.q (data_out) |
); //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE |
`else // !ETH_ALTERA_ALTSYNCRAM |
always @ (posedge clk) |
begin |
if(write & clear) |
fifo[0] <= data_in; |
else |
if(write & ~full) |
fifo[write_pointer] <= data_in; |
end |
|
|
always @ (posedge clk) |
begin |
if(clear) |
data_out <= fifo[0]; |
else |
data_out <= fifo[read_pointer]; |
end |
`endif // !ETH_ALTERA_ALTSYNCRAM |
`endif // !ETH_FIFO_XILINX |
|
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_random.v
0,0 → 1,139
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_random.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// - Novan Hartadi (novan@vlsi.itb.ac.id) //// |
//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.2 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// Revision 1.3 2001/06/19 18:16:40 mohor |
// TxClk changed to MTxClk (as discribed in the documentation). |
// Crc changed so only one file can be used instead of two. |
// |
// Revision 1.2 2001/06/19 10:38:07 mohor |
// Minor changes in header. |
// |
// Revision 1.1 2001/06/19 10:27:57 mohor |
// TxEthMAC initial release. |
// |
// |
// |
// |
|
`include "timescale.v" |
|
module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt, |
RandomEq0, RandomEqByteCnt); |
|
input MTxClk; |
input Reset; |
input StateJam; |
input StateJam_q; |
input [3:0] RetryCnt; |
input [15:0] NibCnt; |
input [9:0] ByteCnt; |
output RandomEq0; |
output RandomEqByteCnt; |
|
wire Feedback; |
reg [9:0] x; |
wire [9:0] Random; |
reg [9:0] RandomLatched; |
|
|
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
x[9:0] <= 0; |
else |
x[9:0] <= {x[8:0], Feedback}; |
end |
|
assign Feedback = ~(x[2] ^ x[9]); |
|
assign Random [0] = x[0]; |
assign Random [1] = (RetryCnt > 1) ? x[1] : 1'b0; |
assign Random [2] = (RetryCnt > 2) ? x[2] : 1'b0; |
assign Random [3] = (RetryCnt > 3) ? x[3] : 1'b0; |
assign Random [4] = (RetryCnt > 4) ? x[4] : 1'b0; |
assign Random [5] = (RetryCnt > 5) ? x[5] : 1'b0; |
assign Random [6] = (RetryCnt > 6) ? x[6] : 1'b0; |
assign Random [7] = (RetryCnt > 7) ? x[7] : 1'b0; |
assign Random [8] = (RetryCnt > 8) ? x[8] : 1'b0; |
assign Random [9] = (RetryCnt > 9) ? x[9] : 1'b0; |
|
|
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
RandomLatched <= 10'h000; |
else |
begin |
if(StateJam & StateJam_q) |
RandomLatched <= Random; |
end |
end |
|
// Random Number == 0 IEEE 802.3 page 68. If 0 we go to defer and not to backoff. |
assign RandomEq0 = RandomLatched == 10'h0; |
|
assign RandomEqByteCnt = ByteCnt[9:0] == RandomLatched & (&NibCnt[6:0]); |
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_cop.v
0,0 → 1,399
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_cop.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001, 2002 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/10/10 16:43:59 mohor |
// Minor $display change. |
// |
// Revision 1.2 2002/09/09 12:54:13 mohor |
// error acknowledge cycle termination added to display. |
// |
// Revision 1.1 2002/08/14 17:16:07 mohor |
// Traffic cop with 2 wishbone master interfaces and 2 wishbona slave |
// interfaces: |
// - Host connects to the master interface |
// - Ethernet master (DMA) connects to the second master interface |
// - Memory interface connects to the slave interface |
// - Ethernet slave interface (access to registers and BDs) connects to second |
// slave interface |
// |
// |
// |
// |
// |
|
`include "timescale.v" |
|
module eth_cop |
( |
// WISHBONE common |
wb_clk_i, wb_rst_i, |
|
// WISHBONE MASTER 1 |
m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i, m1_wb_dat_o, |
m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o, |
m1_wb_err_o, |
|
// WISHBONE MASTER 2 |
m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i, m2_wb_dat_o, |
m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o, |
m2_wb_err_o, |
|
// WISHBONE slave 1 |
s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o, s1_wb_cyc_o, |
s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i, |
s1_wb_dat_o, |
|
// WISHBONE slave 2 |
s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o, s2_wb_cyc_o, |
s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i, |
s2_wb_dat_o |
); |
|
parameter ETH_BASE = 32'hd0000000; |
parameter ETH_WIDTH = 32'h800; |
parameter MEMORY_BASE = 32'h2000; |
parameter MEMORY_WIDTH = 32'h10000; |
|
// WISHBONE common |
input wb_clk_i, wb_rst_i; |
|
// WISHBONE MASTER 1 |
input [31:0] m1_wb_adr_i, m1_wb_dat_i; |
input [3:0] m1_wb_sel_i; |
input m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i; |
output [31:0] m1_wb_dat_o; |
output m1_wb_ack_o, m1_wb_err_o; |
|
// WISHBONE MASTER 2 |
input [31:0] m2_wb_adr_i, m2_wb_dat_i; |
input [3:0] m2_wb_sel_i; |
input m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i; |
output [31:0] m2_wb_dat_o; |
output m2_wb_ack_o, m2_wb_err_o; |
|
// WISHBONE slave 1 |
input [31:0] s1_wb_dat_i; |
input s1_wb_ack_i, s1_wb_err_i; |
output [31:0] s1_wb_adr_o, s1_wb_dat_o; |
output [3:0] s1_wb_sel_o; |
output s1_wb_we_o, s1_wb_cyc_o, s1_wb_stb_o; |
|
// WISHBONE slave 2 |
input [31:0] s2_wb_dat_i; |
input s2_wb_ack_i, s2_wb_err_i; |
output [31:0] s2_wb_adr_o, s2_wb_dat_o; |
output [3:0] s2_wb_sel_o; |
output s2_wb_we_o, s2_wb_cyc_o, s2_wb_stb_o; |
|
reg m1_in_progress; |
reg m2_in_progress; |
reg [31:0] s1_wb_adr_o; |
reg [3:0] s1_wb_sel_o; |
reg s1_wb_we_o; |
reg [31:0] s1_wb_dat_o; |
reg s1_wb_cyc_o; |
reg s1_wb_stb_o; |
reg [31:0] s2_wb_adr_o; |
reg [3:0] s2_wb_sel_o; |
reg s2_wb_we_o; |
reg [31:0] s2_wb_dat_o; |
reg s2_wb_cyc_o; |
reg s2_wb_stb_o; |
|
reg m1_wb_ack_o; |
reg [31:0] m1_wb_dat_o; |
reg m2_wb_ack_o; |
reg [31:0] m2_wb_dat_o; |
|
reg m1_wb_err_o; |
reg m2_wb_err_o; |
|
wire m_wb_access_finished; |
wire m1_addressed_s1 = (m1_wb_adr_i >= ETH_BASE) & |
(m1_wb_adr_i < (ETH_BASE + ETH_WIDTH)); |
wire m1_addressed_s2 = (m1_wb_adr_i >= MEMORY_BASE) & |
(m1_wb_adr_i < (MEMORY_BASE + MEMORY_WIDTH)); |
wire m2_addressed_s1 = (m2_wb_adr_i >= ETH_BASE) & |
(m2_wb_adr_i < (ETH_BASE + ETH_WIDTH)); |
wire m2_addressed_s2 = (m2_wb_adr_i >= MEMORY_BASE) & |
(m2_wb_adr_i < (MEMORY_BASE + MEMORY_WIDTH)); |
|
wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (m1_addressed_s1 | m1_addressed_s2); |
wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (m2_addressed_s1 | m2_addressed_s2); |
|
always @ (posedge wb_clk_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
begin |
m1_in_progress <= 0; |
m2_in_progress <= 0; |
s1_wb_adr_o <= 0; |
s1_wb_sel_o <= 0; |
s1_wb_we_o <= 0; |
s1_wb_dat_o <= 0; |
s1_wb_cyc_o <= 0; |
s1_wb_stb_o <= 0; |
s2_wb_adr_o <= 0; |
s2_wb_sel_o <= 0; |
s2_wb_we_o <= 0; |
s2_wb_dat_o <= 0; |
s2_wb_cyc_o <= 0; |
s2_wb_stb_o <= 0; |
end |
else |
begin |
case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished}) // synopsys_full_case synopsys_paralel_case |
5'b00_10_0, 5'b00_11_0 : |
begin |
m1_in_progress <= 1'b1; // idle: m1 or (m1 & m2) want access: m1 -> m |
if(m1_addressed_s1) |
begin |
s1_wb_adr_o <= m1_wb_adr_i; |
s1_wb_sel_o <= m1_wb_sel_i; |
s1_wb_we_o <= m1_wb_we_i; |
s1_wb_dat_o <= m1_wb_dat_i; |
s1_wb_cyc_o <= 1'b1; |
s1_wb_stb_o <= 1'b1; |
end |
else if(m1_addressed_s2) |
begin |
s2_wb_adr_o <= m1_wb_adr_i; |
s2_wb_sel_o <= m1_wb_sel_i; |
s2_wb_we_o <= m1_wb_we_i; |
s2_wb_dat_o <= m1_wb_dat_i; |
s2_wb_cyc_o <= 1'b1; |
s2_wb_stb_o <= 1'b1; |
end |
else |
$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time); |
end |
5'b00_01_0 : |
begin |
m2_in_progress <= 1'b1; // idle: m2 wants access: m2 -> m |
if(m2_addressed_s1) |
begin |
s1_wb_adr_o <= m2_wb_adr_i; |
s1_wb_sel_o <= m2_wb_sel_i; |
s1_wb_we_o <= m2_wb_we_i; |
s1_wb_dat_o <= m2_wb_dat_i; |
s1_wb_cyc_o <= 1'b1; |
s1_wb_stb_o <= 1'b1; |
end |
else if(m2_addressed_s2) |
begin |
s2_wb_adr_o <= m2_wb_adr_i; |
s2_wb_sel_o <= m2_wb_sel_i; |
s2_wb_we_o <= m2_wb_we_i; |
s2_wb_dat_o <= m2_wb_dat_i; |
s2_wb_cyc_o <= 1'b1; |
s2_wb_stb_o <= 1'b1; |
end |
else |
$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time); |
end |
5'b10_10_1, 5'b10_11_1 : |
begin |
m1_in_progress <= 1'b0; // m1 in progress. Cycle is finished. Send ack or err to m1. |
if(m1_addressed_s1) |
begin |
s1_wb_cyc_o <= 1'b0; |
s1_wb_stb_o <= 1'b0; |
end |
else if(m1_addressed_s2) |
begin |
s2_wb_cyc_o <= 1'b0; |
s2_wb_stb_o <= 1'b0; |
end |
end |
5'b01_01_1, 5'b01_11_1 : |
begin |
m2_in_progress <= 1'b0; // m2 in progress. Cycle is finished. Send ack or err to m2. |
if(m2_addressed_s1) |
begin |
s1_wb_cyc_o <= 1'b0; |
s1_wb_stb_o <= 1'b0; |
end |
else if(m2_addressed_s2) |
begin |
s2_wb_cyc_o <= 1'b0; |
s2_wb_stb_o <= 1'b0; |
end |
end |
endcase |
end |
end |
|
// Generating Ack for master 1 |
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or m1_addressed_s1 or m1_addressed_s2) |
begin |
if(m1_in_progress) |
begin |
if(m1_addressed_s1) begin |
m1_wb_ack_o <= s1_wb_ack_i; |
m1_wb_dat_o <= s1_wb_dat_i; |
end |
else if(m1_addressed_s2) begin |
m1_wb_ack_o <= s2_wb_ack_i; |
m1_wb_dat_o <= s2_wb_dat_i; |
end |
end |
else |
m1_wb_ack_o <= 0; |
end |
|
|
// Generating Ack for master 2 |
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or m2_addressed_s1 or m2_addressed_s2) |
begin |
if(m2_in_progress) |
begin |
if(m2_addressed_s1) begin |
m2_wb_ack_o <= s1_wb_ack_i; |
m2_wb_dat_o <= s1_wb_dat_i; |
end |
else if(m2_addressed_s2) begin |
m2_wb_ack_o <= s2_wb_ack_i; |
m2_wb_dat_o <= s2_wb_dat_i; |
end |
end |
else |
m2_wb_ack_o <= 0; |
end |
|
|
// Generating Err for master 1 |
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or m2_addressed_s1 or m2_addressed_s2 or |
m1_wb_cyc_i or m1_wb_stb_i) |
begin |
if(m1_in_progress) begin |
if(m1_addressed_s1) |
m1_wb_err_o <= s1_wb_err_i; |
else if(m1_addressed_s2) |
m1_wb_err_o <= s2_wb_err_i; |
end |
else if(m1_wb_cyc_i & m1_wb_stb_i & ~m1_addressed_s1 & ~m1_addressed_s2) |
m1_wb_err_o <= 1'b1; |
else |
m1_wb_err_o <= 1'b0; |
end |
|
|
// Generating Err for master 2 |
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or m2_addressed_s1 or m2_addressed_s2 or |
m2_wb_cyc_i or m2_wb_stb_i) |
begin |
if(m2_in_progress) begin |
if(m2_addressed_s1) |
m2_wb_err_o <= s1_wb_err_i; |
else if(m2_addressed_s2) |
m2_wb_err_o <= s2_wb_err_i; |
end |
else if(m2_wb_cyc_i & m2_wb_stb_i & ~m2_addressed_s1 & ~m2_addressed_s2) |
m2_wb_err_o <= 1'b1; |
else |
m2_wb_err_o <= 1'b0; |
end |
|
|
assign m_wb_access_finished = m1_wb_ack_o | m1_wb_err_o | m2_wb_ack_o | m2_wb_err_o; |
|
|
// Activity monitor |
integer cnt; |
always @ (posedge wb_clk_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
cnt <= 0; |
else |
if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i) |
cnt <= 0; |
else |
if(s1_wb_cyc_o | s2_wb_cyc_o) |
cnt <= cnt+1; |
end |
|
always @ (posedge wb_clk_i) |
begin |
if(cnt==1000) begin |
$display("(%0t)(%m) ERROR: WB activity ??? ", $time); |
if(s1_wb_cyc_o) begin |
$display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o); |
$display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o); |
$display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o); |
$display("s1_wb_we_o = 0x%0x", s1_wb_we_o); |
end |
else if(s2_wb_cyc_o) begin |
$display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o); |
$display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o); |
$display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o); |
$display("s2_wb_we_o = 0x%0x", s2_wb_we_o); |
end |
|
$stop; |
end |
end |
|
|
always @ (posedge wb_clk_i) |
begin |
if(s1_wb_err_i & s1_wb_cyc_o) begin |
$display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time); |
$display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o); |
$display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o); |
$display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o); |
$display("s1_wb_we_o = 0x%0x", s1_wb_we_o); |
$stop; |
end |
if(s2_wb_err_i & s2_wb_cyc_o) begin |
$display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time); |
$display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o); |
$display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o); |
$display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o); |
$display("s2_wb_we_o = 0x%0x", s2_wb_we_o); |
$stop; |
end |
end |
|
|
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_rxaddrcheck.v
0,0 → 1,214
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_rxaddrcheck.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac/ //// |
//// //// |
//// Author(s): //// |
//// - Bill Dittenhofer (billditt@aol.com) //// |
//// - Olof Kindgren (olof@opencores.org) //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001, 2011 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// 2011-07-06 Olof Kindgren <olof@opencores.org> |
// Reset AdressMiss when a new frame arrives. Otherwise it will report |
// the last value when a frame is less than seven bytes |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2002/11/19 17:34:52 mohor |
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying |
// that a frame was received because of the promiscous mode. |
// |
// Revision 1.7 2002/09/04 18:41:06 mohor |
// Bug when last byte of destination address was not checked fixed. |
// |
// Revision 1.6 2002/03/20 15:14:11 mohor |
// When in promiscous mode some frames were not received correctly. Fixed. |
// |
// Revision 1.5 2002/03/02 21:06:32 mohor |
// Log info was missing. |
// |
// |
// Revision 1.1 2002/02/08 12:51:54 ditt |
// Initial release of the ethernet addresscheck module. |
// |
// |
// |
// |
// |
|
|
`include "timescale.v" |
|
|
module eth_rxaddrcheck(MRxClk, Reset, RxData, Broadcast ,r_Bro ,r_Pro, |
ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5, |
ByteCntEq6, ByteCntEq7, HASH0, HASH1, ByteCntEq0, |
CrcHash, CrcHashGood, StateData, RxEndFrm, |
Multicast, MAC, RxAbort, AddressMiss, PassAll, |
ControlFrmAddressOK |
); |
|
|
input MRxClk; |
input Reset; |
input [7:0] RxData; |
input Broadcast; |
input r_Bro; |
input r_Pro; |
input ByteCntEq0; |
input ByteCntEq2; |
input ByteCntEq3; |
input ByteCntEq4; |
input ByteCntEq5; |
input ByteCntEq6; |
input ByteCntEq7; |
input [31:0] HASH0; |
input [31:0] HASH1; |
input [5:0] CrcHash; |
input CrcHashGood; |
input Multicast; |
input [47:0] MAC; |
input [1:0] StateData; |
input RxEndFrm; |
input PassAll; |
input ControlFrmAddressOK; |
|
output RxAbort; |
output AddressMiss; |
|
wire BroadcastOK; |
wire ByteCntEq2; |
wire ByteCntEq3; |
wire ByteCntEq4; |
wire ByteCntEq5; |
wire RxAddressInvalid; |
wire RxCheckEn; |
wire HashBit; |
wire [31:0] IntHash; |
reg [7:0] ByteHash; |
reg MulticastOK; |
reg UnicastOK; |
reg RxAbort; |
reg AddressMiss; |
|
assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK | r_Pro); |
|
assign BroadcastOK = Broadcast & ~r_Bro; |
|
assign RxCheckEn = | StateData; |
|
// Address Error Reported at end of address cycle |
// RxAbort clears after one cycle |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxAbort <= 1'b0; |
else if(RxAddressInvalid & ByteCntEq7 & RxCheckEn) |
RxAbort <= 1'b1; |
else |
RxAbort <= 1'b0; |
end |
|
|
// This ff holds the "Address Miss" information that is written to the RX BD status. |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
AddressMiss <= 1'b0; |
else if(ByteCntEq0) |
AddressMiss <= 1'b0; |
else if(ByteCntEq7 & RxCheckEn) |
AddressMiss <= (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK))); |
end |
|
|
// Hash Address Check, Multicast |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
MulticastOK <= 1'b0; |
else if(RxEndFrm | RxAbort) |
MulticastOK <= 1'b0; |
else if(CrcHashGood & Multicast) |
MulticastOK <= HashBit; |
end |
|
|
// Address Detection (unicast) |
// start with ByteCntEq2 due to delay of addres from RxData |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
UnicastOK <= 1'b0; |
else |
if(RxCheckEn & ByteCntEq2) |
UnicastOK <= RxData[7:0] == MAC[47:40]; |
else |
if(RxCheckEn & ByteCntEq3) |
UnicastOK <= ( RxData[7:0] == MAC[39:32]) & UnicastOK; |
else |
if(RxCheckEn & ByteCntEq4) |
UnicastOK <= ( RxData[7:0] == MAC[31:24]) & UnicastOK; |
else |
if(RxCheckEn & ByteCntEq5) |
UnicastOK <= ( RxData[7:0] == MAC[23:16]) & UnicastOK; |
else |
if(RxCheckEn & ByteCntEq6) |
UnicastOK <= ( RxData[7:0] == MAC[15:8]) & UnicastOK; |
else |
if(RxCheckEn & ByteCntEq7) |
UnicastOK <= ( RxData[7:0] == MAC[7:0]) & UnicastOK; |
else |
if(RxEndFrm | RxAbort) |
UnicastOK <= 1'b0; |
end |
|
assign IntHash = (CrcHash[5])? HASH1 : HASH0; |
|
always@(CrcHash or IntHash) |
begin |
case(CrcHash[4:3]) |
2'b00: ByteHash = IntHash[7:0]; |
2'b01: ByteHash = IntHash[15:8]; |
2'b10: ByteHash = IntHash[23:16]; |
2'b11: ByteHash = IntHash[31:24]; |
endcase |
end |
|
assign HashBit = ByteHash[CrcHash[2:0]]; |
|
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_fifo.v
0,0 → 1,218
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_fifo.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/04/22 13:45:52 mohor |
// Generic ram or Xilinx ram can be used in fifo (selectable by setting |
// ETH_FIFO_XILINX in eth_defines.v). |
// |
// Revision 1.2 2002/03/25 13:33:04 mohor |
// When clear and read/write are active at the same time, cnt and pointers are |
// set to 1. |
// |
// Revision 1.1 2002/02/05 16:44:39 mohor |
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 |
// MHz. Statuses, overrun, control frame transmission and reception still need |
// to be fixed. |
// |
// |
|
`include "ethmac_defines.v" |
`include "timescale.v" |
|
module eth_fifo (data_in, data_out, clk, reset, write, read, clear, |
almost_full, full, almost_empty, empty, cnt); |
|
parameter DATA_WIDTH = 32; |
parameter DEPTH = 8; |
parameter CNT_WIDTH = 4; |
|
input clk; |
input reset; |
input write; |
input read; |
input clear; |
input [DATA_WIDTH-1:0] data_in; |
|
output [DATA_WIDTH-1:0] data_out; |
output almost_full; |
output full; |
output almost_empty; |
output empty; |
output [CNT_WIDTH-1:0] cnt; |
|
`ifdef ETH_FIFO_XILINX |
`else |
`ifdef ETH_ALTERA_ALTSYNCRAM |
`else |
reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1]; |
reg [DATA_WIDTH-1:0] data_out; |
`endif |
`endif |
|
reg [CNT_WIDTH-1:0] cnt; |
reg [CNT_WIDTH-2:0] read_pointer; |
reg [CNT_WIDTH-2:0] write_pointer; |
|
|
always @ (posedge clk or posedge reset) |
begin |
if(reset) |
cnt <= 0; |
else |
if(clear) |
cnt <= { {(CNT_WIDTH-1){1'b0}}, read^write}; |
else |
if(read ^ write) |
if(read) |
cnt <= cnt - 1; |
else |
cnt <= cnt + 1; |
end |
|
|
always @ (posedge clk or posedge reset) |
begin |
if(reset) |
read_pointer <= 0; |
else |
if(clear) |
read_pointer <= { {(CNT_WIDTH-2){1'b0}}, read}; |
else |
if(read & ~empty) |
read_pointer <= read_pointer + 1'b1; |
end |
|
always @ (posedge clk or posedge reset) |
begin |
if(reset) |
write_pointer <= 0; |
else |
if(clear) |
write_pointer <= { {(CNT_WIDTH-2){1'b0}}, write}; |
else |
if(write & ~full) |
write_pointer <= write_pointer + 1'b1; |
end |
|
assign empty = ~(|cnt); |
assign almost_empty = cnt == 1; |
assign full = cnt == DEPTH; |
assign almost_full = &cnt[CNT_WIDTH-2:0]; |
|
|
|
`ifdef ETH_FIFO_XILINX |
xilinx_dist_ram_16x32 fifo |
( .data_out(data_out), |
.we(write & ~full), |
.data_in(data_in), |
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer), |
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer), |
.wclk(clk) |
); |
`else // !ETH_FIFO_XILINX |
`ifdef ETH_ALTERA_ALTSYNCRAM |
|
|
|
/* |
altera_dpram_16x32 altera_dpram_16x32_inst |
( |
.data (data_in), |
.wren (write & ~full), |
.wraddress (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer), |
.rdaddress (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ), |
.clock (clk), |
.q (data_out) |
); //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE |
|
alt_dpram alt_dpram_inst ( |
.clock ( clk ), |
.data ( data_in ), |
.rdaddress ( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ), |
.wraddress ( clear ? {CNT_WIDTH-1{1'b0}} : write_pointer ), |
.wren ( write & ~full ), |
.q ( data_out ) |
); |
*/ |
|
simple_dual_port_ram |
#( |
.Dw(DATA_WIDTH), |
.Aw(CNT_WIDTH-1) |
) |
dpram |
( |
.data(data_in), |
.read_addr (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer), |
.write_addr(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer), |
.we( write & ~full), |
.clk(clk), |
.q(data_out) |
); |
|
|
|
`else // !ETH_ALTERA_ALTSYNCRAM |
always @ (posedge clk) |
begin |
if(write & clear) |
fifo[0] <= data_in; |
else |
if(write & ~full) |
fifo[write_pointer] <= data_in; |
end |
|
|
always @ (posedge clk) |
begin |
if(clear) |
data_out <= fifo[0]; |
else |
data_out <= fifo[read_pointer]; |
end |
`endif // !ETH_ALTERA_ALTSYNCRAM |
`endif // !ETH_FIFO_XILINX |
|
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/ethmac_defines.v.bak
0,0 → 1,335
////////////////////////////////////////////////////////////////////// |
//// //// |
//// ethmac_defines.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is available in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001, 2002 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// Renamed from eth_defines.v to ethmac_defines.v to fit better into |
// OpenCores defined project structure 2011-08-04 olof@opencores.org |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.33 2003/11/12 18:24:58 tadejm |
// WISHBONE slave changed and tested from only 32-bit accesss to byte access. |
// |
// Revision 1.32 2003/10/17 07:46:13 markom |
// mbist signals updated according to newest convention |
// |
// Revision 1.31 2003/08/14 16:42:58 simons |
// Artisan ram instance added. |
// |
// Revision 1.30 2003/06/13 11:55:37 mohor |
// Define file in eth_cop.v is changed to eth_defines.v. Some defines were |
// moved from tb_eth_defines.v to eth_defines.v. |
// |
// Revision 1.29 2002/11/19 18:13:49 mohor |
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. |
// |
// Revision 1.28 2002/11/15 14:27:15 mohor |
// Since r_Rst bit is not used any more, default value is changed to 0xa000. |
// |
// Revision 1.27 2002/11/01 18:19:34 mohor |
// Defines fixed to use generic RAM by default. |
// |
// Revision 1.26 2002/10/24 18:53:03 mohor |
// fpga define added. |
// |
// Revision 1.3 2002/10/11 16:57:54 igorm |
// eth_defines.v tagged with rel_5 used. |
// |
// Revision 1.25 2002/10/10 16:47:44 mohor |
// Defines changed to have ETH_ prolog. |
// ETH_WISHBONE_B# define added. |
// |
// Revision 1.24 2002/10/10 16:33:11 mohor |
// Bist added. |
// |
// Revision 1.23 2002/09/23 18:22:48 mohor |
// Virtual Silicon RAM might be used in the ASIC implementation of the ethernet |
// core. |
// |
// Revision 1.22 2002/09/04 18:36:49 mohor |
// Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). |
// |
// Revision 1.21 2002/08/16 22:09:47 mohor |
// Defines for register width added. mii_rst signal in MIIMODER register |
// changed. |
// |
// Revision 1.20 2002/08/14 19:31:48 mohor |
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No |
// need to multiply or devide any more. |
// |
// Revision 1.19 2002/07/23 15:28:31 mohor |
// Ram , used for BDs changed from generic_spram to eth_spram_256x32. |
// |
// Revision 1.18 2002/05/03 10:15:50 mohor |
// Outputs registered. Reset changed for eth_wishbone module. |
// |
// Revision 1.17 2002/04/24 08:52:19 mohor |
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision" |
// bug fixed. |
// |
// Revision 1.16 2002/03/19 12:53:29 mohor |
// Some defines that are used in testbench only were moved to tb_eth_defines.v |
// file. |
// |
// Revision 1.15 2002/02/26 16:11:32 mohor |
// Number of interrupts changed |
// |
// Revision 1.14 2002/02/16 14:03:44 mohor |
// Registered trimmed. Unused registers removed. |
// |
// Revision 1.13 2002/02/16 13:06:33 mohor |
// EXTERNAL_DMA used instead of WISHBONE_DMA. |
// |
// Revision 1.12 2002/02/15 10:58:31 mohor |
// Changed that were lost with last update put back to the file. |
// |
// Revision 1.11 2002/02/14 20:19:41 billditt |
// Modified for Address Checking, |
// addition of eth_addrcheck.v |
// |
// Revision 1.10 2002/02/12 17:01:19 mohor |
// HASH0 and HASH1 registers added. |
|
// Revision 1.9 2002/02/08 16:21:54 mohor |
// Rx status is written back to the BD. |
// |
// Revision 1.8 2002/02/05 16:44:38 mohor |
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 |
// MHz. Statuses, overrun, control frame transmission and reception still need |
// to be fixed. |
// |
// Revision 1.7 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.6 2001/12/05 15:00:16 mohor |
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors |
// instead of the number of RX descriptors). |
// |
// Revision 1.5 2001/12/05 10:21:37 mohor |
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. |
// |
// Revision 1.4 2001/11/13 14:23:56 mohor |
// Generic memory model is used. Defines are changed for the same reason. |
// |
// Revision 1.3 2001/10/18 12:07:11 mohor |
// Status signals changed, Adress decoding changed, interrupt controller |
// added. |
// |
// Revision 1.2 2001/09/24 15:02:56 mohor |
// Defines changed (All precede with ETH_). Small changes because some |
// tools generate warnings when two operands are together. Synchronization |
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC |
// demands). |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// |
// |
// |
// |
|
|
|
//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS |
|
`define ETH_MBIST_CTRL_WIDTH 3 // width of MBIST control bus |
|
// Ethernet implemented in Xilinx Chips (uncomment following lines) |
// `define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo |
// `define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors |
// Core is going to be implemented in Virtex FPGA and contains Virtex |
// specific elements. |
|
// Ethernet implemented in Altera Chips (uncomment following lines) |
//`define ETH_ALTERA_ALTSYNCRAM |
|
// Ethernet implemented in ASIC with Virtual Silicon RAMs |
// `define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation) |
|
// Ethernet implemented in ASIC with Artisan RAMs |
// `define ETH_ARTISAN_RAM // Artisan RAMS used storing buffer decriptors (ASIC implementation) |
|
// Uncomment when Avalon bus is used |
//`define ETH_AVALON_BUS |
|
`define ETH_MODER_ADR 8'h0 // 0x0 |
`define ETH_INT_SOURCE_ADR 8'h1 // 0x4 |
`define ETH_INT_MASK_ADR 8'h2 // 0x8 |
`define ETH_IPGT_ADR 8'h3 // 0xC |
`define ETH_IPGR1_ADR 8'h4 // 0x10 |
`define ETH_IPGR2_ADR 8'h5 // 0x14 |
`define ETH_PACKETLEN_ADR 8'h6 // 0x18 |
`define ETH_COLLCONF_ADR 8'h7 // 0x1C |
`define ETH_TX_BD_NUM_ADR 8'h8 // 0x20 |
`define ETH_CTRLMODER_ADR 8'h9 // 0x24 |
`define ETH_MIIMODER_ADR 8'hA // 0x28 |
`define ETH_MIICOMMAND_ADR 8'hB // 0x2C |
`define ETH_MIIADDRESS_ADR 8'hC // 0x30 |
`define ETH_MIITX_DATA_ADR 8'hD // 0x34 |
`define ETH_MIIRX_DATA_ADR 8'hE // 0x38 |
`define ETH_MIISTATUS_ADR 8'hF // 0x3C |
`define ETH_MAC_ADDR0_ADR 8'h10 // 0x40 |
`define ETH_MAC_ADDR1_ADR 8'h11 // 0x44 |
`define ETH_HASH0_ADR 8'h12 // 0x48 |
`define ETH_HASH1_ADR 8'h13 // 0x4C |
`define ETH_TX_CTRL_ADR 8'h14 // 0x50 |
`define ETH_RX_CTRL_ADR 8'h15 // 0x54 |
`define ETH_DBG_ADR 8'h16 // 0x58 |
|
`define ETH_MODER_DEF_0 8'h00 |
`define ETH_MODER_DEF_1 8'hA0 |
`define ETH_MODER_DEF_2 1'h0 |
`define ETH_INT_MASK_DEF_0 7'h0 |
`define ETH_IPGT_DEF_0 7'h12 |
`define ETH_IPGR1_DEF_0 7'h0C |
`define ETH_IPGR2_DEF_0 7'h12 |
`define ETH_PACKETLEN_DEF_0 8'h00 |
`define ETH_PACKETLEN_DEF_1 8'h06 |
`define ETH_PACKETLEN_DEF_2 8'h40 |
`define ETH_PACKETLEN_DEF_3 8'h00 |
`define ETH_COLLCONF_DEF_0 6'h3f |
`define ETH_COLLCONF_DEF_2 4'hF |
`define ETH_TX_BD_NUM_DEF_0 8'h40 |
`define ETH_CTRLMODER_DEF_0 3'h0 |
`define ETH_MIIMODER_DEF_0 8'h64 |
`define ETH_MIIMODER_DEF_1 1'h0 |
`define ETH_MIIADDRESS_DEF_0 5'h00 |
`define ETH_MIIADDRESS_DEF_1 5'h00 |
`define ETH_MIITX_DATA_DEF_0 8'h00 |
`define ETH_MIITX_DATA_DEF_1 8'h00 |
`define ETH_MIIRX_DATA_DEF 16'h0000 // not written from WB |
`define ETH_MAC_ADDR0_DEF_0 8'h00 |
`define ETH_MAC_ADDR0_DEF_1 8'h00 |
`define ETH_MAC_ADDR0_DEF_2 8'h00 |
`define ETH_MAC_ADDR0_DEF_3 8'h00 |
`define ETH_MAC_ADDR1_DEF_0 8'h00 |
`define ETH_MAC_ADDR1_DEF_1 8'h00 |
`define ETH_HASH0_DEF_0 8'h00 |
`define ETH_HASH0_DEF_1 8'h00 |
`define ETH_HASH0_DEF_2 8'h00 |
`define ETH_HASH0_DEF_3 8'h00 |
`define ETH_HASH1_DEF_0 8'h00 |
`define ETH_HASH1_DEF_1 8'h00 |
`define ETH_HASH1_DEF_2 8'h00 |
`define ETH_HASH1_DEF_3 8'h00 |
`define ETH_TX_CTRL_DEF_0 8'h00 // |
`define ETH_TX_CTRL_DEF_1 8'h00 // |
`define ETH_TX_CTRL_DEF_2 1'h0 // |
`define ETH_RX_CTRL_DEF_0 8'h00 |
`define ETH_RX_CTRL_DEF_1 8'h00 |
|
|
`define ETH_MODER_WIDTH_0 8 |
`define ETH_MODER_WIDTH_1 8 |
`define ETH_MODER_WIDTH_2 1 |
`define ETH_INT_SOURCE_WIDTH_0 7 |
`define ETH_INT_MASK_WIDTH_0 7 |
`define ETH_IPGT_WIDTH_0 7 |
`define ETH_IPGR1_WIDTH_0 7 |
`define ETH_IPGR2_WIDTH_0 7 |
`define ETH_PACKETLEN_WIDTH_0 8 |
`define ETH_PACKETLEN_WIDTH_1 8 |
`define ETH_PACKETLEN_WIDTH_2 8 |
`define ETH_PACKETLEN_WIDTH_3 8 |
`define ETH_COLLCONF_WIDTH_0 6 |
`define ETH_COLLCONF_WIDTH_2 4 |
`define ETH_TX_BD_NUM_WIDTH_0 8 |
`define ETH_CTRLMODER_WIDTH_0 3 |
`define ETH_MIIMODER_WIDTH_0 8 |
`define ETH_MIIMODER_WIDTH_1 1 |
`define ETH_MIICOMMAND_WIDTH_0 3 |
`define ETH_MIIADDRESS_WIDTH_0 5 |
`define ETH_MIIADDRESS_WIDTH_1 5 |
`define ETH_MIITX_DATA_WIDTH_0 8 |
`define ETH_MIITX_DATA_WIDTH_1 8 |
`define ETH_MIIRX_DATA_WIDTH 16 // not written from WB |
`define ETH_MIISTATUS_WIDTH 3 // not written from WB |
`define ETH_MAC_ADDR0_WIDTH_0 8 |
`define ETH_MAC_ADDR0_WIDTH_1 8 |
`define ETH_MAC_ADDR0_WIDTH_2 8 |
`define ETH_MAC_ADDR0_WIDTH_3 8 |
`define ETH_MAC_ADDR1_WIDTH_0 8 |
`define ETH_MAC_ADDR1_WIDTH_1 8 |
`define ETH_HASH0_WIDTH_0 8 |
`define ETH_HASH0_WIDTH_1 8 |
`define ETH_HASH0_WIDTH_2 8 |
`define ETH_HASH0_WIDTH_3 8 |
`define ETH_HASH1_WIDTH_0 8 |
`define ETH_HASH1_WIDTH_1 8 |
`define ETH_HASH1_WIDTH_2 8 |
`define ETH_HASH1_WIDTH_3 8 |
`define ETH_TX_CTRL_WIDTH_0 8 |
`define ETH_TX_CTRL_WIDTH_1 8 |
`define ETH_TX_CTRL_WIDTH_2 1 |
`define ETH_RX_CTRL_WIDTH_0 8 |
`define ETH_RX_CTRL_WIDTH_1 8 |
|
|
// Outputs are registered (uncomment when needed) |
`define ETH_REGISTERED_OUTPUTS |
|
// Settings for TX FIFO |
`define ETH_TX_FIFO_CNT_WIDTH 5 |
`define ETH_TX_FIFO_DEPTH 16 |
`define ETH_TX_FIFO_DATA_WIDTH 32 |
|
// Settings for RX FIFO |
`define ETH_RX_FIFO_CNT_WIDTH 5 |
`define ETH_RX_FIFO_DEPTH 16 |
`define ETH_RX_FIFO_DATA_WIDTH 32 |
|
// Burst length |
`define ETH_BURST_LENGTH 4 // Change also ETH_BURST_CNT_WIDTH |
`define ETH_BURST_CNT_WIDTH 3 // The counter must be width enough to count to ETH_BURST_LENGTH |
|
// WISHBONE interface is Revision B3 compliant (uncomment when needed) |
//`define ETH_WISHBONE_B3 |
|
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_miim.v
0,0 → 1,446
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_miim.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.6 2005/02/21 12:48:07 igorm |
// Warning fixes. |
// |
// Revision 1.5 2003/05/16 10:08:27 mohor |
// Busy was set 2 cycles too late. Reported by Dennis Scott. |
// |
// Revision 1.4 2002/08/14 18:32:10 mohor |
// - Busy signal was not set on time when scan status operation was performed |
// and clock was divided with more than 2. |
// - Nvalid remains valid two more clocks (was previously cleared too soon). |
// |
// Revision 1.3 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.2 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.2 2001/08/02 09:25:31 mohor |
// Unconnected signals are now connected. |
// |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// Revision 1.3 2001/06/01 22:28:56 mohor |
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. |
// |
// |
|
`include "timescale.v" |
|
|
module eth_miim |
( |
Clk, |
Reset, |
Divider, |
NoPre, |
CtrlData, |
Rgad, |
Fiad, |
WCtrlData, |
RStat, |
ScanStat, |
Mdi, |
Mdo, |
MdoEn, |
Mdc, |
Busy, |
Prsd, |
LinkFail, |
Nvalid, |
WCtrlDataStart, |
RStatStart, |
UpdateMIIRX_DATAReg |
); |
|
|
|
input Clk; // Host Clock |
input Reset; // General Reset |
input [7:0] Divider; // Divider for the host clock |
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.) |
input [4:0] Rgad; // Register Address (within the PHY) |
input [4:0] Fiad; // PHY Address |
input NoPre; // No Preamble (no 32-bit preamble) |
input WCtrlData; // Write Control Data operation |
input RStat; // Read Status operation |
input ScanStat; // Scan Status operation |
input Mdi; // MII Management Data In |
|
output Mdc; // MII Management Data Clock |
output Mdo; // MII Management Data Output |
output MdoEn; // MII Management Data Output Enable |
output Busy; // Busy Signal |
output LinkFail; // Link Integrity Signal |
output Nvalid; // Invalid Status (qualifier for the valid scan result) |
|
output [15:0] Prsd; // Read Status Data (data read from the PHY) |
|
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register |
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register |
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data |
|
|
reg Nvalid; |
reg EndBusy_d; // Pre-end Busy signal |
reg EndBusy; // End Busy signal (stops the operation in progress) |
|
reg WCtrlData_q1; // Write Control Data operation delayed 1 Clk cycle |
reg WCtrlData_q2; // Write Control Data operation delayed 2 Clk cycles |
reg WCtrlData_q3; // Write Control Data operation delayed 3 Clk cycles |
reg WCtrlDataStart; // Start Write Control Data Command (positive edge detected) |
reg WCtrlDataStart_q; |
reg WCtrlDataStart_q1; // Start Write Control Data Command delayed 1 Mdc cycle |
reg WCtrlDataStart_q2; // Start Write Control Data Command delayed 2 Mdc cycles |
|
reg RStat_q1; // Read Status operation delayed 1 Clk cycle |
reg RStat_q2; // Read Status operation delayed 2 Clk cycles |
reg RStat_q3; // Read Status operation delayed 3 Clk cycles |
reg RStatStart; // Start Read Status Command (positive edge detected) |
reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc cycle |
reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc cycles |
|
reg ScanStat_q1; // Scan Status operation delayed 1 cycle |
reg ScanStat_q2; // Scan Status operation delayed 2 cycles |
reg SyncStatMdcEn; // Scan Status operation delayed at least cycles and synchronized to MdcEn |
|
wire WriteDataOp; // Write Data Operation (positive edge detected) |
wire ReadStatusOp; // Read Status Operation (positive edge detected) |
wire ScanStatusOp; // Scan Status Operation (positive edge detected) |
wire StartOp; // Start Operation (start of any of the preceding operations) |
wire EndOp; // End of Operation |
|
reg InProgress; // Operation in progress |
reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle |
reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles |
reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles |
|
reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress) |
reg [6:0] BitCounter; // Bit Counter |
|
|
wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register. |
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises. |
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal |
wire MdcEn_n; |
|
wire LatchByte1_d2; |
wire LatchByte0_d2; |
reg LatchByte1_d; |
reg LatchByte0_d; |
reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register |
|
reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data |
|
|
|
|
|
// Generation of the EndBusy signal. It is used for ending the MII Management operation. |
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
begin |
EndBusy_d <= 1'b0; |
EndBusy <= 1'b0; |
end |
else |
begin |
EndBusy_d <= ~InProgress_q2 & InProgress_q3; |
EndBusy <= EndBusy_d; |
end |
end |
|
|
// Update MII RX_DATA register |
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
UpdateMIIRX_DATAReg <= 0; |
else |
if(EndBusy & ~WCtrlDataStart_q) |
UpdateMIIRX_DATAReg <= 1; |
else |
UpdateMIIRX_DATAReg <= 0; |
end |
|
|
|
// Generation of the delayed signals used for positive edge triggering. |
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
begin |
WCtrlData_q1 <= 1'b0; |
WCtrlData_q2 <= 1'b0; |
WCtrlData_q3 <= 1'b0; |
|
RStat_q1 <= 1'b0; |
RStat_q2 <= 1'b0; |
RStat_q3 <= 1'b0; |
|
ScanStat_q1 <= 1'b0; |
ScanStat_q2 <= 1'b0; |
SyncStatMdcEn <= 1'b0; |
end |
else |
begin |
WCtrlData_q1 <= WCtrlData; |
WCtrlData_q2 <= WCtrlData_q1; |
WCtrlData_q3 <= WCtrlData_q2; |
|
RStat_q1 <= RStat; |
RStat_q2 <= RStat_q1; |
RStat_q3 <= RStat_q2; |
|
ScanStat_q1 <= ScanStat; |
ScanStat_q2 <= ScanStat_q1; |
if(MdcEn) |
SyncStatMdcEn <= ScanStat_q2; |
end |
end |
|
|
// Generation of the Start Commands (Write Control Data or Read Status) |
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
begin |
WCtrlDataStart <= 1'b0; |
WCtrlDataStart_q <= 1'b0; |
RStatStart <= 1'b0; |
end |
else |
begin |
if(EndBusy) |
begin |
WCtrlDataStart <= 1'b0; |
RStatStart <= 1'b0; |
end |
else |
begin |
if(WCtrlData_q2 & ~WCtrlData_q3) |
WCtrlDataStart <= 1'b1; |
if(RStat_q2 & ~RStat_q3) |
RStatStart <= 1'b1; |
WCtrlDataStart_q <= WCtrlDataStart; |
end |
end |
end |
|
|
// Generation of the Nvalid signal (indicates when the status is invalid) |
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
Nvalid <= 1'b0; |
else |
begin |
if(~InProgress_q2 & InProgress_q3) |
begin |
Nvalid <= 1'b0; |
end |
else |
begin |
if(ScanStat_q2 & ~SyncStatMdcEn) |
Nvalid <= 1'b1; |
end |
end |
end |
|
// Signals used for the generation of the Operation signals (positive edge) |
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
begin |
WCtrlDataStart_q1 <= 1'b0; |
WCtrlDataStart_q2 <= 1'b0; |
|
RStatStart_q1 <= 1'b0; |
RStatStart_q2 <= 1'b0; |
|
InProgress_q1 <= 1'b0; |
InProgress_q2 <= 1'b0; |
InProgress_q3 <= 1'b0; |
|
LatchByte0_d <= 1'b0; |
LatchByte1_d <= 1'b0; |
|
LatchByte <= 2'b00; |
end |
else |
begin |
if(MdcEn) |
begin |
WCtrlDataStart_q1 <= WCtrlDataStart; |
WCtrlDataStart_q2 <= WCtrlDataStart_q1; |
|
RStatStart_q1 <= RStatStart; |
RStatStart_q2 <= RStatStart_q1; |
|
LatchByte[0] <= LatchByte0_d; |
LatchByte[1] <= LatchByte1_d; |
|
LatchByte0_d <= LatchByte0_d2; |
LatchByte1_d <= LatchByte1_d2; |
|
InProgress_q1 <= InProgress; |
InProgress_q2 <= InProgress_q1; |
InProgress_q3 <= InProgress_q2; |
end |
end |
end |
|
|
// Generation of the Operation signals |
assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2; |
assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2; |
assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2; |
assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp; |
|
// Busy |
assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid; |
|
|
// Generation of the InProgress signal (indicates when an operation is in progress) |
// Generation of the WriteOp signal (indicates when a write is in progress) |
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
begin |
InProgress <= 1'b0; |
WriteOp <= 1'b0; |
end |
else |
begin |
if(MdcEn) |
begin |
if(StartOp) |
begin |
if(~InProgress) |
WriteOp <= WriteDataOp; |
InProgress <= 1'b1; |
end |
else |
begin |
if(EndOp) |
begin |
InProgress <= 1'b0; |
WriteOp <= 1'b0; |
end |
end |
end |
end |
end |
|
|
|
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted) |
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
BitCounter[6:0] <= 7'h0; |
else |
begin |
if(MdcEn) |
begin |
if(InProgress) |
begin |
if(NoPre & ( BitCounter == 7'h0 )) |
BitCounter[6:0] <= 7'h21; |
else |
BitCounter[6:0] <= BitCounter[6:0] + 1; |
end |
else |
BitCounter[6:0] <= 7'h0; |
end |
end |
end |
|
|
// Operation ends when the Bit Counter reaches 63 |
assign EndOp = BitCounter==63; |
|
assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20))); |
assign ByteSelect[1] = InProgress & (BitCounter == 7'h28); |
assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30); |
assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38); |
|
|
// Latch Byte selects which part of Read Status Data is updated from the shift register |
assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37; |
assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F; |
|
|
// Connecting the Clock Generator Module |
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc) |
); |
|
// Connecting the Shift Register Module |
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad), |
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte), |
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail) |
); |
|
// Connecting the Output Control Module |
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress), |
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre), |
.Mdo(Mdo), .MdoEn(MdoEn) |
); |
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/BUGS
0,0 → 1,55
////////////////////////////////////////////////////////////////////// |
//// //// |
//// BUGS //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is available in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001, 2002 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
|
|
FIXED BUGS: |
|
- Bug CarrierSenseLost when operating in Full duplex fixed. |
|
|
|
|
KNOWN BUGS: |
|
- |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/ethmac_defines.v
0,0 → 1,335
////////////////////////////////////////////////////////////////////// |
//// //// |
//// ethmac_defines.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is available in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001, 2002 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// Renamed from eth_defines.v to ethmac_defines.v to fit better into |
// OpenCores defined project structure 2011-08-04 olof@opencores.org |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.33 2003/11/12 18:24:58 tadejm |
// WISHBONE slave changed and tested from only 32-bit accesss to byte access. |
// |
// Revision 1.32 2003/10/17 07:46:13 markom |
// mbist signals updated according to newest convention |
// |
// Revision 1.31 2003/08/14 16:42:58 simons |
// Artisan ram instance added. |
// |
// Revision 1.30 2003/06/13 11:55:37 mohor |
// Define file in eth_cop.v is changed to eth_defines.v. Some defines were |
// moved from tb_eth_defines.v to eth_defines.v. |
// |
// Revision 1.29 2002/11/19 18:13:49 mohor |
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. |
// |
// Revision 1.28 2002/11/15 14:27:15 mohor |
// Since r_Rst bit is not used any more, default value is changed to 0xa000. |
// |
// Revision 1.27 2002/11/01 18:19:34 mohor |
// Defines fixed to use generic RAM by default. |
// |
// Revision 1.26 2002/10/24 18:53:03 mohor |
// fpga define added. |
// |
// Revision 1.3 2002/10/11 16:57:54 igorm |
// eth_defines.v tagged with rel_5 used. |
// |
// Revision 1.25 2002/10/10 16:47:44 mohor |
// Defines changed to have ETH_ prolog. |
// ETH_WISHBONE_B# define added. |
// |
// Revision 1.24 2002/10/10 16:33:11 mohor |
// Bist added. |
// |
// Revision 1.23 2002/09/23 18:22:48 mohor |
// Virtual Silicon RAM might be used in the ASIC implementation of the ethernet |
// core. |
// |
// Revision 1.22 2002/09/04 18:36:49 mohor |
// Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). |
// |
// Revision 1.21 2002/08/16 22:09:47 mohor |
// Defines for register width added. mii_rst signal in MIIMODER register |
// changed. |
// |
// Revision 1.20 2002/08/14 19:31:48 mohor |
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No |
// need to multiply or devide any more. |
// |
// Revision 1.19 2002/07/23 15:28:31 mohor |
// Ram , used for BDs changed from generic_spram to eth_spram_256x32. |
// |
// Revision 1.18 2002/05/03 10:15:50 mohor |
// Outputs registered. Reset changed for eth_wishbone module. |
// |
// Revision 1.17 2002/04/24 08:52:19 mohor |
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision" |
// bug fixed. |
// |
// Revision 1.16 2002/03/19 12:53:29 mohor |
// Some defines that are used in testbench only were moved to tb_eth_defines.v |
// file. |
// |
// Revision 1.15 2002/02/26 16:11:32 mohor |
// Number of interrupts changed |
// |
// Revision 1.14 2002/02/16 14:03:44 mohor |
// Registered trimmed. Unused registers removed. |
// |
// Revision 1.13 2002/02/16 13:06:33 mohor |
// EXTERNAL_DMA used instead of WISHBONE_DMA. |
// |
// Revision 1.12 2002/02/15 10:58:31 mohor |
// Changed that were lost with last update put back to the file. |
// |
// Revision 1.11 2002/02/14 20:19:41 billditt |
// Modified for Address Checking, |
// addition of eth_addrcheck.v |
// |
// Revision 1.10 2002/02/12 17:01:19 mohor |
// HASH0 and HASH1 registers added. |
|
// Revision 1.9 2002/02/08 16:21:54 mohor |
// Rx status is written back to the BD. |
// |
// Revision 1.8 2002/02/05 16:44:38 mohor |
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 |
// MHz. Statuses, overrun, control frame transmission and reception still need |
// to be fixed. |
// |
// Revision 1.7 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.6 2001/12/05 15:00:16 mohor |
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors |
// instead of the number of RX descriptors). |
// |
// Revision 1.5 2001/12/05 10:21:37 mohor |
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. |
// |
// Revision 1.4 2001/11/13 14:23:56 mohor |
// Generic memory model is used. Defines are changed for the same reason. |
// |
// Revision 1.3 2001/10/18 12:07:11 mohor |
// Status signals changed, Adress decoding changed, interrupt controller |
// added. |
// |
// Revision 1.2 2001/09/24 15:02:56 mohor |
// Defines changed (All precede with ETH_). Small changes because some |
// tools generate warnings when two operands are together. Synchronization |
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC |
// demands). |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// |
// |
// |
// |
|
|
|
//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS |
|
`define ETH_MBIST_CTRL_WIDTH 3 // width of MBIST control bus |
|
// Ethernet implemented in Xilinx Chips (uncomment following lines) |
// `define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo |
// `define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors |
// Core is going to be implemented in Virtex FPGA and contains Virtex |
// specific elements. |
|
// Ethernet implemented in Altera Chips (uncomment following lines) |
`define ETH_ALTERA_ALTSYNCRAM |
|
// Ethernet implemented in ASIC with Virtual Silicon RAMs |
// `define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation) |
|
// Ethernet implemented in ASIC with Artisan RAMs |
// `define ETH_ARTISAN_RAM // Artisan RAMS used storing buffer decriptors (ASIC implementation) |
|
// Uncomment when Avalon bus is used |
//`define ETH_AVALON_BUS |
|
`define ETH_MODER_ADR 8'h0 // 0x0 |
`define ETH_INT_SOURCE_ADR 8'h1 // 0x4 |
`define ETH_INT_MASK_ADR 8'h2 // 0x8 |
`define ETH_IPGT_ADR 8'h3 // 0xC |
`define ETH_IPGR1_ADR 8'h4 // 0x10 |
`define ETH_IPGR2_ADR 8'h5 // 0x14 |
`define ETH_PACKETLEN_ADR 8'h6 // 0x18 |
`define ETH_COLLCONF_ADR 8'h7 // 0x1C |
`define ETH_TX_BD_NUM_ADR 8'h8 // 0x20 |
`define ETH_CTRLMODER_ADR 8'h9 // 0x24 |
`define ETH_MIIMODER_ADR 8'hA // 0x28 |
`define ETH_MIICOMMAND_ADR 8'hB // 0x2C |
`define ETH_MIIADDRESS_ADR 8'hC // 0x30 |
`define ETH_MIITX_DATA_ADR 8'hD // 0x34 |
`define ETH_MIIRX_DATA_ADR 8'hE // 0x38 |
`define ETH_MIISTATUS_ADR 8'hF // 0x3C |
`define ETH_MAC_ADDR0_ADR 8'h10 // 0x40 |
`define ETH_MAC_ADDR1_ADR 8'h11 // 0x44 |
`define ETH_HASH0_ADR 8'h12 // 0x48 |
`define ETH_HASH1_ADR 8'h13 // 0x4C |
`define ETH_TX_CTRL_ADR 8'h14 // 0x50 |
`define ETH_RX_CTRL_ADR 8'h15 // 0x54 |
`define ETH_DBG_ADR 8'h16 // 0x58 |
|
`define ETH_MODER_DEF_0 8'h00 |
`define ETH_MODER_DEF_1 8'hA0 |
`define ETH_MODER_DEF_2 1'h0 |
`define ETH_INT_MASK_DEF_0 7'h0 |
`define ETH_IPGT_DEF_0 7'h12 |
`define ETH_IPGR1_DEF_0 7'h0C |
`define ETH_IPGR2_DEF_0 7'h12 |
`define ETH_PACKETLEN_DEF_0 8'h00 |
`define ETH_PACKETLEN_DEF_1 8'h06 |
`define ETH_PACKETLEN_DEF_2 8'h40 |
`define ETH_PACKETLEN_DEF_3 8'h00 |
`define ETH_COLLCONF_DEF_0 6'h3f |
`define ETH_COLLCONF_DEF_2 4'hF |
`define ETH_TX_BD_NUM_DEF_0 8'h40 |
`define ETH_CTRLMODER_DEF_0 3'h0 |
`define ETH_MIIMODER_DEF_0 8'h64 |
`define ETH_MIIMODER_DEF_1 1'h0 |
`define ETH_MIIADDRESS_DEF_0 5'h00 |
`define ETH_MIIADDRESS_DEF_1 5'h00 |
`define ETH_MIITX_DATA_DEF_0 8'h00 |
`define ETH_MIITX_DATA_DEF_1 8'h00 |
`define ETH_MIIRX_DATA_DEF 16'h0000 // not written from WB |
`define ETH_MAC_ADDR0_DEF_0 8'h00 |
`define ETH_MAC_ADDR0_DEF_1 8'h00 |
`define ETH_MAC_ADDR0_DEF_2 8'h00 |
`define ETH_MAC_ADDR0_DEF_3 8'h00 |
`define ETH_MAC_ADDR1_DEF_0 8'h00 |
`define ETH_MAC_ADDR1_DEF_1 8'h00 |
`define ETH_HASH0_DEF_0 8'h00 |
`define ETH_HASH0_DEF_1 8'h00 |
`define ETH_HASH0_DEF_2 8'h00 |
`define ETH_HASH0_DEF_3 8'h00 |
`define ETH_HASH1_DEF_0 8'h00 |
`define ETH_HASH1_DEF_1 8'h00 |
`define ETH_HASH1_DEF_2 8'h00 |
`define ETH_HASH1_DEF_3 8'h00 |
`define ETH_TX_CTRL_DEF_0 8'h00 // |
`define ETH_TX_CTRL_DEF_1 8'h00 // |
`define ETH_TX_CTRL_DEF_2 1'h0 // |
`define ETH_RX_CTRL_DEF_0 8'h00 |
`define ETH_RX_CTRL_DEF_1 8'h00 |
|
|
`define ETH_MODER_WIDTH_0 8 |
`define ETH_MODER_WIDTH_1 8 |
`define ETH_MODER_WIDTH_2 1 |
`define ETH_INT_SOURCE_WIDTH_0 7 |
`define ETH_INT_MASK_WIDTH_0 7 |
`define ETH_IPGT_WIDTH_0 7 |
`define ETH_IPGR1_WIDTH_0 7 |
`define ETH_IPGR2_WIDTH_0 7 |
`define ETH_PACKETLEN_WIDTH_0 8 |
`define ETH_PACKETLEN_WIDTH_1 8 |
`define ETH_PACKETLEN_WIDTH_2 8 |
`define ETH_PACKETLEN_WIDTH_3 8 |
`define ETH_COLLCONF_WIDTH_0 6 |
`define ETH_COLLCONF_WIDTH_2 4 |
`define ETH_TX_BD_NUM_WIDTH_0 8 |
`define ETH_CTRLMODER_WIDTH_0 3 |
`define ETH_MIIMODER_WIDTH_0 8 |
`define ETH_MIIMODER_WIDTH_1 1 |
`define ETH_MIICOMMAND_WIDTH_0 3 |
`define ETH_MIIADDRESS_WIDTH_0 5 |
`define ETH_MIIADDRESS_WIDTH_1 5 |
`define ETH_MIITX_DATA_WIDTH_0 8 |
`define ETH_MIITX_DATA_WIDTH_1 8 |
`define ETH_MIIRX_DATA_WIDTH 16 // not written from WB |
`define ETH_MIISTATUS_WIDTH 3 // not written from WB |
`define ETH_MAC_ADDR0_WIDTH_0 8 |
`define ETH_MAC_ADDR0_WIDTH_1 8 |
`define ETH_MAC_ADDR0_WIDTH_2 8 |
`define ETH_MAC_ADDR0_WIDTH_3 8 |
`define ETH_MAC_ADDR1_WIDTH_0 8 |
`define ETH_MAC_ADDR1_WIDTH_1 8 |
`define ETH_HASH0_WIDTH_0 8 |
`define ETH_HASH0_WIDTH_1 8 |
`define ETH_HASH0_WIDTH_2 8 |
`define ETH_HASH0_WIDTH_3 8 |
`define ETH_HASH1_WIDTH_0 8 |
`define ETH_HASH1_WIDTH_1 8 |
`define ETH_HASH1_WIDTH_2 8 |
`define ETH_HASH1_WIDTH_3 8 |
`define ETH_TX_CTRL_WIDTH_0 8 |
`define ETH_TX_CTRL_WIDTH_1 8 |
`define ETH_TX_CTRL_WIDTH_2 1 |
`define ETH_RX_CTRL_WIDTH_0 8 |
`define ETH_RX_CTRL_WIDTH_1 8 |
|
|
// Outputs are registered (uncomment when needed) |
`define ETH_REGISTERED_OUTPUTS |
|
// Settings for TX FIFO |
`define ETH_TX_FIFO_CNT_WIDTH 5 |
`define ETH_TX_FIFO_DEPTH 16 |
`define ETH_TX_FIFO_DATA_WIDTH 32 |
|
// Settings for RX FIFO |
`define ETH_RX_FIFO_CNT_WIDTH 5 |
`define ETH_RX_FIFO_DEPTH 16 |
`define ETH_RX_FIFO_DATA_WIDTH 32 |
|
// Burst length |
`define ETH_BURST_LENGTH 4 // Change also ETH_BURST_CNT_WIDTH |
`define ETH_BURST_CNT_WIDTH 3 // The counter must be width enough to count to ETH_BURST_LENGTH |
|
// WISHBONE interface is Revision B3 compliant (uncomment when needed) |
//`define ETH_WISHBONE_B3 |
|
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_maccontrol.v
0,0 → 1,269
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_maccontrol.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.6 2002/11/22 01:57:06 mohor |
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort |
// synchronized. |
// |
// Revision 1.5 2002/11/21 00:14:39 mohor |
// TxDone and TxAbort changed so they're not propagated to the wishbone |
// module when control frame is transmitted. |
// |
// Revision 1.4 2002/11/19 17:37:32 mohor |
// When control frame (PAUSE) was sent, status was written in the |
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed. |
// Only TXC interrupt is set. |
// |
// Revision 1.3 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.2 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// Revision 1.1 2001/07/03 12:51:54 mohor |
// Initial release of the MAC Control module. |
// |
// |
// |
// |
|
|
`include "timescale.v" |
|
|
module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxStartFrmIn, TxUsedDataIn, |
TxEndFrmIn, TxDoneIn, TxAbortIn, RxData, RxValid, RxStartFrm, RxEndFrm, ReceiveEnd, |
ReceivedPacketGood, ReceivedLengthOK, TxFlow, RxFlow, DlyCrcEn, TxPauseTV, |
MAC, PadIn, PadOut, CrcEnIn, CrcEnOut, TxDataOut, TxStartFrmOut, TxEndFrmOut, |
TxDoneOut, TxAbortOut, TxUsedDataOut, WillSendControlFrame, TxCtrlEndFrm, |
ReceivedPauseFrm, ControlFrmAddressOK, SetPauseTimer, r_PassAll, RxStatusWriteLatched_sync2 |
); |
|
|
|
input MTxClk; // Transmit clock (from PHY) |
input MRxClk; // Receive clock (from PHY) |
input TxReset; // Transmit reset |
input RxReset; // Receive reset |
input TPauseRq; // Transmit control frame (from host) |
input [7:0] TxDataIn; // Transmit packet data byte (from host) |
input TxStartFrmIn; // Transmit packet start frame input (from host) |
input TxUsedDataIn; // Transmit packet used data (from TxEthMAC) |
input TxEndFrmIn; // Transmit packet end frame input (from host) |
input TxDoneIn; // Transmit packet done (from TxEthMAC) |
input TxAbortIn; // Transmit packet abort (input from TxEthMAC) |
input PadIn; // Padding (input from registers) |
input CrcEnIn; // Crc append (input from registers) |
input [7:0] RxData; // Receive Packet Data (from RxEthMAC) |
input RxValid; // Received a valid packet |
input RxStartFrm; // Receive packet start frame (input from RxEthMAC) |
input RxEndFrm; // Receive packet end frame (input from RxEthMAC) |
input ReceiveEnd; // End of receiving of the current packet (input from RxEthMAC) |
input ReceivedPacketGood; // Received packet is good |
input ReceivedLengthOK; // Length of the received packet is OK |
input TxFlow; // Tx flow control (from registers) |
input RxFlow; // Rx flow control (from registers) |
input DlyCrcEn; // Delayed CRC enabled (from registers) |
input [15:0] TxPauseTV; // Transmit Pause Timer Value (from registers) |
input [47:0] MAC; // MAC address (from registers) |
input RxStatusWriteLatched_sync2; |
input r_PassAll; |
|
output [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC) |
output TxStartFrmOut; // Transmit packet start frame (output to TxEthMAC) |
output TxEndFrmOut; // Transmit packet end frame (output to TxEthMAC) |
output TxDoneOut; // Transmit packet done (to host) |
output TxAbortOut; // Transmit packet aborted (to host) |
output TxUsedDataOut; // Transmit packet used data (to host) |
output PadOut; // Padding (output to TxEthMAC) |
output CrcEnOut; // Crc append (output to TxEthMAC) |
output WillSendControlFrame; |
output TxCtrlEndFrm; |
output ReceivedPauseFrm; |
output ControlFrmAddressOK; |
output SetPauseTimer; |
|
reg TxUsedDataOutDetected; |
reg TxAbortInLatched; |
reg TxDoneInLatched; |
reg MuxedDone; |
reg MuxedAbort; |
|
wire Pause; |
wire TxCtrlStartFrm; |
wire [7:0] ControlData; |
wire CtrlMux; |
wire SendingCtrlFrm; // Sending Control Frame (enables padding and CRC) |
wire BlockTxDone; |
|
|
// Signal TxUsedDataOut was detected (a transfer is already in progress) |
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
TxUsedDataOutDetected <= 1'b0; |
else |
if(TxDoneIn | TxAbortIn) |
TxUsedDataOutDetected <= 1'b0; |
else |
if(TxUsedDataOut) |
TxUsedDataOutDetected <= 1'b1; |
end |
|
|
// Latching variables |
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
begin |
TxAbortInLatched <= 1'b0; |
TxDoneInLatched <= 1'b0; |
end |
else |
begin |
TxAbortInLatched <= TxAbortIn; |
TxDoneInLatched <= TxDoneIn; |
end |
end |
|
|
|
// Generating muxed abort signal |
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
MuxedAbort <= 1'b0; |
else |
if(TxStartFrmIn) |
MuxedAbort <= 1'b0; |
else |
if(TxAbortIn & ~TxAbortInLatched & TxUsedDataOutDetected) |
MuxedAbort <= 1'b1; |
end |
|
|
// Generating muxed done signal |
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
MuxedDone <= 1'b0; |
else |
if(TxStartFrmIn) |
MuxedDone <= 1'b0; |
else |
if(TxDoneIn & (~TxDoneInLatched) & TxUsedDataOutDetected) |
MuxedDone <= 1'b1; |
end |
|
|
// TxDoneOut |
assign TxDoneOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedDone) : |
((~TxStartFrmIn) & (~BlockTxDone) & TxDoneIn); |
|
// TxAbortOut |
assign TxAbortOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedAbort) : |
((~TxStartFrmIn) & (~BlockTxDone) & TxAbortIn); |
|
// TxUsedDataOut |
assign TxUsedDataOut = ~CtrlMux & TxUsedDataIn; |
|
// TxStartFrmOut |
assign TxStartFrmOut = CtrlMux? TxCtrlStartFrm : (TxStartFrmIn & ~Pause); |
|
|
// TxEndFrmOut |
assign TxEndFrmOut = CtrlMux? TxCtrlEndFrm : TxEndFrmIn; |
|
|
// TxDataOut[7:0] |
assign TxDataOut[7:0] = CtrlMux? ControlData[7:0] : TxDataIn[7:0]; |
|
|
// PadOut |
assign PadOut = PadIn | SendingCtrlFrm; |
|
|
// CrcEnOut |
assign CrcEnOut = CrcEnIn | SendingCtrlFrm; |
|
|
|
// Connecting receivecontrol module |
eth_receivecontrol receivecontrol1 |
( |
.MTxClk(MTxClk), .MRxClk(MRxClk), .TxReset(TxReset), .RxReset(RxReset), .RxData(RxData), |
.RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow), |
.ReceiveEnd(ReceiveEnd), .MAC(MAC), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn), |
.TxAbortIn(TxAbortIn), .TxStartFrmOut(TxStartFrmOut), .ReceivedLengthOK(ReceivedLengthOK), |
.ReceivedPacketGood(ReceivedPacketGood), .TxUsedDataOutDetected(TxUsedDataOutDetected), |
.Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm), .AddressOK(ControlFrmAddressOK), |
.r_PassAll(r_PassAll), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .SetPauseTimer(SetPauseTimer) |
); |
|
|
eth_transmitcontrol transmitcontrol1 |
( |
.MTxClk(MTxClk), .TxReset(TxReset), .TxUsedDataIn(TxUsedDataIn), .TxUsedDataOut(TxUsedDataOut), |
.TxDoneIn(TxDoneIn), .TxAbortIn(TxAbortIn), .TxStartFrmIn(TxStartFrmIn), .TPauseRq(TPauseRq), |
.TxUsedDataOutDetected(TxUsedDataOutDetected), .TxFlow(TxFlow), .DlyCrcEn(DlyCrcEn), .TxPauseTV(TxPauseTV), |
.MAC(MAC), .TxCtrlStartFrm(TxCtrlStartFrm), .TxCtrlEndFrm(TxCtrlEndFrm), .SendingCtrlFrm(SendingCtrlFrm), |
.CtrlMux(CtrlMux), .ControlData(ControlData), .WillSendControlFrame(WillSendControlFrame), .BlockTxDone(BlockTxDone) |
); |
|
|
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/ethmac.v
0,0 → 1,1182
////////////////////////////////////////////////////////////////////// |
//// //// |
//// ethmac.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is available in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001, 2002 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// 2011-08-09 olof@opencores.org |
// Renamed from eth_top.v to ethmac.v to better fit into the OpenCores |
// Structure |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.51 2005/02/21 11:13:17 igorm |
// Defer indication fixed. |
// |
// Revision 1.50 2004/04/26 15:26:23 igorm |
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the |
// previous update of the core. |
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register. |
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER |
// register. (thanks to Mathias and Torbjorn) |
// - Multicast reception was fixed. Thanks to Ulrich Gries |
// |
// Revision 1.49 2003/11/12 18:24:59 tadejm |
// WISHBONE slave changed and tested from only 32-bit accesss to byte access. |
// |
// Revision 1.48 2003/10/17 07:46:16 markom |
// mbist signals updated according to newest convention |
// |
// Revision 1.47 2003/10/06 15:43:45 knguyen |
// Update RxEnSync only when mrxdv_pad_i is inactive (LOW). |
// |
// Revision 1.46 2003/01/30 13:30:22 tadejm |
// Defer indication changed. |
// |
// Revision 1.45 2003/01/22 13:49:26 tadejm |
// When control packets were received, they were ignored in some cases. |
// |
// Revision 1.44 2003/01/21 12:09:40 mohor |
// When receiving normal data frame and RxFlow control was switched on, RXB |
// interrupt was not set. |
// |
// Revision 1.43 2002/11/22 01:57:06 mohor |
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort |
// synchronized. |
// |
// Revision 1.42 2002/11/21 00:09:19 mohor |
// TPauseRq synchronized to tx_clk. |
// |
// Revision 1.41 2002/11/19 18:13:49 mohor |
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. |
// |
// Revision 1.40 2002/11/19 17:34:25 mohor |
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying |
// that a frame was received because of the promiscous mode. |
// |
// Revision 1.39 2002/11/18 17:31:55 mohor |
// wb_rst_i is used for MIIM reset. |
// |
// Revision 1.38 2002/11/14 18:37:20 mohor |
// r_Rst signal does not reset any module any more and is removed from the design. |
// |
// Revision 1.37 2002/11/13 22:25:36 tadejm |
// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. |
// |
// Revision 1.36 2002/10/18 17:04:20 tadejm |
// Changed BIST scan signals. |
// |
// Revision 1.35 2002/10/11 13:36:58 mohor |
// Typo error fixed. (When using Bist) |
// |
// Revision 1.34 2002/10/10 16:49:50 mohor |
// Signals for WISHBONE B3 compliant interface added. |
// |
// Revision 1.33 2002/10/10 16:29:30 mohor |
// BIST added. |
// |
// Revision 1.32 2002/09/20 17:12:58 mohor |
// CsMiss added. When address between 0x800 and 0xfff is accessed within |
// Ethernet Core, error acknowledge is generated. |
// |
// Revision 1.31 2002/09/12 14:50:17 mohor |
// CarrierSenseLost bug fixed when operating in full duplex mode. |
// |
// Revision 1.30 2002/09/10 10:35:23 mohor |
// Ethernet debug registers removed. |
// |
// Revision 1.29 2002/09/09 13:03:13 mohor |
// Error acknowledge is generated when accessing BDs and RST bit in the |
// MODER register (r_Rst) is set. |
// |
// Revision 1.28 2002/09/04 18:44:10 mohor |
// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4 |
// connected. |
// |
// Revision 1.27 2002/07/25 18:15:37 mohor |
// RxAbort changed. Packets received with MRxErr (from PHY) are also |
// aborted. |
// |
// Revision 1.26 2002/07/17 18:51:50 mohor |
// EXTERNAL_DMA removed. External DMA not supported. |
// |
// Revision 1.25 2002/05/03 10:15:50 mohor |
// Outputs registered. Reset changed for eth_wishbone module. |
// |
// Revision 1.24 2002/04/22 14:15:42 mohor |
// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is |
// selected in eth_defines.v |
// |
// Revision 1.23 2002/03/25 13:33:53 mohor |
// md_padoen_o changed to md_padoe_o. Signal was always active high, just |
// name was incorrect. |
// |
// Revision 1.22 2002/02/26 16:59:54 mohor |
// Small fixes for external/internal DMA missmatches. |
// |
// Revision 1.21 2002/02/26 16:21:00 mohor |
// Interrupts changed in the top file |
// |
// Revision 1.20 2002/02/18 10:40:17 mohor |
// Small fixes. |
// |
// Revision 1.19 2002/02/16 14:03:44 mohor |
// Registered trimmed. Unused registers removed. |
// |
// Revision 1.18 2002/02/16 13:06:33 mohor |
// EXTERNAL_DMA used instead of WISHBONE_DMA. |
// |
// Revision 1.17 2002/02/16 07:15:27 mohor |
// Testbench fixed, code simplified, unused signals removed. |
// |
// Revision 1.16 2002/02/15 13:49:39 mohor |
// RxAbort is connected differently. |
// |
// Revision 1.15 2002/02/15 11:38:26 mohor |
// Changes that were lost when updating from 1.11 to 1.14 fixed. |
// |
// Revision 1.14 2002/02/14 20:19:11 billditt |
// Modified for Address Checking, |
// addition of eth_addrcheck.v |
// |
// Revision 1.13 2002/02/12 17:03:03 mohor |
// HASH0 and HASH1 registers added. Registers address width was |
// changed to 8 bits. |
// |
// Revision 1.12 2002/02/11 09:18:22 mohor |
// Tx status is written back to the BD. |
// |
// Revision 1.11 2002/02/08 16:21:54 mohor |
// Rx status is written back to the BD. |
// |
// Revision 1.10 2002/02/06 14:10:21 mohor |
// non-DMA host interface added. Select the right configutation in eth_defines. |
// |
// Revision 1.9 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.8 2001/12/05 15:00:16 mohor |
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors |
// instead of the number of RX descriptors). |
// |
// Revision 1.7 2001/12/05 10:45:59 mohor |
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. |
// |
// Revision 1.6 2001/10/19 11:24:29 mohor |
// Number of addresses (wb_adr_i) minimized. |
// |
// Revision 1.5 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
// |
// Revision 1.4 2001/10/18 12:07:11 mohor |
// Status signals changed, Adress decoding changed, interrupt controller |
// added. |
// |
// Revision 1.3 2001/09/24 15:02:56 mohor |
// Defines changed (All precede with ETH_). Small changes because some |
// tools generate warnings when two operands are together. Synchronization |
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC |
// demands). |
// |
// Revision 1.2 2001/08/15 14:03:59 mohor |
// Signal names changed on the top level for easier pad insertion (ASIC). |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.2 2001/08/02 09:25:31 mohor |
// Unconnected signals are now connected. |
// |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// |
// |
// |
|
|
`include "ethmac_defines.v" |
`include "timescale.v" |
|
|
module ethmac |
( |
// WISHBONE common |
wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o, |
|
// WISHBONE slave |
wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o, |
|
// WISHBONE master |
m_wb_adr_o, m_wb_sel_o, m_wb_we_o, |
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o, |
m_wb_stb_o, m_wb_ack_i, m_wb_err_i, |
|
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o, m_wb_bte_o, |
`endif |
|
//TX |
mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o, |
|
//RX |
mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i, |
|
// MIIM |
mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o, |
|
int_o |
|
// Bist |
`ifdef ETH_BIST |
, |
// debug chain signals |
mbist_si_i, // bist scan serial in |
mbist_so_o, // bist scan serial out |
mbist_ctrl_i // bist chain shift control |
`endif |
|
); |
|
|
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH; |
parameter TX_FIFO_DEPTH = `ETH_TX_FIFO_DEPTH; |
parameter TX_FIFO_CNT_WIDTH = `ETH_TX_FIFO_CNT_WIDTH; |
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH; |
parameter RX_FIFO_DEPTH = `ETH_RX_FIFO_DEPTH; |
parameter RX_FIFO_CNT_WIDTH = `ETH_RX_FIFO_CNT_WIDTH; |
|
|
// WISHBONE common |
input wb_clk_i; // WISHBONE clock |
input wb_rst_i; // WISHBONE reset |
input [31:0] wb_dat_i; // WISHBONE data input |
output [31:0] wb_dat_o; // WISHBONE data output |
output wb_err_o; // WISHBONE error output |
|
// WISHBONE slave |
input [11:2] wb_adr_i; // WISHBONE address input |
input [3:0] wb_sel_i; // WISHBONE byte select input |
input wb_we_i; // WISHBONE write enable input |
input wb_cyc_i; // WISHBONE cycle input |
input wb_stb_i; // WISHBONE strobe input |
output wb_ack_o; // WISHBONE acknowledge output |
|
// WISHBONE master |
output [31:0] m_wb_adr_o; |
output [3:0] m_wb_sel_o; |
output m_wb_we_o; |
input [31:0] m_wb_dat_i; |
output [31:0] m_wb_dat_o; |
output m_wb_cyc_o; |
output m_wb_stb_o; |
input m_wb_ack_i; |
input m_wb_err_i; |
|
wire [29:0] m_wb_adr_tmp; |
|
`ifdef ETH_WISHBONE_B3 |
output [2:0] m_wb_cti_o; // Cycle Type Identifier |
output [1:0] m_wb_bte_o; // Burst Type Extension |
`endif |
|
// Tx |
input mtx_clk_pad_i; // Transmit clock (from PHY) |
output [3:0] mtxd_pad_o; // Transmit nibble (to PHY) |
output mtxen_pad_o; // Transmit enable (to PHY) |
output mtxerr_pad_o; // Transmit error (to PHY) |
|
// Rx |
input mrx_clk_pad_i; // Receive clock (from PHY) |
input [3:0] mrxd_pad_i; // Receive nibble (from PHY) |
input mrxdv_pad_i; // Receive data valid (from PHY) |
input mrxerr_pad_i; // Receive data error (from PHY) |
|
// Common Tx and Rx |
input mcoll_pad_i; // Collision (from PHY) |
input mcrs_pad_i; // Carrier sense (from PHY) |
|
// MII Management interface |
input md_pad_i; // MII data input (from I/O cell) |
output mdc_pad_o; // MII Management data clock (to PHY) |
output md_pad_o; // MII data output (to I/O cell) |
output md_padoe_o; // MII data output enable (to I/O cell) |
|
output int_o; // Interrupt output |
|
// Bist |
`ifdef ETH_BIST |
input mbist_si_i; // bist scan serial in |
output mbist_so_o; // bist scan serial out |
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control |
`endif |
|
wire [31:0] wb_dbg_dat0; |
|
wire [7:0] r_ClkDiv; |
wire r_MiiNoPre; |
wire [15:0] r_CtrlData; |
wire [4:0] r_FIAD; |
wire [4:0] r_RGAD; |
wire r_WCtrlData; |
wire r_RStat; |
wire r_ScanStat; |
wire NValid_stat; |
wire Busy_stat; |
wire LinkFail; |
wire [15:0] Prsd; // Read Status Data (data read from the PHY) |
wire WCtrlDataStart; |
wire RStatStart; |
wire UpdateMIIRX_DATAReg; |
|
wire TxStartFrm; |
wire TxEndFrm; |
wire TxUsedData; |
wire [7:0] TxData; |
wire TxRetry; |
wire TxAbort; |
wire TxUnderRun; |
wire TxDone; |
|
|
reg WillSendControlFrame_sync1; |
reg WillSendControlFrame_sync2; |
reg WillSendControlFrame_sync3; |
reg RstTxPauseRq; |
|
reg TxPauseRq_sync1; |
reg TxPauseRq_sync2; |
reg TxPauseRq_sync3; |
reg TPauseRq; |
|
|
// Connecting Miim module |
eth_miim miim1 |
( |
.Clk(wb_clk_i), |
.Reset(wb_rst_i), |
.Divider(r_ClkDiv), |
.NoPre(r_MiiNoPre), |
.CtrlData(r_CtrlData), |
.Rgad(r_RGAD), |
.Fiad(r_FIAD), |
.WCtrlData(r_WCtrlData), |
.RStat(r_RStat), |
.ScanStat(r_ScanStat), |
.Mdi(md_pad_i), |
.Mdo(md_pad_o), |
.MdoEn(md_padoe_o), |
.Mdc(mdc_pad_o), |
.Busy(Busy_stat), |
.Prsd(Prsd), |
.LinkFail(LinkFail), |
.Nvalid(NValid_stat), |
.WCtrlDataStart(WCtrlDataStart), |
.RStatStart(RStatStart), |
.UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg) |
); |
|
|
|
|
wire [3:0] RegCs; // Connected to registers |
wire [31:0] RegDataOut; // Multiplexed to wb_dat_o |
wire r_RecSmall; // Receive small frames |
wire r_LoopBck; // Loopback |
wire r_TxEn; // Tx Enable |
wire r_RxEn; // Rx Enable |
|
wire MRxDV_Lb; // Muxed MII receive data valid |
wire MRxErr_Lb; // Muxed MII Receive Error |
wire [3:0] MRxD_Lb; // Muxed MII Receive Data |
wire Transmitting; // Indication that TxEthMAC is transmitting |
wire r_HugEn; // Huge packet enable |
wire r_DlyCrcEn; // Delayed CRC enabled |
wire [15:0] r_MaxFL; // Maximum frame length |
|
wire [15:0] r_MinFL; // Minimum frame length |
wire ShortFrame; |
wire DribbleNibble; // Extra nibble received |
wire ReceivedPacketTooBig; // Received packet is too big |
wire [47:0] r_MAC; // MAC address |
wire LoadRxStatus; // Rx status was loaded |
wire [31:0] r_HASH0; // HASH table, lower 4 bytes |
wire [31:0] r_HASH1; // HASH table, upper 4 bytes |
wire [7:0] r_TxBDNum; // Receive buffer descriptor number |
wire [6:0] r_IPGT; // |
wire [6:0] r_IPGR1; // |
wire [6:0] r_IPGR2; // |
wire [5:0] r_CollValid; // |
wire [15:0] r_TxPauseTV; // Transmit PAUSE value |
wire r_TxPauseRq; // Transmit PAUSE request |
|
wire [3:0] r_MaxRet; // |
wire r_NoBckof; // |
wire r_ExDfrEn; // |
wire r_TxFlow; // Tx flow control enable |
wire r_IFG; // Minimum interframe gap for incoming packets |
|
wire TxB_IRQ; // Interrupt Tx Buffer |
wire TxE_IRQ; // Interrupt Tx Error |
wire RxB_IRQ; // Interrupt Rx Buffer |
wire RxE_IRQ; // Interrupt Rx Error |
wire Busy_IRQ; // Interrupt Busy (lack of buffers) |
|
//wire DWord; |
wire ByteSelected; |
wire BDAck; |
wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module |
//(for buffer descriptors read/write) |
wire [3:0] BDCs; // Buffer descriptor CS |
wire CsMiss; // When access to the address between 0x800 |
// and 0xfff occurs, acknowledge is set |
// but data is not valid. |
wire r_Pad; |
wire r_CrcEn; |
wire r_FullD; |
wire r_Pro; |
wire r_Bro; |
wire r_NoPre; |
wire r_RxFlow; |
wire r_PassAll; |
wire TxCtrlEndFrm; |
wire StartTxDone; |
wire SetPauseTimer; |
wire TxUsedDataIn; |
wire TxDoneIn; |
wire TxAbortIn; |
wire PerPacketPad; |
wire PadOut; |
wire PerPacketCrcEn; |
wire CrcEnOut; |
wire TxStartFrmOut; |
wire TxEndFrmOut; |
wire ReceivedPauseFrm; |
wire ControlFrmAddressOK; |
wire RxStatusWriteLatched_sync2; |
wire LateCollision; |
wire DeferIndication; |
wire LateCollLatched; |
wire DeferLatched; |
wire RstDeferLatched; |
wire CarrierSenseLost; |
|
wire temp_wb_ack_o; |
wire [31:0] temp_wb_dat_o; |
wire temp_wb_err_o; |
|
`ifdef ETH_REGISTERED_OUTPUTS |
reg temp_wb_ack_o_reg; |
reg [31:0] temp_wb_dat_o_reg; |
reg temp_wb_err_o_reg; |
`endif |
|
//assign DWord = &wb_sel_i; |
assign ByteSelected = |wb_sel_i; |
assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3]; // 0x0 - 0x3FF |
assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2]; // 0x0 - 0x3FF |
assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1]; // 0x0 - 0x3FF |
assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0]; // 0x0 - 0x3FF |
assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF |
assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF |
assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF |
assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF |
assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF |
assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O; |
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss); |
|
`ifdef ETH_REGISTERED_OUTPUTS |
assign wb_ack_o = temp_wb_ack_o_reg; |
assign wb_dat_o[31:0] = temp_wb_dat_o_reg; |
assign wb_err_o = temp_wb_err_o_reg; |
`else |
assign wb_ack_o = temp_wb_ack_o; |
assign wb_dat_o[31:0] = temp_wb_dat_o; |
assign wb_err_o = temp_wb_err_o; |
`endif |
|
`ifdef ETH_AVALON_BUS |
// As Avalon has no corresponding "error" signal, I (erroneously) will |
// send an ack to Avalon, even when accessing undefined memory. This |
// is a grey area in Avalon vs. Wishbone specs: My understanding |
// is that Avalon expects all memory addressable by the addr bus feeding |
// a slave to be, at the very minimum, readable. |
assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss; |
`else // WISHBONE |
assign temp_wb_ack_o = (|RegCs) | BDAck; |
`endif |
|
`ifdef ETH_REGISTERED_OUTPUTS |
always @ (posedge wb_clk_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
begin |
temp_wb_ack_o_reg <= 1'b0; |
temp_wb_dat_o_reg <= 32'h0; |
temp_wb_err_o_reg <= 1'b0; |
end |
else |
begin |
temp_wb_ack_o_reg <= temp_wb_ack_o & ~temp_wb_ack_o_reg; |
temp_wb_dat_o_reg <= temp_wb_dat_o; |
temp_wb_err_o_reg <= temp_wb_err_o & ~temp_wb_err_o_reg; |
end |
end |
`endif |
|
|
// Connecting Ethernet registers |
eth_registers ethreg1 |
( |
.DataIn(wb_dat_i), |
.Address(wb_adr_i[9:2]), |
.Rw(wb_we_i), |
.Cs(RegCs), |
.Clk(wb_clk_i), |
.Reset(wb_rst_i), |
.DataOut(RegDataOut), |
.r_RecSmall(r_RecSmall), |
.r_Pad(r_Pad), |
.r_HugEn(r_HugEn), |
.r_CrcEn(r_CrcEn), |
.r_DlyCrcEn(r_DlyCrcEn), |
.r_FullD(r_FullD), |
.r_ExDfrEn(r_ExDfrEn), |
.r_NoBckof(r_NoBckof), |
.r_LoopBck(r_LoopBck), |
.r_IFG(r_IFG), |
.r_Pro(r_Pro), |
.r_Iam(), |
.r_Bro(r_Bro), |
.r_NoPre(r_NoPre), |
.r_TxEn(r_TxEn), |
.r_RxEn(r_RxEn), |
.Busy_IRQ(Busy_IRQ), |
.RxE_IRQ(RxE_IRQ), |
.RxB_IRQ(RxB_IRQ), |
.TxE_IRQ(TxE_IRQ), |
.TxB_IRQ(TxB_IRQ), |
.r_IPGT(r_IPGT), |
.r_IPGR1(r_IPGR1), |
.r_IPGR2(r_IPGR2), |
.r_MinFL(r_MinFL), |
.r_MaxFL(r_MaxFL), |
.r_MaxRet(r_MaxRet), |
.r_CollValid(r_CollValid), |
.r_TxFlow(r_TxFlow), |
.r_RxFlow(r_RxFlow), |
.r_PassAll(r_PassAll), |
.r_MiiNoPre(r_MiiNoPre), |
.r_ClkDiv(r_ClkDiv), |
.r_WCtrlData(r_WCtrlData), |
.r_RStat(r_RStat), |
.r_ScanStat(r_ScanStat), |
.r_RGAD(r_RGAD), |
.r_FIAD(r_FIAD), |
.r_CtrlData(r_CtrlData), |
.NValid_stat(NValid_stat), |
.Busy_stat(Busy_stat), |
.LinkFail(LinkFail), |
.r_MAC(r_MAC), |
.WCtrlDataStart(WCtrlDataStart), |
.RStatStart(RStatStart), |
.UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), |
.Prsd(Prsd), |
.r_TxBDNum(r_TxBDNum), |
.int_o(int_o), |
.r_HASH0(r_HASH0), |
.r_HASH1(r_HASH1), |
.r_TxPauseRq(r_TxPauseRq), |
.r_TxPauseTV(r_TxPauseTV), |
.RstTxPauseRq(RstTxPauseRq), |
.TxCtrlEndFrm(TxCtrlEndFrm), |
.StartTxDone(StartTxDone), |
.TxClk(mtx_clk_pad_i), |
.RxClk(mrx_clk_pad_i), |
.dbg_dat(wb_dbg_dat0), |
.SetPauseTimer(SetPauseTimer) |
|
); |
|
|
|
wire [7:0] RxData; |
wire RxValid; |
wire RxStartFrm; |
wire RxEndFrm; |
wire RxAbort; |
|
wire WillTransmit; // Will transmit (to RxEthMAC) |
wire ResetCollision; // Reset Collision (for synchronizing |
// collision) |
wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC) |
wire WillSendControlFrame; |
wire ReceiveEnd; |
wire ReceivedPacketGood; |
wire ReceivedLengthOK; |
wire InvalidSymbol; |
wire LatchedCrcError; |
wire RxLateCollision; |
wire [3:0] RetryCntLatched; |
wire [3:0] RetryCnt; |
wire StartTxAbort; |
wire MaxCollisionOccured; |
wire RetryLimit; |
wire StatePreamble; |
wire [1:0] StateData; |
|
// Connecting MACControl |
eth_maccontrol maccontrol1 |
( |
.MTxClk(mtx_clk_pad_i), |
.TPauseRq(TPauseRq), |
.TxPauseTV(r_TxPauseTV), |
.TxDataIn(TxData), |
.TxStartFrmIn(TxStartFrm), |
.TxEndFrmIn(TxEndFrm), |
.TxUsedDataIn(TxUsedDataIn), |
.TxDoneIn(TxDoneIn), |
.TxAbortIn(TxAbortIn), |
.MRxClk(mrx_clk_pad_i), |
.RxData(RxData), |
.RxValid(RxValid), |
.RxStartFrm(RxStartFrm), |
.RxEndFrm(RxEndFrm), |
.ReceiveEnd(ReceiveEnd), |
.ReceivedPacketGood(ReceivedPacketGood), |
.TxFlow(r_TxFlow), |
.RxFlow(r_RxFlow), |
.DlyCrcEn(r_DlyCrcEn), |
.MAC(r_MAC), |
.PadIn(r_Pad | PerPacketPad), |
.PadOut(PadOut), |
.CrcEnIn(r_CrcEn | PerPacketCrcEn), |
.CrcEnOut(CrcEnOut), |
.TxReset(wb_rst_i), |
.RxReset(wb_rst_i), |
.ReceivedLengthOK(ReceivedLengthOK), |
.TxDataOut(TxDataOut), |
.TxStartFrmOut(TxStartFrmOut), |
.TxEndFrmOut(TxEndFrmOut), |
.TxUsedDataOut(TxUsedData), |
.TxDoneOut(TxDone), |
.TxAbortOut(TxAbort), |
.WillSendControlFrame(WillSendControlFrame), |
.TxCtrlEndFrm(TxCtrlEndFrm), |
.ReceivedPauseFrm(ReceivedPauseFrm), |
.ControlFrmAddressOK(ControlFrmAddressOK), |
.SetPauseTimer(SetPauseTimer), |
.RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), |
.r_PassAll(r_PassAll) |
); |
|
|
|
wire TxCarrierSense; // Synchronized CarrierSense (to Tx clock) |
wire Collision; // Synchronized Collision |
|
reg CarrierSense_Tx1; |
reg CarrierSense_Tx2; |
reg Collision_Tx1; |
reg Collision_Tx2; |
|
reg RxEnSync; // Synchronized Receive Enable |
reg WillTransmit_q; |
reg WillTransmit_q2; |
|
|
|
// Muxed MII receive data valid |
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync; |
|
// Muxed MII Receive Error |
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync; |
|
// Muxed MII Receive Data |
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0]; |
|
|
|
// Connecting TxEthMAC |
eth_txethmac txethmac1 |
( |
.MTxClk(mtx_clk_pad_i), |
.Reset(wb_rst_i), |
.CarrierSense(TxCarrierSense), |
.Collision(Collision), |
.TxData(TxDataOut), |
.TxStartFrm(TxStartFrmOut), |
.TxUnderRun(TxUnderRun), |
.TxEndFrm(TxEndFrmOut), |
.Pad(PadOut), |
.MinFL(r_MinFL), |
.CrcEn(CrcEnOut), |
.FullD(r_FullD), |
.HugEn(r_HugEn), |
.DlyCrcEn(r_DlyCrcEn), |
.IPGT(r_IPGT), |
.IPGR1(r_IPGR1), |
.IPGR2(r_IPGR2), |
.CollValid(r_CollValid), |
.MaxRet(r_MaxRet), |
.NoBckof(r_NoBckof), |
.ExDfrEn(r_ExDfrEn), |
.MaxFL(r_MaxFL), |
.MTxEn(mtxen_pad_o), |
.MTxD(mtxd_pad_o), |
.MTxErr(mtxerr_pad_o), |
.TxUsedData(TxUsedDataIn), |
.TxDone(TxDoneIn), |
.TxRetry(TxRetry), |
.TxAbort(TxAbortIn), |
.WillTransmit(WillTransmit), |
.ResetCollision(ResetCollision), |
.RetryCnt(RetryCnt), |
.StartTxDone(StartTxDone), |
.StartTxAbort(StartTxAbort), |
.MaxCollisionOccured(MaxCollisionOccured), |
.LateCollision(LateCollision), |
.DeferIndication(DeferIndication), |
.StatePreamble(StatePreamble), |
.StateData(StateData) |
); |
|
|
|
|
wire [15:0] RxByteCnt; |
wire RxByteCntEq0; |
wire RxByteCntGreat2; |
wire RxByteCntMaxFrame; |
wire RxCrcError; |
wire RxStateIdle; |
wire RxStatePreamble; |
wire RxStateSFD; |
wire [1:0] RxStateData; |
wire AddressMiss; |
|
|
|
// Connecting RxEthMAC |
eth_rxethmac rxethmac1 |
( |
.MRxClk(mrx_clk_pad_i), |
.MRxDV(MRxDV_Lb), |
.MRxD(MRxD_Lb), |
.Transmitting(Transmitting), |
.HugEn(r_HugEn), |
.DlyCrcEn(r_DlyCrcEn), |
.MaxFL(r_MaxFL), |
.r_IFG(r_IFG), |
.Reset(wb_rst_i), |
.RxData(RxData), |
.RxValid(RxValid), |
.RxStartFrm(RxStartFrm), |
.RxEndFrm(RxEndFrm), |
.ByteCnt(RxByteCnt), |
.ByteCntEq0(RxByteCntEq0), |
.ByteCntGreat2(RxByteCntGreat2), |
.ByteCntMaxFrame(RxByteCntMaxFrame), |
.CrcError(RxCrcError), |
.StateIdle(RxStateIdle), |
.StatePreamble(RxStatePreamble), |
.StateSFD(RxStateSFD), |
.StateData(RxStateData), |
.MAC(r_MAC), |
.r_Pro(r_Pro), |
.r_Bro(r_Bro), |
.r_HASH0(r_HASH0), |
.r_HASH1(r_HASH1), |
.RxAbort(RxAbort), |
.AddressMiss(AddressMiss), |
.PassAll(r_PassAll), |
.ControlFrmAddressOK(ControlFrmAddressOK) |
); |
|
|
// MII Carrier Sense Synchronization |
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
begin |
CarrierSense_Tx1 <= 1'b0; |
CarrierSense_Tx2 <= 1'b0; |
end |
else |
begin |
CarrierSense_Tx1 <= mcrs_pad_i; |
CarrierSense_Tx2 <= CarrierSense_Tx1; |
end |
end |
|
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2; |
|
|
// MII Collision Synchronization |
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
begin |
Collision_Tx1 <= 1'b0; |
Collision_Tx2 <= 1'b0; |
end |
else |
begin |
Collision_Tx1 <= mcoll_pad_i; |
if(ResetCollision) |
Collision_Tx2 <= 1'b0; |
else |
if(Collision_Tx1) |
Collision_Tx2 <= 1'b1; |
end |
end |
|
|
// Synchronized Collision |
assign Collision = ~r_FullD & Collision_Tx2; |
|
|
|
// Delayed WillTransmit |
always @ (posedge mrx_clk_pad_i) |
begin |
WillTransmit_q <= WillTransmit; |
WillTransmit_q2 <= WillTransmit_q; |
end |
|
|
assign Transmitting = ~r_FullD & WillTransmit_q2; |
|
|
|
// Synchronized Receive Enable |
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
RxEnSync <= 1'b0; |
else |
if(~mrxdv_pad_i) |
RxEnSync <= r_RxEn; |
end |
|
|
|
// Synchronizing WillSendControlFrame to WB_CLK; |
always @ (posedge wb_clk_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
WillSendControlFrame_sync1 <= 1'b0; |
else |
WillSendControlFrame_sync1 <= WillSendControlFrame; |
end |
|
always @ (posedge wb_clk_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
WillSendControlFrame_sync2 <= 1'b0; |
else |
WillSendControlFrame_sync2 <= WillSendControlFrame_sync1; |
end |
|
always @ (posedge wb_clk_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
WillSendControlFrame_sync3 <= 1'b0; |
else |
WillSendControlFrame_sync3 <= WillSendControlFrame_sync2; |
end |
|
always @ (posedge wb_clk_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
RstTxPauseRq <= 1'b0; |
else |
RstTxPauseRq <= WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3; |
end |
|
|
|
|
// TX Pause request Synchronization |
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
begin |
TxPauseRq_sync1 <= 1'b0; |
TxPauseRq_sync2 <= 1'b0; |
TxPauseRq_sync3 <= 1'b0; |
end |
else |
begin |
TxPauseRq_sync1 <= (r_TxPauseRq & r_TxFlow); |
TxPauseRq_sync2 <= TxPauseRq_sync1; |
TxPauseRq_sync3 <= TxPauseRq_sync2; |
end |
end |
|
|
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
TPauseRq <= 1'b0; |
else |
TPauseRq <= TxPauseRq_sync2 & (~TxPauseRq_sync3); |
end |
|
|
wire LatchedMRxErr; |
reg RxAbort_latch; |
reg RxAbort_sync1; |
reg RxAbort_wb; |
reg RxAbortRst_sync1; |
reg RxAbortRst; |
|
// Synchronizing RxAbort to the WISHBONE clock |
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
RxAbort_latch <= 1'b0; |
else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & |
~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll))) |
RxAbort_latch <= 1'b1; |
else if(RxAbortRst) |
RxAbort_latch <= 1'b0; |
end |
|
always @ (posedge wb_clk_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
begin |
RxAbort_sync1 <= 1'b0; |
RxAbort_wb <= 1'b0; |
RxAbort_wb <= 1'b0; |
end |
else |
begin |
RxAbort_sync1 <= RxAbort_latch; |
RxAbort_wb <= RxAbort_sync1; |
end |
end |
|
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
begin |
RxAbortRst_sync1 <= 1'b0; |
RxAbortRst <= 1'b0; |
end |
else |
begin |
RxAbortRst_sync1 <= RxAbort_wb; |
RxAbortRst <= RxAbortRst_sync1; |
end |
end |
|
|
|
// Connecting Wishbone module |
eth_wishbone #(.TX_FIFO_DATA_WIDTH(TX_FIFO_DATA_WIDTH), |
.TX_FIFO_DEPTH (TX_FIFO_DEPTH), |
.TX_FIFO_CNT_WIDTH (TX_FIFO_CNT_WIDTH), |
.RX_FIFO_DATA_WIDTH(RX_FIFO_DATA_WIDTH), |
.RX_FIFO_DEPTH (RX_FIFO_DEPTH), |
.RX_FIFO_CNT_WIDTH (RX_FIFO_CNT_WIDTH)) |
wishbone |
( |
.WB_CLK_I(wb_clk_i), |
.WB_DAT_I(wb_dat_i), |
.WB_DAT_O(BD_WB_DAT_O), |
|
// WISHBONE slave |
.WB_ADR_I(wb_adr_i[9:2]), |
.WB_WE_I(wb_we_i), |
.BDCs(BDCs), |
.WB_ACK_O(BDAck), |
.Reset(wb_rst_i), |
|
// WISHBONE master |
.m_wb_adr_o(m_wb_adr_tmp), |
.m_wb_sel_o(m_wb_sel_o), |
.m_wb_we_o(m_wb_we_o), |
.m_wb_dat_i(m_wb_dat_i), |
.m_wb_dat_o(m_wb_dat_o), |
.m_wb_cyc_o(m_wb_cyc_o), |
.m_wb_stb_o(m_wb_stb_o), |
.m_wb_ack_i(m_wb_ack_i), |
.m_wb_err_i(m_wb_err_i), |
|
`ifdef ETH_WISHBONE_B3 |
.m_wb_cti_o(m_wb_cti_o), |
.m_wb_bte_o(m_wb_bte_o), |
`endif |
|
//TX |
.MTxClk(mtx_clk_pad_i), |
.TxStartFrm(TxStartFrm), |
.TxEndFrm(TxEndFrm), |
.TxUsedData(TxUsedData), |
.TxData(TxData), |
.TxRetry(TxRetry), |
.TxAbort(TxAbort), |
.TxUnderRun(TxUnderRun), |
.TxDone(TxDone), |
.PerPacketCrcEn(PerPacketCrcEn), |
.PerPacketPad(PerPacketPad), |
|
// Register |
.r_TxEn(r_TxEn), |
.r_RxEn(r_RxEn), |
.r_TxBDNum(r_TxBDNum), |
.r_RxFlow(r_RxFlow), |
.r_PassAll(r_PassAll), |
|
//RX |
.MRxClk(mrx_clk_pad_i), |
.RxData(RxData), |
.RxValid(RxValid), |
.RxStartFrm(RxStartFrm), |
.RxEndFrm(RxEndFrm), |
.Busy_IRQ(Busy_IRQ), |
.RxE_IRQ(RxE_IRQ), |
.RxB_IRQ(RxB_IRQ), |
.TxE_IRQ(TxE_IRQ), |
.TxB_IRQ(TxB_IRQ), |
|
.RxAbort(RxAbort_wb), |
.RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), |
|
.InvalidSymbol(InvalidSymbol), |
.LatchedCrcError(LatchedCrcError), |
.RxLength(RxByteCnt), |
.RxLateCollision(RxLateCollision), |
.ShortFrame(ShortFrame), |
.DribbleNibble(DribbleNibble), |
.ReceivedPacketTooBig(ReceivedPacketTooBig), |
.LoadRxStatus(LoadRxStatus), |
.RetryCntLatched(RetryCntLatched), |
.RetryLimit(RetryLimit), |
.LateCollLatched(LateCollLatched), |
.DeferLatched(DeferLatched), |
.RstDeferLatched(RstDeferLatched), |
.CarrierSenseLost(CarrierSenseLost), |
.ReceivedPacketGood(ReceivedPacketGood), |
.AddressMiss(AddressMiss), |
.ReceivedPauseFrm(ReceivedPauseFrm) |
|
`ifdef ETH_BIST |
, |
.mbist_si_i (mbist_si_i), |
.mbist_so_o (mbist_so_o), |
.mbist_ctrl_i (mbist_ctrl_i) |
`endif |
`ifdef WISHBONE_DEBUG |
, |
.dbg_dat0(wb_dbg_dat0) |
`endif |
|
); |
|
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0}; |
|
// Connecting MacStatus module |
eth_macstatus macstatus1 |
( |
.MRxClk(mrx_clk_pad_i), |
.Reset(wb_rst_i), |
.ReceiveEnd(ReceiveEnd), |
.ReceivedPacketGood(ReceivedPacketGood), |
.ReceivedLengthOK(ReceivedLengthOK), |
.RxCrcError(RxCrcError), |
.MRxErr(MRxErr_Lb), |
.MRxDV(MRxDV_Lb), |
.RxStateSFD(RxStateSFD), |
.RxStateData(RxStateData), |
.RxStatePreamble(RxStatePreamble), |
.RxStateIdle(RxStateIdle), |
.Transmitting(Transmitting), |
.RxByteCnt(RxByteCnt), |
.RxByteCntEq0(RxByteCntEq0), |
.RxByteCntGreat2(RxByteCntGreat2), |
.RxByteCntMaxFrame(RxByteCntMaxFrame), |
.InvalidSymbol(InvalidSymbol), |
.MRxD(MRxD_Lb), |
.LatchedCrcError(LatchedCrcError), |
.Collision(mcoll_pad_i), |
.CollValid(r_CollValid), |
.RxLateCollision(RxLateCollision), |
.r_RecSmall(r_RecSmall), |
.r_MinFL(r_MinFL), |
.r_MaxFL(r_MaxFL), |
.ShortFrame(ShortFrame), |
.DribbleNibble(DribbleNibble), |
.ReceivedPacketTooBig(ReceivedPacketTooBig), |
.r_HugEn(r_HugEn), |
.LoadRxStatus(LoadRxStatus), |
.RetryCnt(RetryCnt), |
.StartTxDone(StartTxDone), |
.StartTxAbort(StartTxAbort), |
.RetryCntLatched(RetryCntLatched), |
.MTxClk(mtx_clk_pad_i), |
.MaxCollisionOccured(MaxCollisionOccured), |
.RetryLimit(RetryLimit), |
.LateCollision(LateCollision), |
.LateCollLatched(LateCollLatched), |
.DeferIndication(DeferIndication), |
.DeferLatched(DeferLatched), |
.RstDeferLatched(RstDeferLatched), |
.TxStartFrm(TxStartFrmOut), |
.StatePreamble(StatePreamble), |
.StateData(StateData), |
.CarrierSense(CarrierSense_Tx2), |
.CarrierSenseLost(CarrierSenseLost), |
.TxUsedData(TxUsedDataIn), |
.LatchedMRxErr(LatchedMRxErr), |
.Loopback(r_LoopBck), |
.r_FullD(r_FullD) |
); |
|
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_top.v
0,0 → 1,1190
////////////////////////////////////////////////////////////////////// |
//// //// |
//// ethmac.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is available in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001, 2002 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// 2011-08-09 olof@opencores.org |
// Renamed from eth_top.v to ethmac.v to better fit into the OpenCores |
// Structure |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.51 2005/02/21 11:13:17 igorm |
// Defer indication fixed. |
// |
// Revision 1.50 2004/04/26 15:26:23 igorm |
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the |
// previous update of the core. |
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register. |
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER |
// register. (thanks to Mathias and Torbjorn) |
// - Multicast reception was fixed. Thanks to Ulrich Gries |
// |
// Revision 1.49 2003/11/12 18:24:59 tadejm |
// WISHBONE slave changed and tested from only 32-bit accesss to byte access. |
// |
// Revision 1.48 2003/10/17 07:46:16 markom |
// mbist signals updated according to newest convention |
// |
// Revision 1.47 2003/10/06 15:43:45 knguyen |
// Update RxEnSync only when mrxdv_pad_i is inactive (LOW). |
// |
// Revision 1.46 2003/01/30 13:30:22 tadejm |
// Defer indication changed. |
// |
// Revision 1.45 2003/01/22 13:49:26 tadejm |
// When control packets were received, they were ignored in some cases. |
// |
// Revision 1.44 2003/01/21 12:09:40 mohor |
// When receiving normal data frame and RxFlow control was switched on, RXB |
// interrupt was not set. |
// |
// Revision 1.43 2002/11/22 01:57:06 mohor |
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort |
// synchronized. |
// |
// Revision 1.42 2002/11/21 00:09:19 mohor |
// TPauseRq synchronized to tx_clk. |
// |
// Revision 1.41 2002/11/19 18:13:49 mohor |
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. |
// |
// Revision 1.40 2002/11/19 17:34:25 mohor |
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying |
// that a frame was received because of the promiscous mode. |
// |
// Revision 1.39 2002/11/18 17:31:55 mohor |
// wb_rst_i is used for MIIM reset. |
// |
// Revision 1.38 2002/11/14 18:37:20 mohor |
// r_Rst signal does not reset any module any more and is removed from the design. |
// |
// Revision 1.37 2002/11/13 22:25:36 tadejm |
// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. |
// |
// Revision 1.36 2002/10/18 17:04:20 tadejm |
// Changed BIST scan signals. |
// |
// Revision 1.35 2002/10/11 13:36:58 mohor |
// Typo error fixed. (When using Bist) |
// |
// Revision 1.34 2002/10/10 16:49:50 mohor |
// Signals for WISHBONE B3 compliant interface added. |
// |
// Revision 1.33 2002/10/10 16:29:30 mohor |
// BIST added. |
// |
// Revision 1.32 2002/09/20 17:12:58 mohor |
// CsMiss added. When address between 0x800 and 0xfff is accessed within |
// Ethernet Core, error acknowledge is generated. |
// |
// Revision 1.31 2002/09/12 14:50:17 mohor |
// CarrierSenseLost bug fixed when operating in full duplex mode. |
// |
// Revision 1.30 2002/09/10 10:35:23 mohor |
// Ethernet debug registers removed. |
// |
// Revision 1.29 2002/09/09 13:03:13 mohor |
// Error acknowledge is generated when accessing BDs and RST bit in the |
// MODER register (r_Rst) is set. |
// |
// Revision 1.28 2002/09/04 18:44:10 mohor |
// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4 |
// connected. |
// |
// Revision 1.27 2002/07/25 18:15:37 mohor |
// RxAbort changed. Packets received with MRxErr (from PHY) are also |
// aborted. |
// |
// Revision 1.26 2002/07/17 18:51:50 mohor |
// EXTERNAL_DMA removed. External DMA not supported. |
// |
// Revision 1.25 2002/05/03 10:15:50 mohor |
// Outputs registered. Reset changed for eth_wishbone module. |
// |
// Revision 1.24 2002/04/22 14:15:42 mohor |
// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is |
// selected in eth_defines.v |
// |
// Revision 1.23 2002/03/25 13:33:53 mohor |
// md_padoen_o changed to md_padoe_o. Signal was always active high, just |
// name was incorrect. |
// |
// Revision 1.22 2002/02/26 16:59:54 mohor |
// Small fixes for external/internal DMA missmatches. |
// |
// Revision 1.21 2002/02/26 16:21:00 mohor |
// Interrupts changed in the top file |
// |
// Revision 1.20 2002/02/18 10:40:17 mohor |
// Small fixes. |
// |
// Revision 1.19 2002/02/16 14:03:44 mohor |
// Registered trimmed. Unused registers removed. |
// |
// Revision 1.18 2002/02/16 13:06:33 mohor |
// EXTERNAL_DMA used instead of WISHBONE_DMA. |
// |
// Revision 1.17 2002/02/16 07:15:27 mohor |
// Testbench fixed, code simplified, unused signals removed. |
// |
// Revision 1.16 2002/02/15 13:49:39 mohor |
// RxAbort is connected differently. |
// |
// Revision 1.15 2002/02/15 11:38:26 mohor |
// Changes that were lost when updating from 1.11 to 1.14 fixed. |
// |
// Revision 1.14 2002/02/14 20:19:11 billditt |
// Modified for Address Checking, |
// addition of eth_addrcheck.v |
// |
// Revision 1.13 2002/02/12 17:03:03 mohor |
// HASH0 and HASH1 registers added. Registers address width was |
// changed to 8 bits. |
// |
// Revision 1.12 2002/02/11 09:18:22 mohor |
// Tx status is written back to the BD. |
// |
// Revision 1.11 2002/02/08 16:21:54 mohor |
// Rx status is written back to the BD. |
// |
// Revision 1.10 2002/02/06 14:10:21 mohor |
// non-DMA host interface added. Select the right configutation in eth_defines. |
// |
// Revision 1.9 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.8 2001/12/05 15:00:16 mohor |
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors |
// instead of the number of RX descriptors). |
// |
// Revision 1.7 2001/12/05 10:45:59 mohor |
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. |
// |
// Revision 1.6 2001/10/19 11:24:29 mohor |
// Number of addresses (wb_adr_i) minimized. |
// |
// Revision 1.5 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
// |
// Revision 1.4 2001/10/18 12:07:11 mohor |
// Status signals changed, Adress decoding changed, interrupt controller |
// added. |
// |
// Revision 1.3 2001/09/24 15:02:56 mohor |
// Defines changed (All precede with ETH_). Small changes because some |
// tools generate warnings when two operands are together. Synchronization |
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC |
// demands). |
// |
// Revision 1.2 2001/08/15 14:03:59 mohor |
// Signal names changed on the top level for easier pad insertion (ASIC). |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.2 2001/08/02 09:25:31 mohor |
// Unconnected signals are now connected. |
// |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// |
// |
// |
|
|
`include "ethmac_defines.v" |
`include "timescale.v" |
|
|
module eth_top |
( |
// WISHBONE common |
wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o, |
|
// WISHBONE slave |
wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o, |
|
// WISHBONE master |
m_wb_adr_o, m_wb_sel_o, m_wb_we_o, |
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o, |
m_wb_stb_o, m_wb_ack_i, m_wb_err_i, |
|
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o, m_wb_bte_o, |
`endif |
|
//TX |
mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o, |
|
//RX |
mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i, |
|
// MIIM |
mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o, |
|
int_o |
|
// Bist |
`ifdef ETH_BIST |
, |
// debug chain signals |
mbist_si_i, // bist scan serial in |
mbist_so_o, // bist scan serial out |
mbist_ctrl_i // bist chain shift control |
`endif |
|
); |
|
|
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH; |
parameter TX_FIFO_DEPTH = `ETH_TX_FIFO_DEPTH; |
parameter TX_FIFO_CNT_WIDTH = `ETH_TX_FIFO_CNT_WIDTH; |
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH; |
parameter RX_FIFO_DEPTH = `ETH_RX_FIFO_DEPTH; |
parameter RX_FIFO_CNT_WIDTH = `ETH_RX_FIFO_CNT_WIDTH; |
|
|
// WISHBONE common |
input wb_clk_i; // WISHBONE clock |
input wb_rst_i; // WISHBONE reset |
input [31:0] wb_dat_i; // WISHBONE data input |
output [31:0] wb_dat_o; // WISHBONE data output |
output wb_err_o; // WISHBONE error output |
|
// WISHBONE slave |
input [11:2] wb_adr_i; // WISHBONE address input |
input [3:0] wb_sel_i; // WISHBONE byte select input |
input wb_we_i; // WISHBONE write enable input |
input wb_cyc_i; // WISHBONE cycle input |
input wb_stb_i; // WISHBONE strobe input |
output wb_ack_o; // WISHBONE acknowledge output |
|
// WISHBONE master |
output [31:0] m_wb_adr_o; |
output [3:0] m_wb_sel_o; |
output m_wb_we_o; |
input [31:0] m_wb_dat_i; |
output [31:0] m_wb_dat_o; |
output m_wb_cyc_o; |
output m_wb_stb_o; |
input m_wb_ack_i; |
input m_wb_err_i; |
|
wire [29:0] m_wb_adr_tmp; |
|
`ifdef ETH_WISHBONE_B3 |
output [2:0] m_wb_cti_o; // Cycle Type Identifier |
output [1:0] m_wb_bte_o; // Burst Type Extension |
`endif |
|
// Tx |
input mtx_clk_pad_i; // Transmit clock (from PHY) |
output [3:0] mtxd_pad_o; // Transmit nibble (to PHY) |
output mtxen_pad_o; // Transmit enable (to PHY) |
output mtxerr_pad_o; // Transmit error (to PHY) |
|
// Rx |
input mrx_clk_pad_i; // Receive clock (from PHY) |
input [3:0] mrxd_pad_i; // Receive nibble (from PHY) |
input mrxdv_pad_i; // Receive data valid (from PHY) |
input mrxerr_pad_i; // Receive data error (from PHY) |
|
// Common Tx and Rx |
input mcoll_pad_i; // Collision (from PHY) |
input mcrs_pad_i; // Carrier sense (from PHY) |
|
// MII Management interface |
input md_pad_i; // MII data input (from I/O cell) |
output mdc_pad_o; // MII Management data clock (to PHY) |
output md_pad_o; // MII data output (to I/O cell) |
output md_padoe_o; // MII data output enable (to I/O cell) |
|
output int_o; // Interrupt output |
|
// Bist |
`ifdef ETH_BIST |
input mbist_si_i; // bist scan serial in |
output mbist_so_o; // bist scan serial out |
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control |
`endif |
|
wire [31:0] wb_dbg_dat0; |
|
wire [7:0] r_ClkDiv; |
wire r_MiiNoPre; |
wire [15:0] r_CtrlData; |
wire [4:0] r_FIAD; |
wire [4:0] r_RGAD; |
wire r_WCtrlData; |
wire r_RStat; |
wire r_ScanStat; |
wire NValid_stat; |
wire Busy_stat; |
wire LinkFail; |
wire [15:0] Prsd; // Read Status Data (data read from the PHY) |
wire WCtrlDataStart; |
wire RStatStart; |
wire UpdateMIIRX_DATAReg; |
|
wire TxStartFrm; |
wire TxEndFrm; |
wire TxUsedData; |
wire [7:0] TxData; |
wire TxRetry; |
wire TxAbort; |
wire TxUnderRun; |
wire TxDone; |
|
|
reg WillSendControlFrame_sync1; |
reg WillSendControlFrame_sync2; |
reg WillSendControlFrame_sync3; |
reg RstTxPauseRq; |
|
reg TxPauseRq_sync1; |
reg TxPauseRq_sync2; |
reg TxPauseRq_sync3; |
reg TPauseRq; |
|
initial |
begin |
$display(" *********************************************"); |
$display(" ============================================="); |
$display(" eth_top.v will be removed shortly."); |
$display(" Please use ethmac.v as top level file instead"); |
$display(" ============================================="); |
$display(" *********************************************"); |
end |
// Connecting Miim module |
eth_miim miim1 |
( |
.Clk(wb_clk_i), |
.Reset(wb_rst_i), |
.Divider(r_ClkDiv), |
.NoPre(r_MiiNoPre), |
.CtrlData(r_CtrlData), |
.Rgad(r_RGAD), |
.Fiad(r_FIAD), |
.WCtrlData(r_WCtrlData), |
.RStat(r_RStat), |
.ScanStat(r_ScanStat), |
.Mdi(md_pad_i), |
.Mdo(md_pad_o), |
.MdoEn(md_padoe_o), |
.Mdc(mdc_pad_o), |
.Busy(Busy_stat), |
.Prsd(Prsd), |
.LinkFail(LinkFail), |
.Nvalid(NValid_stat), |
.WCtrlDataStart(WCtrlDataStart), |
.RStatStart(RStatStart), |
.UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg) |
); |
|
|
|
|
wire [3:0] RegCs; // Connected to registers |
wire [31:0] RegDataOut; // Multiplexed to wb_dat_o |
wire r_RecSmall; // Receive small frames |
wire r_LoopBck; // Loopback |
wire r_TxEn; // Tx Enable |
wire r_RxEn; // Rx Enable |
|
wire MRxDV_Lb; // Muxed MII receive data valid |
wire MRxErr_Lb; // Muxed MII Receive Error |
wire [3:0] MRxD_Lb; // Muxed MII Receive Data |
wire Transmitting; // Indication that TxEthMAC is transmitting |
wire r_HugEn; // Huge packet enable |
wire r_DlyCrcEn; // Delayed CRC enabled |
wire [15:0] r_MaxFL; // Maximum frame length |
|
wire [15:0] r_MinFL; // Minimum frame length |
wire ShortFrame; |
wire DribbleNibble; // Extra nibble received |
wire ReceivedPacketTooBig; // Received packet is too big |
wire [47:0] r_MAC; // MAC address |
wire LoadRxStatus; // Rx status was loaded |
wire [31:0] r_HASH0; // HASH table, lower 4 bytes |
wire [31:0] r_HASH1; // HASH table, upper 4 bytes |
wire [7:0] r_TxBDNum; // Receive buffer descriptor number |
wire [6:0] r_IPGT; // |
wire [6:0] r_IPGR1; // |
wire [6:0] r_IPGR2; // |
wire [5:0] r_CollValid; // |
wire [15:0] r_TxPauseTV; // Transmit PAUSE value |
wire r_TxPauseRq; // Transmit PAUSE request |
|
wire [3:0] r_MaxRet; // |
wire r_NoBckof; // |
wire r_ExDfrEn; // |
wire r_TxFlow; // Tx flow control enable |
wire r_IFG; // Minimum interframe gap for incoming packets |
|
wire TxB_IRQ; // Interrupt Tx Buffer |
wire TxE_IRQ; // Interrupt Tx Error |
wire RxB_IRQ; // Interrupt Rx Buffer |
wire RxE_IRQ; // Interrupt Rx Error |
wire Busy_IRQ; // Interrupt Busy (lack of buffers) |
|
//wire DWord; |
wire ByteSelected; |
wire BDAck; |
wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module |
//(for buffer descriptors read/write) |
wire [3:0] BDCs; // Buffer descriptor CS |
wire CsMiss; // When access to the address between 0x800 |
// and 0xfff occurs, acknowledge is set |
// but data is not valid. |
wire r_Pad; |
wire r_CrcEn; |
wire r_FullD; |
wire r_Pro; |
wire r_Bro; |
wire r_NoPre; |
wire r_RxFlow; |
wire r_PassAll; |
wire TxCtrlEndFrm; |
wire StartTxDone; |
wire SetPauseTimer; |
wire TxUsedDataIn; |
wire TxDoneIn; |
wire TxAbortIn; |
wire PerPacketPad; |
wire PadOut; |
wire PerPacketCrcEn; |
wire CrcEnOut; |
wire TxStartFrmOut; |
wire TxEndFrmOut; |
wire ReceivedPauseFrm; |
wire ControlFrmAddressOK; |
wire RxStatusWriteLatched_sync2; |
wire LateCollision; |
wire DeferIndication; |
wire LateCollLatched; |
wire DeferLatched; |
wire RstDeferLatched; |
wire CarrierSenseLost; |
|
wire temp_wb_ack_o; |
wire [31:0] temp_wb_dat_o; |
wire temp_wb_err_o; |
|
`ifdef ETH_REGISTERED_OUTPUTS |
reg temp_wb_ack_o_reg; |
reg [31:0] temp_wb_dat_o_reg; |
reg temp_wb_err_o_reg; |
`endif |
|
//assign DWord = &wb_sel_i; |
assign ByteSelected = |wb_sel_i; |
assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3]; // 0x0 - 0x3FF |
assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2]; // 0x0 - 0x3FF |
assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1]; // 0x0 - 0x3FF |
assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0]; // 0x0 - 0x3FF |
assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF |
assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF |
assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF |
assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF |
assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF |
assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O; |
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss); |
|
`ifdef ETH_REGISTERED_OUTPUTS |
assign wb_ack_o = temp_wb_ack_o_reg; |
assign wb_dat_o[31:0] = temp_wb_dat_o_reg; |
assign wb_err_o = temp_wb_err_o_reg; |
`else |
assign wb_ack_o = temp_wb_ack_o; |
assign wb_dat_o[31:0] = temp_wb_dat_o; |
assign wb_err_o = temp_wb_err_o; |
`endif |
|
`ifdef ETH_AVALON_BUS |
// As Avalon has no corresponding "error" signal, I (erroneously) will |
// send an ack to Avalon, even when accessing undefined memory. This |
// is a grey area in Avalon vs. Wishbone specs: My understanding |
// is that Avalon expects all memory addressable by the addr bus feeding |
// a slave to be, at the very minimum, readable. |
assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss; |
`else // WISHBONE |
assign temp_wb_ack_o = (|RegCs) | BDAck; |
`endif |
|
`ifdef ETH_REGISTERED_OUTPUTS |
always @ (posedge wb_clk_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
begin |
temp_wb_ack_o_reg <= 1'b0; |
temp_wb_dat_o_reg <= 32'h0; |
temp_wb_err_o_reg <= 1'b0; |
end |
else |
begin |
temp_wb_ack_o_reg <= temp_wb_ack_o & ~temp_wb_ack_o_reg; |
temp_wb_dat_o_reg <= temp_wb_dat_o; |
temp_wb_err_o_reg <= temp_wb_err_o & ~temp_wb_err_o_reg; |
end |
end |
`endif |
|
|
// Connecting Ethernet registers |
eth_registers ethreg1 |
( |
.DataIn(wb_dat_i), |
.Address(wb_adr_i[9:2]), |
.Rw(wb_we_i), |
.Cs(RegCs), |
.Clk(wb_clk_i), |
.Reset(wb_rst_i), |
.DataOut(RegDataOut), |
.r_RecSmall(r_RecSmall), |
.r_Pad(r_Pad), |
.r_HugEn(r_HugEn), |
.r_CrcEn(r_CrcEn), |
.r_DlyCrcEn(r_DlyCrcEn), |
.r_FullD(r_FullD), |
.r_ExDfrEn(r_ExDfrEn), |
.r_NoBckof(r_NoBckof), |
.r_LoopBck(r_LoopBck), |
.r_IFG(r_IFG), |
.r_Pro(r_Pro), |
.r_Iam(), |
.r_Bro(r_Bro), |
.r_NoPre(r_NoPre), |
.r_TxEn(r_TxEn), |
.r_RxEn(r_RxEn), |
.Busy_IRQ(Busy_IRQ), |
.RxE_IRQ(RxE_IRQ), |
.RxB_IRQ(RxB_IRQ), |
.TxE_IRQ(TxE_IRQ), |
.TxB_IRQ(TxB_IRQ), |
.r_IPGT(r_IPGT), |
.r_IPGR1(r_IPGR1), |
.r_IPGR2(r_IPGR2), |
.r_MinFL(r_MinFL), |
.r_MaxFL(r_MaxFL), |
.r_MaxRet(r_MaxRet), |
.r_CollValid(r_CollValid), |
.r_TxFlow(r_TxFlow), |
.r_RxFlow(r_RxFlow), |
.r_PassAll(r_PassAll), |
.r_MiiNoPre(r_MiiNoPre), |
.r_ClkDiv(r_ClkDiv), |
.r_WCtrlData(r_WCtrlData), |
.r_RStat(r_RStat), |
.r_ScanStat(r_ScanStat), |
.r_RGAD(r_RGAD), |
.r_FIAD(r_FIAD), |
.r_CtrlData(r_CtrlData), |
.NValid_stat(NValid_stat), |
.Busy_stat(Busy_stat), |
.LinkFail(LinkFail), |
.r_MAC(r_MAC), |
.WCtrlDataStart(WCtrlDataStart), |
.RStatStart(RStatStart), |
.UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), |
.Prsd(Prsd), |
.r_TxBDNum(r_TxBDNum), |
.int_o(int_o), |
.r_HASH0(r_HASH0), |
.r_HASH1(r_HASH1), |
.r_TxPauseRq(r_TxPauseRq), |
.r_TxPauseTV(r_TxPauseTV), |
.RstTxPauseRq(RstTxPauseRq), |
.TxCtrlEndFrm(TxCtrlEndFrm), |
.StartTxDone(StartTxDone), |
.TxClk(mtx_clk_pad_i), |
.RxClk(mrx_clk_pad_i), |
.dbg_dat(wb_dbg_dat0), |
.SetPauseTimer(SetPauseTimer) |
|
); |
|
|
|
wire [7:0] RxData; |
wire RxValid; |
wire RxStartFrm; |
wire RxEndFrm; |
wire RxAbort; |
|
wire WillTransmit; // Will transmit (to RxEthMAC) |
wire ResetCollision; // Reset Collision (for synchronizing |
// collision) |
wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC) |
wire WillSendControlFrame; |
wire ReceiveEnd; |
wire ReceivedPacketGood; |
wire ReceivedLengthOK; |
wire InvalidSymbol; |
wire LatchedCrcError; |
wire RxLateCollision; |
wire [3:0] RetryCntLatched; |
wire [3:0] RetryCnt; |
wire StartTxAbort; |
wire MaxCollisionOccured; |
wire RetryLimit; |
wire StatePreamble; |
wire [1:0] StateData; |
|
// Connecting MACControl |
eth_maccontrol maccontrol1 |
( |
.MTxClk(mtx_clk_pad_i), |
.TPauseRq(TPauseRq), |
.TxPauseTV(r_TxPauseTV), |
.TxDataIn(TxData), |
.TxStartFrmIn(TxStartFrm), |
.TxEndFrmIn(TxEndFrm), |
.TxUsedDataIn(TxUsedDataIn), |
.TxDoneIn(TxDoneIn), |
.TxAbortIn(TxAbortIn), |
.MRxClk(mrx_clk_pad_i), |
.RxData(RxData), |
.RxValid(RxValid), |
.RxStartFrm(RxStartFrm), |
.RxEndFrm(RxEndFrm), |
.ReceiveEnd(ReceiveEnd), |
.ReceivedPacketGood(ReceivedPacketGood), |
.TxFlow(r_TxFlow), |
.RxFlow(r_RxFlow), |
.DlyCrcEn(r_DlyCrcEn), |
.MAC(r_MAC), |
.PadIn(r_Pad | PerPacketPad), |
.PadOut(PadOut), |
.CrcEnIn(r_CrcEn | PerPacketCrcEn), |
.CrcEnOut(CrcEnOut), |
.TxReset(wb_rst_i), |
.RxReset(wb_rst_i), |
.ReceivedLengthOK(ReceivedLengthOK), |
.TxDataOut(TxDataOut), |
.TxStartFrmOut(TxStartFrmOut), |
.TxEndFrmOut(TxEndFrmOut), |
.TxUsedDataOut(TxUsedData), |
.TxDoneOut(TxDone), |
.TxAbortOut(TxAbort), |
.WillSendControlFrame(WillSendControlFrame), |
.TxCtrlEndFrm(TxCtrlEndFrm), |
.ReceivedPauseFrm(ReceivedPauseFrm), |
.ControlFrmAddressOK(ControlFrmAddressOK), |
.SetPauseTimer(SetPauseTimer), |
.RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), |
.r_PassAll(r_PassAll) |
); |
|
|
|
wire TxCarrierSense; // Synchronized CarrierSense (to Tx clock) |
wire Collision; // Synchronized Collision |
|
reg CarrierSense_Tx1; |
reg CarrierSense_Tx2; |
reg Collision_Tx1; |
reg Collision_Tx2; |
|
reg RxEnSync; // Synchronized Receive Enable |
reg WillTransmit_q; |
reg WillTransmit_q2; |
|
|
|
// Muxed MII receive data valid |
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync; |
|
// Muxed MII Receive Error |
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync; |
|
// Muxed MII Receive Data |
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0]; |
|
|
|
// Connecting TxEthMAC |
eth_txethmac txethmac1 |
( |
.MTxClk(mtx_clk_pad_i), |
.Reset(wb_rst_i), |
.CarrierSense(TxCarrierSense), |
.Collision(Collision), |
.TxData(TxDataOut), |
.TxStartFrm(TxStartFrmOut), |
.TxUnderRun(TxUnderRun), |
.TxEndFrm(TxEndFrmOut), |
.Pad(PadOut), |
.MinFL(r_MinFL), |
.CrcEn(CrcEnOut), |
.FullD(r_FullD), |
.HugEn(r_HugEn), |
.DlyCrcEn(r_DlyCrcEn), |
.IPGT(r_IPGT), |
.IPGR1(r_IPGR1), |
.IPGR2(r_IPGR2), |
.CollValid(r_CollValid), |
.MaxRet(r_MaxRet), |
.NoBckof(r_NoBckof), |
.ExDfrEn(r_ExDfrEn), |
.MaxFL(r_MaxFL), |
.MTxEn(mtxen_pad_o), |
.MTxD(mtxd_pad_o), |
.MTxErr(mtxerr_pad_o), |
.TxUsedData(TxUsedDataIn), |
.TxDone(TxDoneIn), |
.TxRetry(TxRetry), |
.TxAbort(TxAbortIn), |
.WillTransmit(WillTransmit), |
.ResetCollision(ResetCollision), |
.RetryCnt(RetryCnt), |
.StartTxDone(StartTxDone), |
.StartTxAbort(StartTxAbort), |
.MaxCollisionOccured(MaxCollisionOccured), |
.LateCollision(LateCollision), |
.DeferIndication(DeferIndication), |
.StatePreamble(StatePreamble), |
.StateData(StateData) |
); |
|
|
|
|
wire [15:0] RxByteCnt; |
wire RxByteCntEq0; |
wire RxByteCntGreat2; |
wire RxByteCntMaxFrame; |
wire RxCrcError; |
wire RxStateIdle; |
wire RxStatePreamble; |
wire RxStateSFD; |
wire [1:0] RxStateData; |
wire AddressMiss; |
|
|
|
// Connecting RxEthMAC |
eth_rxethmac rxethmac1 |
( |
.MRxClk(mrx_clk_pad_i), |
.MRxDV(MRxDV_Lb), |
.MRxD(MRxD_Lb), |
.Transmitting(Transmitting), |
.HugEn(r_HugEn), |
.DlyCrcEn(r_DlyCrcEn), |
.MaxFL(r_MaxFL), |
.r_IFG(r_IFG), |
.Reset(wb_rst_i), |
.RxData(RxData), |
.RxValid(RxValid), |
.RxStartFrm(RxStartFrm), |
.RxEndFrm(RxEndFrm), |
.ByteCnt(RxByteCnt), |
.ByteCntEq0(RxByteCntEq0), |
.ByteCntGreat2(RxByteCntGreat2), |
.ByteCntMaxFrame(RxByteCntMaxFrame), |
.CrcError(RxCrcError), |
.StateIdle(RxStateIdle), |
.StatePreamble(RxStatePreamble), |
.StateSFD(RxStateSFD), |
.StateData(RxStateData), |
.MAC(r_MAC), |
.r_Pro(r_Pro), |
.r_Bro(r_Bro), |
.r_HASH0(r_HASH0), |
.r_HASH1(r_HASH1), |
.RxAbort(RxAbort), |
.AddressMiss(AddressMiss), |
.PassAll(r_PassAll), |
.ControlFrmAddressOK(ControlFrmAddressOK) |
); |
|
|
// MII Carrier Sense Synchronization |
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
begin |
CarrierSense_Tx1 <= 1'b0; |
CarrierSense_Tx2 <= 1'b0; |
end |
else |
begin |
CarrierSense_Tx1 <= mcrs_pad_i; |
CarrierSense_Tx2 <= CarrierSense_Tx1; |
end |
end |
|
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2; |
|
|
// MII Collision Synchronization |
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
begin |
Collision_Tx1 <= 1'b0; |
Collision_Tx2 <= 1'b0; |
end |
else |
begin |
Collision_Tx1 <= mcoll_pad_i; |
if(ResetCollision) |
Collision_Tx2 <= 1'b0; |
else |
if(Collision_Tx1) |
Collision_Tx2 <= 1'b1; |
end |
end |
|
|
// Synchronized Collision |
assign Collision = ~r_FullD & Collision_Tx2; |
|
|
|
// Delayed WillTransmit |
always @ (posedge mrx_clk_pad_i) |
begin |
WillTransmit_q <= WillTransmit; |
WillTransmit_q2 <= WillTransmit_q; |
end |
|
|
assign Transmitting = ~r_FullD & WillTransmit_q2; |
|
|
|
// Synchronized Receive Enable |
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
RxEnSync <= 1'b0; |
else |
if(~mrxdv_pad_i) |
RxEnSync <= r_RxEn; |
end |
|
|
|
// Synchronizing WillSendControlFrame to WB_CLK; |
always @ (posedge wb_clk_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
WillSendControlFrame_sync1 <= 1'b0; |
else |
WillSendControlFrame_sync1 <= WillSendControlFrame; |
end |
|
always @ (posedge wb_clk_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
WillSendControlFrame_sync2 <= 1'b0; |
else |
WillSendControlFrame_sync2 <= WillSendControlFrame_sync1; |
end |
|
always @ (posedge wb_clk_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
WillSendControlFrame_sync3 <= 1'b0; |
else |
WillSendControlFrame_sync3 <= WillSendControlFrame_sync2; |
end |
|
always @ (posedge wb_clk_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
RstTxPauseRq <= 1'b0; |
else |
RstTxPauseRq <= WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3; |
end |
|
|
|
|
// TX Pause request Synchronization |
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
begin |
TxPauseRq_sync1 <= 1'b0; |
TxPauseRq_sync2 <= 1'b0; |
TxPauseRq_sync3 <= 1'b0; |
end |
else |
begin |
TxPauseRq_sync1 <= (r_TxPauseRq & r_TxFlow); |
TxPauseRq_sync2 <= TxPauseRq_sync1; |
TxPauseRq_sync3 <= TxPauseRq_sync2; |
end |
end |
|
|
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
TPauseRq <= 1'b0; |
else |
TPauseRq <= TxPauseRq_sync2 & (~TxPauseRq_sync3); |
end |
|
|
wire LatchedMRxErr; |
reg RxAbort_latch; |
reg RxAbort_sync1; |
reg RxAbort_wb; |
reg RxAbortRst_sync1; |
reg RxAbortRst; |
|
// Synchronizing RxAbort to the WISHBONE clock |
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
RxAbort_latch <= 1'b0; |
else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & |
~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll))) |
RxAbort_latch <= 1'b1; |
else if(RxAbortRst) |
RxAbort_latch <= 1'b0; |
end |
|
always @ (posedge wb_clk_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
begin |
RxAbort_sync1 <= 1'b0; |
RxAbort_wb <= 1'b0; |
RxAbort_wb <= 1'b0; |
end |
else |
begin |
RxAbort_sync1 <= RxAbort_latch; |
RxAbort_wb <= RxAbort_sync1; |
end |
end |
|
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
begin |
RxAbortRst_sync1 <= 1'b0; |
RxAbortRst <= 1'b0; |
end |
else |
begin |
RxAbortRst_sync1 <= RxAbort_wb; |
RxAbortRst <= RxAbortRst_sync1; |
end |
end |
|
|
|
// Connecting Wishbone module |
eth_wishbone #(.TX_FIFO_DATA_WIDTH(TX_FIFO_DATA_WIDTH), |
.TX_FIFO_DEPTH (TX_FIFO_DEPTH), |
.TX_FIFO_CNT_WIDTH (TX_FIFO_CNT_WIDTH), |
.RX_FIFO_DATA_WIDTH(RX_FIFO_DATA_WIDTH), |
.RX_FIFO_DEPTH (RX_FIFO_DEPTH), |
.RX_FIFO_CNT_WIDTH (RX_FIFO_CNT_WIDTH)) |
wishbone |
( |
.WB_CLK_I(wb_clk_i), |
.WB_DAT_I(wb_dat_i), |
.WB_DAT_O(BD_WB_DAT_O), |
|
// WISHBONE slave |
.WB_ADR_I(wb_adr_i[9:2]), |
.WB_WE_I(wb_we_i), |
.BDCs(BDCs), |
.WB_ACK_O(BDAck), |
.Reset(wb_rst_i), |
|
// WISHBONE master |
.m_wb_adr_o(m_wb_adr_tmp), |
.m_wb_sel_o(m_wb_sel_o), |
.m_wb_we_o(m_wb_we_o), |
.m_wb_dat_i(m_wb_dat_i), |
.m_wb_dat_o(m_wb_dat_o), |
.m_wb_cyc_o(m_wb_cyc_o), |
.m_wb_stb_o(m_wb_stb_o), |
.m_wb_ack_i(m_wb_ack_i), |
.m_wb_err_i(m_wb_err_i), |
|
`ifdef ETH_WISHBONE_B3 |
.m_wb_cti_o(m_wb_cti_o), |
.m_wb_bte_o(m_wb_bte_o), |
`endif |
|
//TX |
.MTxClk(mtx_clk_pad_i), |
.TxStartFrm(TxStartFrm), |
.TxEndFrm(TxEndFrm), |
.TxUsedData(TxUsedData), |
.TxData(TxData), |
.TxRetry(TxRetry), |
.TxAbort(TxAbort), |
.TxUnderRun(TxUnderRun), |
.TxDone(TxDone), |
.PerPacketCrcEn(PerPacketCrcEn), |
.PerPacketPad(PerPacketPad), |
|
// Register |
.r_TxEn(r_TxEn), |
.r_RxEn(r_RxEn), |
.r_TxBDNum(r_TxBDNum), |
.r_RxFlow(r_RxFlow), |
.r_PassAll(r_PassAll), |
|
//RX |
.MRxClk(mrx_clk_pad_i), |
.RxData(RxData), |
.RxValid(RxValid), |
.RxStartFrm(RxStartFrm), |
.RxEndFrm(RxEndFrm), |
.Busy_IRQ(Busy_IRQ), |
.RxE_IRQ(RxE_IRQ), |
.RxB_IRQ(RxB_IRQ), |
.TxE_IRQ(TxE_IRQ), |
.TxB_IRQ(TxB_IRQ), |
|
.RxAbort(RxAbort_wb), |
.RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), |
|
.InvalidSymbol(InvalidSymbol), |
.LatchedCrcError(LatchedCrcError), |
.RxLength(RxByteCnt), |
.RxLateCollision(RxLateCollision), |
.ShortFrame(ShortFrame), |
.DribbleNibble(DribbleNibble), |
.ReceivedPacketTooBig(ReceivedPacketTooBig), |
.LoadRxStatus(LoadRxStatus), |
.RetryCntLatched(RetryCntLatched), |
.RetryLimit(RetryLimit), |
.LateCollLatched(LateCollLatched), |
.DeferLatched(DeferLatched), |
.RstDeferLatched(RstDeferLatched), |
.CarrierSenseLost(CarrierSenseLost), |
.ReceivedPacketGood(ReceivedPacketGood), |
.AddressMiss(AddressMiss), |
.ReceivedPauseFrm(ReceivedPauseFrm) |
|
`ifdef ETH_BIST |
, |
.mbist_si_i (mbist_si_i), |
.mbist_so_o (mbist_so_o), |
.mbist_ctrl_i (mbist_ctrl_i) |
`endif |
`ifdef WISHBONE_DEBUG |
, |
.dbg_dat0(wb_dbg_dat0) |
`endif |
|
); |
|
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0}; |
|
// Connecting MacStatus module |
eth_macstatus macstatus1 |
( |
.MRxClk(mrx_clk_pad_i), |
.Reset(wb_rst_i), |
.ReceiveEnd(ReceiveEnd), |
.ReceivedPacketGood(ReceivedPacketGood), |
.ReceivedLengthOK(ReceivedLengthOK), |
.RxCrcError(RxCrcError), |
.MRxErr(MRxErr_Lb), |
.MRxDV(MRxDV_Lb), |
.RxStateSFD(RxStateSFD), |
.RxStateData(RxStateData), |
.RxStatePreamble(RxStatePreamble), |
.RxStateIdle(RxStateIdle), |
.Transmitting(Transmitting), |
.RxByteCnt(RxByteCnt), |
.RxByteCntEq0(RxByteCntEq0), |
.RxByteCntGreat2(RxByteCntGreat2), |
.RxByteCntMaxFrame(RxByteCntMaxFrame), |
.InvalidSymbol(InvalidSymbol), |
.MRxD(MRxD_Lb), |
.LatchedCrcError(LatchedCrcError), |
.Collision(mcoll_pad_i), |
.CollValid(r_CollValid), |
.RxLateCollision(RxLateCollision), |
.r_RecSmall(r_RecSmall), |
.r_MinFL(r_MinFL), |
.r_MaxFL(r_MaxFL), |
.ShortFrame(ShortFrame), |
.DribbleNibble(DribbleNibble), |
.ReceivedPacketTooBig(ReceivedPacketTooBig), |
.r_HugEn(r_HugEn), |
.LoadRxStatus(LoadRxStatus), |
.RetryCnt(RetryCnt), |
.StartTxDone(StartTxDone), |
.StartTxAbort(StartTxAbort), |
.RetryCntLatched(RetryCntLatched), |
.MTxClk(mtx_clk_pad_i), |
.MaxCollisionOccured(MaxCollisionOccured), |
.RetryLimit(RetryLimit), |
.LateCollision(LateCollision), |
.LateCollLatched(LateCollLatched), |
.DeferIndication(DeferIndication), |
.DeferLatched(DeferLatched), |
.RstDeferLatched(RstDeferLatched), |
.TxStartFrm(TxStartFrmOut), |
.StatePreamble(StatePreamble), |
.StateData(StateData), |
.CarrierSense(CarrierSense_Tx2), |
.CarrierSenseLost(CarrierSenseLost), |
.TxUsedData(TxUsedDataIn), |
.LatchedMRxErr(LatchedMRxErr), |
.Loopback(r_LoopBck), |
.r_FullD(r_FullD) |
); |
|
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_crc.v
0,0 → 1,143
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_crc.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// - Novan Hartadi (novan@vlsi.itb.ac.id) //// |
//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// Revision 1.3 2001/06/19 18:16:40 mohor |
// TxClk changed to MTxClk (as discribed in the documentation). |
// Crc changed so only one file can be used instead of two. |
// |
// Revision 1.2 2001/06/19 10:38:07 mohor |
// Minor changes in header. |
// |
// Revision 1.1 2001/06/19 10:27:57 mohor |
// TxEthMAC initial release. |
// |
// |
// |
|
|
`include "timescale.v" |
|
module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError); |
|
|
input Clk; |
input Reset; |
input [3:0] Data; |
input Enable; |
input Initialize; |
|
output [31:0] Crc; |
output CrcError; |
|
reg [31:0] Crc; |
|
wire [31:0] CrcNext; |
|
|
assign CrcNext[0] = Enable & (Data[0] ^ Crc[28]); |
assign CrcNext[1] = Enable & (Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29]); |
assign CrcNext[2] = Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30]); |
assign CrcNext[3] = Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31]); |
assign CrcNext[4] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[0]; |
assign CrcNext[5] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[1]; |
assign CrcNext[6] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[ 2]; |
assign CrcNext[7] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[3]; |
assign CrcNext[8] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[4]; |
assign CrcNext[9] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[5]; |
assign CrcNext[10] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[6]; |
assign CrcNext[11] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[7]; |
assign CrcNext[12] = (Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30])) ^ Crc[8]; |
assign CrcNext[13] = (Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31])) ^ Crc[9]; |
assign CrcNext[14] = (Enable & (Data[3] ^ Data[2] ^ Crc[30] ^ Crc[31])) ^ Crc[10]; |
assign CrcNext[15] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[11]; |
assign CrcNext[16] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[12]; |
assign CrcNext[17] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[13]; |
assign CrcNext[18] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[14]; |
assign CrcNext[19] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[15]; |
assign CrcNext[20] = Crc[16]; |
assign CrcNext[21] = Crc[17]; |
assign CrcNext[22] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[18]; |
assign CrcNext[23] = (Enable & (Data[1] ^ Data[0] ^ Crc[29] ^ Crc[28])) ^ Crc[19]; |
assign CrcNext[24] = (Enable & (Data[2] ^ Data[1] ^ Crc[30] ^ Crc[29])) ^ Crc[20]; |
assign CrcNext[25] = (Enable & (Data[3] ^ Data[2] ^ Crc[31] ^ Crc[30])) ^ Crc[21]; |
assign CrcNext[26] = (Enable & (Data[3] ^ Data[0] ^ Crc[31] ^ Crc[28])) ^ Crc[22]; |
assign CrcNext[27] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[23]; |
assign CrcNext[28] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[24]; |
assign CrcNext[29] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[25]; |
assign CrcNext[30] = Crc[26]; |
assign CrcNext[31] = Crc[27]; |
|
|
always @ (posedge Clk or posedge Reset) |
begin |
if (Reset) |
Crc <= 32'hffffffff; |
else |
if(Initialize) |
Crc <= 32'hffffffff; |
else |
Crc <= CrcNext; |
end |
|
assign CrcError = Crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number |
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_shiftreg.v
0,0 → 1,151
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_shiftreg.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2002/08/14 18:16:59 mohor |
// LinkFail signal was not latching appropriate bit. |
// |
// Revision 1.4 2002/03/02 21:06:01 mohor |
// LinkFail signal was not latching appropriate bit. |
// |
// Revision 1.3 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.2 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// Revision 1.3 2001/06/01 22:28:56 mohor |
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. |
// |
// |
|
`include "timescale.v" |
|
|
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect, |
LatchByte, ShiftedBit, Prsd, LinkFail); |
|
|
input Clk; // Input clock (Host clock) |
input Reset; // Reset signal |
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls. |
input Mdi; // MII input data |
input [4:0] Fiad; // PHY address |
input [4:0] Rgad; // Register address (within the selected PHY) |
input [15:0]CtrlData; // Control data (data to be written to the PHY) |
input WriteOp; // The current operation is a PHY register write operation |
input [3:0] ByteSelect; // Byte select |
input [1:0] LatchByte; // Byte select for latching (read operation) |
|
output ShiftedBit; // Bit shifted out of the shift register |
output[15:0]Prsd; // Read Status Data (data read from the PHY) |
output LinkFail; // Link Integrity Signal |
|
reg [7:0] ShiftReg; // Shift register for shifting the data in and out |
reg [15:0]Prsd; |
reg LinkFail; |
|
|
|
|
// ShiftReg[7:0] :: Shift Register Data |
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
begin |
ShiftReg[7:0] <= 8'h0; |
Prsd[15:0] <= 16'h0; |
LinkFail <= 1'b0; |
end |
else |
begin |
if(MdcEn_n) |
begin |
if(|ByteSelect) |
begin |
/* verilator lint_off CASEINCOMPLETE */ |
case (ByteSelect[3:0]) // synopsys parallel_case full_case |
4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]}; |
4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10}; |
4'h4 : ShiftReg[7:0] <= CtrlData[15:8]; |
4'h8 : ShiftReg[7:0] <= CtrlData[7:0]; |
endcase // case (ByteSelect[3:0]) |
/* verilator lint_on CASEINCOMPLETE */ |
end |
else |
begin |
ShiftReg[7:0] <= {ShiftReg[6:0], Mdi}; |
if(LatchByte[0]) |
begin |
Prsd[7:0] <= {ShiftReg[6:0], Mdi}; |
if(Rgad == 5'h01) |
LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet |
end |
else |
begin |
if(LatchByte[1]) |
Prsd[15:8] <= {ShiftReg[6:0], Mdi}; |
end |
end |
end |
end |
end |
|
|
assign ShiftedBit = ShiftReg[7]; |
|
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_receivecontrol.v
0,0 → 1,437
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_receivecontrol.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2002/11/22 01:57:06 mohor |
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort |
// synchronized. |
// |
// Revision 1.3 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.2 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// Revision 1.1 2001/07/03 12:51:54 mohor |
// Initial release of the MAC Control module. |
// |
// |
// |
// |
// |
|
|
`include "timescale.v" |
|
|
module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm, |
RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDoneIn, |
TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood, |
TxUsedDataOutDetected, Pause, ReceivedPauseFrm, AddressOK, |
RxStatusWriteLatched_sync2, r_PassAll, SetPauseTimer |
); |
|
|
input MTxClk; |
input MRxClk; |
input TxReset; |
input RxReset; |
input [7:0] RxData; |
input RxValid; |
input RxStartFrm; |
input RxEndFrm; |
input RxFlow; |
input ReceiveEnd; |
input [47:0]MAC; |
input DlyCrcEn; |
input TxDoneIn; |
input TxAbortIn; |
input TxStartFrmOut; |
input ReceivedLengthOK; |
input ReceivedPacketGood; |
input TxUsedDataOutDetected; |
input RxStatusWriteLatched_sync2; |
input r_PassAll; |
|
output Pause; |
output ReceivedPauseFrm; |
output AddressOK; |
output SetPauseTimer; |
|
|
reg Pause; |
reg AddressOK; // Multicast or unicast address detected |
reg TypeLengthOK; // Type/Length field contains 0x8808 |
reg DetectionWindow; // Detection of the PAUSE frame is possible within this window |
reg OpCodeOK; // PAUSE opcode detected (0x0001) |
reg [2:0] DlyCrcCnt; |
reg [4:0] ByteCnt; |
reg [15:0] AssembledTimerValue; |
reg [15:0] LatchedTimerValue; |
reg ReceivedPauseFrm; |
reg ReceivedPauseFrmWAddr; |
reg PauseTimerEq0_sync1; |
reg PauseTimerEq0_sync2; |
reg [15:0] PauseTimer; |
reg Divider2; |
reg [5:0] SlotTimer; |
|
wire [47:0] ReservedMulticast; // 0x0180C2000001 |
wire [15:0] TypeLength; // 0x8808 |
wire ResetByteCnt; // |
wire IncrementByteCnt; // |
wire ByteCntEq0; // ByteCnt = 0 |
wire ByteCntEq1; // ByteCnt = 1 |
wire ByteCntEq2; // ByteCnt = 2 |
wire ByteCntEq3; // ByteCnt = 3 |
wire ByteCntEq4; // ByteCnt = 4 |
wire ByteCntEq5; // ByteCnt = 5 |
wire ByteCntEq12; // ByteCnt = 12 |
wire ByteCntEq13; // ByteCnt = 13 |
wire ByteCntEq14; // ByteCnt = 14 |
wire ByteCntEq15; // ByteCnt = 15 |
wire ByteCntEq16; // ByteCnt = 16 |
wire ByteCntEq17; // ByteCnt = 17 |
wire ByteCntEq18; // ByteCnt = 18 |
wire DecrementPauseTimer; // |
wire PauseTimerEq0; // |
wire ResetSlotTimer; // |
wire IncrementSlotTimer; // |
wire SlotFinished; // |
|
|
|
// Reserved multicast address and Type/Length for PAUSE control |
assign ReservedMulticast = 48'h0180C2000001; |
assign TypeLength = 16'h8808; |
|
|
// Address Detection (Multicast or unicast) |
always @ (posedge MRxClk or posedge RxReset) |
begin |
if(RxReset) |
AddressOK <= 1'b0; |
else |
if(DetectionWindow & ByteCntEq0) |
AddressOK <= RxData[7:0] == ReservedMulticast[47:40] | RxData[7:0] == MAC[47:40]; |
else |
if(DetectionWindow & ByteCntEq1) |
AddressOK <= (RxData[7:0] == ReservedMulticast[39:32] | RxData[7:0] == MAC[39:32]) & AddressOK; |
else |
if(DetectionWindow & ByteCntEq2) |
AddressOK <= (RxData[7:0] == ReservedMulticast[31:24] | RxData[7:0] == MAC[31:24]) & AddressOK; |
else |
if(DetectionWindow & ByteCntEq3) |
AddressOK <= (RxData[7:0] == ReservedMulticast[23:16] | RxData[7:0] == MAC[23:16]) & AddressOK; |
else |
if(DetectionWindow & ByteCntEq4) |
AddressOK <= (RxData[7:0] == ReservedMulticast[15:8] | RxData[7:0] == MAC[15:8]) & AddressOK; |
else |
if(DetectionWindow & ByteCntEq5) |
AddressOK <= (RxData[7:0] == ReservedMulticast[7:0] | RxData[7:0] == MAC[7:0]) & AddressOK; |
else |
if(ReceiveEnd) |
AddressOK <= 1'b0; |
end |
|
|
|
// TypeLengthOK (Type/Length Control frame detected) |
always @ (posedge MRxClk or posedge RxReset ) |
begin |
if(RxReset) |
TypeLengthOK <= 1'b0; |
else |
if(DetectionWindow & ByteCntEq12) |
TypeLengthOK <= ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]); |
else |
if(DetectionWindow & ByteCntEq13) |
TypeLengthOK <= ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK; |
else |
if(ReceiveEnd) |
TypeLengthOK <= 1'b0; |
end |
|
|
|
// Latch Control Frame Opcode |
always @ (posedge MRxClk or posedge RxReset ) |
begin |
if(RxReset) |
OpCodeOK <= 1'b0; |
else |
if(ByteCntEq16) |
OpCodeOK <= 1'b0; |
else |
begin |
if(DetectionWindow & ByteCntEq14) |
OpCodeOK <= ByteCntEq14 & RxData[7:0] == 8'h00; |
|
if(DetectionWindow & ByteCntEq15) |
OpCodeOK <= ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK; |
end |
end |
|
|
// ReceivedPauseFrmWAddr (+Address Check) |
always @ (posedge MRxClk or posedge RxReset ) |
begin |
if(RxReset) |
ReceivedPauseFrmWAddr <= 1'b0; |
else |
if(ReceiveEnd) |
ReceivedPauseFrmWAddr <= 1'b0; |
else |
if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK) |
ReceivedPauseFrmWAddr <= 1'b1; |
end |
|
|
|
// Assembling 16-bit timer value from two 8-bit data |
always @ (posedge MRxClk or posedge RxReset ) |
begin |
if(RxReset) |
AssembledTimerValue[15:0] <= 16'h0; |
else |
if(RxStartFrm) |
AssembledTimerValue[15:0] <= 16'h0; |
else |
begin |
if(DetectionWindow & ByteCntEq16) |
AssembledTimerValue[15:8] <= RxData[7:0]; |
if(DetectionWindow & ByteCntEq17) |
AssembledTimerValue[7:0] <= RxData[7:0]; |
end |
end |
|
|
// Detection window (while PAUSE detection is possible) |
always @ (posedge MRxClk or posedge RxReset ) |
begin |
if(RxReset) |
DetectionWindow <= 1'b1; |
else |
if(ByteCntEq18) |
DetectionWindow <= 1'b0; |
else |
if(ReceiveEnd) |
DetectionWindow <= 1'b1; |
end |
|
|
|
// Latching Timer Value |
always @ (posedge MRxClk or posedge RxReset ) |
begin |
if(RxReset) |
LatchedTimerValue[15:0] <= 16'h0; |
else |
if(DetectionWindow & ReceivedPauseFrmWAddr & ByteCntEq18) |
LatchedTimerValue[15:0] <= AssembledTimerValue[15:0]; |
else |
if(ReceiveEnd) |
LatchedTimerValue[15:0] <= 16'h0; |
end |
|
|
|
// Delayed CEC counter |
always @ (posedge MRxClk or posedge RxReset) |
begin |
if(RxReset) |
DlyCrcCnt <= 3'h0; |
else |
if(RxValid & RxEndFrm) |
DlyCrcCnt <= 3'h0; |
else |
if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2]) |
DlyCrcCnt <= DlyCrcCnt + 3'd1; |
end |
|
|
assign ResetByteCnt = RxEndFrm; |
assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & |
(~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]); |
|
|
// Byte counter |
always @ (posedge MRxClk or posedge RxReset) |
begin |
if(RxReset) |
ByteCnt[4:0] <= 5'h0; |
else |
if(ResetByteCnt) |
ByteCnt[4:0] <= 5'h0; |
else |
if(IncrementByteCnt) |
ByteCnt[4:0] <= ByteCnt[4:0] + 5'd1; |
end |
|
|
assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0; |
assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1; |
assign ByteCntEq2 = RxValid & ByteCnt[4:0] == 5'h2; |
assign ByteCntEq3 = RxValid & ByteCnt[4:0] == 5'h3; |
assign ByteCntEq4 = RxValid & ByteCnt[4:0] == 5'h4; |
assign ByteCntEq5 = RxValid & ByteCnt[4:0] == 5'h5; |
assign ByteCntEq12 = RxValid & ByteCnt[4:0] == 5'h0C; |
assign ByteCntEq13 = RxValid & ByteCnt[4:0] == 5'h0D; |
assign ByteCntEq14 = RxValid & ByteCnt[4:0] == 5'h0E; |
assign ByteCntEq15 = RxValid & ByteCnt[4:0] == 5'h0F; |
assign ByteCntEq16 = RxValid & ByteCnt[4:0] == 5'h10; |
assign ByteCntEq17 = RxValid & ByteCnt[4:0] == 5'h11; |
assign ByteCntEq18 = RxValid & ByteCnt[4:0] == 5'h12 & DetectionWindow; |
|
|
assign SetPauseTimer = ReceiveEnd & ReceivedPauseFrmWAddr & ReceivedPacketGood & ReceivedLengthOK & RxFlow; |
assign DecrementPauseTimer = SlotFinished & |PauseTimer; |
|
|
// PauseTimer[15:0] |
always @ (posedge MRxClk or posedge RxReset) |
begin |
if(RxReset) |
PauseTimer[15:0] <= 16'h0; |
else |
if(SetPauseTimer) |
PauseTimer[15:0] <= LatchedTimerValue[15:0]; |
else |
if(DecrementPauseTimer) |
PauseTimer[15:0] <= PauseTimer[15:0] - 16'd1; |
end |
|
assign PauseTimerEq0 = ~(|PauseTimer[15:0]); |
|
|
|
// Synchronization of the pause timer |
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
begin |
PauseTimerEq0_sync1 <= 1'b1; |
PauseTimerEq0_sync2 <= 1'b1; |
end |
else |
begin |
PauseTimerEq0_sync1 <= PauseTimerEq0; |
PauseTimerEq0_sync2 <= PauseTimerEq0_sync1; |
end |
end |
|
|
// Pause signal generation |
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
Pause <= 1'b0; |
else |
if((TxDoneIn | TxAbortIn | ~TxUsedDataOutDetected) & ~TxStartFrmOut) |
Pause <= RxFlow & ~PauseTimerEq0_sync2; |
end |
|
|
// Divider2 is used for incrementing the Slot timer every other clock |
always @ (posedge MRxClk or posedge RxReset) |
begin |
if(RxReset) |
Divider2 <= 1'b0; |
else |
if(|PauseTimer[15:0] & RxFlow) |
Divider2 <= ~Divider2; |
else |
Divider2 <= 1'b0; |
end |
|
|
assign ResetSlotTimer = RxReset; |
assign IncrementSlotTimer = Pause & RxFlow & Divider2; |
|
|
// SlotTimer |
always @ (posedge MRxClk or posedge RxReset) |
begin |
if(RxReset) |
SlotTimer[5:0] <= 6'h0; |
else |
if(ResetSlotTimer) |
SlotTimer[5:0] <= 6'h0; |
else |
if(IncrementSlotTimer) |
SlotTimer[5:0] <= SlotTimer[5:0] + 6'd1; |
end |
|
|
assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer; // Slot is 512 bits (64 bytes) |
|
|
|
// Pause Frame received |
always @ (posedge MRxClk or posedge RxReset) |
begin |
if(RxReset) |
ReceivedPauseFrm <= 1'b0; |
else |
if(RxStatusWriteLatched_sync2 & r_PassAll | ReceivedPauseFrm & (~r_PassAll)) |
ReceivedPauseFrm <= 1'b0; |
else |
if(ByteCntEq16 & TypeLengthOK & OpCodeOK) |
ReceivedPauseFrm <= 1'b1; |
end |
|
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_register.v
0,0 → 1,108
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_register.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001, 2002 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2002/08/16 12:33:27 mohor |
// Parameter ResetValue changed to capital letters. |
// |
// Revision 1.4 2002/02/26 16:18:08 mohor |
// Reset values are passed to registers through parameters |
// |
// Revision 1.3 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.2 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// |
// |
// |
// |
// |
// |
|
`include "timescale.v" |
|
|
module eth_register(DataIn, DataOut, Write, Clk, Reset, SyncReset); |
|
parameter WIDTH = 8; // default parameter of the register width |
parameter RESET_VALUE = 0; |
|
input [WIDTH-1:0] DataIn; |
|
input Write; |
input Clk; |
input Reset; |
input SyncReset; |
|
output [WIDTH-1:0] DataOut; |
reg [WIDTH-1:0] DataOut; |
|
|
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
DataOut<= RESET_VALUE; |
else |
if(SyncReset) |
DataOut<= RESET_VALUE; |
else |
if(Write) // write |
DataOut<= DataIn; |
end |
|
|
|
endmodule // Register |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_clockgen.v
0,0 → 1,129
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_clockgen.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.2 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// Revision 1.3 2001/06/01 22:28:55 mohor |
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. |
// |
// |
|
`include "timescale.v" |
|
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc); |
|
input Clk; // Input clock (Host clock) |
input Reset; // Reset signal |
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0]) |
|
output Mdc; // Output clock |
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises. |
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls. |
|
reg Mdc; |
reg [7:0] Counter; |
|
wire CountEq0; |
wire [7:0] CounterPreset; |
wire [7:0] TempDivider; |
|
|
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2 |
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 8'b1; // We are counting half of period |
|
|
// Counter counts half period |
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
Counter[7:0] <= 8'h1; |
else |
begin |
if(CountEq0) |
begin |
Counter[7:0] <= CounterPreset[7:0]; |
end |
else |
Counter[7:0] <= Counter - 8'h1; |
end |
end |
|
|
// Mdc is asserted every other half period |
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
Mdc <= 1'b0; |
else |
begin |
if(CountEq0) |
Mdc <= ~Mdc; |
end |
end |
|
|
assign CountEq0 = Counter == 8'h0; |
assign MdcEn = CountEq0 & ~Mdc; |
assign MdcEn_n = CountEq0 & Mdc; |
|
endmodule |
|
|
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/greybox_tmp/cbx_args.txt
0,0 → 1,12
INTENDED_DEVICE_FAMILY="Cyclone IV E" |
LPM_ADDRESS_CONTROL=REGISTERED |
LPM_INDATA=REGISTERED |
LPM_OUTDATA=UNREGISTERED |
LPM_WIDTH=32 |
LPM_WIDTHAD=8 |
USE_EAB=OFF |
DEVICE_FAMILY="Cyclone IV E" |
address |
inclock |
we |
q |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/xilinx_dist_ram_16x32.v
0,0 → 1,50
module xilinx_dist_ram_16x32 |
( |
data_out, |
we, |
data_in, |
read_address, |
write_address, |
wclk |
); |
output [31:0] data_out; |
input we, wclk; |
input [31:0] data_in; |
input [3:0] write_address, read_address; |
|
wire [3:0] waddr = write_address ; |
wire [3:0] raddr = read_address ; |
|
RAM16X1D ram00 (.DPO(data_out[0]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[0]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram01 (.DPO(data_out[1]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[1]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram02 (.DPO(data_out[2]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[2]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram03 (.DPO(data_out[3]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[3]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram04 (.DPO(data_out[4]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[4]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram05 (.DPO(data_out[5]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[5]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram06 (.DPO(data_out[6]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[6]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram07 (.DPO(data_out[7]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[7]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram08 (.DPO(data_out[8]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[8]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram09 (.DPO(data_out[9]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[9]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram10 (.DPO(data_out[10]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[10]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram11 (.DPO(data_out[11]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[11]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram12 (.DPO(data_out[12]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[12]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram13 (.DPO(data_out[13]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[13]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram14 (.DPO(data_out[14]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[14]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram15 (.DPO(data_out[15]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[15]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram16 (.DPO(data_out[16]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[16]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram17 (.DPO(data_out[17]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[17]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram18 (.DPO(data_out[18]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[18]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram19 (.DPO(data_out[19]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[19]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram20 (.DPO(data_out[20]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[20]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram21 (.DPO(data_out[21]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[21]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram22 (.DPO(data_out[22]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[22]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram23 (.DPO(data_out[23]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[23]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram24 (.DPO(data_out[24]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[24]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram25 (.DPO(data_out[25]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[25]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram26 (.DPO(data_out[26]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[26]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram27 (.DPO(data_out[27]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[27]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram28 (.DPO(data_out[28]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[28]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram29 (.DPO(data_out[29]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[29]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram30 (.DPO(data_out[30]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[30]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
RAM16X1D ram31 (.DPO(data_out[31]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[31]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we)); |
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/TODO
0,0 → 1,65
////////////////////////////////////////////////////////////////////// |
//// //// |
//// TODO //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is available in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001, 2002 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/11/21 00:33:32 mohor |
// In loopback rx_clk is not looped back. Possible CRC error. Consider if usage |
// of additional logic is necessery (FIFO for looping the data). |
// |
// Revision 1.1 2002/09/10 10:42:06 mohor |
// HASH improvement needed. |
// |
|
|
- Add logic for easier use of the HASH table: First write MAC address to some |
register. Then issue a command. CRC is calculated from this MAC and appropriate |
bit written to the HASH register. |
|
- In loopback rx_clk is not looped back. Possible CRC error. Consider if usage of |
additional logic is necessery (FIFO for looping the data). |
|
- When sending frames bigger than MaxFL, MaxFL is sent, BD marked as finished, |
TxB_IRQ interrupt is set and MTxErr is set for a short period. Fix MTxErr or |
prevent sending too big frames or set TxE_IRQ instead. |
|
|
|
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_outputcontrol.v
0,0 → 1,145
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_outputcontrol.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.2 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// Revision 1.3 2001/06/01 22:28:56 mohor |
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. |
// |
// |
|
`include "timescale.v" |
|
module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn); |
|
input Clk; // Host Clock |
input Reset; // General Reset |
input WriteOp; // Write Operation Latch (When asserted, write operation is in progress) |
input NoPre; // No Preamble (no 32-bit preamble) |
input InProgress; // Operation in progress |
input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal |
input [6:0] BitCounter; // Bit Counter |
input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls. |
|
output Mdo; // MII Management Data Output |
output MdoEn; // MII Management Data Output Enable |
|
wire SerialEn; |
|
reg MdoEn_2d; |
reg MdoEn_d; |
reg MdoEn; |
|
reg Mdo_2d; |
reg Mdo_d; |
reg Mdo; // MII Management Data Output |
|
|
|
// Generation of the Serial Enable signal (enables the serialization of the data) |
assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) ) |
| ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre )); |
|
|
// Generation of the MdoEn signal |
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
begin |
MdoEn_2d <= 1'b0; |
MdoEn_d <= 1'b0; |
MdoEn <= 1'b0; |
end |
else |
begin |
if(MdcEn_n) |
begin |
MdoEn_2d <= SerialEn | InProgress & BitCounter<32; |
MdoEn_d <= MdoEn_2d; |
MdoEn <= MdoEn_d; |
end |
end |
end |
|
|
// Generation of the Mdo signal. |
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
begin |
Mdo_2d <= 1'b0; |
Mdo_d <= 1'b0; |
Mdo <= 1'b0; |
end |
else |
begin |
if(MdcEn_n) |
begin |
Mdo_2d <= ~SerialEn & BitCounter<32; |
Mdo_d <= ShiftedBit | Mdo_2d; |
Mdo <= Mdo_d; |
end |
end |
end |
|
|
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_transmitcontrol.v
0,0 → 1,324
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_transmitcontrol.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2002/11/19 17:37:32 mohor |
// When control frame (PAUSE) was sent, status was written in the |
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed. |
// Only TXC interrupt is set. |
// |
// Revision 1.4 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.3 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
// |
// Revision 1.2 2001/09/11 14:17:00 mohor |
// Few little NCSIM warnings fixed. |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// Revision 1.1 2001/07/03 12:51:54 mohor |
// Initial release of the MAC Control module. |
// |
// |
// |
// |
// |
// |
|
|
`include "timescale.v" |
|
|
module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn, |
TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn, |
TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux, |
ControlData, WillSendControlFrame, BlockTxDone |
); |
|
|
input MTxClk; |
input TxReset; |
input TxUsedDataIn; |
input TxUsedDataOut; |
input TxDoneIn; |
input TxAbortIn; |
input TxStartFrmIn; |
input TPauseRq; |
input TxUsedDataOutDetected; |
input TxFlow; |
input DlyCrcEn; |
input [15:0] TxPauseTV; |
input [47:0] MAC; |
|
output TxCtrlStartFrm; |
output TxCtrlEndFrm; |
output SendingCtrlFrm; |
output CtrlMux; |
output [7:0] ControlData; |
output WillSendControlFrame; |
output BlockTxDone; |
|
reg SendingCtrlFrm; |
reg CtrlMux; |
reg WillSendControlFrame; |
reg [3:0] DlyCrcCnt; |
reg [5:0] ByteCnt; |
reg ControlEnd_q; |
reg [7:0] MuxedCtrlData; |
reg TxCtrlStartFrm; |
reg TxCtrlStartFrm_q; |
reg TxCtrlEndFrm; |
reg [7:0] ControlData; |
reg TxUsedDataIn_q; |
reg BlockTxDone; |
|
wire IncrementDlyCrcCnt; |
wire ResetByteCnt; |
wire IncrementByteCnt; |
wire ControlEnd; |
wire IncrementByteCntBy2; |
wire EnableCnt; |
|
|
// A command for Sending the control frame is active (latched) |
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
WillSendControlFrame <= 1'b0; |
else |
if(TxCtrlEndFrm & CtrlMux) |
WillSendControlFrame <= 1'b0; |
else |
if(TPauseRq & TxFlow) |
WillSendControlFrame <= 1'b1; |
end |
|
|
// Generation of the transmit control packet start frame |
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
TxCtrlStartFrm <= 1'b0; |
else |
if(TxUsedDataIn_q & CtrlMux) |
TxCtrlStartFrm <= 1'b0; |
else |
if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected))) |
TxCtrlStartFrm <= 1'b1; |
end |
|
|
|
// Generation of the transmit control packet end frame |
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
TxCtrlEndFrm <= 1'b0; |
else |
if(ControlEnd | ControlEnd_q) |
TxCtrlEndFrm <= 1'b1; |
else |
TxCtrlEndFrm <= 1'b0; |
end |
|
|
// Generation of the multiplexer signal (controls muxes for switching between |
// normal and control packets) |
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
CtrlMux <= 1'b0; |
else |
if(WillSendControlFrame & ~TxUsedDataOut) |
CtrlMux <= 1'b1; |
else |
if(TxDoneIn) |
CtrlMux <= 1'b0; |
end |
|
|
|
// Generation of the Sending Control Frame signal (enables padding and CRC) |
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
SendingCtrlFrm <= 1'b0; |
else |
if(WillSendControlFrame & TxCtrlStartFrm) |
SendingCtrlFrm <= 1'b1; |
else |
if(TxDoneIn) |
SendingCtrlFrm <= 1'b0; |
end |
|
|
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
TxUsedDataIn_q <= 1'b0; |
else |
TxUsedDataIn_q <= TxUsedDataIn; |
end |
|
|
|
// Generation of the signal that will block sending the Done signal to the eth_wishbone module |
// While sending the control frame |
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
BlockTxDone <= 1'b0; |
else |
if(TxCtrlStartFrm) |
BlockTxDone <= 1'b1; |
else |
if(TxStartFrmIn) |
BlockTxDone <= 1'b0; |
end |
|
|
always @ (posedge MTxClk) |
begin |
ControlEnd_q <= ControlEnd; |
TxCtrlStartFrm_q <= TxCtrlStartFrm; |
end |
|
|
assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn & ~DlyCrcCnt[2]; |
|
|
// Delayed CRC counter |
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
DlyCrcCnt <= 4'h0; |
else |
if(ResetByteCnt) |
DlyCrcCnt <= 4'h0; |
else |
if(IncrementDlyCrcCnt) |
DlyCrcCnt <= DlyCrcCnt + 4'd1; |
end |
|
|
assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn)); |
assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd); |
assign IncrementByteCntBy2 = CtrlMux & TxCtrlStartFrm & (~TxCtrlStartFrm_q) & TxUsedDataIn; // When TxUsedDataIn and CtrlMux are set at the same time |
|
assign EnableCnt = (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0])); |
// Byte counter |
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
ByteCnt <= 6'h0; |
else |
if(ResetByteCnt) |
ByteCnt <= 6'h0; |
else |
if(IncrementByteCntBy2 & EnableCnt) |
ByteCnt <= (ByteCnt[5:0] ) + 6'd2; |
else |
if(IncrementByteCnt & EnableCnt) |
ByteCnt <= (ByteCnt[5:0] ) + 6'd1; |
end |
|
|
assign ControlEnd = ByteCnt[5:0] == 6'h22; |
|
|
// Control data generation (goes to the TxEthMAC module) |
always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt) |
begin |
case(ByteCnt) |
6'h0: if(~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0])) |
MuxedCtrlData[7:0] = 8'h01; // Reserved Multicast Address |
else |
MuxedCtrlData[7:0] = 8'h0; |
6'h2: MuxedCtrlData[7:0] = 8'h80; |
6'h4: MuxedCtrlData[7:0] = 8'hC2; |
6'h6: MuxedCtrlData[7:0] = 8'h00; |
6'h8: MuxedCtrlData[7:0] = 8'h00; |
6'hA: MuxedCtrlData[7:0] = 8'h01; |
6'hC: MuxedCtrlData[7:0] = MAC[47:40]; |
6'hE: MuxedCtrlData[7:0] = MAC[39:32]; |
6'h10: MuxedCtrlData[7:0] = MAC[31:24]; |
6'h12: MuxedCtrlData[7:0] = MAC[23:16]; |
6'h14: MuxedCtrlData[7:0] = MAC[15:8]; |
6'h16: MuxedCtrlData[7:0] = MAC[7:0]; |
6'h18: MuxedCtrlData[7:0] = 8'h88; // Type/Length |
6'h1A: MuxedCtrlData[7:0] = 8'h08; |
6'h1C: MuxedCtrlData[7:0] = 8'h00; // Opcode |
6'h1E: MuxedCtrlData[7:0] = 8'h01; |
6'h20: MuxedCtrlData[7:0] = TxPauseTV[15:8]; // Pause timer value |
6'h22: MuxedCtrlData[7:0] = TxPauseTV[7:0]; |
default: MuxedCtrlData[7:0] = 8'h0; |
endcase |
end |
|
|
// Latched Control data |
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
ControlData[7:0] <= 8'h0; |
else |
if(~ByteCnt[0]) |
ControlData[7:0] <= MuxedCtrlData[7:0]; |
end |
|
|
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_macstatus.v
0,0 → 1,423
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_macstatus.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is available in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001, 2002 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.16 2005/02/21 10:42:11 igorm |
// Defer indication fixed. |
// |
// Revision 1.15 2003/01/30 13:28:19 tadejm |
// Defer indication changed. |
// |
// Revision 1.14 2002/11/22 01:57:06 mohor |
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort |
// synchronized. |
// |
// Revision 1.13 2002/11/13 22:30:58 tadejm |
// Late collision is reported only when not in the full duplex. |
// Sample is taken (for status) as soon as MRxDV is not valid (regardless |
// of the received byte cnt). |
// |
// Revision 1.12 2002/09/12 14:50:16 mohor |
// CarrierSenseLost bug fixed when operating in full duplex mode. |
// |
// Revision 1.11 2002/09/04 18:38:03 mohor |
// CarrierSenseLost status is not set when working in loopback mode. |
// |
// Revision 1.10 2002/07/25 18:17:46 mohor |
// InvalidSymbol generation changed. |
// |
// Revision 1.9 2002/04/22 13:51:44 mohor |
// Short frame and ReceivedLengthOK were not detected correctly. |
// |
// Revision 1.8 2002/02/18 10:40:17 mohor |
// Small fixes. |
// |
// Revision 1.7 2002/02/15 17:07:39 mohor |
// Status was not written correctly when frames were discarted because of |
// address mismatch. |
// |
// Revision 1.6 2002/02/11 09:18:21 mohor |
// Tx status is written back to the BD. |
// |
// Revision 1.5 2002/02/08 16:21:54 mohor |
// Rx status is written back to the BD. |
// |
// Revision 1.4 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.3 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
// |
// Revision 1.2 2001/09/11 14:17:00 mohor |
// Few little NCSIM warnings fixed. |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// |
// |
// |
// |
|
`include "timescale.v" |
|
|
module eth_macstatus( |
MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError, |
MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting, |
RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, |
InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision, |
r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn, |
LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured, |
RetryLimit, LateCollision, LateCollLatched, DeferIndication, DeferLatched, RstDeferLatched, TxStartFrm, |
StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback, |
r_FullD |
); |
|
|
|
|
input MRxClk; |
input Reset; |
input RxCrcError; |
input MRxErr; |
input MRxDV; |
|
input RxStateSFD; |
input [1:0] RxStateData; |
input RxStatePreamble; |
input RxStateIdle; |
input Transmitting; |
input [15:0] RxByteCnt; |
input RxByteCntEq0; |
input RxByteCntGreat2; |
input RxByteCntMaxFrame; |
input [3:0] MRxD; |
input Collision; |
input [5:0] CollValid; |
input r_RecSmall; |
input [15:0] r_MinFL; |
input [15:0] r_MaxFL; |
input r_HugEn; |
input StartTxDone; |
input StartTxAbort; |
input [3:0] RetryCnt; |
input MTxClk; |
input MaxCollisionOccured; |
input LateCollision; |
input DeferIndication; |
input TxStartFrm; |
input StatePreamble; |
input [1:0] StateData; |
input CarrierSense; |
input TxUsedData; |
input Loopback; |
input r_FullD; |
|
|
output ReceivedLengthOK; |
output ReceiveEnd; |
output ReceivedPacketGood; |
output InvalidSymbol; |
output LatchedCrcError; |
output RxLateCollision; |
output ShortFrame; |
output DribbleNibble; |
output ReceivedPacketTooBig; |
output LoadRxStatus; |
output [3:0] RetryCntLatched; |
output RetryLimit; |
output LateCollLatched; |
output DeferLatched; |
input RstDeferLatched; |
output CarrierSenseLost; |
output LatchedMRxErr; |
|
|
reg ReceiveEnd; |
|
reg LatchedCrcError; |
reg LatchedMRxErr; |
reg LoadRxStatus; |
reg InvalidSymbol; |
reg [3:0] RetryCntLatched; |
reg RetryLimit; |
reg LateCollLatched; |
reg DeferLatched; |
reg CarrierSenseLost; |
|
wire TakeSample; |
wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps |
|
// Crc error |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LatchedCrcError <= 1'b0; |
else |
if(RxStateSFD) |
LatchedCrcError <= 1'b0; |
else |
if(RxStateData[0]) |
LatchedCrcError <= RxCrcError & ~RxByteCntEq0; |
end |
|
|
// LatchedMRxErr |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LatchedMRxErr <= 1'b0; |
else |
if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting)) |
LatchedMRxErr <= 1'b1; |
else |
LatchedMRxErr <= 1'b0; |
end |
|
|
// ReceivedPacketGood |
assign ReceivedPacketGood = ~LatchedCrcError; |
|
|
// ReceivedLengthOK |
assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0]; |
|
|
|
|
|
// Time to take a sample |
//assign TakeSample = |RxStateData & ~MRxDV & RxByteCntGreat2 | |
assign TakeSample = (|RxStateData) & (~MRxDV) | |
RxStateData[0] & MRxDV & RxByteCntMaxFrame; |
|
|
// LoadRxStatus |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LoadRxStatus <= 1'b0; |
else |
LoadRxStatus <= TakeSample; |
end |
|
|
|
// ReceiveEnd |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ReceiveEnd <= 1'b0; |
else |
ReceiveEnd <= LoadRxStatus; |
end |
|
|
// Invalid Symbol received during 100Mbps mode |
assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he; |
|
|
// InvalidSymbol |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
InvalidSymbol <= 1'b0; |
else |
if(LoadRxStatus & ~SetInvalidSymbol) |
InvalidSymbol <= 1'b0; |
else |
if(SetInvalidSymbol) |
InvalidSymbol <= 1'b1; |
end |
|
|
// Late Collision |
|
reg RxLateCollision; |
reg RxColWindow; |
// Collision Window |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxLateCollision <= 1'b0; |
else |
if(LoadRxStatus) |
RxLateCollision <= 1'b0; |
else |
if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall)) |
RxLateCollision <= 1'b1; |
end |
|
// Collision Window |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxColWindow <= 1'b1; |
else |
if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1]) |
RxColWindow <= 1'b0; |
else |
if(RxStateIdle) |
RxColWindow <= 1'b1; |
end |
|
|
// ShortFrame |
reg ShortFrame; |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ShortFrame <= 1'b0; |
else |
if(LoadRxStatus) |
ShortFrame <= 1'b0; |
else |
if(TakeSample) |
ShortFrame <= RxByteCnt[15:0] < r_MinFL[15:0]; |
end |
|
|
// DribbleNibble |
reg DribbleNibble; |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
DribbleNibble <= 1'b0; |
else |
if(RxStateSFD) |
DribbleNibble <= 1'b0; |
else |
if(~MRxDV & RxStateData[1]) |
DribbleNibble <= 1'b1; |
end |
|
|
reg ReceivedPacketTooBig; |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ReceivedPacketTooBig <= 1'b0; |
else |
if(LoadRxStatus) |
ReceivedPacketTooBig <= 1'b0; |
else |
if(TakeSample) |
ReceivedPacketTooBig <= ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0]; |
end |
|
|
|
// Latched Retry counter for tx status |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
RetryCntLatched <= 4'h0; |
else |
if(StartTxDone | StartTxAbort) |
RetryCntLatched <= RetryCnt; |
end |
|
|
// Latched Retransmission limit |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
RetryLimit <= 1'h0; |
else |
if(StartTxDone | StartTxAbort) |
RetryLimit <= MaxCollisionOccured; |
end |
|
|
// Latched Late Collision |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
LateCollLatched <= 1'b0; |
else |
if(StartTxDone | StartTxAbort) |
LateCollLatched <= LateCollision; |
end |
|
|
|
// Latched Defer state |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
DeferLatched <= 1'b0; |
else |
if(DeferIndication) |
DeferLatched <= 1'b1; |
else |
if(RstDeferLatched) |
DeferLatched <= 1'b0; |
end |
|
|
// CarrierSenseLost |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
CarrierSenseLost <= 1'b0; |
else |
if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD) |
CarrierSenseLost <= 1'b1; |
else |
if(TxStartFrm) |
CarrierSenseLost <= 1'b0; |
end |
|
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/timescale.v
0,0 → 1,50
////////////////////////////////////////////////////////////////////// |
//// //// |
//// timescale.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/10/19 11:36:31 mohor |
// Log file added. |
// |
// |
// |
|
`timescale 1ns / 1ns |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_spram_256x32.v.bak
0,0 → 1,311
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_spram_256x32.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is available in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001, 2002 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.9 2003/12/05 12:43:06 tadejm |
// Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. |
// |
// Revision 1.8 2003/12/04 14:59:13 simons |
// Lapsus fixed (!we -> ~we). |
// |
// Revision 1.7 2003/11/12 18:24:59 tadejm |
// WISHBONE slave changed and tested from only 32-bit accesss to byte access. |
// |
// Revision 1.6 2003/10/17 07:46:15 markom |
// mbist signals updated according to newest convention |
// |
// Revision 1.5 2003/08/14 16:42:58 simons |
// Artisan ram instance added. |
// |
// Revision 1.4 2002/10/18 17:04:20 tadejm |
// Changed BIST scan signals. |
// |
// Revision 1.3 2002/10/10 16:29:30 mohor |
// BIST added. |
// |
// Revision 1.2 2002/09/23 18:24:31 mohor |
// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). |
// |
// Revision 1.1 2002/07/23 16:36:09 mohor |
// ethernet spram added. So far a generic ram and xilinx RAMB4 are used. |
// |
// |
// |
|
`include "ethmac_defines.v" |
`include "timescale.v" |
|
module eth_spram_256x32( |
// Generic synchronous single-port RAM interface |
clk, rst, ce, we, oe, addr, di, dato |
|
`ifdef ETH_BIST |
, |
// debug chain signals |
mbist_si_i, // bist scan serial in |
mbist_so_o, // bist scan serial out |
mbist_ctrl_i // bist chain shift control |
`endif |
|
|
|
); |
|
// |
// Generic synchronous single-port RAM interface |
// |
input clk; // Clock, rising edge |
input rst; // Reset, active high |
input ce; // Chip enable input, active high |
input [3:0] we; // Write enable input, active high |
input oe; // Output enable input, active high |
input [7:0] addr; // address bus inputs |
input [31:0] di; // input data bus |
output [31:0] dato; // output data bus |
|
`ifdef ETH_BIST |
input mbist_si_i; // bist scan serial in |
output mbist_so_o; // bist scan serial out |
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control |
`endif |
|
`ifdef ETH_XILINX_RAMB4 |
|
/*RAMB4_S16 ram0 |
( |
.DO (do[15:0]), |
.ADDR (addr), |
.DI (di[15:0]), |
.EN (ce), |
.CLK (clk), |
.WE (we), |
.RST (rst) |
); |
|
RAMB4_S16 ram1 |
( |
.DO (do[31:16]), |
.ADDR (addr), |
.DI (di[31:16]), |
.EN (ce), |
.CLK (clk), |
.WE (we), |
.RST (rst) |
);*/ |
|
RAMB4_S8 ram0 |
( |
.DO (dato[7:0]), |
.ADDR ({1'b0, addr}), |
.DI (di[7:0]), |
.EN (ce), |
.CLK (clk), |
.WE (we[0]), |
.RST (rst) |
); |
|
RAMB4_S8 ram1 |
( |
.DO (dato[15:8]), |
.ADDR ({1'b0, addr}), |
.DI (di[15:8]), |
.EN (ce), |
.CLK (clk), |
.WE (we[1]), |
.RST (rst) |
); |
|
RAMB4_S8 ram2 |
( |
.DO (dato[23:16]), |
.ADDR ({1'b0, addr}), |
.DI (di[23:16]), |
.EN (ce), |
.CLK (clk), |
.WE (we[2]), |
.RST (rst) |
); |
|
RAMB4_S8 ram3 |
( |
.DO (dato[31:24]), |
.ADDR ({1'b0, addr}), |
.DI (di[31:24]), |
.EN (ce), |
.CLK (clk), |
.WE (we[3]), |
.RST (rst) |
); |
|
`else // !ETH_XILINX_RAMB4 |
`ifdef ETH_VIRTUAL_SILICON_RAM |
`ifdef ETH_BIST |
//vs_hdsp_256x32_bist ram0_bist |
vs_hdsp_256x32_bw_bist ram0_bist |
`else |
//vs_hdsp_256x32 ram0 |
vs_hdsp_256x32_bw ram0 |
`endif |
( |
.CK (clk), |
.CEN (!ce), |
.WEN (~we), |
.OEN (!oe), |
.ADR (addr), |
.DI (di), |
.DOUT (dato) |
|
`ifdef ETH_BIST |
, |
// debug chain signals |
.mbist_si_i (mbist_si_i), |
.mbist_so_o (mbist_so_o), |
.mbist_ctrl_i (mbist_ctrl_i) |
`endif |
); |
|
`else // !ETH_VIRTUAL_SILICON_RAM |
|
`ifdef ETH_ARTISAN_RAM |
`ifdef ETH_BIST |
//art_hssp_256x32_bist ram0_bist |
art_hssp_256x32_bw_bist ram0_bist |
`else |
//art_hssp_256x32 ram0 |
art_hssp_256x32_bw ram0 |
`endif |
( |
.CLK (clk), |
.CEN (!ce), |
.WEN (~we), |
.OEN (!oe), |
.A (addr), |
.D (di), |
.Q (dato) |
|
`ifdef ETH_BIST |
, |
// debug chain signals |
.mbist_si_i (mbist_si_i), |
.mbist_so_o (mbist_so_o), |
.mbist_ctrl_i (mbist_ctrl_i) |
`endif |
); |
|
`else // !ETH_ARTISAN_RAM |
`ifdef ETH_ALTERA_ALTSYNCRAM |
|
altera_spram_256x32 altera_spram_256x32_inst |
( |
.address (addr), |
.wren (ce & we), |
.clock (clk), |
.data (di), |
.q (dato) |
); //exemplar attribute altera_spram_256x32_inst NOOPT TRUE |
|
`else // !ETH_ALTERA_ALTSYNCRAM |
|
|
// |
// Generic single-port synchronous RAM model |
// |
|
// |
// Generic RAM's registers and wires |
// |
reg [ 7: 0] mem0 [255:0]; // RAM content |
reg [15: 8] mem1 [255:0]; // RAM content |
reg [23:16] mem2 [255:0]; // RAM content |
reg [31:24] mem3 [255:0]; // RAM content |
wire [31:0] q; // RAM output |
reg [7:0] raddr; // RAM read address |
// |
// Data output drivers |
// |
assign dato = (oe & ce) ? q : {32{1'bz}}; |
|
// |
// RAM read and write |
// |
|
// read operation |
always@(posedge clk) |
if (ce) |
raddr <= addr; // read address needs to be registered to read clock |
|
assign q = rst ? {32{1'b0}} : {mem3[raddr], |
mem2[raddr], |
mem1[raddr], |
mem0[raddr]}; |
|
// write operation |
always@(posedge clk) |
begin |
if (ce && we[3]) |
mem3[addr] <= di[31:24]; |
if (ce && we[2]) |
mem2[addr] <= di[23:16]; |
if (ce && we[1]) |
mem1[addr] <= di[15: 8]; |
if (ce && we[0]) |
mem0[addr] <= di[ 7: 0]; |
end |
|
// Task prints range of memory |
// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations. |
task print_ram; |
input [7:0] start; |
input [7:0] finish; |
integer rnum; |
begin |
for (rnum={24'd0,start};rnum<={24'd0,finish};rnum=rnum+1) |
$display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]); |
end |
endtask |
|
`endif // !ETH_ALTERA_ALTSYNCRAM |
`endif // !ETH_ARTISAN_RAM |
`endif // !ETH_VIRTUAL_SILICON_RAM |
`endif // !ETH_XILINX_RAMB4 |
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_rxstatem.v
0,0 → 1,193
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_rxstatem.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// - Novan Hartadi (novan@vlsi.itb.ac.id) //// |
//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.4 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
// |
// Revision 1.3 2001/10/18 12:07:11 mohor |
// Status signals changed, Adress decoding changed, interrupt controller |
// added. |
// |
// Revision 1.2 2001/09/11 14:17:00 mohor |
// Few little NCSIM warnings fixed. |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// Revision 1.2 2001/07/03 12:55:41 mohor |
// Minor changes because of the synthesys warnings. |
// |
// |
// Revision 1.1 2001/06/27 21:26:19 mohor |
// Initial release of the RxEthMAC module. |
// |
// |
// |
// |
|
|
`include "timescale.v" |
|
|
module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD, |
IFGCounterEq24, ByteCntMaxFrame, StateData, StateIdle, StatePreamble, StateSFD, |
StateDrop |
); |
|
input MRxClk; |
input Reset; |
input MRxDV; |
input ByteCntEq0; |
input ByteCntGreat2; |
input MRxDEq5; |
input Transmitting; |
input MRxDEqD; |
input IFGCounterEq24; |
input ByteCntMaxFrame; |
|
output [1:0] StateData; |
output StateIdle; |
output StateDrop; |
output StatePreamble; |
output StateSFD; |
|
reg StateData0; |
reg StateData1; |
reg StateIdle; |
reg StateDrop; |
reg StatePreamble; |
reg StateSFD; |
|
wire StartIdle; |
wire StartDrop; |
wire StartData0; |
wire StartData1; |
wire StartPreamble; |
wire StartSFD; |
|
|
// Defining the next state |
assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | (|StateData)); |
|
assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting); |
|
assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting | StatePreamble); |
|
assign StartData0 = MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1); |
|
assign StartData1 = MRxDV & StateData0 & (~ByteCntMaxFrame); |
|
assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 & |
MRxDEqD | StateData0 & ByteCntMaxFrame); |
|
// Rx State Machine |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
begin |
StateIdle <= 1'b0; |
StateDrop <= 1'b1; |
StatePreamble <= 1'b0; |
StateSFD <= 1'b0; |
StateData0 <= 1'b0; |
StateData1 <= 1'b0; |
end |
else |
begin |
if(StartPreamble | StartSFD | StartDrop) |
StateIdle <= 1'b0; |
else |
if(StartIdle) |
StateIdle <= 1'b1; |
|
if(StartIdle) |
StateDrop <= 1'b0; |
else |
if(StartDrop) |
StateDrop <= 1'b1; |
|
if(StartSFD | StartIdle | StartDrop) |
StatePreamble <= 1'b0; |
else |
if(StartPreamble) |
StatePreamble <= 1'b1; |
|
if(StartPreamble | StartIdle | StartData0 | StartDrop) |
StateSFD <= 1'b0; |
else |
if(StartSFD) |
StateSFD <= 1'b1; |
|
if(StartIdle | StartData1 | StartDrop) |
StateData0 <= 1'b0; |
else |
if(StartData0) |
StateData0 <= 1'b1; |
|
if(StartIdle | StartData0 | StartDrop) |
StateData1 <= 1'b0; |
else |
if(StartData1) |
StateData1 <= 1'b1; |
end |
end |
|
assign StateData[1:0] = {StateData1, StateData0}; |
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/README.txt
0,0 → 1,101
////////////////////////////////////////////////////////////////////// |
//// //// |
//// README.txt //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// - Olof Kindgren (olof@opencores.org) //// |
//// //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001, 2002 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// |
// |
// |
|
RUNNING the simulation/Testbench in Icarus Verilog: |
|
Go to the scripts directory and write "make rtl-tests" |
All logs will be saved in the log directory |
|
To activate VCD dumps, run with "make rtl-tests VCD=1". The VCD is saved |
in build/sim/ethmac.vcd |
|
|
RUNNING the simulation/Testbench in ModelSIM: |
|
Open ModelSIM project: ethernet/sim/rtl_sim/modelsim_sim/bin/ethernet.mpf |
Run the macro do.do (write "do do.do" in the command window). |
Simulation will be automatically started. Logs are stored in the /log |
directory. tb_ethernet test is performed. |
|
|
|
RUNNING the simulation/Testbench in Ncsim: |
|
Go to the ethernet\sim\rtl_sim\ncsim_sim\run directory. Run the |
run_eth_sim_regr.scr script. Simulation is automatically started. Logs are |
stored in the /log directory. Before running the script for another time, |
run the clean script that deletes files from previous runs. tb_ethernet test |
is performed. |
|
|
|
|
|
|
Why are eth_cop.v, eth_host.v, eth_memory, tb_cop.v and tb_ethernet_with_cop.v |
files used for? |
|
Although the testbench does not include the traffic coprocessor, the |
coprocessor is part of the ethernet environment. eth_cop multiplexes |
two wishbone interface between 4 modules: |
- First wishbone master interface is connected to the HOST (eth_host) |
- Second wishbone master interface is connected to the Ethernet Core (for |
accessing data in the memory (eth_memory)). |
- First wishbone slave interface is connected to the Ethernet Core (for |
accessing registers and buffer descriptors). |
- Second wishbone slave interface is connected to the memory (eth_memory) |
so host can write data to the memory (or read data from the memory. |
|
tb_cop.c is a testbench just for the traffic coprocessor (eth_cop). |
tb_ethernet_with_cop.v is a simple testbench where all above mentioned |
modules are connected into a single environment. Few packets are transmitted |
and received. The "main" testbench is tb_ethernet.v file. It performs several |
tests (eth_cop is not part of the simulation environment). |
|
|
|
|
|
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_registers.v
0,0 → 1,1184
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_registers.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001, 2002 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.28 2004/04/26 15:26:23 igorm |
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the |
// previous update of the core. |
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register. |
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER |
// register. (thanks to Mathias and Torbjorn) |
// - Multicast reception was fixed. Thanks to Ulrich Gries |
// |
// Revision 1.27 2004/04/26 11:42:17 igorm |
// TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. |
// |
// Revision 1.26 2003/11/12 18:24:59 tadejm |
// WISHBONE slave changed and tested from only 32-bit accesss to byte access. |
// |
// Revision 1.25 2003/04/18 16:26:25 mohor |
// RxBDAddress was updated also when value to r_TxBDNum was written with |
// greater value than allowed. |
// |
// Revision 1.24 2002/11/22 01:57:06 mohor |
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort |
// synchronized. |
// |
// Revision 1.23 2002/11/19 18:13:49 mohor |
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. |
// |
// Revision 1.22 2002/11/14 18:37:20 mohor |
// r_Rst signal does not reset any module any more and is removed from the design. |
// |
// Revision 1.21 2002/09/10 10:35:23 mohor |
// Ethernet debug registers removed. |
// |
// Revision 1.20 2002/09/04 18:40:25 mohor |
// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to |
// the control frames connected. |
// |
// Revision 1.19 2002/08/19 16:01:40 mohor |
// Only values smaller or equal to 0x80 can be written to TX_BD_NUM register. |
// r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut. |
// |
// Revision 1.18 2002/08/16 22:28:23 mohor |
// Syntax error fixed. |
// |
// Revision 1.17 2002/08/16 22:23:03 mohor |
// Syntax error fixed. |
// |
// Revision 1.16 2002/08/16 22:14:22 mohor |
// Synchronous reset added to all registers. Defines used for width. r_MiiMRst |
// changed from bit position 10 to 9. |
// |
// Revision 1.15 2002/08/14 18:26:37 mohor |
// LinkFailRegister is reflecting the status of the PHY's link fail status bit. |
// |
// Revision 1.14 2002/04/22 14:03:44 mohor |
// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled |
// or not. |
// |
// Revision 1.13 2002/02/26 16:18:09 mohor |
// Reset values are passed to registers through parameters |
// |
// Revision 1.12 2002/02/17 13:23:42 mohor |
// Define missmatch fixed. |
// |
// Revision 1.11 2002/02/16 14:03:44 mohor |
// Registered trimmed. Unused registers removed. |
// |
// Revision 1.10 2002/02/15 11:08:25 mohor |
// File format fixed a bit. |
// |
// Revision 1.9 2002/02/14 20:19:41 billditt |
// Modified for Address Checking, |
// addition of eth_addrcheck.v |
// |
// Revision 1.8 2002/02/12 17:01:19 mohor |
// HASH0 and HASH1 registers added. |
|
// Revision 1.7 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.6 2001/12/05 15:00:16 mohor |
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors |
// instead of the number of RX descriptors). |
// |
// Revision 1.5 2001/12/05 10:22:19 mohor |
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. |
// |
// Revision 1.4 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
// |
// Revision 1.3 2001/10/18 12:07:11 mohor |
// Status signals changed, Adress decoding changed, interrupt controller |
// added. |
// |
// Revision 1.2 2001/09/24 15:02:56 mohor |
// Defines changed (All precede with ETH_). Small changes because some |
// tools generate warnings when two operands are together. Synchronization |
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC |
// demands). |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.2 2001/08/02 09:25:31 mohor |
// Unconnected signals are now connected. |
// |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// |
// |
// |
// |
// |
|
`include "ethmac_defines.v" |
`include "timescale.v" |
|
|
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut, |
r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn, |
r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG, |
r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn, |
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, |
r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet, |
r_CollValid, r_TxFlow, r_RxFlow, r_PassAll, |
r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat, |
r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat, |
LinkFail, r_MAC, WCtrlDataStart, RStatStart, |
UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o, |
r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm, |
dbg_dat, |
StartTxDone, TxClk, RxClk, SetPauseTimer |
); |
|
input [31:0] DataIn; |
input [7:0] Address; |
|
input Rw; |
input [3:0] Cs; |
input Clk; |
input Reset; |
|
input WCtrlDataStart; |
input RStatStart; |
|
input UpdateMIIRX_DATAReg; |
input [15:0] Prsd; |
|
output [31:0] DataOut; |
reg [31:0] DataOut; |
|
output r_RecSmall; |
output r_Pad; |
output r_HugEn; |
output r_CrcEn; |
output r_DlyCrcEn; |
output r_FullD; |
output r_ExDfrEn; |
output r_NoBckof; |
output r_LoopBck; |
output r_IFG; |
output r_Pro; |
output r_Iam; |
output r_Bro; |
output r_NoPre; |
output r_TxEn; |
output r_RxEn; |
output [31:0] r_HASH0; |
output [31:0] r_HASH1; |
|
input TxB_IRQ; |
input TxE_IRQ; |
input RxB_IRQ; |
input RxE_IRQ; |
input Busy_IRQ; |
|
output [6:0] r_IPGT; |
|
output [6:0] r_IPGR1; |
|
output [6:0] r_IPGR2; |
|
output [15:0] r_MinFL; |
output [15:0] r_MaxFL; |
|
output [3:0] r_MaxRet; |
output [5:0] r_CollValid; |
|
output r_TxFlow; |
output r_RxFlow; |
output r_PassAll; |
|
output r_MiiNoPre; |
output [7:0] r_ClkDiv; |
|
output r_WCtrlData; |
output r_RStat; |
output r_ScanStat; |
|
output [4:0] r_RGAD; |
output [4:0] r_FIAD; |
|
output [15:0]r_CtrlData; |
|
|
input NValid_stat; |
input Busy_stat; |
input LinkFail; |
|
output [47:0]r_MAC; |
output [7:0] r_TxBDNum; |
output int_o; |
output [15:0]r_TxPauseTV; |
output r_TxPauseRq; |
input RstTxPauseRq; |
input TxCtrlEndFrm; |
input StartTxDone; |
input TxClk; |
input RxClk; |
input SetPauseTimer; |
|
input [31:0] dbg_dat; // debug data input |
|
reg irq_txb; |
reg irq_txe; |
reg irq_rxb; |
reg irq_rxe; |
reg irq_busy; |
reg irq_txc; |
reg irq_rxc; |
|
reg SetTxCIrq_txclk; |
reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3; |
reg SetTxCIrq; |
reg ResetTxCIrq_sync1, ResetTxCIrq_sync2; |
|
reg SetRxCIrq_rxclk; |
reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3; |
reg SetRxCIrq; |
reg ResetRxCIrq_sync1; |
reg ResetRxCIrq_sync2; |
reg ResetRxCIrq_sync3; |
|
wire [3:0] Write = Cs & {4{Rw}}; |
wire Read = (|Cs) & ~Rw; |
|
wire MODER_Sel = (Address == `ETH_MODER_ADR ); |
wire INT_SOURCE_Sel = (Address == `ETH_INT_SOURCE_ADR ); |
wire INT_MASK_Sel = (Address == `ETH_INT_MASK_ADR ); |
wire IPGT_Sel = (Address == `ETH_IPGT_ADR ); |
wire IPGR1_Sel = (Address == `ETH_IPGR1_ADR ); |
wire IPGR2_Sel = (Address == `ETH_IPGR2_ADR ); |
wire PACKETLEN_Sel = (Address == `ETH_PACKETLEN_ADR ); |
wire COLLCONF_Sel = (Address == `ETH_COLLCONF_ADR ); |
|
wire CTRLMODER_Sel = (Address == `ETH_CTRLMODER_ADR ); |
wire MIIMODER_Sel = (Address == `ETH_MIIMODER_ADR ); |
wire MIICOMMAND_Sel = (Address == `ETH_MIICOMMAND_ADR ); |
wire MIIADDRESS_Sel = (Address == `ETH_MIIADDRESS_ADR ); |
wire MIITX_DATA_Sel = (Address == `ETH_MIITX_DATA_ADR ); |
wire MAC_ADDR0_Sel = (Address == `ETH_MAC_ADDR0_ADR ); |
wire MAC_ADDR1_Sel = (Address == `ETH_MAC_ADDR1_ADR ); |
wire HASH0_Sel = (Address == `ETH_HASH0_ADR ); |
wire HASH1_Sel = (Address == `ETH_HASH1_ADR ); |
wire TXCTRL_Sel = (Address == `ETH_TX_CTRL_ADR ); |
wire RXCTRL_Sel = (Address == `ETH_RX_CTRL_ADR ); |
wire DBG_REG_Sel = (Address == `ETH_DBG_ADR ); |
wire TX_BD_NUM_Sel = (Address == `ETH_TX_BD_NUM_ADR ); |
|
|
wire [2:0] MODER_Wr; |
wire [0:0] INT_SOURCE_Wr; |
wire [0:0] INT_MASK_Wr; |
wire [0:0] IPGT_Wr; |
wire [0:0] IPGR1_Wr; |
wire [0:0] IPGR2_Wr; |
wire [3:0] PACKETLEN_Wr; |
wire [2:0] COLLCONF_Wr; |
wire [0:0] CTRLMODER_Wr; |
wire [1:0] MIIMODER_Wr; |
wire [0:0] MIICOMMAND_Wr; |
wire [1:0] MIIADDRESS_Wr; |
wire [1:0] MIITX_DATA_Wr; |
wire MIIRX_DATA_Wr; |
wire [3:0] MAC_ADDR0_Wr; |
wire [1:0] MAC_ADDR1_Wr; |
wire [3:0] HASH0_Wr; |
wire [3:0] HASH1_Wr; |
wire [2:0] TXCTRL_Wr; |
wire [0:0] TX_BD_NUM_Wr; |
|
assign MODER_Wr[0] = Write[0] & MODER_Sel; |
assign MODER_Wr[1] = Write[1] & MODER_Sel; |
assign MODER_Wr[2] = Write[2] & MODER_Sel; |
assign INT_SOURCE_Wr[0] = Write[0] & INT_SOURCE_Sel; |
assign INT_MASK_Wr[0] = Write[0] & INT_MASK_Sel; |
assign IPGT_Wr[0] = Write[0] & IPGT_Sel; |
assign IPGR1_Wr[0] = Write[0] & IPGR1_Sel; |
assign IPGR2_Wr[0] = Write[0] & IPGR2_Sel; |
assign PACKETLEN_Wr[0] = Write[0] & PACKETLEN_Sel; |
assign PACKETLEN_Wr[1] = Write[1] & PACKETLEN_Sel; |
assign PACKETLEN_Wr[2] = Write[2] & PACKETLEN_Sel; |
assign PACKETLEN_Wr[3] = Write[3] & PACKETLEN_Sel; |
assign COLLCONF_Wr[0] = Write[0] & COLLCONF_Sel; |
assign COLLCONF_Wr[1] = 1'b0; // Not used |
assign COLLCONF_Wr[2] = Write[2] & COLLCONF_Sel; |
|
assign CTRLMODER_Wr[0] = Write[0] & CTRLMODER_Sel; |
assign MIIMODER_Wr[0] = Write[0] & MIIMODER_Sel; |
assign MIIMODER_Wr[1] = Write[1] & MIIMODER_Sel; |
assign MIICOMMAND_Wr[0] = Write[0] & MIICOMMAND_Sel; |
assign MIIADDRESS_Wr[0] = Write[0] & MIIADDRESS_Sel; |
assign MIIADDRESS_Wr[1] = Write[1] & MIIADDRESS_Sel; |
assign MIITX_DATA_Wr[0] = Write[0] & MIITX_DATA_Sel; |
assign MIITX_DATA_Wr[1] = Write[1] & MIITX_DATA_Sel; |
assign MIIRX_DATA_Wr = UpdateMIIRX_DATAReg; |
assign MAC_ADDR0_Wr[0] = Write[0] & MAC_ADDR0_Sel; |
assign MAC_ADDR0_Wr[1] = Write[1] & MAC_ADDR0_Sel; |
assign MAC_ADDR0_Wr[2] = Write[2] & MAC_ADDR0_Sel; |
assign MAC_ADDR0_Wr[3] = Write[3] & MAC_ADDR0_Sel; |
assign MAC_ADDR1_Wr[0] = Write[0] & MAC_ADDR1_Sel; |
assign MAC_ADDR1_Wr[1] = Write[1] & MAC_ADDR1_Sel; |
assign HASH0_Wr[0] = Write[0] & HASH0_Sel; |
assign HASH0_Wr[1] = Write[1] & HASH0_Sel; |
assign HASH0_Wr[2] = Write[2] & HASH0_Sel; |
assign HASH0_Wr[3] = Write[3] & HASH0_Sel; |
assign HASH1_Wr[0] = Write[0] & HASH1_Sel; |
assign HASH1_Wr[1] = Write[1] & HASH1_Sel; |
assign HASH1_Wr[2] = Write[2] & HASH1_Sel; |
assign HASH1_Wr[3] = Write[3] & HASH1_Sel; |
assign TXCTRL_Wr[0] = Write[0] & TXCTRL_Sel; |
assign TXCTRL_Wr[1] = Write[1] & TXCTRL_Sel; |
assign TXCTRL_Wr[2] = Write[2] & TXCTRL_Sel; |
assign TX_BD_NUM_Wr[0] = Write[0] & TX_BD_NUM_Sel & (DataIn<='h80); |
|
|
|
wire [31:0] MODEROut; |
wire [31:0] INT_SOURCEOut; |
wire [31:0] INT_MASKOut; |
wire [31:0] IPGTOut; |
wire [31:0] IPGR1Out; |
wire [31:0] IPGR2Out; |
wire [31:0] PACKETLENOut; |
wire [31:0] COLLCONFOut; |
wire [31:0] CTRLMODEROut; |
wire [31:0] MIIMODEROut; |
wire [31:0] MIICOMMANDOut; |
wire [31:0] MIIADDRESSOut; |
wire [31:0] MIITX_DATAOut; |
wire [31:0] MIIRX_DATAOut; |
wire [31:0] MIISTATUSOut; |
wire [31:0] MAC_ADDR0Out; |
wire [31:0] MAC_ADDR1Out; |
wire [31:0] TX_BD_NUMOut; |
wire [31:0] HASH0Out; |
wire [31:0] HASH1Out; |
wire [31:0] TXCTRLOut; |
wire [31:0] DBGOut; |
|
// MODER Register |
eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0) MODER_0 |
( |
.DataIn (DataIn[`ETH_MODER_WIDTH_0 - 1:0]), |
.DataOut (MODEROut[`ETH_MODER_WIDTH_0 - 1:0]), |
.Write (MODER_Wr[0]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_MODER_WIDTH_1, `ETH_MODER_DEF_1) MODER_1 |
( |
.DataIn (DataIn[`ETH_MODER_WIDTH_1 + 7:8]), |
.DataOut (MODEROut[`ETH_MODER_WIDTH_1 + 7:8]), |
.Write (MODER_Wr[1]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_MODER_WIDTH_2, `ETH_MODER_DEF_2) MODER_2 |
( |
.DataIn (DataIn[`ETH_MODER_WIDTH_2 + 15:16]), |
.DataOut (MODEROut[`ETH_MODER_WIDTH_2 + 15:16]), |
.Write (MODER_Wr[2]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
assign MODEROut[31:`ETH_MODER_WIDTH_2 + 16] = 0; |
|
// INT_MASK Register |
eth_register #(`ETH_INT_MASK_WIDTH_0, `ETH_INT_MASK_DEF_0) INT_MASK_0 |
( |
.DataIn (DataIn[`ETH_INT_MASK_WIDTH_0 - 1:0]), |
.DataOut (INT_MASKOut[`ETH_INT_MASK_WIDTH_0 - 1:0]), |
.Write (INT_MASK_Wr[0]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH_0] = 0; |
|
// IPGT Register |
eth_register #(`ETH_IPGT_WIDTH_0, `ETH_IPGT_DEF_0) IPGT_0 |
( |
.DataIn (DataIn[`ETH_IPGT_WIDTH_0 - 1:0]), |
.DataOut (IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0]), |
.Write (IPGT_Wr[0]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
assign IPGTOut[31:`ETH_IPGT_WIDTH_0] = 0; |
|
// IPGR1 Register |
eth_register #(`ETH_IPGR1_WIDTH_0, `ETH_IPGR1_DEF_0) IPGR1_0 |
( |
.DataIn (DataIn[`ETH_IPGR1_WIDTH_0 - 1:0]), |
.DataOut (IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0]), |
.Write (IPGR1_Wr[0]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
assign IPGR1Out[31:`ETH_IPGR1_WIDTH_0] = 0; |
|
// IPGR2 Register |
eth_register #(`ETH_IPGR2_WIDTH_0, `ETH_IPGR2_DEF_0) IPGR2_0 |
( |
.DataIn (DataIn[`ETH_IPGR2_WIDTH_0 - 1:0]), |
.DataOut (IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0]), |
.Write (IPGR2_Wr[0]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
assign IPGR2Out[31:`ETH_IPGR2_WIDTH_0] = 0; |
|
// PACKETLEN Register |
eth_register #(`ETH_PACKETLEN_WIDTH_0, `ETH_PACKETLEN_DEF_0) PACKETLEN_0 |
( |
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_0 - 1:0]), |
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_0 - 1:0]), |
.Write (PACKETLEN_Wr[0]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_PACKETLEN_WIDTH_1, `ETH_PACKETLEN_DEF_1) PACKETLEN_1 |
( |
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_1 + 7:8]), |
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_1 + 7:8]), |
.Write (PACKETLEN_Wr[1]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_PACKETLEN_WIDTH_2, `ETH_PACKETLEN_DEF_2) PACKETLEN_2 |
( |
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_2 + 15:16]), |
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_2 + 15:16]), |
.Write (PACKETLEN_Wr[2]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_PACKETLEN_WIDTH_3, `ETH_PACKETLEN_DEF_3) PACKETLEN_3 |
( |
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_3 + 23:24]), |
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_3 + 23:24]), |
.Write (PACKETLEN_Wr[3]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
|
// COLLCONF Register |
eth_register #(`ETH_COLLCONF_WIDTH_0, `ETH_COLLCONF_DEF_0) COLLCONF_0 |
( |
.DataIn (DataIn[`ETH_COLLCONF_WIDTH_0 - 1:0]), |
.DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0]), |
.Write (COLLCONF_Wr[0]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_COLLCONF_WIDTH_2, `ETH_COLLCONF_DEF_2) COLLCONF_2 |
( |
.DataIn (DataIn[`ETH_COLLCONF_WIDTH_2 + 15:16]), |
.DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16]), |
.Write (COLLCONF_Wr[2]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
assign COLLCONFOut[15:`ETH_COLLCONF_WIDTH_0] = 0; |
assign COLLCONFOut[31:`ETH_COLLCONF_WIDTH_2 + 16] = 0; |
|
// TX_BD_NUM Register |
eth_register #(`ETH_TX_BD_NUM_WIDTH_0, `ETH_TX_BD_NUM_DEF_0) TX_BD_NUM_0 |
( |
.DataIn (DataIn[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]), |
.DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]), |
.Write (TX_BD_NUM_Wr[0]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH_0] = 0; |
|
// CTRLMODER Register |
eth_register #(`ETH_CTRLMODER_WIDTH_0, `ETH_CTRLMODER_DEF_0) CTRLMODER_0 |
( |
.DataIn (DataIn[`ETH_CTRLMODER_WIDTH_0 - 1:0]), |
.DataOut (CTRLMODEROut[`ETH_CTRLMODER_WIDTH_0 - 1:0]), |
.Write (CTRLMODER_Wr[0]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH_0] = 0; |
|
// MIIMODER Register |
eth_register #(`ETH_MIIMODER_WIDTH_0, `ETH_MIIMODER_DEF_0) MIIMODER_0 |
( |
.DataIn (DataIn[`ETH_MIIMODER_WIDTH_0 - 1:0]), |
.DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_0 - 1:0]), |
.Write (MIIMODER_Wr[0]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_MIIMODER_WIDTH_1, `ETH_MIIMODER_DEF_1) MIIMODER_1 |
( |
.DataIn (DataIn[`ETH_MIIMODER_WIDTH_1 + 7:8]), |
.DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_1 + 7:8]), |
.Write (MIIMODER_Wr[1]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH_1 + 8] = 0; |
|
// MIICOMMAND Register |
eth_register #(1, 0) MIICOMMAND0 |
( |
.DataIn (DataIn[0]), |
.DataOut (MIICOMMANDOut[0]), |
.Write (MIICOMMAND_Wr[0]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(1, 0) MIICOMMAND1 |
( |
.DataIn (DataIn[1]), |
.DataOut (MIICOMMANDOut[1]), |
.Write (MIICOMMAND_Wr[0]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (RStatStart) |
); |
eth_register #(1, 0) MIICOMMAND2 |
( |
.DataIn (DataIn[2]), |
.DataOut (MIICOMMANDOut[2]), |
.Write (MIICOMMAND_Wr[0]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (WCtrlDataStart) |
); |
assign MIICOMMANDOut[31:`ETH_MIICOMMAND_WIDTH_0] = 29'h0; |
|
// MIIADDRESSRegister |
eth_register #(`ETH_MIIADDRESS_WIDTH_0, `ETH_MIIADDRESS_DEF_0) MIIADDRESS_0 |
( |
.DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_0 - 1:0]), |
.DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_0 - 1:0]), |
.Write (MIIADDRESS_Wr[0]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_MIIADDRESS_WIDTH_1, `ETH_MIIADDRESS_DEF_1) MIIADDRESS_1 |
( |
.DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_1 + 7:8]), |
.DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_1 + 7:8]), |
.Write (MIIADDRESS_Wr[1]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
assign MIIADDRESSOut[7:`ETH_MIIADDRESS_WIDTH_0] = 0; |
assign MIIADDRESSOut[31:`ETH_MIIADDRESS_WIDTH_1 + 8] = 0; |
|
// MIITX_DATA Register |
eth_register #(`ETH_MIITX_DATA_WIDTH_0, `ETH_MIITX_DATA_DEF_0) MIITX_DATA_0 |
( |
.DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_0 - 1:0]), |
.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_0 - 1:0]), |
.Write (MIITX_DATA_Wr[0]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_MIITX_DATA_WIDTH_1, `ETH_MIITX_DATA_DEF_1) MIITX_DATA_1 |
( |
.DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_1 + 7:8]), |
.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_1 + 7:8]), |
.Write (MIITX_DATA_Wr[1]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH_1 + 8] = 0; |
|
// MIIRX_DATA Register |
eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA |
( |
.DataIn (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]), |
.DataOut (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]), |
.Write (MIIRX_DATA_Wr), // not written from WB |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0; |
|
// MAC_ADDR0 Register |
eth_register #(`ETH_MAC_ADDR0_WIDTH_0, `ETH_MAC_ADDR0_DEF_0) MAC_ADDR0_0 |
( |
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]), |
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]), |
.Write (MAC_ADDR0_Wr[0]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_MAC_ADDR0_WIDTH_1, `ETH_MAC_ADDR0_DEF_1) MAC_ADDR0_1 |
( |
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]), |
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]), |
.Write (MAC_ADDR0_Wr[1]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_MAC_ADDR0_WIDTH_2, `ETH_MAC_ADDR0_DEF_2) MAC_ADDR0_2 |
( |
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]), |
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]), |
.Write (MAC_ADDR0_Wr[2]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_MAC_ADDR0_WIDTH_3, `ETH_MAC_ADDR0_DEF_3) MAC_ADDR0_3 |
( |
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]), |
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]), |
.Write (MAC_ADDR0_Wr[3]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
|
// MAC_ADDR1 Register |
eth_register #(`ETH_MAC_ADDR1_WIDTH_0, `ETH_MAC_ADDR1_DEF_0) MAC_ADDR1_0 |
( |
.DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]), |
.DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]), |
.Write (MAC_ADDR1_Wr[0]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_MAC_ADDR1_WIDTH_1, `ETH_MAC_ADDR1_DEF_1) MAC_ADDR1_1 |
( |
.DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]), |
.DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]), |
.Write (MAC_ADDR1_Wr[1]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH_1 + 8] = 0; |
|
// RXHASH0 Register |
eth_register #(`ETH_HASH0_WIDTH_0, `ETH_HASH0_DEF_0) RXHASH0_0 |
( |
.DataIn (DataIn[`ETH_HASH0_WIDTH_0 - 1:0]), |
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_0 - 1:0]), |
.Write (HASH0_Wr[0]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_HASH0_WIDTH_1, `ETH_HASH0_DEF_1) RXHASH0_1 |
( |
.DataIn (DataIn[`ETH_HASH0_WIDTH_1 + 7:8]), |
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_1 + 7:8]), |
.Write (HASH0_Wr[1]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_HASH0_WIDTH_2, `ETH_HASH0_DEF_2) RXHASH0_2 |
( |
.DataIn (DataIn[`ETH_HASH0_WIDTH_2 + 15:16]), |
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_2 + 15:16]), |
.Write (HASH0_Wr[2]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_HASH0_WIDTH_3, `ETH_HASH0_DEF_3) RXHASH0_3 |
( |
.DataIn (DataIn[`ETH_HASH0_WIDTH_3 + 23:24]), |
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_3 + 23:24]), |
.Write (HASH0_Wr[3]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
|
// RXHASH1 Register |
eth_register #(`ETH_HASH1_WIDTH_0, `ETH_HASH1_DEF_0) RXHASH1_0 |
( |
.DataIn (DataIn[`ETH_HASH1_WIDTH_0 - 1:0]), |
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_0 - 1:0]), |
.Write (HASH1_Wr[0]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_HASH1_WIDTH_1, `ETH_HASH1_DEF_1) RXHASH1_1 |
( |
.DataIn (DataIn[`ETH_HASH1_WIDTH_1 + 7:8]), |
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_1 + 7:8]), |
.Write (HASH1_Wr[1]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_HASH1_WIDTH_2, `ETH_HASH1_DEF_2) RXHASH1_2 |
( |
.DataIn (DataIn[`ETH_HASH1_WIDTH_2 + 15:16]), |
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_2 + 15:16]), |
.Write (HASH1_Wr[2]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_HASH1_WIDTH_3, `ETH_HASH1_DEF_3) RXHASH1_3 |
( |
.DataIn (DataIn[`ETH_HASH1_WIDTH_3 + 23:24]), |
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_3 + 23:24]), |
.Write (HASH1_Wr[3]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
|
// TXCTRL Register |
eth_register #(`ETH_TX_CTRL_WIDTH_0, `ETH_TX_CTRL_DEF_0) TXCTRL_0 |
( |
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH_0 - 1:0]), |
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_0 - 1:0]), |
.Write (TXCTRL_Wr[0]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_TX_CTRL_WIDTH_1, `ETH_TX_CTRL_DEF_1) TXCTRL_1 |
( |
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH_1 + 7:8]), |
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_1 + 7:8]), |
.Write (TXCTRL_Wr[1]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_TX_CTRL_WIDTH_2, `ETH_TX_CTRL_DEF_2) TXCTRL_2 // Request bit is synchronously reset |
( |
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH_2 + 15:16]), |
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_2 + 15:16]), |
.Write (TXCTRL_Wr[2]), |
.Clk (Clk), |
.Reset (Reset), |
.SyncReset (RstTxPauseRq) |
); |
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0; |
|
|
|
// Reading data from registers |
always @ (Address or Read or MODEROut or INT_SOURCEOut or |
INT_MASKOut or IPGTOut or IPGR1Out or IPGR2Out or |
PACKETLENOut or COLLCONFOut or CTRLMODEROut or MIIMODEROut or |
MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or MIIRX_DATAOut or |
MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or TX_BD_NUMOut or |
HASH0Out or HASH1Out or TXCTRLOut |
) |
begin |
if(Read) // read |
begin |
case(Address) |
`ETH_MODER_ADR : DataOut=MODEROut; |
`ETH_INT_SOURCE_ADR : DataOut=INT_SOURCEOut; |
`ETH_INT_MASK_ADR : DataOut=INT_MASKOut; |
`ETH_IPGT_ADR : DataOut=IPGTOut; |
`ETH_IPGR1_ADR : DataOut=IPGR1Out; |
`ETH_IPGR2_ADR : DataOut=IPGR2Out; |
`ETH_PACKETLEN_ADR : DataOut=PACKETLENOut; |
`ETH_COLLCONF_ADR : DataOut=COLLCONFOut; |
`ETH_CTRLMODER_ADR : DataOut=CTRLMODEROut; |
`ETH_MIIMODER_ADR : DataOut=MIIMODEROut; |
`ETH_MIICOMMAND_ADR : DataOut=MIICOMMANDOut; |
`ETH_MIIADDRESS_ADR : DataOut=MIIADDRESSOut; |
`ETH_MIITX_DATA_ADR : DataOut=MIITX_DATAOut; |
`ETH_MIIRX_DATA_ADR : DataOut=MIIRX_DATAOut; |
`ETH_MIISTATUS_ADR : DataOut=MIISTATUSOut; |
`ETH_MAC_ADDR0_ADR : DataOut=MAC_ADDR0Out; |
`ETH_MAC_ADDR1_ADR : DataOut=MAC_ADDR1Out; |
`ETH_TX_BD_NUM_ADR : DataOut=TX_BD_NUMOut; |
`ETH_HASH0_ADR : DataOut=HASH0Out; |
`ETH_HASH1_ADR : DataOut=HASH1Out; |
`ETH_TX_CTRL_ADR : DataOut=TXCTRLOut; |
`ETH_DBG_ADR : DataOut=dbg_dat; |
default: DataOut=32'h0; |
endcase |
end |
else |
DataOut=32'h0; |
end |
|
|
assign r_RecSmall = MODEROut[16]; |
assign r_Pad = MODEROut[15]; |
assign r_HugEn = MODEROut[14]; |
assign r_CrcEn = MODEROut[13]; |
assign r_DlyCrcEn = MODEROut[12]; |
// assign r_Rst = MODEROut[11]; This signal is not used any more |
assign r_FullD = MODEROut[10]; |
assign r_ExDfrEn = MODEROut[9]; |
assign r_NoBckof = MODEROut[8]; |
assign r_LoopBck = MODEROut[7]; |
assign r_IFG = MODEROut[6]; |
assign r_Pro = MODEROut[5]; |
assign r_Iam = MODEROut[4]; |
assign r_Bro = MODEROut[3]; |
assign r_NoPre = MODEROut[2]; |
assign r_TxEn = MODEROut[1] & (TX_BD_NUMOut>0); // Transmission is enabled when there is at least one TxBD. |
assign r_RxEn = MODEROut[0] & (TX_BD_NUMOut<'h80); // Reception is enabled when there is at least one RxBD. |
|
assign r_IPGT[6:0] = IPGTOut[6:0]; |
|
assign r_IPGR1[6:0] = IPGR1Out[6:0]; |
|
assign r_IPGR2[6:0] = IPGR2Out[6:0]; |
|
assign r_MinFL[15:0] = PACKETLENOut[31:16]; |
assign r_MaxFL[15:0] = PACKETLENOut[15:0]; |
|
assign r_MaxRet[3:0] = COLLCONFOut[19:16]; |
assign r_CollValid[5:0] = COLLCONFOut[5:0]; |
|
assign r_TxFlow = CTRLMODEROut[2]; |
assign r_RxFlow = CTRLMODEROut[1]; |
assign r_PassAll = CTRLMODEROut[0]; |
|
assign r_MiiNoPre = MIIMODEROut[8]; |
assign r_ClkDiv[7:0] = MIIMODEROut[7:0]; |
|
assign r_WCtrlData = MIICOMMANDOut[2]; |
assign r_RStat = MIICOMMANDOut[1]; |
assign r_ScanStat = MIICOMMANDOut[0]; |
|
assign r_RGAD[4:0] = MIIADDRESSOut[12:8]; |
assign r_FIAD[4:0] = MIIADDRESSOut[4:0]; |
|
assign r_CtrlData[15:0] = MIITX_DATAOut[15:0]; |
|
assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0; |
assign MIISTATUSOut[2] = NValid_stat ; |
assign MIISTATUSOut[1] = Busy_stat ; |
assign MIISTATUSOut[0] = LinkFail ; |
|
assign r_MAC[31:0] = MAC_ADDR0Out[31:0]; |
assign r_MAC[47:32] = MAC_ADDR1Out[15:0]; |
assign r_HASH1[31:0] = HASH1Out; |
assign r_HASH0[31:0] = HASH0Out; |
|
assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0]; |
|
assign r_TxPauseTV[15:0] = TXCTRLOut[15:0]; |
assign r_TxPauseRq = TXCTRLOut[16]; |
|
|
// Synchronizing TxC Interrupt |
always @ (posedge TxClk or posedge Reset) |
begin |
if(Reset) |
SetTxCIrq_txclk <= 1'b0; |
else |
if(TxCtrlEndFrm & StartTxDone & r_TxFlow) |
SetTxCIrq_txclk <= 1'b1; |
else |
if(ResetTxCIrq_sync2) |
SetTxCIrq_txclk <= 1'b0; |
end |
|
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetTxCIrq_sync1 <= 1'b0; |
else |
SetTxCIrq_sync1 <= SetTxCIrq_txclk; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetTxCIrq_sync2 <= 1'b0; |
else |
SetTxCIrq_sync2 <= SetTxCIrq_sync1; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetTxCIrq_sync3 <= 1'b0; |
else |
SetTxCIrq_sync3 <= SetTxCIrq_sync2; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetTxCIrq <= 1'b0; |
else |
SetTxCIrq <= SetTxCIrq_sync2 & ~SetTxCIrq_sync3; |
end |
|
always @ (posedge TxClk or posedge Reset) |
begin |
if(Reset) |
ResetTxCIrq_sync1 <= 1'b0; |
else |
ResetTxCIrq_sync1 <= SetTxCIrq_sync2; |
end |
|
always @ (posedge TxClk or posedge Reset) |
begin |
if(Reset) |
ResetTxCIrq_sync2 <= 1'b0; |
else |
ResetTxCIrq_sync2 <= SetTxCIrq_sync1; |
end |
|
|
// Synchronizing RxC Interrupt |
always @ (posedge RxClk or posedge Reset) |
begin |
if(Reset) |
SetRxCIrq_rxclk <= 1'b0; |
else |
if(SetPauseTimer & r_RxFlow) |
SetRxCIrq_rxclk <= 1'b1; |
else |
if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3)) |
SetRxCIrq_rxclk <= 1'b0; |
end |
|
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetRxCIrq_sync1 <= 1'b0; |
else |
SetRxCIrq_sync1 <= SetRxCIrq_rxclk; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetRxCIrq_sync2 <= 1'b0; |
else |
SetRxCIrq_sync2 <= SetRxCIrq_sync1; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetRxCIrq_sync3 <= 1'b0; |
else |
SetRxCIrq_sync3 <= SetRxCIrq_sync2; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetRxCIrq <= 1'b0; |
else |
SetRxCIrq <= SetRxCIrq_sync2 & ~SetRxCIrq_sync3; |
end |
|
always @ (posedge RxClk or posedge Reset) |
begin |
if(Reset) |
ResetRxCIrq_sync1 <= 1'b0; |
else |
ResetRxCIrq_sync1 <= SetRxCIrq_sync2; |
end |
|
always @ (posedge RxClk or posedge Reset) |
begin |
if(Reset) |
ResetRxCIrq_sync2 <= 1'b0; |
else |
ResetRxCIrq_sync2 <= ResetRxCIrq_sync1; |
end |
|
always @ (posedge RxClk or posedge Reset) |
begin |
if(Reset) |
ResetRxCIrq_sync3 <= 1'b0; |
else |
ResetRxCIrq_sync3 <= ResetRxCIrq_sync2; |
end |
|
|
|
// Interrupt generation |
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
irq_txb <= 1'b0; |
else |
if(TxB_IRQ) |
irq_txb <= 1'b1; |
else |
if(INT_SOURCE_Wr[0] & DataIn[0]) |
irq_txb <= 1'b0; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
irq_txe <= 1'b0; |
else |
if(TxE_IRQ) |
irq_txe <= 1'b1; |
else |
if(INT_SOURCE_Wr[0] & DataIn[1]) |
irq_txe <= 1'b0; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
irq_rxb <= 1'b0; |
else |
if(RxB_IRQ) |
irq_rxb <= 1'b1; |
else |
if(INT_SOURCE_Wr[0] & DataIn[2]) |
irq_rxb <= 1'b0; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
irq_rxe <= 1'b0; |
else |
if(RxE_IRQ) |
irq_rxe <= 1'b1; |
else |
if(INT_SOURCE_Wr[0] & DataIn[3]) |
irq_rxe <= 1'b0; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
irq_busy <= 1'b0; |
else |
if(Busy_IRQ) |
irq_busy <= 1'b1; |
else |
if(INT_SOURCE_Wr[0] & DataIn[4]) |
irq_busy <= 1'b0; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
irq_txc <= 1'b0; |
else |
if(SetTxCIrq) |
irq_txc <= 1'b1; |
else |
if(INT_SOURCE_Wr[0] & DataIn[5]) |
irq_txc <= 1'b0; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
irq_rxc <= 1'b0; |
else |
if(SetRxCIrq) |
irq_rxc <= 1'b1; |
else |
if(INT_SOURCE_Wr[0] & DataIn[6]) |
irq_rxc <= 1'b0; |
end |
|
// Generating interrupt signal |
assign int_o = irq_txb & INT_MASKOut[0] | |
irq_txe & INT_MASKOut[1] | |
irq_rxb & INT_MASKOut[2] | |
irq_rxe & INT_MASKOut[3] | |
irq_busy & INT_MASKOut[4] | |
irq_txc & INT_MASKOut[5] | |
irq_rxc & INT_MASKOut[6] ; |
|
// For reading interrupt status |
assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH_0){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb}; |
|
|
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/rtl/eth_txstatem.v
0,0 → 1,282
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_txstatem.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// - Novan Hartadi (novan@vlsi.itb.ac.id) //// |
//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) //// |
//// //// |
//// All additional information is avaliable in the Readme.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2002/10/30 12:54:50 mohor |
// State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. |
// |
// Revision 1.4 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// Revision 1.3 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
// |
// Revision 1.2 2001/09/11 14:17:00 mohor |
// Few little NCSIM warnings fixed. |
// |
// Revision 1.1 2001/08/06 14:44:29 mohor |
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
// Include files fixed to contain no path. |
// File names and module names changed ta have a eth_ prologue in the name. |
// File eth_timescale.v is used to define timescale |
// All pin names on the top module are changed to contain _I, _O or _OE at the end. |
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
// and Mdo_OE. The bidirectional signal must be created on the top level. This |
// is done due to the ASIC tools. |
// |
// Revision 1.1 2001/07/30 21:23:42 mohor |
// Directory structure changed. Files checked and joind together. |
// |
// Revision 1.3 2001/06/19 18:16:40 mohor |
// TxClk changed to MTxClk (as discribed in the documentation). |
// Crc changed so only one file can be used instead of two. |
// |
// Revision 1.2 2001/06/19 10:38:07 mohor |
// Minor changes in header. |
// |
// Revision 1.1 2001/06/19 10:27:57 mohor |
// TxEthMAC initial release. |
// |
// |
// |
// |
|
|
`include "timescale.v" |
|
|
module eth_txstatem (MTxClk, Reset, ExcessiveDefer, CarrierSense, NibCnt, IPGT, IPGR1, |
IPGR2, FullD, TxStartFrm, TxEndFrm, TxUnderRun, Collision, UnderRun, |
StartTxDone, TooBig, NibCntEq7, NibCntEq15, MaxFrame, Pad, CrcEn, |
NibbleMinFl, RandomEq0, ColWindow, RetryMax, NoBckof, RandomEqByteCnt, |
StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS, |
StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam, |
StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG |
); |
|
input MTxClk; |
input Reset; |
input ExcessiveDefer; |
input CarrierSense; |
input [6:0] NibCnt; |
input [6:0] IPGT; |
input [6:0] IPGR1; |
input [6:0] IPGR2; |
input FullD; |
input TxStartFrm; |
input TxEndFrm; |
input TxUnderRun; |
input Collision; |
input UnderRun; |
input StartTxDone; |
input TooBig; |
input NibCntEq7; |
input NibCntEq15; |
input MaxFrame; |
input Pad; |
input CrcEn; |
input NibbleMinFl; |
input RandomEq0; |
input ColWindow; |
input RetryMax; |
input NoBckof; |
input RandomEqByteCnt; |
|
|
output StateIdle; // Idle state |
output StateIPG; // IPG state |
output StatePreamble; // Preamble state |
output [1:0] StateData; // Data state |
output StatePAD; // PAD state |
output StateFCS; // FCS state |
output StateJam; // Jam state |
output StateJam_q; // Delayed Jam state |
output StateBackOff; // Backoff state |
output StateDefer; // Defer state |
|
output StartFCS; // FCS state will be activated in next clock |
output StartJam; // Jam state will be activated in next clock |
output StartBackoff; // Backoff state will be activated in next clock |
output StartDefer; // Defer state will be activated in next clock |
output DeferIndication; |
output StartPreamble; // Preamble state will be activated in next clock |
output [1:0] StartData; // Data state will be activated in next clock |
output StartIPG; // IPG state will be activated in next clock |
|
wire StartIdle; // Idle state will be activated in next clock |
wire StartPAD; // PAD state will be activated in next clock |
|
|
reg StateIdle; |
reg StateIPG; |
reg StatePreamble; |
reg [1:0] StateData; |
reg StatePAD; |
reg StateFCS; |
reg StateJam; |
reg StateJam_q; |
reg StateBackOff; |
reg StateDefer; |
reg Rule1; |
|
|
// Defining the next state |
assign StartIPG = StateDefer & ~ExcessiveDefer & ~CarrierSense; |
|
assign StartIdle = StateIPG & (Rule1 & NibCnt[6:0] >= IPGT | ~Rule1 & NibCnt[6:0] >= IPGR2); |
|
assign StartPreamble = StateIdle & TxStartFrm & ~CarrierSense; |
|
assign StartData[0] = ~Collision & (StatePreamble & NibCntEq15 | StateData[1] & ~TxEndFrm); |
|
assign StartData[1] = ~Collision & StateData[0] & ~TxUnderRun & ~MaxFrame; |
|
assign StartPAD = ~Collision & StateData[1] & TxEndFrm & Pad & ~NibbleMinFl; |
|
assign StartFCS = ~Collision & StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & CrcEn |
| ~Collision & StatePAD & NibbleMinFl & CrcEn; |
|
assign StartJam = (Collision | UnderRun) & ((StatePreamble & NibCntEq15) | (|StateData[1:0]) | StatePAD | StateFCS); |
|
assign StartBackoff = StateJam & ~RandomEq0 & ColWindow & ~RetryMax & NibCntEq7 & ~NoBckof; |
|
assign StartDefer = StateIPG & ~Rule1 & CarrierSense & NibCnt[6:0] <= IPGR1 & NibCnt[6:0] != IPGR2 |
| StateIdle & CarrierSense |
| StateJam & NibCntEq7 & (NoBckof | RandomEq0 | ~ColWindow | RetryMax) |
| StateBackOff & (TxUnderRun | RandomEqByteCnt) |
| StartTxDone | TooBig; |
|
assign DeferIndication = StateIdle & CarrierSense; |
|
// Tx State Machine |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
begin |
StateIPG <= 1'b0; |
StateIdle <= 1'b0; |
StatePreamble <= 1'b0; |
StateData[1:0] <= 2'b0; |
StatePAD <= 1'b0; |
StateFCS <= 1'b0; |
StateJam <= 1'b0; |
StateJam_q <= 1'b0; |
StateBackOff <= 1'b0; |
StateDefer <= 1'b1; |
end |
else |
begin |
StateData[1:0] <= StartData[1:0]; |
StateJam_q <= StateJam; |
|
if(StartDefer | StartIdle) |
StateIPG <= 1'b0; |
else |
if(StartIPG) |
StateIPG <= 1'b1; |
|
if(StartDefer | StartPreamble) |
StateIdle <= 1'b0; |
else |
if(StartIdle) |
StateIdle <= 1'b1; |
|
if(StartData[0] | StartJam) |
StatePreamble <= 1'b0; |
else |
if(StartPreamble) |
StatePreamble <= 1'b1; |
|
if(StartFCS | StartJam) |
StatePAD <= 1'b0; |
else |
if(StartPAD) |
StatePAD <= 1'b1; |
|
if(StartJam | StartDefer) |
StateFCS <= 1'b0; |
else |
if(StartFCS) |
StateFCS <= 1'b1; |
|
if(StartBackoff | StartDefer) |
StateJam <= 1'b0; |
else |
if(StartJam) |
StateJam <= 1'b1; |
|
if(StartDefer) |
StateBackOff <= 1'b0; |
else |
if(StartBackoff) |
StateBackOff <= 1'b1; |
|
if(StartIPG) |
StateDefer <= 1'b0; |
else |
if(StartDefer) |
StateDefer <= 1'b1; |
end |
end |
|
|
// This sections defines which interpack gap rule to use |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
Rule1 <= 1'b0; |
else |
begin |
if(StateIdle | StateBackOff) |
Rule1 <= 1'b0; |
else |
if(StatePreamble | FullD) |
Rule1 <= 1'b1; |
end |
end |
|
|
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/ethmac/ethtop.v
0,0 → 1,190
|
|
|
`include "ethmac_defines.v" |
`include "timescale.v" |
|
|
module ethtop |
( |
// WISHBONE common |
wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o, |
|
// WISHBONE slave |
wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o, |
|
// WISHBONE master |
m_wb_adr_o, m_wb_sel_o, m_wb_we_o, |
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o, |
m_wb_stb_o, m_wb_ack_i, m_wb_err_i, |
|
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o, m_wb_bte_o, |
`endif |
|
//TX |
mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o, |
|
//RX |
mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i, |
|
// MIIM |
mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o, |
|
int_o |
|
// Bist |
`ifdef ETH_BIST |
, |
// debug chain signals |
mbist_si_i, // bist scan serial in |
mbist_so_o, // bist scan serial out |
mbist_ctrl_i // bist chain shift control |
`endif |
|
); |
|
|
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH; |
parameter TX_FIFO_DEPTH = `ETH_TX_FIFO_DEPTH; |
parameter TX_FIFO_CNT_WIDTH = `ETH_TX_FIFO_CNT_WIDTH; |
parameter RX_FIFO_DATA_WIDTH = `ETH_RX_FIFO_DATA_WIDTH; |
parameter RX_FIFO_DEPTH = `ETH_RX_FIFO_DEPTH; |
parameter RX_FIFO_CNT_WIDTH = `ETH_RX_FIFO_CNT_WIDTH; |
|
|
// WISHBONE common |
input wb_clk_i; // WISHBONE clock |
input wb_rst_i; // WISHBONE reset |
input [31:0] wb_dat_i; // WISHBONE data input |
output [31:0] wb_dat_o; // WISHBONE data output |
output wb_err_o; // WISHBONE error output |
|
// WISHBONE slave |
input [9:0] wb_adr_i; // WISHBONE address input |
input [3:0] wb_sel_i; // WISHBONE byte select input |
input wb_we_i; // WISHBONE write enable input |
input wb_cyc_i; // WISHBONE cycle input |
input wb_stb_i; // WISHBONE strobe input |
output wb_ack_o; // WISHBONE acknowledge output |
|
// WISHBONE master |
output [31:0] m_wb_adr_o; |
output [3:0] m_wb_sel_o; |
output m_wb_we_o; |
input [31:0] m_wb_dat_i; |
output [31:0] m_wb_dat_o; |
output m_wb_cyc_o; |
output m_wb_stb_o; |
input m_wb_ack_i; |
input m_wb_err_i; |
|
wire [29:0] m_wb_adr_tmp; |
|
`ifdef ETH_WISHBONE_B3 |
output [2:0] m_wb_cti_o; // Cycle Type Identifier |
output [1:0] m_wb_bte_o; // Burst Type Extension |
`endif |
|
// Tx |
input mtx_clk_pad_i; // Transmit clock (from PHY) |
output [3:0] mtxd_pad_o; // Transmit nibble (to PHY) |
output mtxen_pad_o; // Transmit enable (to PHY) |
output mtxerr_pad_o; // Transmit error (to PHY) |
|
// Rx |
input mrx_clk_pad_i; // Receive clock (from PHY) |
input [3:0] mrxd_pad_i; // Receive nibble (from PHY) |
input mrxdv_pad_i; // Receive data valid (from PHY) |
input mrxerr_pad_i; // Receive data error (from PHY) |
|
// Common Tx and Rx |
input mcoll_pad_i; // Collision (from PHY) |
input mcrs_pad_i; // Carrier sense (from PHY) |
|
// MII Management interface |
input md_pad_i; // MII data input (from I/O cell) |
output mdc_pad_o; // MII Management data clock (to PHY) |
output md_pad_o; // MII data output (to I/O cell) |
output md_padoe_o; // MII data output enable (to I/O cell) |
|
output int_o; // Interrupt output |
|
// Bist |
`ifdef ETH_BIST |
input mbist_si_i; // bist scan serial in |
output mbist_so_o; // bist scan serial out |
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control |
`endif |
|
wire [31:0] m_wb_adr_o_in_byte; |
|
eth_top top |
( |
// WISHBONE common |
.wb_clk_i(wb_clk_i), |
.wb_rst_i(wb_rst_i), |
.wb_dat_i(wb_dat_i), |
.wb_dat_o(wb_dat_o), |
|
// WISHBONE slave |
.wb_adr_i(wb_adr_i), |
.wb_sel_i(wb_sel_i), |
.wb_we_i(wb_we_i), |
.wb_cyc_i(wb_cyc_i), |
.wb_stb_i(wb_stb_i), |
.wb_ack_o(wb_ack_o), |
.wb_err_o(wb_err_o), |
|
|
// WISHBONE master |
.m_wb_adr_o(m_wb_adr_o_in_byte), |
.m_wb_sel_o(m_wb_sel_o), |
.m_wb_we_o(m_wb_we_o), |
.m_wb_dat_o(m_wb_dat_o), |
.m_wb_dat_i(m_wb_dat_i), |
.m_wb_cyc_o(m_wb_cyc_o), |
.m_wb_stb_o(m_wb_stb_o), |
.m_wb_ack_i(m_wb_ack_i), |
.m_wb_err_i(m_wb_err_i), |
|
`ifdef ETH_WISHBONE_B3 |
.m_wb_cti_o(m_wb_cti_o), |
.m_wb_bte_o(m_wb_bte_o), |
`endif |
|
//TX |
.mtx_clk_pad_i(mtx_clk_pad_i), |
.mtxd_pad_o(mtxd_pad_o), |
.mtxen_pad_o(mtxen_pad_o), |
.mtxerr_pad_o(mtxerr_pad_o), |
|
//RX |
.mrx_clk_pad_i(mrx_clk_pad_i), |
.mrxd_pad_i(mrxd_pad_i), |
.mrxdv_pad_i(mrxdv_pad_i), |
.mrxerr_pad_i(mrxerr_pad_i), |
.mcoll_pad_i(mcoll_pad_i), |
.mcrs_pad_i(mcrs_pad_i), |
|
// MIIM |
.mdc_pad_o(mdc_pad_o), |
.md_pad_i(md_pad_i), |
.md_pad_o(md_pad_o), |
.md_padoe_o(md_padoe_o), |
.int_o(int_o) |
|
// Bist |
`ifdef ETH_BIST |
, |
// debug chain signals |
.mbist_si_i(mbist_si_i), // bist scan serial in |
.mbist_so_o(mbist_so_o), // bist scan serial out |
.mbist_ctrl_i(mbist_ctrl_i) // bist chain shift control |
`endif |
|
); |
|
assign m_wb_adr_o= {2'b00,m_wb_adr_o_in_byte[31:2]}; |
|
endmodule |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16.h
File deleted
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16
0,0 → 1,117
#ifndef ${IP}_H |
#define ${IP}_H |
|
|
#define ${IP}_WAIT_CNT (${IP}_CLK_MHZ*100) |
#define ${IP}_COLUMN_NUM 16 |
#define ${IP}_ROW_NUM 2 |
|
const char base_y[4]={0x80,0xc0,${IP}_COLUMN_NUM+0x80,${IP}_COLUMN_NUM+0xc0}; |
|
#define ${IP}_set_8_bit_1_line() ${IP}_wr_cmd_func(0x30) |
#define ${IP}_set_8_bit_2_line() ${IP}_wr_cmd_func(0x38) |
#define ${IP}_set_4_bit_1_line() ${IP}_wr_cmd_func(0x20) |
#define ${IP}_set_4_bit_3_line() ${IP}_wr_cmd_func(0x28) |
#define ${IP}_entry_mode() ${IP}_wr_cmd_func(0x06) |
//(clearing display without clearing ddram content) |
#define ${IP}_dsply_off_cursor_off() ${IP}_wr_cmd_func(0x08) |
#define ${IP}_dsply_on_cursor_on() ${IP}_wr_cmd_func(0x0e) |
#define ${IP}_dsply_on_cursor_off() ${IP}_wr_cmd_func(0x0c) |
#define ${IP}_dsply_on_cursor_blink() ${IP}_wr_cmd_func(0x0f) |
#define ${IP}_shift_dsply_left() ${IP}_wr_cmd_func(0x18) |
#define ${IP}_shift_dsply_right() ${IP}_wr_cmd_func(0x1c) |
#define ${IP}_shift_cursor_left() ${IP}_wr_cmd_func(0x10) |
#define ${IP}_shift_cursor_right() ${IP}_wr_cmd_func(0x14) |
//(also clear ddram content) |
#define ${IP}_clr_dsply() ${IP}_wr_cmd_func(0x01) |
#define ${IP}_goto_line(line_num) ${IP}_wr_cmd_func(base_y[line_num-1]) // 1<= lines num <= ${IP}_ROW_NUM |
#define ${IP}_gotoxy(x,y) ${IP}_wr_cmd_func(base_y[y]+x)// 0<= x< ${IP}_COLUMN_NUM; 0<= y < ${IP}_ROW_NUM |
#define ${IP}_show_character(c) ${IP}_wr_data_func(c); |
|
|
|
void ${IP}_wait(unsigned int volatile num){ |
while (num>0){ |
num--; |
asm volatile ("nop"); |
} |
return; |
} |
|
|
inline void ${IP}_wr_cmd_func( char data){ |
${IP}_WR_CMD= data; |
${IP}_wait(${IP}_WAIT_CNT); |
} |
|
inline void ${IP}_wr_data_func( char data){ |
${IP}_WR_DATA=data; |
${IP}_wait(${IP}_WAIT_CNT); |
} |
|
|
|
|
|
|
void ${IP}_init() |
{ |
${IP}_set_8_bit_2_line(); |
${IP}_dsply_on_cursor_off(); |
${IP}_clr_dsply(); |
${IP}_entry_mode(); |
${IP}_goto_line(1); |
} |
|
//------------------------------------------------------------------------- |
void ${IP}_show_text(char* Text, unsigned char length) |
{ |
int i; |
for(i=0;i<length;i++) ${IP}_show_character(Text[i]); |
} |
|
|
|
|
|
|
#ifdef ${IP}_TEST_ENABLE |
|
|
|
//------------------------------------------------------------------------- |
|
const char test_text[4][17]= {"${IP} 2x16 test ", " ProNoC SoC ","Test Line 3 ","Test Line 4 "}; |
|
|
void ${IP}_test() |
{ |
unsigned int x,y; |
|
// Initial ${IP} |
${IP}_init(); |
// Show Text to ${IP} |
for(y=1;y<=${IP}_ROW_NUM;y++) { |
${IP}_goto_line(y); |
${IP}_show_text((char*)test_text[y-1],16); |
} |
|
${IP}_wait(1000*${IP}_WAIT_CNT); |
${IP}_clr_dsply(); |
|
for(y=0;y<${IP}_ROW_NUM;y++){ |
for(x=0;x<${IP}_COLUMN_NUM;x++){ |
|
${IP}_gotoxy(x,y); |
${IP}_show_character(test_text[y][x]); |
${IP}_wait(500*${IP}_WAIT_CNT); |
} |
} |
|
|
} |
//------------------------------------------------------------------------- |
|
#endif |
|
#endif |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16.v
4,8 → 4,10
|
|
module lcd_2x16 #( |
parameter CLK_MHZ= 50, |
parameter Dw = 8, // wishbone bus data width |
parameter Aw = 2 |
|
)( |
clk, |
reset, |
27,7 → 29,21
); |
|
|
function integer log2; |
input integer number; begin |
log2=0; |
while(2**log2<number) begin |
log2=log2+1; |
end |
end |
endfunction // log2 |
|
|
|
localparam Cw=log2(CLK_MHZ); |
|
|
|
input clk; |
input reset; |
|
50,7 → 66,7
inout [ 7: 0] lcd_data; |
|
|
reg [5:0]cnt; |
reg [Cw-1:0]cnt; |
|
|
assign lcd_rw = s_addr_i[0]; |
68,7 → 84,7
cnt=6'd0; |
end else begin |
s_ack_o <= s_stb_i & (cnt==2); |
if(s_stb_i && cnt==0) cnt=6'h111111; |
if(s_stb_i && cnt==0) cnt={Cw{1'b1}}; // minimum 1 ms delay for holfing lcd en signal |
else if(lcd_en)cnt=cnt-1'b1; |
end |
end |
76,5 → 92,3
|
endmodule |
|
|
|
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/perl/hdr_file_gen.pl
13,9 → 13,56
|
|
|
sub get_instance_global_variable{ |
my ($soc,$id) = @_; |
my $module =$soc->soc_get_module($id); |
my $module_name =$soc->soc_get_module_name($id); |
my $category =$soc->soc_get_category($id); |
my $inst =$soc->soc_get_instance_name($id); |
my @plugs= $soc->soc_get_all_plugs_of_an_instance($id); |
my %params= $soc->soc_get_module_param($id); |
#add two extra variable the instance name and base addresses |
$params{IP}=$inst; |
$params{CORE}=$id; |
foreach my $plug (@plugs){ |
my @nums=$soc->soc_list_plug_nums($id,$plug); |
foreach my $num (@nums){ |
my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($id,$plug,$num); |
#wishbone slave address |
if((defined $connect_socket) && ($connect_socket eq 'wb_slave')){ |
#print "$addr,$base,$end,$connect_id,$connect_socket,$connect_socket_num\n"; |
my $base_hex=sprintf("0X%08x", $base); |
my $end_hex=sprintf("0X%08x", $end); |
my $val="BASE".$num; |
$params{$val}=$base_hex; |
|
} |
|
|
} |
} |
$params{BASE}=$params{BASE0} if(defined $params{BASE0}); |
|
|
return (\%params); |
} |
|
|
sub replace_golb_var{ |
my ($hdr,$ref)=@_; |
my %params= %{$ref}; |
foreach my $p (sort keys %params){ |
my $pattern= '\$\{?' . $p . '(\}|\b)'; |
($hdr=$hdr)=~s/$pattern/$params{$p}/g; |
} |
return $hdr; |
|
} |
|
|
|
sub generate_header_file{ |
my ($soc)= @_; |
my ($soc,$project_dir,$target_dir,$dir)= @_; |
my $soc_name=$soc->soc_get_soc_name(); |
$soc_name = uc($soc_name); |
if(!defined $soc_name){$soc_name='soc'}; |
33,27 → 80,20
my $module_name =$soc->soc_get_module_name($id); |
my $category =$soc->soc_get_category($id); |
my $inst =$soc->soc_get_instance_name($id); |
|
|
add_text_to_string(\$system_h,"\n \n /* $inst */ \n"); |
$inst=uc($inst); |
# print base address |
my @plugs= $soc->soc_get_all_plugs_of_an_instance($id); |
|
|
my %params= %{get_instance_global_variable($soc,$id)}; |
|
|
foreach my $plug (@plugs){ |
my @nums=$soc->soc_list_plug_nums($id,$plug); |
foreach my $num (@nums){ |
my ($addr,$base,$end,$name,$connect_id,$connect_socket,$connect_socket_num)=$soc->soc_get_plug($id,$plug,$num); |
#wishbone slave address |
if((defined $connect_socket) && ($connect_socket eq 'wb_slave')){ |
|
#print "$addr,$base,$end,$connect_id,$connect_socket,$connect_socket_num\n"; |
my $base_hex=sprintf("0X%08x", $base); |
my $end_hex=sprintf("0X%08x", $end); |
|
add_text_to_string(\$system_h,"#define $inst\_BASE_ADDR$num \t\t $base_hex\n"); |
add_text_to_string(\$system_h,"#define $inst\_BASE_ADDR \t\t $inst\_BASE_ADDR0\n") if ($num==0); |
|
|
} |
#intrrupt |
if((defined $connect_socket) && ($connect_socket eq 'interrupt_peripheral')){ |
add_text_to_string(\$system_h,"//intrrupt flag location\n"); |
65,27 → 105,52
} |
|
|
my $hdr =$ip->ip_get_hdr($category,$module); |
my $hdr =$ip->ip_get($category,$module,"system_h"); |
#print "$hdr"; |
|
|
# \$\{?IP(\b|\}) |
if(defined $hdr){ |
#replace IP name |
my $key='\$IP\\\\'; |
($hdr=$hdr)=~s/$key/$inst/g; |
$hdr=replace_golb_var($hdr,\%params); |
add_text_to_string(\$system_h,"$hdr\n"); |
} |
|
$key='\$IP'; |
($hdr=$hdr)=~s/$key/$inst/g; |
# Write Software gen files |
my @sw_file_gen = $ip->ip_get_list($category,$module,"gen_sw_files"); |
foreach my $file (@sw_file_gen){ |
if(defined $file ){ |
my ($path,$rename)=split('frename_sep_t',$file); |
$rename=replace_golb_var($rename,\%params); |
#read the file content |
my $content=read_file_cntent($path,$project_dir); |
$content=replace_golb_var($content,\%params); |
|
|
if(defined $rename){ |
|
#replace BASE addr |
$key='\$BASE'; |
($hdr=$hdr)=~s/$key/$inst\_BASE_ADDR/g; |
|
add_text_to_string(\$system_h,"$hdr\n"); |
open(FILE, ">lib/verilog/$rename") || die "Can not open: $!"; |
print FILE $content; |
close(FILE) || die "Error closing file: $!"; |
move ("$dir/lib/verilog/$rename","$target_dir/sw/"); |
|
|
} |
} |
} |
|
|
} |
|
add_text_to_string(\$system_h,"#endif\n"); |
return $system_h; |
my $name=$soc->soc_get_soc_name(); |
open(FILE, ">lib/verilog/$name.h") || die "Can not open: $!"; |
print FILE $system_h; |
close(FILE) || die "Error closing file: $!"; |
move ("$dir/lib/verilog/$name.h","$target_dir/sw/"); |
|
|
|
|
} |
|
|
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/perl/temp.pl
1,58 → 1,160
#! /usr/bin/perl -w |
|
use Glib qw/TRUE FALSE/; |
use Gtk2 '-init'; |
|
use strict; |
use warnings; |
our $spinner1; |
|
sub get_value |
{ |
my ($button, $format) = @_; |
|
if ('int' eq $format) |
{ |
$button->{val_label}->set_text (sprintf ("%d", |
$spinner1->get_value_as_int)); |
} |
else |
{ |
$button->{val_label}->set_text (sprintf ("%0.*f", |
$spinner1->get_digits, |
$spinner1->get_value)); |
} |
} |
|
$window = Gtk2::Window->new ('toplevel'); |
$window->signal_connect (destroy => sub { Gtk2->main_quit; 0; }); |
$window->set_title ("Spin Button"); |
|
$main_vbox = Gtk2::VBox->new (FALSE, 5); |
$main_vbox->set_border_width (10); |
$window->add ($main_vbox); |
|
my @nums=(0,2,3,6,7); |
$frame = Gtk2::Frame->new ("Not accelerated"); |
$main_vbox->pack_start ($frame, TRUE, TRUE, 0); |
|
my $s=compress_nums(@nums); |
$vbox = Gtk2::VBox->new (FALSE, 0); |
$vbox->set_border_width (10); |
$frame->add ($vbox); |
|
print "$s\n"; |
# Day, month, year spinners |
$hbox = Gtk2::HBox->new (FALSE, 0); |
$vbox->pack_start ($hbox, TRUE, TRUE, 5); |
|
$vbox2 = Gtk2::VBox->new (FALSE, 0); |
$hbox->pack_start ($vbox2, TRUE, TRUE, 5); |
|
sub compress_nums{ |
my @nums=@_; |
my @f=sort { $a <=> $b } @nums; |
my $s; |
my $ls; |
my $range=0; |
my $x; |
|
$label = Gtk2::Label->new ("Day :"); |
$label->set_alignment (0.0, 0.5); # left halignment, middle valignment |
$vbox2->pack_start ($label, FALSE, TRUE, 0); |
|
foreach my $p (@f){ |
if(!defined $x) { |
$s="$p"; |
$ls=$p; |
|
} |
else{ |
if($p-$x>1){ #gap exist |
if( $range){ |
$s=($x-$ls>1 )? "$s:$x,$p": "$s,$x,$p"; |
$ls=$p; |
$range=0; |
}else{ |
$s= "$s,$p"; |
$ls=$p; |
$adj = Gtk2::Adjustment->new (1.0, 1.0, 31.0, 1.0, 5.0, 0.0); |
$spinner = Gtk2::SpinButton->new ($adj, 0, 0); |
$spinner->set_wrap (TRUE); |
$vbox2->pack_start ($spinner, FALSE, TRUE, 0); |
|
} |
|
}else {$range=1;} |
$vbox2 = Gtk2::VBox->new (FALSE, 0); |
$hbox->pack_start ($vbox2, TRUE, TRUE, 5); |
|
$label = Gtk2::Label->new ("Month :"); |
$label->set_alignment (0.0, 0.5); # left halignment, middle valignment |
$vbox2->pack_start ($label, FALSE, TRUE, 0); |
|
|
} |
|
$x=$p |
} |
if($range==1){ $s= ($x-$ls>1 )? "$s:$x": "$s,$x";} |
#update $s($ls,$hs); |
$adj = Gtk2::Adjustment->new (1.0, 1.0, 12.0, 1.0, 5.0, 0.0); |
$spinner = Gtk2::SpinButton->new ($adj, 0, 0); |
$spinner->set_wrap (TRUE); |
$vbox2->pack_start ($spinner, FALSE, TRUE, 0); |
|
return $s; |
|
} |
$vbox2 = Gtk2::VBox->new (FALSE, 0); |
$hbox->pack_start ($vbox2, TRUE, TRUE, 5); |
|
$label = Gtk2::Label->new ("Year :"); |
$label->set_alignment (0.0, 0.5); # left halignment, middle valignment |
$vbox2->pack_start ($label, FALSE, TRUE, 0); |
|
$adj = Gtk2::Adjustment->new (1998.0, 1.0, 2100.0, 1.0, 100.0, 0.0); |
$spinner = Gtk2::SpinButton->new ($adj, 0, 0); |
$spinner->set_wrap (TRUE); |
$spinner->set_size_request (55, -1); |
$vbox2->pack_start ($spinner, FALSE, TRUE, 0); |
|
$frame = Gtk2::Frame->new ("Accelerated"); |
$main_vbox->pack_start ($frame, TRUE, TRUE, 0); |
|
$vbox = Gtk2::VBox->new (FALSE, 0); |
$vbox->set_border_width (5); |
$frame->add ($vbox); |
|
$hbox = Gtk2::HBox->new (FALSE, 0); |
$vbox->pack_start ($hbox, TRUE, TRUE, 5); |
|
$vbox2 = Gtk2::VBox->new (FALSE, 0); |
$hbox->pack_start ($vbox2, TRUE, TRUE, 5); |
|
$label = Gtk2::Label->new ("Value :"); |
$label->set_alignment (0.0, 0.5); # left halignment, middle valignment |
$vbox2->pack_start ($label, FALSE, TRUE, 0); |
|
$adj = Gtk2::Adjustment->new (0.0, -10000.0, 10000.0, 0.5, 100.0, 0.0); |
$spinner1 = Gtk2::SpinButton->new ($adj, 1.0, 2); |
$spinner1->set_wrap (TRUE); |
$spinner1->set_size_request (100, -1); |
$vbox2->pack_start ($spinner1, FALSE, TRUE, 0); |
|
$vbox2 = Gtk2::VBox->new (FALSE, 0); |
$hbox->pack_start ($vbox2, TRUE, TRUE, 5); |
|
$label = Gtk2::Label->new ("Digits :"); |
$label->set_alignment (0.0, 0.5); # left halignment, middle valignment |
$vbox2->pack_start ($label, FALSE, TRUE, 0); |
|
$adj = Gtk2::Adjustment->new (2, 1, 5, 1, 1, 0); |
$spinner2 = Gtk2::SpinButton->new ($adj, 0.0, 0); |
$spinner2->set_wrap (TRUE); |
$adj->signal_connect (value_changed => sub { |
$spinner1->set_digits ($spinner2->get_value_as_int ()); |
}); |
$vbox2->pack_start ($spinner2, FALSE, TRUE, 0); |
|
$button = Gtk2::CheckButton->new ("Snap to 0.5-ticks"); |
$button->signal_connect (clicked => sub { |
$spinner1->set_snap_to_ticks ($_[0]->get_active); |
}); |
$vbox->pack_start ($button, TRUE, TRUE, 0); |
$button->set_active (TRUE); |
|
$button = Gtk2::CheckButton->new ("Numeric only input mode"); |
$button->signal_connect (clicked => sub { |
$spinner1->set_numeric ($_[0]->get_active); |
}); |
$vbox->pack_start ($button, TRUE, TRUE, 0); |
$button->set_active (TRUE); |
|
$val_label = Gtk2::Label->new (""); |
|
$hbox = Gtk2::HBox->new (FALSE, 0); |
$vbox->pack_start ($hbox, FALSE, TRUE, 5); |
$button = Gtk2::Button->new ("Value as Int"); |
$button->{val_label} = $val_label; |
$button->signal_connect (clicked => \&get_value, 'int'); |
$hbox->pack_start ($button, TRUE, TRUE, 5); |
|
$button = Gtk2::Button->new ("Value as Float"); |
$button->{val_label} = $val_label; |
$button->signal_connect (clicked => \&get_value, 'float'); |
$hbox->pack_start ($button, TRUE, TRUE, 5); |
|
$vbox->pack_start ($val_label, TRUE, TRUE, 0); |
$val_label->set_text ("0"); |
|
$hbox = Gtk2::HBox->new (FALSE, 0); |
$main_vbox->pack_start ($hbox, FALSE, TRUE, 0); |
|
$button = Gtk2::Button->new ("Close"); |
$button->signal_connect (clicked => sub { $window->destroy; }); |
$hbox->pack_start ($button, TRUE, TRUE, 0); |
|
$window->show_all; |
|
Gtk2->main; |
|
0; |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/perl/ip.pm
229,20 → 229,7
return @r; |
} |
|
sub get_describtion{ |
my ($self,$category,$module)=@_; |
my $r; |
if (!defined($module) ) {return $r;} |
$r=$self->{categories}{$category}{names}{$module}{Describtion}; |
|
return $r; |
|
} |
|
|
|
|
|
sub get_param_default{ |
my ($self,$category,$module)=@_; |
my %r; |
382,52 → 369,53
} |
|
|
sub ip_get_module_name{ |
my ($self, $category,$module)=@_; |
my $module_name; |
if(exists $self->{categories}{$category}{names}{$module}{module_name}){ |
$module_name= $self->{categories}{$category}{names}{$module}{module_name}; |
} |
return $module_name; |
} |
|
|
sub ip_get_hdr{ |
my ($self, $category,$module)=@_; |
my $hdr; |
if(exists($self->{categories}{$category}{names}{$module}{header})){ |
$hdr=$self->{categories}{$category}{names}{$module}{header}; |
} |
return $hdr; |
|
|
|
sub ip_add{ |
my ($self,$category,$module,$filed_name,$filed_data)=@_; |
$self->{categories}{$category}{names}{$module}{$filed_name}=$filed_data; |
} |
|
|
sub ip_get_files{ |
my ($self, $category,$module,$list_name)=@_; |
sub ip_get{ |
my ($self,$category,$module,$filed_name)=@_; |
return $self->{categories}{$category}{names}{$module}{$filed_name}; |
} |
|
|
sub ip_get_list{ |
my ($self,$category,$module,$filed_name)=@_; |
my @l; |
@l=@{$self->{categories}{$category}{names}{$module}{$list_name}} if(defined $self->{categories}{$category}{names}{$module}{$list_name}); |
return @l; |
if( defined $self->{categories}{$category}{names}{$module}{$filed_name}){ |
@l=@{$self->{categories}{$category}{names}{$module}{$filed_name}}; |
} |
return @l; |
} |
|
|
sub ip_get_unsuded_intfc_ports{ |
my ($self, $category,$module)=@_; |
return $self->{categories}{$category}{names}{$module}{"unused"}; |
|
sub ip_remove{ |
my ($self,$category,$module,$filed_name)=@_; |
delete $self->{categories}{$category}{names}{$module}{$filed_name}; |
} |
|
|
|
|
sub add_ip{ |
|
my ($self,$ipgen) =@_; |
my $module; |
$module = $ipgen->ipgen_get_ip_name(); |
my $module_name =$ipgen->ipgen_get_module_name(); |
$module = $ipgen->ipgen_get("ip_name"); |
my $module_name =$ipgen->ipgen_get("module_name"); |
if(!defined $module){ $module = $module_name} |
my $category= $ipgen->ipgen_get_category(); |
my $Describtion= $ipgen->ipgen_get_description(); |
my $category= $ipgen->ipgen_get("category"); |
|
|
$self->{categories}{$category}{names}{$module}={}; |
$self->{categories}{$category}{names}{$module}{Describtion}=$Describtion; |
|
$self->{categories}{$category}{names}{$module}{module_name}=$module_name; |
my @plugs= $ipgen->ipgen_list_plugs(); |
#print "$module:@plugs\n"; |
450,24 → 438,20
ip_add_parameter($self,$category,$module,$param,$deafult,$type,$content,$info,$glob_param,$redefine_param); |
|
} |
my @params_order= $ipgen->ipgen_get_parameters_order(); |
$self->{categories}{$category}{names}{$module}{parameters_order}=\@params_order; |
|
my @ports= $ipgen->ipgen_list_ports(); |
foreach my $port (@ports){ |
my($range,$type,$intfc_name,$intfc_port)=$ipgen->ipgen_get_port($port); |
ip_add_port($self,$category,$module,$port,$type,$range,$intfc_name,$intfc_port); |
} |
my $hdr= $ipgen->ipgen_get_hdr(); |
$self->{categories}{$category}{names}{$module}{header}=$hdr; |
|
my @hdl_files= $ipgen->ipgen_get_files_list("hdl_files"); |
$self->{categories}{$category}{names}{$module}{"hdl_files"}=\@hdl_files; |
my @fileds =("system_h","hdl_files","sw_files","gen_sw_files","sw_params_list","unused","parameters_order","description"); |
foreach my $p (@fileds){ |
my $val=$ipgen->ipgen_get($p); |
$self->{categories}{$category}{names}{$module}{$p}=$ipgen->ipgen_get($p) if(defined $val ); |
} |
|
my @sw_files= $ipgen->ipgen_get_files_list("sw_files"); |
$self->{categories}{$category}{names}{$module}{"sw_files"}=\@sw_files; |
$self->{categories}{$category}{names}{$module}{"unused"}=$ipgen->ipgen_get_unused_intfc_ports(); |
|
|
|
} |
|
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/perl/mpsoc_gen.pl
89,7 → 89,7
$step=~ s/\D//g; |
$widget=gen_spin($min,$max,$step); |
$widget->set_value($value); |
$widget-> signal_connect("changed" => sub{ |
$widget-> signal_connect("value_changed" => sub{ |
my $new_param_value=$widget->get_value_as_int(); |
$mpsoc->mpsoc_add_param($param,$new_param_value); |
set_state($state,"ref",1); |
440,7 → 440,7
my $spin=gen_spin($min,$max,$step); |
$spin->set_value($param_value{$p}); |
$table->attach_defaults ($spin, 3, 4, $row, $row+1); |
$spin-> signal_connect("changed" => sub{$param_value{$p}=$spin->get_value_as_int();}); |
$spin-> signal_connect("value_changed" => sub{$param_value{$p}=$spin->get_value_as_int();}); |
|
# $box=def_label_spin_help_box ($param,$info, $value,$min,$max,$step, 2); |
} |
1131,7 → 1131,7
foreach my $soc_name (@soc_list){ |
my @n=$mpsoc->mpsoc_get_soc_tiles_num($soc_name); |
if(scalar @n){ |
#this soc has been used generate the verilog files of it |
#generate the verilog files of it |
push(@used_socs,$soc_name); |
} |
} |
1222,15 → 1222,12
|
|
# Write header file |
my $file_h=generate_header_file($soc); |
open(FILE, ">lib/verilog/$soc_name.h") || die "Can not open: $!"; |
print FILE $file_h; |
close(FILE) || die "Error closing file: $!"; |
generate_header_file($soc,$project_dir,$target_dir,$dir); |
|
|
|
move ("$dir/lib/verilog/$soc_name.h","$target_dir/sw/"); |
|
|
#use File::Copy::Recursive qw(dircopy); |
#dircopy("$dir/../src_processor/aeMB/compiler","$target_dir/sw/") or die("$!\n"); |
|
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/perl/soc_gen.pl
163,7 → 163,7
my $spin=gen_spin($min,$max,$step); |
$spin->set_value($value); |
$table->attach_defaults ($spin, 3, 4, $row, $row+1); |
$spin-> signal_connect("changed" => sub{$new_param_value{$p}=$spin->get_value_as_int();}); |
$spin-> signal_connect("value_changed" => sub{ $new_param_value{$p}=$spin->get_value_as_int(); }); |
|
# $box=def_label_spin_help_box ($param,$info, $value,$min,$max,$step, 2); |
} |
749,7 → 749,7
|
my ($category) = $model->get ($iter, CATRGORY_COLUMN); |
my ($module) = $model->get ($iter,MODULE_COLUMN ); |
my $describ=$ip->get_describtion($category,$module); |
my $describ=$ip->ip_get($category,$module,"description"); |
if($describ){ |
#print "$entry describtion is: $describ \n"; |
show_info($info,$describ); |
818,10 → 818,11
my $category =$soc->soc_get_category($id); |
my $inst =$soc->soc_get_instance_name($id); |
|
my @new=$ip->ip_get_files( $category,$module,$list_name); |
my @new=$ip->ip_get_list( $category,$module,$list_name); |
#print "@new\n"; |
foreach my $f(@new){ |
my $n="$project_dir$f"; |
if (!(-f "$n") && !(-f "$f" ) ){ |
if (!(-f "$n") && !(-f "$f" ) && !(-d "$n") && !(-d "$f" ) ){ |
$warnings=(defined $warnings)? "$warnings WARNING: Can not find \"$f\" which is required for \"$inst\" \n":"WARNING: Can not find \"$f\" which is required for \"$inst\"\n "; |
|
} |
877,17 → 878,8
#copy hdl codes in src_verilog |
|
my ($file_ref,$warnings)= get_all_files_list($soc,"hdl_files"); |
foreach my $f(@{$file_ref}){ |
my $n="$project_dir$f"; |
if (-f "$n") { |
copy ("$n","$target_dir/src_verilog/lib"); |
}elsif(-f "$f" ){ |
copy ("$f","$target_dir/src_verilog/lib"); |
|
} |
|
copy_file_and_folders($file_ref,$project_dir,"$target_dir/src_verilog/lib"); |
|
} |
show_info(\$info,$warnings) if(defined $warnings); |
|
|
907,34 → 899,23
|
|
|
# Write header files |
my $file_h=generate_header_file($soc); |
open(FILE, ">lib/verilog/$name.h") || die "Can not open: $!"; |
print FILE $file_h; |
close(FILE) || die "Error closing file: $!"; |
move ("$dir/lib/verilog/$name.h","$target_dir/sw/"); |
# Write system.h and generated file |
generate_header_file($soc,$project_dir,$target_dir,$dir); |
|
|
# Write Software files |
($file_ref,$warnings)= get_all_files_list($soc,"sw_files"); |
|
copy_file_and_folders($file_ref,$project_dir,"$target_dir/sw"); |
|
# Write Software gen files |
($file_ref,$warnings)= get_all_files_list($soc,"gen_sw_files"); |
foreach my $f(@{$file_ref}){ |
my $name= basename($f); |
#print "$f\n"; |
|
my $n="$project_dir$f"; |
if (-f "$n") { #copy file |
copy ("$n","$target_dir/sw"); |
}elsif(-f "$f" ){ |
copy ("$f","$target_dir/sw"); |
|
}elsif (-d "$n") {#copy folder |
dircopy ("$n","$target_dir/sw/$name"); |
}elsif(-d "$f" ){ |
dircopy ("$f","$target_dir/sw/$name"); |
|
} |
|
|
} |
|
} |
|
|
# Write main.c file if not exist |
my $n="$target_dir/sw/main.c"; |
if (!(-f "$n")) { |
1236,11 → 1217,7
my $info; |
if(is_hex($base_in) && is_hex($end_in)){ |
my $size=(hex ($end_in) >= hex ($base_in))? hex ($end_in) - hex ($base_in) +1 : 0; |
my $size_text= $size==0 ? 'Error': |
$size<(1 << 10)? $size: |
$size<(1 << 20)? join (' ', ($size>>10,"K")) : |
$size<(1 << 30)? join (' ', ($size>>20,"M")) : |
join (' ', ($size>>30,"G")) ; |
my $size_text= metric_conversion($size); |
$label= gen_label_in_center($size_text); |
$$newbase_ref[$number]=hex($base_in); |
$$newend_ref[$number]=hex($end_in); |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/perl/widget.pl
135,8 → 135,19
$box->pack_start( $entry, FALSE, FALSE, 3); |
return ($box,$entry); |
|
} |
} |
|
sub def_h_labeled_entry_help{ |
my ($help,$label_name,$initial)=@_; |
my $box = def_hbox(TRUE,0); |
my $label= gen_label_in_left($label_name); |
my ($b,$entry) =gen_entry_help($help,$initial); |
$box->pack_start( $label, FALSE, FALSE, 3); |
$box->pack_start( $b, FALSE, FALSE, 3); |
return ($box,$entry); |
|
} |
|
############## |
# ComboBoxEntry |
############## |
153,6 → 164,25
return $combo_box_entry; |
} |
|
########### |
# |
########### |
|
sub def_h_labeled_checkbutton{ |
my ($label_name,$status)=@_; |
my $box = def_hbox(TRUE,0); |
my $label= gen_label_in_left($label_name); |
my $check= Gtk2::CheckButton->new; |
#if($status==1) $check-> |
$box->pack_start( $label, FALSE, FALSE, 3); |
$box->pack_start( $check, FALSE, FALSE, 3); |
return ($box,$check); |
|
} |
|
|
|
|
############# |
# label |
############ |
897,4 → 927,62
} |
|
|
sub copy_file_and_folders{ |
my ($file_ref,$project_dir,$target_dir)=@_; |
|
foreach my $f(@{$file_ref}){ |
my $name= basename($f); |
my $n="$project_dir$f"; |
if (-f "$n") { #copy file |
copy ("$n","$target_dir"); |
}elsif(-f "$f" ){ |
copy ("$f","$target_dir"); |
}elsif (-d "$n") {#copy folder |
dircopy ("$n","$target_dir/$name"); |
}elsif(-d "$f" ){ |
dircopy ("$f","$target_dir/$name"); |
|
} |
} |
|
} |
|
sub read_file_cntent { |
my ($f,$project_dir)=@_; |
my $n="$project_dir$f"; |
my $str; |
if (-f "$n") { #copy file |
|
$str = do { |
local $/ = undef; |
open my $fh, "<", $n |
or die "could not open $n: $!"; |
<$fh>; |
}; |
|
}elsif(-f "$f" ){ |
$str = do { |
local $/ = undef; |
open my $fh, "<", $f |
or die "could not open $f: $!"; |
<$fh>; |
}; |
|
|
} |
return $str |
|
} |
|
|
sub metric_conversion{ |
my $size=shift; |
my $size_text= $size==0 ? 'Error': |
$size<(1 << 10)? $size: |
$size<(1 << 20)? join (' ', ($size>>10,"K")) : |
$size<(1 << 30)? join (' ', ($size>>20,"M")) : |
join (' ', ($size>>30,"G")) ; |
return $size_text; |
} |
|
1 |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/perl/soc.pm
27,7 → 27,7
if(exists ($self->{instances}{$instance_id})){ |
return 0; |
} |
my $module_name=$ip->ip_get_module_name($category,$module); |
my $module_name=$ip->ip_get($category,$module,"module_name"); |
#print "$module_name\n"; |
$self->{instances}{$instance_id}={}; |
$self->{instances}{$instance_id}{module}=$module; |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/perl/ip_gen.pl
53,7 → 53,7
my ($file,$ipgen,$soc_state,$info)=@_; |
my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$"); |
if($suffix eq '.IP'){ |
$ipgen->ipgen_set_file($file); |
$ipgen->ipgen_add("file_name",$file); |
set_state($soc_state,"load_file",0); |
|
|
74,8 → 74,11
my $vdb = read_file($file); |
my @modules=sort $vdb->get_modules($file); |
#foreach my $p(@module_list) {print "$p\n"} |
$ipgen->ipgen_set_file($file); |
$ipgen->ipgen_set_module_name($modules[0]); |
$ipgen->ipgen_add("file_name",$file); |
|
|
|
$ipgen->ipgen_add("module_name",$modules[0]); |
$ipgen->ipgen_set_module_list(@modules); |
load_deafult_setting($ipgen,$modules[0]); |
|
237,9 → 240,9
my $browse= def_image_button("icons/browse.png","Browse"); |
my $label2= gen_label_in_left(" IP name:"); |
my $entry2= gen_entry(); |
my $file= $ipgen->ipgen_get_file(); |
my $file= $ipgen->ipgen_get("file_name"); |
if(defined $file){$entry->set_text($file);} |
my $ip_name= $ipgen->ipgen_get_ip_name(); |
my $ip_name= $ipgen->ipgen_get("ip_name"); |
if(defined $ip_name){$entry2->set_text($ip_name);} |
show_info(\$info,"Please select the verilog file containig the ip module\n"); |
$browse->signal_connect("clicked"=> sub{ |
290,7 → 293,7
}); |
$entry2->signal_connect("changed"=>sub{ |
my $name=$entry2->get_text(); |
$ipgen->ipgen_set_ip_name($name); |
$ipgen->ipgen_add("ip_name",$name); |
|
}); |
$table->attach_defaults ($label, 0, 1 , $row, $row+1); |
312,7 → 315,7
my ($ipgen,$soc_state,$info,$table,$row)=@_; |
my $label= gen_label_in_left(" Select\n module:"); |
my @modules= $ipgen->ipgen_get_module_list(); |
my $saved_module=$ipgen->ipgen_get_module_name(); |
my $saved_module=$ipgen->ipgen_get("module_name"); |
my $pos=(defined $saved_module ) ? get_scolar_pos( $saved_module,@modules) : 0; |
my $combo = gen_combo(\@modules, $pos); |
my $param= def_image_button("icons/setting.png","Parameter\n setting"); |
319,7 → 322,7
my $def= def_image_button("icons/setting.png","Definition\n file setting"); |
my $label2= gen_label_in_left(" Select\n Category:"); |
my ($category,$category_entry)=gen_entry_help('Define the IP category:e.g RAM, GPIO,...'); |
my $saved_category=$ipgen->ipgen_get_category(); |
my $saved_category=$ipgen->ipgen_get("category"); |
if(defined $saved_category){$category_entry->set_text($saved_category);} |
my $ipinfo= def_image_button("icons/info.png"," IP\n Description"); |
my $header_h= def_image_button("icons/h_file.png","Add Software\n files"); |
358,7 → 361,7
}); |
$category_entry->signal_connect("changed"=> sub{ |
my $name=$category_entry->get_text(); |
$ipgen->ipgen_set_category($name); |
$ipgen->ipgen_add("category",$name); |
|
}); |
$ipinfo->signal_connect("clicked"=> sub{ |
366,11 → 369,61
|
}); |
$header_h->signal_connect("clicked"=> sub{ |
get_software_file($ipgen,$soc_state,$info); |
my %page_info; |
my $help1="The files and folder that selected here will be copied in genertated processing tile SW folder."; |
my $help2="The file listed here can contain some variable with \${var_name} format. The file genertor will replace them with their values during file generation. The variable can be selected from above listed global vairable"; |
my $help3='Define the header file for this peripheral device. You can use global vriables listed at the top. |
|
header file example |
|
#define ${IP}_REG_0 (*((volatile unsigned int *) ($BASE))) |
#define ${IP}_REG_1 (*((volatile unsigned int *) ($BASE+4))) |
|
|
#define ${IP}_WRITE_REG1(value) ${IP}_REG_1=value |
#define ${IP}_READ_REG1() ${IP}_REG_1 |
'; |
|
$page_info{0}{page_name} = "_Add exsiting file/folder"; |
$page_info{0}{filed_name}= "sw_files"; |
$page_info{0}{filed_type}= "exsiting_file/folder"; |
$page_info{0}{rename_file}=undef; |
$page_info{0}{folder_en}=1; |
$page_info{0}{help}=$help1; |
|
$page_info{1}{page_name} = "_Add file generator(s)"; |
$page_info{1}{filed_name}= "gen_sw_files"; |
$page_info{1}{filed_type}= "file_generators"; |
$page_info{1}{rename_file}=1; |
$page_info{1}{folder_en}=0; |
$page_info{1}{help}=$help2; |
|
$page_info{2}{page_name} = "_Add to system.h"; |
$page_info{2}{filed_name}= "system_h"; |
$page_info{2}{filed_type}= "file_content"; |
$page_info{2}{rename_file}=undef; |
$page_info{2}{folder_en}=0; |
$page_info{2}{help}=$help3; |
|
|
get_source_file($ipgen,$soc_state,$info,0,"Add software file(s)","SW",\%page_info); |
#get_software_file($ipgen,$soc_state,$info,0); |
|
}); |
$lib_hdl->signal_connect("clicked"=> sub{ |
get_hdl_file($ipgen,$soc_state,$info); |
my $help1="The files and folder that selected here will be copied in genertated processing tile RTL folder."; |
my %page_info; |
$page_info{0}{page_name} = "_Add exsiting HDL file/folder"; |
$page_info{0}{filed_name}= "hdl_files"; |
$page_info{0}{filed_type}= "exsiting_file/folder"; |
$page_info{0}{rename_file}=undef; |
$page_info{0}{folder_en}=1; |
$page_info{0}{help}=$help1; |
|
get_source_file($ipgen,$soc_state,$info,0,"Add HDL file(s)", "hw",\%page_info); |
|
#get_hdl_file($ipgen,$soc_state,$info); |
|
|
}); |
} |
377,8 → 430,8
|
sub load_deafult_setting{ |
my ($ipgen,$module)=@_; |
my $file= $ipgen->ipgen_get_file(); |
$ipgen->ipgen_set_module_name($module); |
my $file= $ipgen->ipgen_get("file_name"); |
$ipgen->ipgen_add("module_name",$module); |
my $vdb =read_file($file); |
my %parameters = $vdb->get_modules_parameters_not_local($module); |
my @parameters_order= $vdb->get_modules_parameters_not_local_order($module); |
395,7 → 448,7
|
} |
#add parameter order. |
$ipgen->ipgen_add_parameters_order(@parameters_order); |
$ipgen->ipgen_add("parameters_order",\@parameters_order); |
#add port order. |
$ipgen->ipgen_add_ports_order(@ports_order); |
#add ports |
439,10 → 492,9
$scrolled_win->add_with_viewport($table); |
$table->show; |
$scrolled_win->show_all; |
|
|
#print "llllllllllllllllllllllllllllllllllllll\n"; |
|
|
}); |
|
return $scrolled_win; |
519,8 → 571,8
sub get_parameter_setting { |
my ($ipgen,$soc_state,$info)=@_; |
|
my $module = $ipgen->ipgen_get_module_name(); |
my $file= $ipgen->ipgen_get_file(); |
my $module = $ipgen->ipgen_get("module_name"); |
my $file= $ipgen->ipgen_get("file_name"); |
if (!defined $file) { |
message_dialog("The input verilog file is empty"); |
return; |
583,7 → 635,7
|
|
my @parameters=$ipgen->ipgen_get_all_parameters_list(); |
my @params_order= $ipgen->ipgen_get_parameters_order(); |
my @params_order= $ipgen->ipgen_get_list("parameters_order"); |
if((@params_order)) {@parameters=@params_order;} |
|
my $ok = def_image_button('icons/select.png','OK'); |
774,7 → 826,7
|
sub get_Description{ |
my ($ipgen,$soc_state,$info)=@_; |
my $description = $ipgen->ipgen_get_description(); |
my $description = $ipgen->ipgen_get("description"); |
my $table = Gtk2::Table->new (15, 15, TRUE); |
my $window=def_popwin_size(500,500,"Add description"); |
my ($scrwin,$text_view)=create_text(); |
790,7 → 842,7
$window->destroy; |
|
my $text = $text_buffer->get_text($text_buffer->get_bounds, TRUE); |
$ipgen->ipgen_set_description($text); |
$ipgen->ipgen_add("description",$text); |
#print "$text\n"; |
|
}); |
801,204 → 853,85
} |
|
|
########### |
# get header file |
######### |
|
sub get_header_file{ |
my ($ipgen,$soc_state,$info)=@_; |
my $hdr = $ipgen->ipgen_get_hdr(); |
my $table = Gtk2::Table->new (15, 15, TRUE); |
#my $window=def_popwin_size(600,600,"Add header file"); |
my ($scrwin,$text_view)=create_text(); |
|
my $help_text= |
'Define the header file for this peripheral device. |
You can use two variable $BASEn and $IP. |
$BASE is the wishbone base addresse(s) and will be added |
during soc generation to system.h. If more than one slave |
wishbone bus are used define them as $BASE0, $BASE1 ... |
|
$IP: is the peripheral device name. When more than one |
peripheral device is allowed to be called in the SoC, it is |
recommended to add $IP to the global variables, definitions |
and functions. |
|
header file example |
|
#define $IP_REG_0 (*((volatile unsigned int *) ($BASE))) |
#define $IP_REG_1 (*((volatile unsigned int *) ($BASE+4))) |
|
|
#define $IP_WRITE_REG1(value) $IP_REG_1=value |
#define $IP_READ_REG1() $IP_REG_1 |
'; |
|
my $help=gen_label_help($help_text,"Define the header file for this peripheral device. "); |
$table->attach_defaults($help,0,15,0,1); |
$table->attach_defaults($scrwin,0,15,1,14); |
my $text_buffer = $text_view->get_buffer; |
if(defined $hdr) {$text_buffer->set_text($hdr)}; |
|
|
|
my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef); |
$scrolled_win->set_policy( "automatic", "automatic" ); |
$scrolled_win->add_with_viewport($table); |
|
#$window->add($table); |
#$window->show_all(); |
return ($scrolled_win,$text_buffer); |
|
} |
|
############# |
# get hdl files |
############ |
sub get_hdl_file{ |
my ($ipgen,$soc_state,$info)=@_; |
my $table = Gtk2::Table->new (15, 15, TRUE); |
my $window=def_popwin_size(600,600,"Add HDL file()s"); |
my @saved_files=$ipgen->ipgen_get_files_list("hdl_files"); |
my $ok=def_image_button("icons/select.png",' Ok '); |
my $scrwin=gen_file_list($ipgen,"hdl_files",\@saved_files,$ok); |
|
my $label=gen_label_in_left("Selecet the design files you want to include for the IP core"); |
my $brows=def_image_button("icons/browse.png",' Browse'); |
$table->attach_defaults($label,0,10,0,1); |
$table->attach_defaults($brows,10,12,0,1); |
$table->attach_defaults($scrwin,0,15,1,14); |
$table->attach_defaults($ok,6,9,14,15); |
|
my $dir = Cwd::getcwd(); |
my $project_dir = abs_path("$dir/../../"); #mpsoc directory address |
|
|
$brows->signal_connect("clicked"=> sub { |
my @files; |
my $dialog = Gtk2::FileChooserDialog->new( |
'Select a File', |
undef, |
'open', |
'gtk-cancel' => 'cancel', |
'gtk-ok' => 'ok', |
); |
|
my $filter = Gtk2::FileFilter->new(); |
my $dir = Cwd::getcwd(); |
$dialog->set_current_folder ("$dir/..") ; |
$dialog->set_select_multiple(TRUE); |
|
if ( "ok" eq $dialog->run ) { |
@files = $dialog->get_filenames; |
|
@saved_files=$ipgen->ipgen_get_files_list("hdl_files"); |
foreach my $p (@files){ |
#remove $project_dir form beginig of each file |
$p =~ s/$project_dir//; |
if(! grep (/^$p$/,@saved_files)){push(@saved_files,$p)}; |
|
} |
$ipgen->ipgen_set_files_list("hdl_files",\@saved_files); |
$window->destroy; |
get_hdl_file($ipgen,$soc_state,$info); |
|
#$$entry_ref->set_text($file); |
|
#print "file = $file\n"; |
} |
$dialog->destroy; |
|
|
|
} );# # ,\$entry); |
|
|
|
|
|
$ok->signal_connect("clicked"=> sub { |
|
|
|
$window->destroy; |
|
#my $text = $text_buffer->get_text($text_buffer->get_bounds, TRUE); |
#$ipgen->ipgen_set_hdr($text); |
#print "$text\n"; |
|
}); |
|
$window->add($table); |
$window->show_all(); |
|
} |
|
|
|
|
########## |
# |
# gen_file_list |
######### |
|
sub gen_file_list{ |
my ($ipgen,$list_name,$ref,$ok)=@_; |
my @files=@{$ref}; |
my $file_num= scalar @files; |
my ($ipgen,$list_name,$window,$rename_file_en)=@_; |
|
|
my $table=def_table(10,10,TRUE);# my ($row,$col,$homogeneous)=@_; |
my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef); |
my $ok=def_image_button("icons/select.png",' Ok '); |
|
$scrolled_win->set_policy( "automatic", "automatic" ); |
$scrolled_win->add_with_viewport($table); |
|
|
$table->attach_defaults (gen_label_in_center("File path"), 0, 5 , 0, 1); |
$table->attach_defaults (gen_label_help("The target name can contain any of Global variables e.g \$IP\$.h","Copy as"), 5, 9 , 0, 1) if(defined $rename_file_en); |
my $col=0; |
my $row=0; |
my $row=1; |
my @files= $ipgen->ipgen_get_list($list_name); #@{$ref}; |
my $file_num= scalar @files; |
foreach my $p(@files){ |
my $entry=gen_entry($p); |
my $remove=def_image_button("icons/cancel.png"); |
$table->attach_defaults ($entry, 0, 9 , $row, $row+1); |
$table->attach_defaults ($remove, 9,10 , $row, $row+1); |
$row++; |
$remove->signal_connect("clicked"=> sub { |
my @saved_files=$ipgen->ipgen_get_files_list($list_name); |
@saved_files=remove_scolar_from_array(\@saved_files,$p); |
$ipgen->ipgen_set_files_list($list_name,\@saved_files); |
$entry->destroy; |
$remove->destroy; |
my ($path,$rename)=split('frename_sep_t',$p); |
my $entry=gen_entry($path); |
my $entry2=gen_entry($rename) ; |
my $remove=def_image_button("icons/cancel.png"); |
$table->attach_defaults ($entry, 0, 5 , $row, $row+1); |
$table->attach_defaults ($entry2, 5, 9 , $row, $row+1) if(defined $rename_file_en); |
$table->attach_defaults ($remove, 9,10 , $row, $row+1); |
$row++; |
$remove->signal_connect("clicked"=> sub { |
my @saved_files=$ipgen->ipgen_get_list($list_name); |
@saved_files=remove_scolar_from_array(\@saved_files,$p); |
$ipgen->ipgen_add($list_name,\@saved_files); |
$entry->destroy; |
$entry2->destroy if(defined $rename_file_en); |
$remove->destroy; |
|
}); |
$ok->signal_connect("clicked"=> sub { |
if(defined $entry){ |
my $n= $entry->get_text(); |
if($p ne $n){ |
my @saved_files=$ipgen->ipgen_get_files_list($list_name); |
@saved_files=replace_in_array(\@saved_files,$p, $n); |
$ipgen->ipgen_set_files_list($list_name,\@saved_files); |
}); |
$ok->signal_connect("clicked"=> sub { |
if(defined $entry){ |
my $n= $entry->get_text(); |
if(defined $rename_file_en){ |
$n= $n.'frename_sep_t'.$entry2->get_text() ; |
} |
if($p ne $n){ |
my @saved_files=$ipgen->ipgen_get_list($list_name); |
@saved_files=replace_in_array(\@saved_files,$p, $n); |
$ipgen->ipgen_add($list_name,\@saved_files); |
} |
|
} |
|
} |
|
|
|
}); |
}); |
|
#my $seph = Gtk2::HSeparator->new; |
#$table->attach_defaults ($seph, 0, 10 , $row, $row+1); |
#$row++; |
#my $seph = Gtk2::HSeparator->new; |
#$table->attach_defaults ($seph, 0, 10 , $row, $row+1); |
#$row++; |
|
} |
|
|
|
|
$ok->signal_connect("clicked"=> sub { |
$window->destroy; |
}); |
|
# while( $row<10){ |
# my $label=gen_label_in_left(' '); |
# $table->attach_defaults ($label, 0, 1 , $row, $row+1);$row++; |
#} |
|
|
return $scrolled_win; |
|
return ($scrolled_win,$ok); |
} |
|
|
1079,7 → 1012,7
my $advance_button=def_image_button('icons/advance.png','separate'); |
$table->attach_defaults ($type_box, $positions[2], $positions[3], $row, $row+1); |
$table->attach_defaults ($advance_button, $positions[3], $positions[4], $row, $row+1); |
$type_spin->signal_connect("changed"=>sub{ |
$type_spin->signal_connect("value_changed"=>sub{ |
my $wiget=shift; |
my $num=$wiget->get_value_as_int(); |
$ipgen->ipgen_add_soket($p,'num',$num); |
1163,7 → 1096,7
$type_box->pack_start($name_setting,FALSE,FALSE,0); |
$type_spin->set_value($value); |
$table->attach_defaults ($type_box, $positions[2], $positions[3], $row, $row+1); |
$type_spin->signal_connect("changed"=>sub{ |
$type_spin->signal_connect("value_changed"=>sub{ |
my $wiget=shift; |
my $num=$wiget->get_value_as_int(); |
$ipgen->ipgen_add_plug($q,'num',$num); |
1207,8 → 1140,10
return $table; |
|
} |
######## |
# get_intfc_setting |
######## |
|
|
sub get_intfc_setting{ |
|
my ($ipgen,$soc_state,$intfc_name, $intfc_type)=@_; |
1299,6 → 1234,7
my $name_combo=gen_combo(\@list,$pos); |
my $sbox=def_hbox(FALSE,0); |
my $widget; |
my $size_lab; |
my @l=("Fixed","Parameterizable"); |
|
if(!defined $saved_width){ |
1311,6 → 1247,8
$pos= 0; |
$widget=gen_spin(1,31,1); |
$widget->set_value($saved_width); |
my $d=2**$saved_width; |
$size_lab=gen_label_in_left(metric_conversion($d). " Bytes"); |
} else{ |
$pos= 1; |
my @parameters=$ipgen->ipgen_get_all_parameters_list(); |
1317,6 → 1255,7
my $p=get_scolar_pos($saved_width,@parameters); |
|
$widget=gen_combo(\@parameters, $p); |
$size_lab=gen_label_in_left(" "); |
|
} |
|
1329,16 → 1268,38
#$widget->set_value($saved_width); |
$sbox->pack_start($comb,FALSE,FALSE,3); |
$sbox->pack_end($widget,FALSE,FALSE,3); |
|
$sbox->pack_end($size_lab,FALSE,FALSE,3); |
$comb->signal_connect('changed'=>sub{ |
my $condition=$comb->get_active_text(); |
$widget->destroy; |
$size_lab->destroy; |
my @parameters=$ipgen->ipgen_get_all_parameters_list(); |
$widget=($condition eq "Fixed" )? gen_spin(1,31,1):gen_combo(\@parameters, 0); |
$size_lab=($condition eq "Fixed" )? gen_label_in_left("2 Bytes"): gen_label_in_left(" "); |
$sbox->pack_end($widget,FALSE,FALSE,3); |
$sbox->pack_end($size_lab,FALSE,FALSE,3); |
$sbox->show_all(); |
$widget->signal_connect('changed'=>sub{ |
$size_lab->destroy; |
my $in=$comb->get_active_text(); |
my $width=($in eq "Fixed" )? $widget->get_value_as_int(): $widget->get_active_text() ; |
my $d=($in eq "Fixed" )? 2**$width:0; |
|
$size_lab=($in eq "Fixed" )? gen_label_in_left( metric_conversion($d). " Bytes"):gen_label_in_left(" "); |
$sbox->pack_end($size_lab,FALSE,FALSE,3); |
$sbox->show_all(); |
}); |
}); |
|
$widget->signal_connect('changed'=>sub{ |
$size_lab->destroy; |
my $in=$comb->get_active_text(); |
my $width=($in eq "Fixed" )? $widget->get_value_as_int(): $widget->get_active_text() ; |
my $d=($in eq "Fixed" )? 2**$width:0; |
|
$size_lab=($in eq "Fixed" )? gen_label_in_left(metric_conversion($d). " Bytes"):gen_label_in_left(" "); |
$sbox->pack_end($size_lab,FALSE,FALSE,3); |
$sbox->show_all(); |
}); |
|
$table->attach_defaults($name_combo,2,5,$i+1,$i+2); |
$table->attach_defaults($sbox,5,6,$i+1,$i+2); |
1586,14 → 1547,14
|
sub generate_ip{ |
my $ipgen=shift; |
my $name=$ipgen->ipgen_get_module_name(); |
my $category=$ipgen->ipgen_get_category(); |
my $ip_name= $ipgen->ipgen_get_ip_name(); |
my $name=$ipgen->ipgen_get("module_name"); |
my $category=$ipgen->ipgen_get("category"); |
my $ip_name= $ipgen->ipgen_get("ip_name"); |
#check if name has been set |
if(defined ($name) && defined ($category)){ |
if (!defined $ip_name) {$ip_name= $name} |
#check if any source file has been added for this ip |
my @l=$ipgen->ipgen_get_files_list("hdl_files"); |
my @l=$ipgen->ipgen_get_list("hdl_files"); |
if( scalar @l ==0){ |
my $mwindow; |
my $dialog = Gtk2::MessageDialog->new ($mwindow, |
1668,7 → 1629,7
$file = $dialog->get_filename; |
my ($name,$path,$suffix) = fileparse("$file",qr"\..[^.]*$"); |
if($suffix eq '.IP'){ |
$ipgen->ipgen_set_file($file); |
$ipgen->ipgen_add("file_name",$file); |
set_state($soc_state,"load_file",0); |
} |
} |
1680,31 → 1641,83
|
|
|
|
|
|
############ |
# get_source_file |
########### |
# get header file |
######### |
|
sub get_sw_file_folder{ |
my ($ipgen,$soc_state,$info,$window)=@_; |
my @sw_dir = $ipgen->ipgen_get_files_list("sw_files"); |
my $table = Gtk2::Table->new (15, 15, TRUE); |
|
|
sub get_source_file{ |
my($ipgen,$soc_state,$info,$page,$title,$dest,$page_info_ref)=@_; |
|
|
my $var_list='${parameter_name}: Verilog module parameter values. |
|
${BASE}: is the wishbone base addresse(s) and will be added during soc generation to system.h. If more than one slave wishbone bus are used define them as ${BASE0}, ${BASE1}... . |
|
${IP}: is the peripheral device instance name. |
|
${CORE}: is the peripheral device module name.'; |
my $var_help=gen_button_message($var_list,"icons/info.png","Global variables"); |
|
my($width,$hight)=max_win_size(); |
my $window = def_popwin_size($width*2/3,$hight*2/3,$title); |
|
my $help=gen_label_help("The files and folder that selected here will be copied in genertated processing tile SW folder."); |
my $notebook=source_notebook($ipgen,$soc_state,$info,$window,$page,$dest,$page_info_ref); |
my $table=def_table (15, 15, TRUE); |
|
|
$table->attach_defaults ($var_help, 5, 7, 0, 1); |
$table->attach_defaults ($notebook , 0, 15, 1, 15); |
|
$window->add($table); |
$window->show_all; |
return $window; |
|
$table->attach_defaults($help,0,15,0,1); |
my $ok=def_image_button("icons/select.png",' Ok '); |
my $scrwin=gen_file_list($ipgen,"sw_files",\@sw_dir,$ok); |
} |
|
########## |
# source_notebook |
########## |
|
sub source_notebook{ |
my($ipgen,$soc_state,$info,$window,$page,$dest,$page_info_ref)=@_; |
my $notebook = Gtk2::Notebook->new; |
my %page_info=%{$page_info_ref}; |
foreach my $p (sort keys %page_info){ |
my $page_ref; |
$page_ref=get_file_folder($ipgen,$soc_state,$info,$window,$p,$page_info_ref) if($page_info{$p}{filed_type} eq "exsiting_file/folder"); |
$page_ref=get_file_folder($ipgen,$soc_state,$info,$window,$p,$page_info_ref) if($page_info{$p}{filed_type} eq "file_generators"); |
$page_ref=get_file_content($ipgen,$soc_state,$info,$window,$page_info{$p},$page_info_ref) if($page_info{$p}{filed_type} eq "file_content"); |
$notebook->append_page ($page_ref,Gtk2::Label->new_with_mnemonic ($page_info{$p}{page_name})); |
|
} |
$notebook->show_all; |
$notebook->set_current_page($page) if(defined $page); |
return $notebook; |
|
} |
|
########## |
# get_file_folder |
######### |
|
sub get_file_folder{ |
my ($ipgen,$soc_state,$info,$window,$page,$page_info_ref)=@_; |
my %page_info=%{$page_info_ref}; |
my @sw_dir = $ipgen->ipgen_get_list($page_info{$page}{filed_name}); |
my $table = Gtk2::Table->new (15, 15, TRUE); |
my $help=gen_label_help($page_info{$page}{help}); |
$table->attach_defaults($help,0,2,0,1); |
my ($scrwin,$ok)=gen_file_list($ipgen,$page_info{$page}{filed_name},$window,$page_info{$page}{rename_file}); |
|
my $label=gen_label_in_left("Selecet file(s):"); |
my $brows=def_image_button("icons/browse.png",' Browse'); |
$table->attach_defaults($label,1,3,1,2); |
$table->attach_defaults($brows,3,5,1,2); |
my $label2=gen_label_in_left("Selecet folder(s):"); |
my $brows2=def_image_button("icons/browse.png",' Browse'); |
$table->attach_defaults($label2,7,9,1,2); |
$table->attach_defaults($brows2,9,11,1,2); |
$table->attach_defaults($label,2,4,0,1); |
$table->attach_defaults($brows,4,6,0,1); |
|
my $dir = Cwd::getcwd(); |
my $project_dir = abs_path("$dir/../../"); #mpsoc directory address |
1726,170 → 1739,132
$dialog->set_select_multiple(TRUE); |
|
if ( "ok" eq $dialog->run ) { |
@files = $dialog->get_filenames; |
|
@sw_dir=$ipgen->ipgen_get_files_list("sw_files"); |
@files = $dialog->get_filenames; |
@sw_dir=$ipgen->ipgen_get_list($page_info{$page}{filed_name}); |
foreach my $p (@files){ |
#remove $project_dir form beginig of each file |
$p =~ s/$project_dir//; |
$p =~ s/$project_dir//; |
my ($name,$path,$suffix) = fileparse("$p",qr"\..[^.]*$"); |
$p=$p.'frename_sep_t'.$name.$suffix if (defined $page_info{$page}{rename_file}); |
if(! grep (/^$p$/,@sw_dir)){push(@sw_dir,$p)}; |
|
} |
|
$ipgen->ipgen_set_files_list("sw_files",\@sw_dir); |
get_software_file($ipgen,$soc_state,$info); |
} |
$ipgen->ipgen_add($page_info{$page}{filed_name},\@sw_dir); |
get_source_file($ipgen,$soc_state,$info,$page,"Add software file(s)","SW",$page_info_ref); |
$window->destroy; |
|
|
#$$entry_ref->set_text($file); |
|
#print "file = $file\n"; |
} |
$dialog->destroy; |
|
|
|
} );# # ,\$entry); |
|
|
|
|
$brows2->signal_connect("clicked"=> sub { |
my @files; |
if($page_info{$page}{folder_en} eq 1){ |
my $label2=gen_label_in_left("Selecet folder(s):"); |
my $brows2=def_image_button("icons/browse.png",' Browse'); |
$table->attach_defaults($label2,7,9,0,1); |
$table->attach_defaults($brows2,9,11,0,1); |
|
$brows2->signal_connect("clicked"=> sub { |
my @files; |
|
my $dialog = Gtk2::FileChooserDialog->new( |
'Select Folder(s)', |
undef, |
'select-folder', |
'gtk-cancel' => 'cancel', |
'gtk-ok' => 'ok', |
); |
|
|
|
|
my $filter = Gtk2::FileFilter->new(); |
my $dir = Cwd::getcwd(); |
$dialog->set_current_folder ("$dir/..") ; |
$dialog->set_select_multiple(TRUE); |
my $dialog = Gtk2::FileChooserDialog->new( |
'Select Folder(s)', |
undef, |
'select-folder', |
'gtk-cancel' => 'cancel', |
'gtk-ok' => 'ok', |
); |
|
my $filter = Gtk2::FileFilter->new(); |
my $dir = Cwd::getcwd(); |
$dialog->set_current_folder ("$dir/..") ; |
$dialog->set_select_multiple(TRUE); |
|
if ( "ok" eq $dialog->run ) { |
@files = $dialog->get_filenames; |
|
@sw_dir=$ipgen->ipgen_get_files_list("sw_files"); |
foreach my $p (@files){ |
#remove $project_dir form beginig of each file |
$p =~ s/$project_dir//; |
if(! grep (/^$p$/,@sw_dir)){push(@sw_dir,$p)}; |
|
} |
|
$ipgen->ipgen_set_files_list("sw_files",\@sw_dir); |
get_software_file($ipgen,$soc_state,$info); |
$window->destroy; |
|
|
#$$entry_ref->set_text($file); |
if ( "ok" eq $dialog->run ) { |
@files = $dialog->get_filenames; |
|
@sw_dir=$ipgen->ipgen_get_list($page_info{$page}{filed_name}); |
foreach my $p (@files){ |
#remove $project_dir form beginig of each file |
$p =~ s/$project_dir//; |
if(! grep (/^$p$/,@sw_dir)){push(@sw_dir,$p)}; |
|
} |
|
$ipgen->ipgen_add($page_info{$page}{filed_name},\@sw_dir); |
get_source_file($ipgen,$soc_state,$info,$page,"Add software file(s)","SW",$page_info_ref); |
$window->destroy; |
|
|
#$$entry_ref->set_text($file); |
|
#print "file = $file\n"; |
} |
$dialog->destroy; |
|
#print "file = $file\n"; |
} |
$dialog->destroy; |
|
|
|
} );# # ,\$entry); |
} );# # ,\$entry); |
} |
|
|
|
$table->attach_defaults($scrwin,0,15,1,14); |
$table->attach_defaults($ok,6,9,14,15); |
|
return ($table) |
|
|
$table->attach_defaults($scrwin,0,15,2,15); |
#$table->attach_defaults($ok,6,9,14,15); |
|
|
|
|
|
|
my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef); |
$scrolled_win->set_policy( "automatic", "automatic" ); |
$scrolled_win->add_with_viewport($table); |
|
#$window->add($table); |
#$window->show_all(); |
return ($scrolled_win); |
|
} |
|
|
|
########### |
# get_file_content |
######### |
|
sub get_file_content{ |
my ($ipgen,$soc_state,$info,$window,$page_info_ref)=@_; |
my %page_info=%{$page_info_ref}; |
#my $hdr = $ipgen->ipgen_get_hdr(); |
my $hdr = $ipgen-> ipgen_get($page_info{filed_name}); |
my $table = Gtk2::Table->new (14, 15, TRUE); |
#my $window=def_popwin_size(600,600,"Add header file"); |
my ($scrwin,$text_view)=create_text(); |
|
sub get_software_file{ |
my($ipgen,$soc_state,$info)=@_; |
my $help=gen_label_help($page_info{help}); |
$table->attach_defaults($help,0,8,0,1); |
$table->attach_defaults($scrwin,0,15,1,14); |
my $text_buffer = $text_view->get_buffer; |
if(defined $hdr) {$text_buffer->set_text($hdr)}; |
|
my $ok=def_image_button("icons/select.png",' Save '); |
$ok->signal_connect("clicked"=> sub {# |
my $text = $text_buffer->get_text($text_buffer->get_bounds, TRUE); |
$ipgen->ipgen_add($page_info{filed_name},$text); |
$window->destroy; |
|
}); |
|
$table->attach_defaults($ok,6,9,14,15); |
return ($table); |
|
} |
|
my $notebook = Gtk2::Notebook->new; |
#$hbox->pack_start ($notebook, TRUE, TRUE, 0); |
|
my($width,$hight)=max_win_size(); |
my $window = def_popwin_size($width*2/3,$hight*2/3,"Add Software file(s)"); |
|
|
my ($sw_dir)=get_sw_file_folder($ipgen,$soc_state,$info,$window); |
$notebook->append_page ($sw_dir,Gtk2::Label->new_with_mnemonic ("_Add file/folder")); |
|
my ($hdr_file,$text_buffer)= get_header_file($ipgen,$soc_state,$info); |
$notebook->append_page ($hdr_file,Gtk2::Label->new_with_mnemonic ("_Add hedaer file")); |
|
|
|
#my $socgen=socgen_main(); |
#$notebook->append_page ($socgen,Gtk2::Label->new_with_mnemonic ("_Processing tile generator")); |
|
#my $mpsocgen =mpsocgen_main(); |
#$notebook->append_page ($mpsocgen,Gtk2::Label->new_with_mnemonic ("_NoC based MPSoC generator")); |
|
|
my $table=def_table (15, 15, TRUE); |
|
|
my $scrolled_win = new Gtk2::ScrolledWindow (undef, undef); |
$scrolled_win->set_policy( "automatic", "automatic" ); |
$scrolled_win->add_with_viewport($table); |
|
|
|
|
|
|
|
|
my $ok=def_image_button("icons/select.png",' Ok '); |
$ok->signal_connect("clicked"=> sub { |
$window->destroy; |
|
my $text = $text_buffer->get_text($text_buffer->get_bounds, TRUE); |
$ipgen->ipgen_set_hdr($text); |
#print "$text\n"; |
|
}); |
|
#$table->attach_defaults ($event_box, $col, $col+1, $row, $row+1); |
$table->attach_defaults ($ok , 7, 9, 14, 15); |
|
$table->attach_defaults ($notebook , 0, 15, 0, 14); |
# |
$window->add($scrolled_win); |
$window->show_all; |
return $window; |
|
|
|
|
} |
|
|
|
|
|
############ |
# get_unused_intfc_ports_list |
########### |
1900,7 → 1875,7
my ($name_ref,$ref)=get_list_of_all_interfaces($ipgen); |
my @interfaces_name=@{$name_ref}; |
my @interfaces=@{$ref}; |
$ipgen->ipgen_remove_unused_intfc_port( ); |
$ipgen->ipgen_remove("unused"); |
foreach my $intfc_name (@interfaces) |
{ |
#print "$intfc_name\n"; |
1946,6 → 1921,21
} |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
############ |
# main |
############ |
2003,7 → 1993,7
|
my ($state,$timeout)= get_state($soc_state); |
if($state eq "load_file"){ |
my $file=$ipgen->ipgen_get_file(); |
my $file=$ipgen->ipgen_get("file_name"); |
my $pp= eval { do $file }; |
clone_obj($ipgen,$pp); |
|
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/perl/ip_gen.pm
34,39 → 34,8
return $self; |
} |
|
sub ipgen_set_file{ |
my ($self,$file)=@_; |
$self->{file_name}=$file; |
} |
|
|
|
sub ipgen_get_file{ |
my $self=shift; |
return $self->{file_name}; |
} |
|
sub ipgen_set_module_name{ |
my ($self,$module)=@_; |
$self->{module_name}=$module; |
} |
|
sub ipgen_get_module_name{ |
my ($self)=@_; |
return $self->{module_name}; |
} |
|
sub ipgen_set_ip_name{ |
my ($self,$name)=@_; |
$self->{ip_name}=$name; |
} |
|
sub ipgen_get_ip_name{ |
my ($self)=@_; |
return $self->{ip_name}; |
} |
|
|
sub ipgen_set_module_list{ |
my ($self,@list)=@_; |
$self->{modules}={}; |
101,20 → 70,8
|
|
|
sub ipgen_add_parameters_order{ |
my ($self,@parameters_order)=@_; |
$self->{parameters_order}=\@parameters_order; |
|
|
} |
|
|
sub ipgen_get_parameters_order{ |
my $self=shift; |
my @r; |
@r = @{$self->{parameters_order}} if (defined $self->{parameters_order}); |
return @r; |
} |
|
sub ipgen_push_parameters_order{ |
my ($self,$param)=@_; |
378,44 → 335,11
} |
|
|
sub ipgen_set_category{ |
my ($self,$category)=@_; |
if(defined $category){ |
$self->{category}=$category; |
|
} |
|
} |
|
|
|
sub ipgen_get_category{ |
my ($self)=@_; |
my $category; |
if(exists ($self->{category})){ |
$category=$self->{category}; |
} |
return $category; |
} |
|
|
sub ipgen_get_description{ |
my ($self)=@_; |
my $description; |
if(exists ($self->{description})){ |
$description=$self->{description}; |
} |
return $description; |
} |
|
sub ipgen_set_description{ |
my ($self,$description)=@_; |
$self->{description}=$description; |
|
|
} |
|
|
sub ipgen_save_wb_addr{ |
my ($self,$plug,$num,$addr,$width)=@_; |
$self->{plugs}{$plug}{$num}{addr}=$addr; |
473,27 → 397,35
|
} |
|
sub ipgen_set_hdr{ |
my ($self,$hdr)=@_; |
$self->{header}=$hdr; |
} |
|
|
sub ipgen_add_unused_intfc_port{ |
my ($self,$intfc_name,$port)=@_; |
push(@{$self->{unused}{$intfc_name}},$port); |
} |
|
sub ipgen_get_hdr{ |
my ($self)=@_; |
my $hdr; |
if(exists ($self->{header})){ |
$hdr=$self->{header}; |
|
} |
return $hdr; |
|
|
|
|
#add,read,remove object fileds |
|
sub ipgen_add{ |
my ($self,$filed_name,$filed_data)=@_; |
$self->{$filed_name}=$filed_data; |
} |
|
sub ipgen_remove{ |
my ($self,$filed_name)=@_; |
$self->{$filed_name}=undef; |
} |
|
sub ipgen_get{ |
my ($self,$filed_name)=@_; |
return $self->{$filed_name} |
} |
|
|
sub ipgen_get_files_list{ |
sub ipgen_get_list{ |
my ($self,$list_name)=@_; |
my @l; |
if ( defined $self->{$list_name} ){ |
504,28 → 436,8
} |
|
|
sub ipgen_set_files_list{ |
my ($self,$list_name,$ref)=@_; |
$self->{$list_name}= $ref; |
} |
|
|
sub ipgen_add_unused_intfc_port{ |
my ($self,$intfc_name,$port)=@_; |
push(@{$self->{unused}{$intfc_name}},$port); |
} |
|
sub ipgen_get_unused_intfc_ports{ |
my $self=shift; |
return $self->{unused}; |
|
} |
|
sub ipgen_remove_unused_intfc_port{ |
my $self=shift; |
$self->{unused}=undef; |
} |
|
###################################### |
|
|
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/altera_jtag_uart.IP
3,120 → 3,120
'/mpsoc/src_peripheral/jtag/altera_jtag_uart_wb.v' |
], |
'ip_name' => 'altera_jtag_uart', |
'modules' => { |
'qsys_jtag_uart_0_scfifo_w' => {}, |
'qsys_jtag_uart_0_scfifo_r' => {}, |
'qsys_jtag_uart_0_sim_scfifo_r' => {}, |
'qsys_jtag_uart_0' => {}, |
'altera_jtag_uart_wb' => {}, |
'qsys_jtag_uart_0_sim_scfifo_w' => {} |
}, |
'plugs' => { |
'clk' => { |
'clk' => {}, |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num' |
}, |
'reset' => { |
'reset' => {}, |
'value' => 1, |
'0' => { |
'name' => 'reset' |
}, |
'type' => 'num' |
}, |
'interrupt_peripheral' => { |
'interrupt_peripheral' => {}, |
'value' => 1, |
'0' => { |
'name' => 'interrupt_peripheral' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'reset' => { |
'reset' => {}, |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'clk' => { |
'clk' => {}, |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'wb_slave' => { |
'value' => 1, |
'0' => { |
'width' => 5, |
'name' => 'wb_slave', |
'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller' |
}, |
'value' => 1, |
'type' => 'num', |
'wb_slave' => {} |
} |
}, |
'modules' => { |
'qsys_jtag_uart_0_scfifo_w' => {}, |
'qsys_jtag_uart_0_scfifo_r' => {}, |
'altera_jtag_uart_wb' => {}, |
'qsys_jtag_uart_0' => {}, |
'qsys_jtag_uart_0_sim_scfifo_r' => {}, |
'qsys_jtag_uart_0_sim_scfifo_w' => {} |
}, |
'ports' => { |
'wb_irq' => { |
'intfc_name' => 'plug:interrupt_peripheral[0]', |
'intfc_port' => 'int_o', |
'intfc_name' => 'plug:interrupt_peripheral[0]', |
'range' => '', |
'type' => 'output' |
}, |
'stb_i' => { |
'intfc_port' => 'stb_i', |
'cyc_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'cyc_i', |
'range' => '', |
'type' => 'input' |
}, |
'cyc_i' => { |
'intfc_port' => 'cyc_i', |
'stb_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'stb_i', |
'range' => '', |
'type' => 'input' |
}, |
'dat_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => ' 31: 0', |
'type' => 'input' |
}, |
'ack_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'ack_o', |
'range' => '', |
'type' => 'output' |
}, |
'rst' => { |
'intfc_name' => 'plug:reset[0]', |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'range' => '', |
'type' => 'input' |
}, |
'ack_o' => { |
'intfc_port' => 'ack_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'output' |
}, |
'readyfordata' => { |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'output' |
}, |
'dat_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_o', |
'range' => ' 31: 0', |
'type' => 'output' |
}, |
'adr_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'adr_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'input' |
}, |
'dat_o' => { |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => ' 31: 0', |
'type' => 'output' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]', |
'range' => '', |
'type' => 'input' |
}, |
'we_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'we_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'input' |
}, |
'dataavailable' => { |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'output' |
} |
134,11 → 134,11
] |
}, |
'category' => 'Jtag', |
'header' => ' #define $IP_DATA_REG (*((volatile unsigned int *) ($BASE))) |
#define $IP_CONTROL_REG (*((volatile unsigned int *) ($BASE+4))) |
#define $IP_CONTROL_WSPACE_MSK 0xFFFF0000 |
#define $IP_DATA_RVALID_MSK 0x00008000 |
#define $IP_DATA_DATA_MSK 0x000000FF |
'system_h' => '#define ${IP}_DATA_REG (*((volatile unsigned int *) ($BASE))) |
#define ${IP}_CONTROL_REG (*((volatile unsigned int *) ($BASE+4))) |
#define ${IP}_CONTROL_WSPACE_MSK 0xFFFF0000 |
#define ${IP}_DATA_RVALID_MSK 0x00008000 |
#define ${IP}_DATA_DATA_MSK 0x000000FF |
|
//////////////////////////////*basic function for jtag_uart*//////////////////////////////////////// |
void jtag_putchar(char ch); |
147,16 → 147,16
char inbyte(){return jtag_getchar();} |
|
void jtag_putchar(char ch){ //print one char from jtag_uart |
while(($IP_CONTROL_REG&$IP_CONTROL_WSPACE_MSK)==0); |
$IP_DATA_REG=ch; |
while((${IP}_CONTROL_REG&${IP}_CONTROL_WSPACE_MSK)==0); |
${IP}_DATA_REG=ch; |
} |
|
char jtag_getchar(void){ //get one char from jtag_uart |
unsigned int data; |
data=$IP_DATA_REG; |
while(!(data & $IP_DATA_RVALID_MSK)) //wait for terminal input |
data=$IP_DATA_REG; |
return (data&$IP_DATA_DATA_MSK); |
data=${IP}_DATA_REG; |
while(!(data & ${IP}_DATA_RVALID_MSK)) //wait for terminal input |
data=${IP}_DATA_REG; |
return (data&${IP}_DATA_DATA_MSK); |
} |
|
int jtag_scanstr(char* buf){ //scan string until <ENTER> to buf, return str length |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/ext_int.IP
3,6 → 3,45
'/mpsoc/src_peripheral/ext_int/ext_int.v' |
], |
'ip_name' => 'ext_int', |
'plugs' => { |
'interrupt_peripheral' => { |
'interrupt_peripheral' => {}, |
'value' => 1, |
'0' => { |
'name' => 'interrupt' |
}, |
'type' => 'num' |
}, |
'reset' => { |
'reset' => {}, |
'value' => 1, |
'0' => { |
'name' => 'reset' |
}, |
'type' => 'num' |
}, |
'clk' => { |
'clk' => {}, |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num' |
}, |
'wb_slave' => { |
'value' => 1, |
'0' => { |
'width' => 5, |
'name' => 'wb', |
'addr' => '0x9e00_0000 0x9eff_ffff IDE Controller' |
}, |
'type' => 'num', |
'wb_slave' => {} |
} |
}, |
'modules' => { |
'ext_int' => {} |
}, |
'parameters' => { |
'Aw' => { |
'info' => undef, |
11,20 → 50,27
'content' => '', |
'type' => 'Fixed' |
}, |
'TAGw' => { |
'SELw' => { |
'info' => undef, |
'deafult' => '3', |
'deafult' => '4', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed' |
}, |
'SELw' => { |
'TAGw' => { |
'info' => undef, |
'deafult' => '4', |
'deafult' => '3', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed' |
}, |
'Dw' => { |
'info' => undef, |
'deafult' => '32', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed' |
}, |
'EXT_INT_NUM' => { |
'info' => 'number of external interrupt pins.', |
'deafult' => '3', |
31,148 → 77,102
'global_param' => 0, |
'content' => '1,32,1', |
'type' => 'Spin-button' |
}, |
'Dw' => { |
'info' => undef, |
'deafult' => '32', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed' |
} |
} |
}, |
'modules' => { |
'ext_int' => {} |
}, |
'plugs' => { |
'clk' => { |
'clk' => {}, |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'reset' => { |
'reset' => {}, |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'interrupt_peripheral' => { |
'interrupt_peripheral' => {}, |
'0' => { |
'name' => 'interrupt' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'wb_slave' => { |
'0' => { |
'width' => 5, |
'name' => 'wb', |
'addr' => '0x9e00_0000 0x9eff_ffff IDE Controller' |
}, |
'value' => 1, |
'type' => 'num', |
'wb_slave' => {} |
} |
}, |
'ports' => { |
'sa_tag_i' => { |
'intfc_port' => 'tag_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'tag_i', |
'range' => 'TAGw-1 : 0', |
'type' => 'input' |
}, |
'sa_dat_o' => { |
'sa_rty_o' => { |
'intfc_port' => 'rty_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0', |
'range' => '', |
'type' => 'output' |
}, |
'sa_rty_o' => { |
'sa_dat_o' => { |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'rty_o', |
'range' => '', |
'range' => 'Dw-1 : 0', |
'type' => 'output' |
}, |
'sa_sel_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'sel_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'SELw-1 : 0', |
'type' => 'input' |
}, |
'sa_dat_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Dw-1 : 0', |
'type' => 'input' |
}, |
'ext_int_o' => { |
'intfc_name' => 'plug:interrupt_peripheral[0]', |
'intfc_port' => 'int_o', |
'intfc_name' => 'plug:interrupt_peripheral[0]', |
'range' => '', |
'type' => 'output' |
}, |
'sa_we_i' => { |
'intfc_port' => 'we_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'we_i', |
'range' => '', |
'type' => 'input' |
}, |
'sa_cyc_i' => { |
'intfc_port' => 'cyc_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'input' |
}, |
'sa_err_o' => { |
'intfc_port' => 'err_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'err_o', |
'range' => '', |
'type' => 'output' |
}, |
'sa_cyc_i' => { |
'sa_ack_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'cyc_i', |
'intfc_port' => 'ack_o', |
'range' => '', |
'type' => 'input' |
'type' => 'output' |
}, |
'ext_int_i' => { |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'range' => 'EXT_INT_NUM-1 : 0', |
'type' => 'input' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i', |
'range' => '', |
'type' => 'input' |
}, |
'reset' => { |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'intfc_port' => 'reset_i', |
'range' => '', |
'type' => 'input' |
}, |
'clk' => { |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]', |
'range' => '', |
'type' => 'input' |
}, |
'ext_int_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => 'EXT_INT_NUM-1 : 0', |
'type' => 'input' |
}, |
'sa_ack_o' => { |
'intfc_port' => 'ack_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'output' |
}, |
'sa_addr_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'adr_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Aw-1 : 0', |
'type' => 'input' |
}, |
'sa_stb_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'stb_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'input' |
} |
}, |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ext_int/ext_int.v', |
'sockets' => {}, |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ext_int/ext_int.v', |
'module_name' => 'ext_int', |
'unused' => { |
'plug:wb_slave[0]' => [ |
181,10 → 181,10
] |
}, |
'category' => 'interrupt', |
'header' => ' |
#define $IP_GER (*((volatile unsigned int *) ($BASE ))) |
#define $IP_IER_RISE (*((volatile unsigned int *) ($BASE+4 ))) |
#define $IP_IER_FALL (*((volatile unsigned int *) ($BASE+8 ))) |
#define $IP_ISR (*((volatile unsigned int *) ($BASE+12 ))) |
#define $IP_RD (*((volatile unsigned int *) ($BASE+16 )))' |
'system_h' => ' |
#define ${IP}_GER (*((volatile unsigned int *) ($BASE ))) |
#define ${IP}_IER_RISE (*((volatile unsigned int *) ($BASE+4 ))) |
#define ${IP}_IER_FALL (*((volatile unsigned int *) ($BASE+8 ))) |
#define ${IP}_ISR (*((volatile unsigned int *) ($BASE+12 ))) |
#define ${IP}_RD (*((volatile unsigned int *) ($BASE+16 )))' |
}, 'ip_gen' ); |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/lm32.IP
340,5 → 340,5
'type' => 'input' |
} |
}, |
'header' => '#include "lm32_system.h"' |
'system_h' => '#include "lm32_system.h"' |
}, 'ip_gen' ); |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/int_ctrl.IP
4,6 → 4,37
], |
'ip_name' => 'int_ctrl', |
'description' => 'interrupt controller', |
'modules' => { |
'int_ctrl' => {} |
}, |
'plugs' => { |
'clk' => { |
'clk' => {}, |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'reset' => { |
'reset' => {}, |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'wb_slave' => { |
'value' => 1, |
'0' => { |
'width' => 5, |
'name' => 'wb', |
'addr' => '0x9e00_0000 0x9eff_ffff IDE Controller' |
}, |
'type' => 'num', |
'wb_slave' => {} |
} |
}, |
'parameters' => { |
'Aw' => { |
'info' => undef, |
19,6 → 50,13
'content' => '', |
'type' => 'Fixed' |
}, |
'INT_NUM' => { |
'info' => 'number of inerrupt.', |
'deafult' => ' 3', |
'global_param' => 0, |
'content' => '1,32,1', |
'type' => 'Spin-button' |
}, |
'Dw' => { |
'info' => undef, |
'deafult' => ' 32', |
25,149 → 63,111
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed' |
}, |
'INT_NUM' => { |
'info' => 'number of inerrupt.', |
'deafult' => ' 3', |
'global_param' => 0, |
'content' => '1,32,1', |
'type' => 'Spin-button' |
} |
} |
}, |
'plugs' => { |
'reset' => { |
'reset' => {}, |
'value' => 1, |
'0' => { |
'name' => 'reset' |
}, |
'type' => 'num' |
}, |
'clk' => { |
'clk' => {}, |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num' |
}, |
'wb_slave' => { |
'0' => { |
'width' => 5, |
'name' => 'wb', |
'addr' => '0x9e00_0000 0x9eff_ffff IDE Controller' |
}, |
'value' => 1, |
'type' => 'num', |
'wb_slave' => {} |
} |
}, |
'modules' => { |
'int_ctrl' => {} |
}, |
'parameters_order' => [ |
'INT_NUM', |
'Dw', |
'Aw', |
'SELw' |
], |
'ports' => { |
'sa_dat_o' => { |
'sa_rty_o' => { |
'intfc_port' => 'rty_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0', |
'range' => '', |
'type' => 'output' |
}, |
'sa_rty_o' => { |
'sa_dat_o' => { |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'rty_o', |
'range' => '', |
'range' => 'Dw-1 : 0', |
'type' => 'output' |
}, |
'sa_sel_i' => { |
'intfc_port' => 'sel_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'sel_i', |
'range' => 'SELw-1 : 0', |
'type' => 'input' |
}, |
'sa_dat_i' => { |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_i', |
'range' => 'Dw-1 : 0', |
'type' => 'input' |
}, |
'sa_we_i' => { |
'intfc_port' => 'we_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'we_i', |
'range' => '', |
'type' => 'input' |
}, |
'sa_err_o' => { |
'intfc_port' => 'err_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'err_o', |
'range' => '', |
'type' => 'output' |
}, |
'int_o' => { |
'intfc_port' => 'int_o', |
'intfc_name' => 'socket:interrupt_cpu[0]', |
'range' => '', |
'type' => 'output' |
}, |
'clk' => { |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]', |
'range' => '', |
'type' => 'input' |
}, |
'sa_ack_o' => { |
'intfc_port' => 'ack_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'ack_o', |
'range' => '', |
'type' => 'output' |
}, |
'reset' => { |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'intfc_port' => 'reset_i', |
'range' => '', |
'type' => 'input' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i', |
'range' => '', |
'type' => 'input' |
}, |
'int_o' => { |
'intfc_name' => 'socket:interrupt_cpu[0]', |
'intfc_port' => 'int_o', |
'range' => '', |
'type' => 'output' |
}, |
'int_i' => { |
'intfc_port' => 'int_i', |
'intfc_name' => 'socket:interrupt_peripheral[array]', |
'intfc_port' => 'int_i', |
'range' => 'INT_NUM-1 : 0', |
'type' => 'input' |
}, |
'sa_addr_i' => { |
'intfc_port' => 'adr_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'adr_i', |
'range' => 'Aw-1 : 0', |
'type' => 'input' |
}, |
'sa_stb_i' => { |
'intfc_port' => 'stb_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'stb_i', |
'range' => '', |
'type' => 'input' |
} |
}, |
'parameters_order' => [ |
'INT_NUM', |
'Dw', |
'Aw', |
'SELw' |
], |
'sockets' => { |
'interrupt_cpu' => { |
'interrupt_cpu' => {}, |
'connection_num' => 'single connection', |
'value' => 1, |
'0' => { |
'name' => 'int_cpu' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'interrupt_peripheral' => { |
'interrupt_peripheral' => {}, |
'connection_num' => 'single connection', |
'interrupt_peripheral' => {}, |
'value' => 'INT_NUM', |
'0' => { |
'name' => 'int_periph' |
}, |
'value' => 'INT_NUM', |
'type' => 'param' |
} |
}, |
182,9 → 182,9
] |
}, |
'category' => 'interrupt', |
'header' => ' |
#define $IP_MER (*((volatile unsigned int *) ($BASE ))) |
#define $IP_IER (*((volatile unsigned int *) ($BASE+4 ))) |
#define $IP_IAR (*((volatile unsigned int *) ($BASE+8 ))) |
#define $IP_IPR (*((volatile unsigned int *) ($BASE+12 )))' |
'system_h' => ' |
#define ${IP}_MER (*((volatile unsigned int *) ($BASE ))) |
#define ${IP}_IER (*((volatile unsigned int *) ($BASE+4 ))) |
#define ${IP}_IAR (*((volatile unsigned int *) ($BASE+8 ))) |
#define ${IP}_IPR (*((volatile unsigned int *) ($BASE+12 )))' |
}, 'ip_gen' ); |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/gpi.IP
6,33 → 6,33
'description' => 'General inout port', |
'modules' => { |
'gpi' => {}, |
'gpo' => {}, |
'gpio' => {} |
'gpio' => {}, |
'gpo' => {} |
}, |
'plugs' => { |
'clk' => { |
'clk' => {}, |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'reset' => { |
'reset' => {}, |
'value' => 1, |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'clk' => { |
'clk' => {}, |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num' |
}, |
'wb_slave' => { |
'value' => 1, |
'0' => { |
'width' => 5, |
'name' => 'wb', |
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O' |
}, |
'value' => 1, |
'type' => 'num', |
'wb_slave' => {} |
} |
52,16 → 52,16
'content' => '', |
'type' => 'Fixed' |
}, |
'TAGw' => { |
'SELw' => { |
'info' => undef, |
'deafult' => ' 3', |
'deafult' => ' 4', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed' |
}, |
'SELw' => { |
'TAGw' => { |
'info' => undef, |
'deafult' => ' 4', |
'deafult' => ' 3', |
'global_param' => 0, |
'content' => '', |
'type' => 'Fixed' |
76,86 → 76,86
}, |
'ports' => { |
'sa_tag_i' => { |
'intfc_port' => 'tag_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'tag_i', |
'range' => 'TAGw-1 : 0', |
'type' => 'input' |
}, |
'sa_dat_o' => { |
'intfc_port' => 'dat_o', |
'sa_rty_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'rty_o', |
'range' => '', |
'type' => 'output' |
}, |
'sa_rty_o' => { |
'intfc_port' => 'rty_o', |
'sa_dat_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0', |
'type' => 'output' |
}, |
'sa_sel_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'sel_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'SELw-1 : 0', |
'type' => 'input' |
}, |
'sa_dat_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Dw-1 : 0', |
'type' => 'input' |
}, |
'sa_we_i' => { |
'intfc_port' => 'we_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'we_i', |
'range' => '', |
'type' => 'input' |
}, |
'sa_err_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'err_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'output' |
}, |
'sa_cyc_i' => { |
'intfc_port' => 'cyc_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'cyc_i', |
'range' => '', |
'type' => 'input' |
}, |
'sa_ack_o' => { |
'intfc_port' => 'ack_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'output' |
}, |
'reset' => { |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'range' => '', |
'type' => 'input' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]', |
'range' => '', |
'type' => 'input' |
}, |
'reset' => { |
'intfc_name' => 'plug:reset[0]', |
'intfc_port' => 'reset_i', |
'range' => '', |
'type' => 'input' |
}, |
'sa_ack_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'ack_o', |
'range' => '', |
'type' => 'output' |
}, |
'port_i' => { |
'intfc_name' => 'IO', |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => 'PORT_WIDTH-1 : 0', |
'type' => 'input' |
}, |
'sa_addr_i' => { |
'intfc_port' => 'adr_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'adr_i', |
'range' => 'Aw-1 : 0', |
'type' => 'input' |
}, |
'sa_stb_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'stb_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'input' |
} |
177,11 → 177,6
] |
}, |
'category' => 'GPI', |
'header' => ' |
|
|
#define $IP_READ_REG (*((volatile unsigned int *) ($BASE+8))) |
|
|
#define $IP_READ() $IP_READ_REG ' |
'system_h' => '#define ${IP}_READ_REG (*((volatile unsigned int *) ($BASE+8))) |
#define ${IP}_READ() ${IP}_READ_REG ' |
}, 'ip_gen' ); |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/timer.IP
3,46 → 3,24
'/mpsoc/src_peripheral/timer/timer.v' |
], |
'ip_name' => 'timer', |
'parameters_order' => [ |
'CNTw', |
'Dw', |
'Aw', |
'TAGw', |
'SELw' |
], |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/timer/timer.v', |
'sockets' => {}, |
'module_name' => 'timer', |
'unused' => { |
'plug:wb_slave[0]' => [ |
'cti_i', |
'bte_i' |
] |
}, |
'category' => 'TIM', |
'description' => '32 bit timer ', |
'modules' => { |
'timer' => {} |
}, |
'plugs' => { |
'interrupt_peripheral' => { |
'interrupt_peripheral' => {}, |
'0' => { |
'name' => 'interrupt_peripheral' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'reset' => { |
'reset' => {}, |
'value' => 1, |
'0' => { |
'name' => 'reset' |
}, |
'type' => 'num' |
}, |
'clk' => { |
'clk' => {}, |
'value' => 1, |
'0' => { |
'name' => 'clk' |
}, |
'type' => 'num' |
}, |
'wb_slave' => { |
'0' => { |
'width' => 5, |
'name' => 'wb', |
'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl' |
}, |
'value' => 1, |
'type' => 'num', |
'wb_slave' => {} |
} |
}, |
'parameters' => { |
'Aw' => { |
'info' => undef, |
51,6 → 29,13
'content' => '', |
'type' => 'Fixed' |
}, |
'SELw' => { |
'info' => undef, |
'deafult' => ' 4', |
'global_param' => undef, |
'content' => '', |
'type' => 'Fixed' |
}, |
'TAGw' => { |
'info' => undef, |
'deafult' => '3', |
58,9 → 43,9
'content' => '', |
'type' => 'Fixed' |
}, |
'SELw' => { |
'CNTw' => { |
'info' => undef, |
'deafult' => ' 4', |
'deafult' => '32 ', |
'global_param' => undef, |
'content' => '', |
'type' => 'Fixed' |
71,119 → 56,134
'global_param' => undef, |
'content' => '', |
'type' => 'Fixed' |
}, |
'CNTw' => { |
'info' => undef, |
'deafult' => '32 ', |
'global_param' => undef, |
'content' => '', |
'type' => 'Fixed' |
} |
} |
}, |
'parameters_order' => [ |
'CNTw', |
'Dw', |
'Aw', |
'TAGw', |
'SELw' |
], |
'plugs' => { |
'clk' => { |
'clk' => {}, |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'reset' => { |
'reset' => {}, |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'interrupt_peripheral' => { |
'interrupt_peripheral' => {}, |
'value' => 1, |
'0' => { |
'name' => 'interrupt_peripheral' |
}, |
'type' => 'num' |
}, |
'wb_slave' => { |
'value' => 1, |
'0' => { |
'width' => 5, |
'name' => 'wb', |
'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl' |
}, |
'type' => 'num', |
'wb_slave' => {} |
} |
}, |
'modules' => { |
'timer' => {} |
}, |
'ports' => { |
'sa_tag_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'tag_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'TAGw-1 : 0', |
'type' => 'input' |
}, |
'sa_rty_o' => { |
'intfc_port' => 'rty_o', |
'sa_dat_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'intfc_port' => 'dat_o', |
'range' => 'Dw-1 : 0', |
'type' => 'output' |
}, |
'sa_dat_o' => { |
'intfc_port' => 'dat_o', |
'sa_rty_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Dw-1 : 0', |
'intfc_port' => 'rty_o', |
'range' => '', |
'type' => 'output' |
}, |
'sa_sel_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'sel_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'SELw-1 : 0', |
'type' => 'input' |
}, |
'sa_dat_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Dw-1 : 0', |
'type' => 'input' |
}, |
'sa_we_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'we_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'input' |
}, |
'irq' => { |
'intfc_name' => 'plug:interrupt_peripheral[0]', |
'intfc_port' => 'int_o', |
'intfc_name' => 'plug:interrupt_peripheral[0]', |
'range' => '', |
'type' => 'output' |
}, |
'sa_cyc_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'cyc_i', |
'range' => '', |
'type' => 'input' |
}, |
'sa_err_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'err_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'output' |
}, |
'sa_cyc_i' => { |
'intfc_port' => 'cyc_i', |
'sa_ack_o' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'ack_o', |
'range' => '', |
'type' => 'input' |
'type' => 'output' |
}, |
'reset' => { |
'intfc_name' => 'plug:reset[0]', |
'intfc_port' => 'reset_i', |
'range' => '', |
'type' => 'input' |
}, |
'clk' => { |
'intfc_name' => 'plug:clk[0]', |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]', |
'range' => '', |
'type' => 'input' |
}, |
'reset' => { |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'range' => '', |
'type' => 'input' |
}, |
'sa_ack_o' => { |
'intfc_port' => 'ack_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'output' |
}, |
'sa_addr_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'adr_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => 'Aw-1 : 0', |
'type' => 'input' |
}, |
'sa_stb_i' => { |
'intfc_name' => 'plug:wb_slave[0]', |
'intfc_port' => 'stb_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'input' |
} |
}, |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/timer/timer.v', |
'sockets' => {}, |
'module_name' => 'timer', |
'unused' => { |
'plug:wb_slave[0]' => [ |
'cti_i', |
'bte_i' |
] |
}, |
'category' => 'TIM', |
'header' => '#define $IP_TCSR0 (*((volatile unsigned int *) ($BASE ))) |
'system_h' => '#define ${IP}_TCSR0 (*((volatile unsigned int *) ($BASE ))) |
|
/* |
//timer control register |
195,8 → 195,8
1 : int_enble_on_cmp_value |
0 : timer enable |
*/ |
#define $IP_TLR0 (*((volatile unsigned int *) ($BASE+4 ))) |
#define $IP_TCMP0 (*((volatile unsigned int *) ($BASE+8 ))) |
#define ${IP}_TLR0 (*((volatile unsigned int *) ($BASE+4 ))) |
#define ${IP}_TCMP0 (*((volatile unsigned int *) ($BASE+8 ))) |
#ifndef TIMER_EN |
#define TIMER_EN (1 << 0) |
#define TIMER_INT_EN (1 << 1) |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/ethmac_100.IP
0,0 → 1,451
$ethtop = bless( { |
'hdl_files' => [ |
'/mpsoc/src_peripheral/ethmac/rtl/eth_clockgen.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_cop.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_crc.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_fifo.v', |
'/mpsoc/src_peripheral/ethmac/rtl/ethmac.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_maccontrol.v', |
'/mpsoc/src_peripheral/ethmac/rtl/ethmac_defines.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_macstatus.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_miim.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_outputcontrol.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_random.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_receivecontrol.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_register.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_registers.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_rxaddrcheck.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_rxcounters.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_rxethmac.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_rxstatem.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_shiftreg.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_spram_256x32.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_top.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_transmitcontrol.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_txcounters.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_txethmac.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_txstatem.v', |
'/mpsoc/src_peripheral/ethmac/rtl/eth_wishbone.v', |
'/mpsoc/src_peripheral/ethmac/rtl/timescale.v', |
'/mpsoc/src_peripheral/ethmac/rtl/xilinx_dist_ram_16x32.v', |
'/mpsoc/src_peripheral/ram/general_single_port_ram.v', |
'/mpsoc/src_peripheral/ram/general_dual_port_ram.v', |
'/mpsoc/src_peripheral/ethmac/ethtop.v' |
], |
'custom_file' => { |
'0' => {} |
}, |
'system_h' => ' |
|
void ${IP}_init(); |
void ${IP}_interrupt(); |
void ${IP}_recv_ack(void); |
int ${IP}_send(int length); //return (-1) or length (still processing previous) or asserted |
|
#define ${IP}_BASE_ADDR $BASE |
#define ${IP}_MODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x00 ))) |
#define ${IP}_INT_SOURCE (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x04 ))) |
#define ${IP}_INT_MASK (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x08 ))) |
#define ${IP}_IPGT (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x0C ))) |
#define ${IP}_IPGR1 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x10 ))) |
#define ${IP}_IPGR2 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x14 ))) |
#define ${IP}_PACKETLEN (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x18 ))) |
#define ${IP}_COLLCONF (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x1C ))) |
#define ${IP}_TX_BD_NUM (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x20 ))) |
#define ${IP}_CTRLMODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x24 ))) |
#define ${IP}_MIIMODER (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x28 ))) |
#define ${IP}_MIICOMMAND (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x2C ))) |
#define ${IP}_MIIADDR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x30 ))) |
#define ${IP}_MIITX_DATA (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x34 ))) |
#define ${IP}_MIIRX_DATA (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x38 ))) |
#define ${IP}_MIISTATUS (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x3C ))) |
#define ${IP}_MAC_ADDR0 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x40 ))) |
#define ${IP}_MAC_ADDR1 (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x44 ))) |
#define ${IP}_HASH0_ADR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x48 ))) |
#define ${IP}_HASH1_ADR (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x4C ))) |
#define ${IP}_TXCTRL (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x50 ))) |
#define ${IP}_TXBD0H (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x404 ))) |
#define ${IP}_TXBD0L (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x400 ))) |
#define ${IP}_RXBD0H (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x604 ))) //this depends on TX_BD_NUM but this is the standard value |
#define ${IP}_RXBD0L (*((volatile unsigned int *) (${IP}_BASE_ADDR+0x600 ))) //this depends on TX_BD_NUM but this is the standard value |
|
|
#include "${IP}.h"', |
'ip_name' => 'ethmac_100', |
'custom_file_num' => 1, |
'ports_order' => [ |
'wb_clk_i', |
'wb_rst_i', |
'wb_dat_i', |
'wb_dat_o', |
'wb_adr_i', |
'wb_sel_i', |
'wb_we_i', |
'wb_cyc_i', |
'wb_stb_i', |
'wb_ack_o', |
'wb_err_o', |
'm_wb_adr_o', |
'm_wb_sel_o', |
'm_wb_we_o', |
'm_wb_dat_o', |
'm_wb_dat_i', |
'm_wb_cyc_o', |
'm_wb_stb_o', |
'm_wb_ack_i', |
'm_wb_err_i', |
'mtx_clk_pad_i', |
'mtxd_pad_o', |
'mtxen_pad_o', |
'mtxerr_pad_o', |
'mrx_clk_pad_i', |
'mrxd_pad_i', |
'mrxdv_pad_i', |
'mrxerr_pad_i', |
'mcoll_pad_i', |
'mcrs_pad_i', |
'mdc_pad_o', |
'md_pad_i', |
'md_pad_o', |
'md_padoe_o', |
'int_o' |
], |
'parameters_order' => [ |
'TX_FIFO_DATA_WIDTH', |
'TX_FIFO_DEPTH', |
'TX_FIFO_CNT_WIDTH', |
'RX_FIFO_DATA_WIDTH', |
'RX_FIFO_DEPTH', |
'RX_FIFO_CNT_WIDTH' |
], |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ethmac/ethtop.v', |
'module_name' => 'ethtop', |
'gen_sw_files' => [ |
'/mpsoc/src_peripheral/ethmac/ethfrename_sep_t${IP}.h' |
], |
'unused' => { |
'plug:wb_slave[0]' => [ |
'rty_o', |
'tag_i', |
'cti_i', |
'bte_i' |
], |
'plug:wb_master[0]' => [ |
'tag_o', |
'bte_o', |
'cti_o', |
'rty_i' |
] |
}, |
'category' => 'eth', |
'sw_files' => [], |
'parameters' => { |
'RX_FIFO_DEPTH' => { |
'info' => undef, |
'deafult' => ' 16', |
'global_param' => 0, |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
}, |
'TX_FIFO_DATA_WIDTH' => { |
'info' => undef, |
'deafult' => ' 32', |
'global_param' => 0, |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
}, |
'RX_FIFO_DATA_WIDTH' => { |
'info' => undef, |
'deafult' => ' 32', |
'global_param' => 0, |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
}, |
'RX_FIFO_CNT_WIDTH' => { |
'info' => undef, |
'deafult' => ' 5', |
'global_param' => 0, |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
}, |
'TX_FIFO_CNT_WIDTH' => { |
'info' => undef, |
'deafult' => ' 5', |
'global_param' => 0, |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
}, |
'TX_FIFO_DEPTH' => { |
'info' => undef, |
'deafult' => ' 16', |
'global_param' => 0, |
'content' => '', |
'redefine_param' => 1, |
'type' => 'Fixed' |
} |
}, |
'modules' => { |
'ethtop' => {} |
}, |
'plugs' => { |
'wb_master' => { |
'wb_master' => {}, |
'0' => { |
'name' => 'wb_master' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'interrupt_peripheral' => { |
'interrupt_peripheral' => {}, |
'0' => { |
'name' => 'interrupt_peripheral' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'reset' => { |
'reset' => {}, |
'0' => { |
'name' => 'reset' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'clk' => { |
'clk' => {}, |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'wb_slave' => { |
'0' => { |
'width' => 11, |
'name' => 'wb_slave', |
'addr' => '0x9200_0000 0x92ff_ffff Ethernet Controller' |
}, |
'value' => 1, |
'type' => 'num', |
'wb_slave' => {} |
} |
}, |
'ports' => { |
'wb_sel_i' => { |
'intfc_port' => 'sel_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '3:0', |
'type' => 'input' |
}, |
'm_wb_we_o' => { |
'intfc_port' => 'we_o', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'type' => 'output' |
}, |
'wb_we_i' => { |
'intfc_port' => 'we_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'input' |
}, |
'wb_err_o' => { |
'intfc_port' => 'err_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'output' |
}, |
'wb_dat_o' => { |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '31:0', |
'type' => 'output' |
}, |
'wb_rst_i' => { |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'range' => '', |
'type' => 'input' |
}, |
'wb_cyc_i' => { |
'intfc_port' => 'cyc_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'input' |
}, |
'm_wb_err_i' => { |
'intfc_port' => 'err_i', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'type' => 'input' |
}, |
'm_wb_dat_i' => { |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '31:0', |
'type' => 'input' |
}, |
'mdc_pad_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'output' |
}, |
'm_wb_sel_o' => { |
'intfc_port' => 'sel_o', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '3:0', |
'type' => 'output' |
}, |
'md_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'input' |
}, |
'mcrs_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'input' |
}, |
'm_wb_dat_o' => { |
'intfc_port' => 'dat_o', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '31:0', |
'type' => 'output' |
}, |
'md_padoe_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'output' |
}, |
'wb_adr_i' => { |
'intfc_port' => 'adr_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '9:0', |
'type' => 'input' |
}, |
'm_wb_adr_o' => { |
'intfc_port' => 'adr_o', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '31:0', |
'type' => 'output' |
}, |
'mrxerr_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'input' |
}, |
'mrxd_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '3:0', |
'type' => 'input' |
}, |
'mtxd_pad_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '3:0', |
'type' => 'output' |
}, |
'wb_ack_o' => { |
'intfc_port' => 'ack_o', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'output' |
}, |
'mtxen_pad_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'output' |
}, |
'mcoll_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'input' |
}, |
'int_o' => { |
'intfc_port' => 'int_o', |
'intfc_name' => 'plug:interrupt_peripheral[0]', |
'range' => '', |
'type' => 'output' |
}, |
'm_wb_ack_i' => { |
'intfc_port' => 'ack_i', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'type' => 'input' |
}, |
'wb_stb_i' => { |
'intfc_port' => 'stb_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '', |
'type' => 'input' |
}, |
'mrx_clk_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'input' |
}, |
'wb_clk_i' => { |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]', |
'range' => '', |
'type' => 'input' |
}, |
'md_pad_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'output' |
}, |
'm_wb_cyc_o' => { |
'intfc_port' => 'cyc_o', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'type' => 'output' |
}, |
'mrxdv_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'input' |
}, |
'mtxerr_pad_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'output' |
}, |
'mtx_clk_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'input' |
}, |
'm_wb_stb_o' => { |
'intfc_port' => 'stb_o', |
'intfc_name' => 'plug:wb_master[0]', |
'range' => '', |
'type' => 'output' |
}, |
'wb_dat_i' => { |
'intfc_port' => 'dat_i', |
'intfc_name' => 'plug:wb_slave[0]', |
'range' => '31:0', |
'type' => 'input' |
} |
} |
}, 'ip_gen' ); |
an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/ethmac_100.IP
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/lcd_2x16.IP
===================================================================
--- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/lcd_2x16.IP (revision 23)
+++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/lcd_2x16.IP (revision 24)
@@ -2,175 +2,189 @@
'hdl_files' => [
'/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16.v'
],
+ 'system_h' => '#define ${IP}_WR_CMD (*((volatile unsigned int *) ($BASE)))
+#define ${IP}_RD_CMD (*((volatile unsigned int *) ($BASE+4)))
+#define ${IP}_WR_DATA (*((volatile unsigned int *) ($BASE+8)))
+#define ${IP}_RD_DATA (*((volatile unsigned int *) ($BASE+16)))
+
+#define ${IP}_CLK_MHZ $CLK_MHZ
+
+#include "$IP.h"',
+ 'ip_name' => 'lcd_2x16',
+ 'sw_params_list' => [],
+ 'parameters_order' => [
+ 'Dw',
+ 'Aw',
+ 'CLK_MHZ'
+ ],
+ 'ports_order' => [
+ 'clk',
+ 'reset',
+ 's_dat_i',
+ 's_addr_i',
+ 's_stb_i',
+ 's_cyc_i',
+ 's_we_i',
+ 's_dat_o',
+ 's_ack_o',
+ 'lcd_en',
+ 'lcd_rs',
+ 'lcd_rw',
+ 'lcd_data'
+ ],
+ 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16.v',
+ 'module_name' => 'lcd_2x16',
+ 'gen_sw_files' => [
+ '/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16.hgenfrename_sep_t${IP}.h'
+ ],
+ 'unused' => {
+ 'plug:wb_slave[0]' => [
+ 'err_o',
+ 'rty_o',
+ 'tag_i',
+ 'cti_i',
+ 'sel_i',
+ 'bte_i'
+ ]
+ },
+ 'category' => 'Display',
+ 'sw_files' => [],
'description' => 'Alphabet Display LCD 2x16',
- 'ip_name' => 'lcd_2x16',
+ 'parameters' => {
+ 'Aw' => {
+ 'info' => undef,
+ 'deafult' => ' 2',
+ 'global_param' => 0,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'Dw' => {
+ 'info' => undef,
+ 'deafult' => ' 8',
+ 'global_param' => 0,
+ 'content' => '',
+ 'redefine_param' => 1,
+ 'type' => 'Fixed'
+ },
+ 'CLK_MHZ' => {
+ 'info' => 'The LCD controller clock speed in MHZ. It will be used for measuring the lcd enable delay. You can define a larger value than the actual clk speed but not smaller.',
+ 'deafult' => '100',
+ 'global_param' => 0,
+ 'content' => '2,1000,2',
+ 'redefine_param' => 1,
+ 'type' => 'Spin-button'
+ }
+ },
+ 'modules' => {
+ 'lcd_2x16' => {}
+ },
'plugs' => {
+ 'reset' => {
+ 'reset' => {},
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'value' => 1,
+ 'type' => 'num'
+ },
'clk' => {
'clk' => {},
- 'value' => 1,
'0' => {
'name' => 'clk'
},
+ 'value' => 1,
'type' => 'num'
},
- 'reset' => {
- 'reset' => {},
- 'value' => 1,
- '0' => {
- 'name' => 'reset'
- },
- 'type' => 'num'
- },
'wb_slave' => {
- 'value' => 1,
'0' => {
'width' => 5,
'name' => 'wb_slave',
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
},
+ 'value' => 1,
'type' => 'num',
'wb_slave' => {}
}
},
- 'modules' => {
- 'lcd_2x16' => {}
- },
- 'parameters' => {
- 'Aw' => {
- 'info' => undef,
- 'deafult' => ' 2',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- },
- 'Dw' => {
- 'info' => undef,
- 'deafult' => ' 8',
- 'global_param' => 0,
- 'content' => '',
- 'type' => 'Fixed',
- 'redefine_param' => 1
- }
- },
- 'ports_order' => [
- 'clk',
- 'reset',
- 's_dat_i',
- 's_addr_i',
- 's_stb_i',
- 's_cyc_i',
- 's_we_i',
- 's_dat_o',
- 's_ack_o',
- 'lcd_en',
- 'lcd_rs',
- 'lcd_rw',
- 'lcd_data'
- ],
'ports' => {
- 's_cyc_i' => {
+ 's_dat_i' => {
+ 'intfc_port' => 'dat_i',
'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'cyc_i',
- 'range' => '',
+ 'range' => 'Dw-1 : 0',
'type' => 'input'
},
- 's_dat_i' => {
+ 's_cyc_i' => {
+ 'intfc_port' => 'cyc_i',
'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'dat_i',
- 'range' => 'Dw-1 : 0',
+ 'range' => '',
'type' => 'input'
},
'lcd_en' => {
+ 'intfc_port' => 'IO',
'intfc_name' => 'IO',
- 'intfc_port' => 'IO',
'range' => '',
'type' => 'output'
},
's_ack_o' => {
+ 'intfc_port' => 'ack_o',
'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'ack_o',
'range' => '',
'type' => 'output'
},
's_we_i' => {
+ 'intfc_port' => 'we_i',
'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'we_i',
'range' => '',
'type' => 'input'
},
's_stb_i' => {
+ 'intfc_port' => 'stb_i',
'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'stb_i',
'range' => '',
'type' => 'input'
},
'lcd_data' => {
+ 'intfc_port' => 'IO',
'intfc_name' => 'IO',
- 'intfc_port' => 'IO',
'range' => ' 7: 0',
'type' => 'inout'
},
'lcd_rs' => {
+ 'intfc_port' => 'IO',
'intfc_name' => 'IO',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'clk' => {
+ 'intfc_port' => 'clk_i',
+ 'intfc_name' => 'plug:clk[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'lcd_rw' => {
'intfc_port' => 'IO',
+ 'intfc_name' => 'IO',
'range' => '',
'type' => 'output'
},
'reset' => {
+ 'intfc_port' => 'reset_i',
'intfc_name' => 'plug:reset[0]',
- 'intfc_port' => 'reset_i',
'range' => '',
'type' => 'input'
},
- 'lcd_rw' => {
- 'intfc_name' => 'IO',
- 'intfc_port' => 'IO',
- 'range' => '',
- 'type' => 'output'
- },
- 'clk' => {
- 'intfc_name' => 'plug:clk[0]',
- 'intfc_port' => 'clk_i',
- 'range' => '',
- 'type' => 'input'
- },
+ 's_dat_o' => {
+ 'intfc_port' => 'dat_o',
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'range' => 'Dw-1 : 0',
+ 'type' => 'output'
+ },
's_addr_i' => {
+ 'intfc_port' => 'adr_i',
'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'adr_i',
'range' => 'Aw-1 : 0',
'type' => 'input'
- },
- 's_dat_o' => {
- 'intfc_name' => 'plug:wb_slave[0]',
- 'intfc_port' => 'dat_o',
- 'range' => 'Dw-1 : 0',
- 'type' => 'output'
- }
- },
- 'parameters_order' => [
- 'Dw',
- 'Aw'
- ],
- 'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16.v',
- 'module_name' => 'lcd_2x16',
- 'unused' => {
- 'plug:wb_slave[0]' => [
- 'err_o',
- 'rty_o',
- 'tag_i',
- 'cti_i',
- 'sel_i',
- 'bte_i'
- ]
- },
- 'category' => 'Display',
- 'header' => '#define LCD_WR_CMD (*((volatile unsigned int *) ($BASE)))
-#define LCD_RD_CMD (*((volatile unsigned int *) ($BASE+4)))
-#define LCD_WR_DATA (*((volatile unsigned int *) ($BASE+8)))
-#define LCD_RD_DATA (*((volatile unsigned int *) ($BASE+16)))
-#include "lcd_2x16.h"',
- 'sw_files' => [
- '/mpsoc/src_peripheral/display/lcd_2x16/lcd_2x16.h'
- ]
+ }
+ }
}, 'ip_gen' );
Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/gpo.IP
===================================================================
--- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/gpo.IP (revision 23)
+++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/gpo.IP (revision 24)
@@ -5,29 +5,29 @@
'ip_name' => 'gpo',
'description' => 'General output port',
'plugs' => {
+ 'reset' => {
+ 'reset' => {},
+ 'value' => 1,
+ '0' => {
+ 'name' => 'reset'
+ },
+ 'type' => 'num'
+ },
'clk' => {
'clk' => {},
+ 'value' => 1,
'0' => {
'name' => 'clk'
},
- 'value' => 1,
'type' => 'num'
},
- 'reset' => {
- 'reset' => {},
- '0' => {
- 'name' => 'reset'
- },
- 'value' => 1,
- 'type' => 'num'
- },
'wb_slave' => {
- 'value' => 1,
'0' => {
'width' => 5,
'name' => 'wb',
'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
},
+ 'value' => 1,
'type' => 'num',
'wb_slave' => {}
}
@@ -34,8 +34,8 @@
},
'modules' => {
'gpi' => {},
- 'gpo' => {},
- 'gpio' => {}
+ 'gpio' => {},
+ 'gpo' => {}
},
'parameters' => {
'PORT_WIDTH' => {
@@ -52,16 +52,16 @@
'content' => '',
'type' => 'Fixed'
},
- 'TAGw' => {
+ 'SELw' => {
'info' => undef,
- 'deafult' => ' 3',
+ 'deafult' => ' 4',
'global_param' => 0,
'content' => '',
'type' => 'Fixed'
},
- 'SELw' => {
+ 'TAGw' => {
'info' => undef,
- 'deafult' => ' 4',
+ 'deafult' => ' 3',
'global_param' => 0,
'content' => '',
'type' => 'Fixed'
@@ -76,86 +76,86 @@
},
'ports' => {
'sa_tag_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'tag_i',
- 'intfc_name' => 'plug:wb_slave[0]',
'range' => 'TAGw-1 : 0',
'type' => 'input'
},
- 'sa_rty_o' => {
- 'intfc_port' => 'rty_o',
+ 'sa_dat_o' => {
'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
+ 'intfc_port' => 'dat_o',
+ 'range' => 'Dw-1 : 0',
'type' => 'output'
},
- 'sa_dat_o' => {
- 'intfc_port' => 'dat_o',
+ 'sa_rty_o' => {
'intfc_name' => 'plug:wb_slave[0]',
- 'range' => 'Dw-1 : 0',
+ 'intfc_port' => 'rty_o',
+ 'range' => '',
'type' => 'output'
},
'sa_sel_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'sel_i',
- 'intfc_name' => 'plug:wb_slave[0]',
'range' => 'SELw-1 : 0',
'type' => 'input'
},
'sa_dat_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'dat_i',
- 'intfc_name' => 'plug:wb_slave[0]',
'range' => 'Dw-1 : 0',
'type' => 'input'
},
'port_o' => {
+ 'intfc_name' => 'IO',
'intfc_port' => 'IO',
- 'intfc_name' => 'IO',
'range' => 'PORT_WIDTH-1 : 0',
'type' => 'output'
},
'sa_we_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'we_i',
- 'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'input'
},
+ 'sa_cyc_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'cyc_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
'sa_err_o' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'err_o',
- 'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'output'
},
- 'sa_cyc_i' => {
- 'intfc_port' => 'cyc_i',
+ 'sa_ack_o' => {
'intfc_name' => 'plug:wb_slave[0]',
+ 'intfc_port' => 'ack_o',
'range' => '',
- 'type' => 'input'
+ 'type' => 'output'
},
+ 'reset' => {
+ 'intfc_name' => 'plug:reset[0]',
+ 'intfc_port' => 'reset_i',
+ 'range' => '',
+ 'type' => 'input'
+ },
'clk' => {
+ 'intfc_name' => 'plug:clk[0]',
'intfc_port' => 'clk_i',
- 'intfc_name' => 'plug:clk[0]',
'range' => '',
'type' => 'input'
},
- 'reset' => {
- 'intfc_port' => 'reset_i',
- 'intfc_name' => 'plug:reset[0]',
- 'range' => '',
- 'type' => 'input'
- },
- 'sa_ack_o' => {
- 'intfc_port' => 'ack_o',
- 'intfc_name' => 'plug:wb_slave[0]',
- 'range' => '',
- 'type' => 'output'
- },
'sa_addr_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'adr_i',
- 'intfc_name' => 'plug:wb_slave[0]',
'range' => 'Aw-1 : 0',
'type' => 'input'
},
'sa_stb_i' => {
+ 'intfc_name' => 'plug:wb_slave[0]',
'intfc_port' => 'stb_i',
- 'intfc_name' => 'plug:wb_slave[0]',
'range' => '',
'type' => 'input'
}
@@ -177,9 +177,8 @@
]
},
'category' => 'GPI',
- 'header' => '
- #define $IP\\_WRITE_REG (*((volatile unsigned int *) ($BASE+4)))
- #define $IP\\_WRITE(value) $IP\\_WRITE_REG=value
+ 'system_h' => '#define ${IP}_WRITE_REG (*((volatile unsigned int *) ($BASE+4)))
+#define ${IP}_WRITE(value) ${IP}_WRITE_REG=value
'
}, 'ip_gen' );
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/gpio.IP
2,6 → 2,13
'hdl_files' => [ |
'/mpsoc/src_peripheral/gpio/gpio.v' |
], |
'system_h' => '#define ${IP}_DIR_REG (*((volatile unsigned int *) ($BASE))) |
#define ${IP}_WRITE _REG (*((volatile unsigned int *) ($BASE+4))) |
#define ${IP}_READ_REG (*((volatile unsigned int *) ($BASE+8))) |
|
#define ${IP}_DIR_SET(value) ${IP}_DIR_REG=value |
#define ${IP}_WRITE(value) ${IP}_WRITE _REG=value |
#define ${IP}_READ() ${IP}_READ_REG ', |
'description' => 'General inout port', |
'ip_name' => 'gpio', |
'parameters' => { |
67,12 → 74,6
'gpio' => {}, |
'gpo' => {} |
}, |
'parameters_order' => [ |
'PORT_WIDTH', |
'Dw', |
'Aw', |
'SELw' |
], |
'ports' => { |
'sa_dat_o' => { |
'intfc_port' => 'dat_o', |
147,6 → 148,12
'type' => 'input' |
} |
}, |
'parameters_order' => [ |
'PORT_WIDTH', |
'Dw', |
'Aw', |
'SELw' |
], |
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/gpio/gpio.v', |
'sockets' => {}, |
'module_name' => 'gpio', |
158,13 → 165,5
'bte_i' |
] |
}, |
'category' => 'GPI', |
'header' => ' |
#define $IP_DIR_REG (*((volatile unsigned int *) ($BASE))) |
#define $IP_WRITE _REG (*((volatile unsigned int *) ($BASE+4))) |
#define $IP_READ_REG (*((volatile unsigned int *) ($BASE+8))) |
|
#define $IP_DIR_SET(value) $IP_DIR_REG=value |
#define $IP_WRITE(value) $IP_WRITE _REG=value |
#define $IP_READ() $IP_READ_REG ' |
'category' => 'GPI' |
}, 'ip_gen' ); |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/aeMB.IP
367,7 → 367,7
'module_name' => 'aeMB_top', |
'unused' => undef, |
'category' => 'Processor', |
'header' => ' #include <stdio.h> |
'system_h' => ' #include <stdio.h> |
#include <stdlib.h> |
#include "aemb/core.hh" ', |
'sw_files' => [ |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/lib/ip/ni.IP
11,6 → 11,53
], |
'ip_name' => 'ni', |
'description' => 'Network interface', |
'modules' => { |
'ni' => {} |
}, |
'plugs' => { |
'wb_master' => { |
'wb_master' => {}, |
'value' => 1, |
'0' => { |
'name' => 'wb_master' |
}, |
'type' => 'num' |
}, |
'interrupt_peripheral' => { |
'interrupt_peripheral' => {}, |
'value' => 1, |
'0' => { |
'name' => 'int_peripheral' |
}, |
'type' => 'num' |
}, |
'reset' => { |
'reset' => {}, |
'value' => 1, |
'0' => { |
'name' => 'reset' |
}, |
'type' => 'num' |
}, |
'clk' => { |
'clk' => {}, |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'wb_slave' => { |
'value' => 1, |
'0' => { |
'width' => 5, |
'name' => 'wb_slave', |
'addr' => '0xb800_0000 0xbfff_ffff custom devices' |
}, |
'type' => 'num', |
'wb_slave' => {} |
} |
}, |
'parameters' => { |
'Dw' => { |
'info' => undef, |
189,88 → 236,28
'redefine_param' => 1 |
} |
}, |
'plugs' => { |
'wb_master' => { |
'wb_master' => {}, |
'value' => 1, |
'0' => { |
'name' => 'wb_master' |
}, |
'type' => 'num' |
}, |
'interrupt_peripheral' => { |
'interrupt_peripheral' => {}, |
'value' => 1, |
'0' => { |
'name' => 'int_peripheral' |
}, |
'type' => 'num' |
}, |
'reset' => { |
'reset' => {}, |
'value' => 1, |
'0' => { |
'name' => 'reset' |
}, |
'type' => 'num' |
}, |
'clk' => { |
'clk' => {}, |
'0' => { |
'name' => 'clk' |
}, |
'value' => 1, |
'type' => 'num' |
}, |
'wb_slave' => { |
'value' => 1, |
'0' => { |
'width' => 5, |
'name' => 'wb_slave', |
'addr' => '0xb800_0000 0xbfff_ffff custom devices' |
}, |
'type' => 'num', |
'wb_slave' => {} |
} |
}, |
'modules' => { |
'ni' => {} |
}, |
'ports_order' => [ |
'reset', |
'clk', |
'current_x', |
'current_y', |
'flit_out', |
'flit_out_wr', |
'credit_in', |
'flit_in', |
'flit_in_wr', |
'credit_out', |
's_dat_i', |
's_sel_i', |
's_addr_i', |
's_cti_i', |
's_stb_i', |
's_cyc_i', |
's_we_i', |
's_dat_o', |
's_ack_o', |
's_err_o', |
's_rty_o', |
'm_sel_o', |
'm_dat_o', |
'm_addr_o', |
'm_cti_o', |
'm_stb_o', |
'm_cyc_o', |
'm_we_o', |
'm_dat_i', |
'm_ack_i', |
'm_err_i', |
'm_rty_i', |
'irq' |
], |
'parameters_order' => [ |
'V', |
'P', |
'B', |
'NX', |
'NY', |
'Fpay', |
'TOPOLOGY', |
'ROUTE_TYPE', |
'ROUTE_NAME', |
'DEBUG_EN', |
'COMB_MEM_PTR_W', |
'COMB_PCK_SIZE_W', |
'Dw', |
'S_Aw', |
'M_Aw', |
'TAGw', |
'SELw', |
'Yw', |
'Fw', |
'Xw' |
], |
'ports' => { |
'm_addr_o' => { |
'intfc_port' => 'adr_o', |
471,28 → 458,41
'type' => 'output' |
} |
}, |
'parameters_order' => [ |
'V', |
'P', |
'B', |
'NX', |
'NY', |
'Fpay', |
'TOPOLOGY', |
'ROUTE_TYPE', |
'ROUTE_NAME', |
'DEBUG_EN', |
'COMB_MEM_PTR_W', |
'COMB_PCK_SIZE_W', |
'Dw', |
'S_Aw', |
'M_Aw', |
'TAGw', |
'SELw', |
'Yw', |
'Fw', |
'Xw' |
], |
'ports_order' => [ |
'reset', |
'clk', |
'current_x', |
'current_y', |
'flit_out', |
'flit_out_wr', |
'credit_in', |
'flit_in', |
'flit_in_wr', |
'credit_out', |
's_dat_i', |
's_sel_i', |
's_addr_i', |
's_cti_i', |
's_stb_i', |
's_cyc_i', |
's_we_i', |
's_dat_o', |
's_ack_o', |
's_err_o', |
's_rty_o', |
'm_sel_o', |
'm_dat_o', |
'm_addr_o', |
'm_cti_o', |
'm_stb_o', |
'm_cyc_o', |
'm_we_o', |
'm_dat_i', |
'm_ack_i', |
'm_err_i', |
'm_rty_i', |
'irq' |
], |
'sockets' => { |
'ni' => { |
'connection_num' => 'single connection', |
517,32 → 517,36
] |
}, |
'category' => 'NoC', |
'header' => ' #define $IP_CLASS_IN_HDR_WIDTH 8 |
#define $IP_DEST_IN_HDR_WIDTH 8 |
#define $IP_X_Y_IN_HDR_WIDTH 4 |
'system_h' => ' #define ${IP}_BASE_ADDR ${BASE} |
#define ${IP}_ST (*((volatile unsigned int *) (${IP}_BASE_ADDR ))) |
#define ${IP}_RD (*((volatile unsigned int *) (${IP}_BASE_ADDR+4 ))) |
#define ${IP}_WR (*((volatile unsigned int *) (${IP}_BASE_ADDR+8))) |
|
|
|
#define ${IP}_CLASS_IN_HDR_WIDTH 8 |
#define ${IP}_DEST_IN_HDR_WIDTH 8 |
#define ${IP}_X_Y_IN_HDR_WIDTH 4 |
|
#define $IP_BUSY (1<<0) |
#define $IP_WR_DONE (1<<1) |
#define $IP_RD_DONE (1<<2) |
#define $IP_RD_OVR_ERR (1<<3) |
#define $IP_RD_NPCK_ERR (1<<4) |
#define $IP_HAS_PCK (1<<5) |
#define $IP_ALL_VCS_FULL (1<<6) |
#define $IP_WR_DONE_INT_EN (1<<7) |
#define $IP_RD_DONE_INT_EN (1<<8) |
#define $IP_RSV_PCK_INT_EN (1<<9) |
#define $IP_WR_DONE_ISR (1<<10) |
#define $IP_RD_DONE_ISR (1<<11) |
#define $IP_RSV_PCK_ISR (1<<12) |
#define ${IP}_BUSY (1<<0) |
#define ${IP}_WR_DONE (1<<1) |
#define ${IP}_RD_DONE (1<<2) |
#define ${IP}_RD_OVR_ERR (1<<3) |
#define ${IP}_RD_NPCK_ERR (1<<4) |
#define ${IP}_HAS_PCK (1<<5) |
#define ${IP}_ALL_VCS_FULL (1<<6) |
#define ${IP}_WR_DONE_INT_EN (1<<7) |
#define ${IP}_RD_DONE_INT_EN (1<<8) |
#define ${IP}_RSV_PCK_INT_EN (1<<9) |
#define ${IP}_WR_DONE_ISR (1<<10) |
#define ${IP}_RD_DONE_ISR (1<<11) |
#define ${IP}_RSV_PCK_ISR (1<<12) |
|
|
|
#define $IP_PTR_WIDTH 20 |
#define $IP_PCK_SIZE_WIDTH 12 |
#define ${IP}_PTR_WIDTH 20 |
#define ${IP}_PCK_SIZE_WIDTH 12 |
|
#define $IP_ST (*((volatile unsigned int *) ($IP_BASE_ADDR ))) |
#define $IP_RD (*((volatile unsigned int *) ($IP_BASE_ADDR+4 ))) |
#define $IP_WR (*((volatile unsigned int *) ($IP_BASE_ADDR+8))) |
|
|
|
549,14 → 553,14
|
|
|
#define $IP_HDR_DEST_CORE_ADDR(DES_X, DES_Y) ((DES_X << $IP_X_Y_IN_HDR_WIDTH) | DES_Y)<<(2*$IP_X_Y_IN_HDR_WIDTH) |
#define $IP_HDR_CLASS(pck_class) (pck_class << ( $IP_DEST_IN_HDR_WIDTH+ (4* $IP_X_Y_IN_HDR_WIDTH))) |
#define ${IP}_HDR_DEST_CORE_ADDR(DES_X, DES_Y) ((DES_X << ${IP}_X_Y_IN_HDR_WIDTH) | DES_Y)<<(2*${IP}_X_Y_IN_HDR_WIDTH) |
#define ${IP}_HDR_CLASS(pck_class) (pck_class << ( ${IP}_DEST_IN_HDR_WIDTH+ (4* ${IP}_X_Y_IN_HDR_WIDTH))) |
|
|
#define $IP_wait_for_sending_pck() while (!($IP_ST & $IP_WR_DONE)) |
#define $IP_wait_for_reading_pck() while (!($IP_ST & $IP_RD_DONE)) |
#define ${IP}_wait_for_sending_pck() while (!(${IP}_ST & ${IP}_WR_DONE)) |
#define ${IP}_wait_for_reading_pck() while (!(${IP}_ST & ${IP}_RD_DONE)) |
|
#define $IP_wait_for_getting_pck() while (!($IP_ST & $IP_HAS_PCK)) |
#define ${IP}_wait_for_getting_pck() while (!(${IP}_ST & ${IP}_HAS_PCK)) |
|
/***************************************** |
void send_pck (unsigned int * pck_buffer, unsigned int data_size); |
567,10 → 571,10
unsigned int class |
|
****************************************/ |
inline void $IP_send_pck (unsigned int des_x, unsigned int des_y, volatile unsigned int * pck_buffer, unsigned int data_size, unsigned int pck_class){ |
pck_buffer [0] = $IP_HDR_DEST_CORE_ADDR(des_x, des_y) | $IP_HDR_CLASS(pck_class) ; |
$IP_WR = (unsigned int) (& pck_buffer [0]) + (data_size<<$IP_PTR_WIDTH); |
$IP_wait_for_sending_pck(); |
inline void ${IP}_send_pck (unsigned int des_x, unsigned int des_y, volatile unsigned int * pck_buffer, unsigned int data_size, unsigned int pck_class){ |
pck_buffer [0] = ${IP}_HDR_DEST_CORE_ADDR(des_x, des_y) | ${IP}_HDR_CLASS(pck_class) ; |
${IP}_WR = (unsigned int) (& pck_buffer [0]) + (data_size<<${IP}_PTR_WIDTH); |
${IP}_wait_for_sending_pck(); |
|
} |
|
579,8 → 583,8
save a received packet on pck_buffer |
unsigned int * pck_buffer: the buffer for storing the packet; The read data start from buff[1]; |
********************************************/ |
inline void $IP_save_pck (volatile unsigned int * pck_buffer, unsigned int buffer_size){ |
$IP_RD = (unsigned int) (& pck_buffer [0]) + (buffer_size<<$IP_PTR_WIDTH); |
$IP_wait_for_reading_pck(); |
inline void ${IP}_save_pck (volatile unsigned int * pck_buffer, unsigned int buffer_size){ |
${IP}_RD = (unsigned int) (& pck_buffer [0]) + (buffer_size<<${IP}_PTR_WIDTH); |
${IP}_wait_for_reading_pck(); |
}' |
}, 'ip_gen' ); |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/eth_test/eth_test.SOC
0,0 → 1,1101
$eth_test = bless( { |
'hdl_files' => undef, |
'modules' => {}, |
'soc_name' => 'eth_test', |
'top_ip' => bless( { |
'ports' => { |
'ethmac_md_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'input' |
}, |
'ethmac_mtxd_pad_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '3:0', |
'type' => 'output' |
}, |
'ss_clk_in' => { |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]', |
'instance_name' => 'clk_source0', |
'range' => '', |
'type' => 'input' |
}, |
'aeMB_sys_ena_i' => { |
'intfc_port' => 'enable_i', |
'intfc_name' => 'plug:enable[0]', |
'instance_name' => 'aeMB0', |
'range' => '', |
'type' => 'input' |
}, |
'ethmac_mrxdv_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'input' |
}, |
'ethmac_mdc_pad_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'output' |
}, |
'ethmac_md_pad_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'output' |
}, |
'ss_reset_in' => { |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'instance_name' => 'clk_source0', |
'range' => '', |
'type' => 'input' |
}, |
'ethmac_mcoll_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'input' |
}, |
'ethmac_mtxen_pad_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'output' |
}, |
'ethmac_mcrs_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'input' |
}, |
'uart_readyfordata' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'instance_name' => 'altera_jtag_uart0', |
'range' => '', |
'type' => 'output' |
}, |
'ethmac_mrxd_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '3:0', |
'type' => 'input' |
}, |
'ethmac_mrx_clk_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'input' |
}, |
'ethmac_mtx_clk_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'input' |
}, |
'ethmac_mrxerr_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'input' |
}, |
'uart_dataavailable' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'instance_name' => 'altera_jtag_uart0', |
'range' => '', |
'type' => 'output' |
}, |
'ethmac_md_padoe_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'output' |
}, |
'ethmac_mtxerr_pad_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'output' |
} |
}, |
'interface' => { |
'plug:enable[0]' => { |
'ports' => { |
'aeMB_sys_ena_i' => { |
'intfc_port' => 'enable_i', |
'instance_name' => 'aeMB0', |
'range' => '', |
'type' => 'input' |
} |
} |
}, |
'IO' => { |
'ports' => { |
'ethmac_md_pad_i' => { |
'intfc_port' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'input' |
}, |
'ethmac_mtxd_pad_o' => { |
'intfc_port' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '3:0', |
'type' => 'output' |
}, |
'ethmac_mrxdv_pad_i' => { |
'intfc_port' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'input' |
}, |
'ethmac_mcoll_pad_i' => { |
'intfc_port' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'input' |
}, |
'ethmac_md_pad_o' => { |
'intfc_port' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'output' |
}, |
'ethmac_mdc_pad_o' => { |
'intfc_port' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'output' |
}, |
'ethmac_mtxen_pad_o' => { |
'intfc_port' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'output' |
}, |
'ethmac_mcrs_pad_i' => { |
'intfc_port' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'input' |
}, |
'uart_readyfordata' => { |
'intfc_port' => 'IO', |
'instance_name' => 'altera_jtag_uart0', |
'range' => '', |
'type' => 'output' |
}, |
'ethmac_mrxd_pad_i' => { |
'intfc_port' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '3:0', |
'type' => 'input' |
}, |
'ethmac_mrx_clk_pad_i' => { |
'intfc_port' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'input' |
}, |
'ethmac_mtx_clk_pad_i' => { |
'intfc_port' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'input' |
}, |
'ethmac_mrxerr_pad_i' => { |
'intfc_port' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'input' |
}, |
'uart_dataavailable' => { |
'intfc_port' => 'IO', |
'instance_name' => 'altera_jtag_uart0', |
'range' => '', |
'type' => 'output' |
}, |
'ethmac_md_padoe_o' => { |
'intfc_port' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'output' |
}, |
'ethmac_mtxerr_pad_o' => { |
'intfc_port' => 'IO', |
'instance_name' => 'ethmac_1000', |
'range' => '', |
'type' => 'output' |
} |
} |
}, |
'plug:clk[0]' => { |
'ports' => { |
'ss_clk_in' => { |
'intfc_port' => 'clk_i', |
'instance_name' => 'clk_source0', |
'range' => '', |
'type' => 'input' |
} |
} |
}, |
'plug:reset[0]' => { |
'ports' => { |
'ss_reset_in' => { |
'intfc_port' => 'reset_i', |
'instance_name' => 'clk_source0', |
'range' => '', |
'type' => 'input' |
} |
} |
} |
}, |
'instance_ids' => { |
'aeMB0' => { |
'ports' => { |
'aeMB_sys_ena_i' => { |
'intfc_port' => 'enable_i', |
'intfc_name' => 'plug:enable[0]', |
'range' => '', |
'type' => 'input' |
} |
}, |
'module_name' => 'aeMB_top', |
'category' => 'Processor', |
'instance' => 'aeMB', |
'module' => 'aeMB' |
}, |
'clk_source0' => { |
'ports' => { |
'ss_reset_in' => { |
'intfc_port' => 'reset_i', |
'intfc_name' => 'plug:reset[0]', |
'range' => '', |
'type' => 'input' |
}, |
'ss_clk_in' => { |
'intfc_port' => 'clk_i', |
'intfc_name' => 'plug:clk[0]', |
'range' => '', |
'type' => 'input' |
} |
}, |
'module_name' => 'clk_source', |
'category' => 'source', |
'instance' => 'ss', |
'module' => 'clk_source' |
}, |
'wishbone_bus0' => { |
'module_name' => 'wishbone_bus', |
'category' => 'bus', |
'instance' => 'bus', |
'module' => 'wishbone_bus' |
}, |
'int_ctrl0' => { |
'module_name' => 'int_ctrl', |
'category' => 'interrupt', |
'instance' => 'int_ctrl', |
'module' => 'int_ctrl' |
}, |
'ethmac_1000' => { |
'ports' => { |
'ethmac_md_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'input' |
}, |
'ethmac_mrxd_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '3:0', |
'type' => 'input' |
}, |
'ethmac_mtxd_pad_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '3:0', |
'type' => 'output' |
}, |
'ethmac_mtx_clk_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'input' |
}, |
'ethmac_mrx_clk_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'input' |
}, |
'ethmac_mrxerr_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'input' |
}, |
'ethmac_mrxdv_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'input' |
}, |
'ethmac_md_padoe_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'output' |
}, |
'ethmac_mtxerr_pad_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'output' |
}, |
'ethmac_mcoll_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'input' |
}, |
'ethmac_md_pad_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'output' |
}, |
'ethmac_mdc_pad_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'output' |
}, |
'ethmac_mtxen_pad_o' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'output' |
}, |
'ethmac_mcrs_pad_i' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'input' |
} |
}, |
'module_name' => 'ethtop', |
'category' => 'eth', |
'instance' => 'ethmac', |
'module' => 'ethmac_100' |
}, |
'altera_jtag_uart0' => { |
'ports' => { |
'uart_readyfordata' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'output' |
}, |
'uart_dataavailable' => { |
'intfc_port' => 'IO', |
'intfc_name' => 'IO', |
'range' => '', |
'type' => 'output' |
} |
}, |
'module_name' => 'altera_jtag_uart_wb', |
'category' => 'Jtag', |
'instance' => 'uart', |
'module' => 'altera_jtag_uart' |
}, |
'Altera_single_port_ram0' => { |
'parameters' => { |
'ram_Dw' => { |
'info' => undef, |
'deafult' => '32', |
'global_param' => 1, |
'content' => '8,1024,1', |
'redefine_param' => 1, |
'type' => 'Spin-button' |
}, |
'ram_Aw' => { |
'info' => undef, |
'deafult' => 12, |
'global_param' => 1, |
'content' => '4,31,1', |
'redefine_param' => 1, |
'type' => 'Spin-button' |
} |
}, |
'module_name' => 'Altera_single_port_ram', |
'category' => 'RAM', |
'instance' => 'ram', |
'module' => 'Altera_single_port_ram' |
} |
} |
}, 'ip_gen' ), |
'instances' => { |
'aeMB0' => { |
'aeMB0' => {}, |
'instance_name' => 'aeMB', |
'plugs' => { |
'wb_master' => { |
'connection_num' => undef, |
'value' => 2, |
'nums' => { |
'1' => { |
'connect_socket_num' => '1', |
'connect_id' => 'wishbone_bus0', |
'name' => 'dwb', |
'connect_socket' => 'wb_master' |
}, |
'0' => { |
'connect_socket_num' => '0', |
'connect_id' => 'wishbone_bus0', |
'name' => 'iwb', |
'connect_socket' => 'wb_master' |
} |
}, |
'type' => 'num' |
}, |
'interrupt_cpu' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'connect_socket_num' => '0', |
'connect_id' => 'int_ctrl0', |
'name' => 'intrp', |
'connect_socket' => 'interrupt_cpu' |
} |
}, |
'type' => 'num' |
}, |
'enable' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'connect_socket_num' => undef, |
'connect_id' => 'IO', |
'name' => 'enable', |
'connect_socket' => undef |
} |
}, |
'type' => 'num' |
}, |
'reset' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'connect_socket_num' => '0', |
'connect_id' => 'clk_source0', |
'name' => 'reset', |
'connect_socket' => 'reset' |
} |
}, |
'type' => 'num' |
}, |
'clk' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'connect_socket_num' => '0', |
'connect_id' => 'clk_source0', |
'name' => 'clk', |
'connect_socket' => 'clk' |
} |
}, |
'type' => 'num' |
} |
}, |
'parameters' => { |
'AEMB_XWB' => { |
'value' => ' 7' |
}, |
'AEMB_IDX' => { |
'value' => ' 6' |
}, |
'AEMB_MUL' => { |
'value' => ' 1' |
}, |
'AEMB_IWB' => { |
'value' => ' 32' |
}, |
'AEMB_BSF' => { |
'value' => ' 1' |
}, |
'AEMB_ICH' => { |
'value' => ' 11' |
}, |
'AEMB_DWB' => { |
'value' => ' 32' |
} |
}, |
'parameters_order' => [ |
'AEMB_IWB', |
'AEMB_DWB', |
'AEMB_XWB', |
'AEMB_ICH', |
'AEMB_IDX', |
'AEMB_BSF', |
'AEMB_MUL' |
], |
'sockets' => {}, |
'module_name' => 'aeMB_top', |
'category' => 'Processor', |
'module' => 'aeMB' |
}, |
'clk_source0' => { |
'instance_name' => 'ss', |
'plugs' => { |
'reset' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'connect_socket_num' => undef, |
'connect_id' => 'IO', |
'name' => 'reset', |
'connect_socket' => undef |
} |
}, |
'type' => 'num' |
}, |
'clk' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'connect_socket_num' => undef, |
'connect_id' => 'IO', |
'name' => 'clk', |
'connect_socket' => undef |
} |
}, |
'type' => 'num' |
} |
}, |
'parameters' => {}, |
'clk_source0' => {}, |
'parameters_order' => [], |
'sockets' => { |
'reset' => { |
'connection_num' => 'multi connection', |
'value' => 1, |
'nums' => { |
'0' => { |
'name' => 'reset' |
} |
}, |
'type' => 'num' |
}, |
'clk' => { |
'connection_num' => 'multi connection', |
'value' => 1, |
'nums' => { |
'0' => { |
'name' => 'clk' |
} |
}, |
'type' => 'num' |
} |
}, |
'module_name' => 'clk_source', |
'category' => 'source', |
'module' => 'clk_source' |
}, |
'wishbone_bus0' => { |
'wishbone_bus0' => {}, |
'instance_name' => 'bus', |
'plugs' => { |
'reset' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'connect_socket_num' => '0', |
'connect_id' => 'clk_source0', |
'name' => 'reset', |
'connect_socket' => 'reset' |
} |
}, |
'type' => 'num' |
}, |
'clk' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'connect_socket_num' => '0', |
'connect_id' => 'clk_source0', |
'name' => 'clk', |
'connect_socket' => 'clk' |
} |
}, |
'type' => 'num' |
} |
}, |
'parameters' => { |
'S' => { |
'value' => 4 |
}, |
'SELw' => { |
'value' => 'Dw/8' |
}, |
'Dw' => { |
'value' => '32' |
}, |
'BTEw' => { |
'value' => '2 ' |
}, |
'Aw' => { |
'value' => '32' |
}, |
'M' => { |
'value' => 3 |
}, |
'TAGw' => { |
'value' => '3' |
}, |
'CTIw' => { |
'value' => '3' |
} |
}, |
'parameters_order' => [ |
'M', |
'S', |
'Dw', |
'Aw', |
'SELw', |
'TAGw', |
'CTIw', |
'BTEw' |
], |
'sockets' => { |
'wb_master' => { |
'connection_num' => 'single connection', |
'value' => 'M', |
'nums' => { |
'0' => { |
'name' => 'wb_master' |
} |
}, |
'type' => 'param' |
}, |
'wb_addr_map' => { |
'connection_num' => 'single connection', |
'value' => 1, |
'nums' => { |
'0' => { |
'name' => 'wb_addr_map' |
} |
}, |
'type' => 'num' |
}, |
'wb_slave' => { |
'connection_num' => 'single connection', |
'value' => 'S', |
'nums' => { |
'0' => { |
'name' => 'wb_slave' |
} |
}, |
'type' => 'param' |
} |
}, |
'module_name' => 'wishbone_bus', |
'category' => 'bus', |
'module' => 'wishbone_bus' |
}, |
'int_ctrl0' => { |
'instance_name' => 'int_ctrl', |
'int_ctrl0' => {}, |
'plugs' => { |
'reset' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'connect_socket_num' => '0', |
'connect_id' => 'clk_source0', |
'name' => 'reset', |
'connect_socket' => 'reset' |
} |
}, |
'type' => 'num' |
}, |
'clk' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'connect_socket_num' => '0', |
'connect_id' => 'clk_source0', |
'name' => 'clk', |
'connect_socket' => 'clk' |
} |
}, |
'type' => 'num' |
}, |
'wb_slave' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'base' => 2650800128, |
'width' => 5, |
'connect_socket_num' => '2', |
'name' => 'wb', |
'end' => 2650800159, |
'connect_socket' => 'wb_slave', |
'connect_id' => 'wishbone_bus0', |
'addr' => '0x9e00_0000 0x9eff_ffff IDE Controller' |
} |
}, |
'type' => 'num' |
} |
}, |
'parameters' => { |
'Aw' => { |
'value' => ' 3' |
}, |
'SELw' => { |
'value' => ' 4 ' |
}, |
'INT_NUM' => { |
'value' => 1 |
}, |
'Dw' => { |
'value' => ' 32' |
} |
}, |
'parameters_order' => [ |
'INT_NUM', |
'Dw', |
'Aw', |
'SELw' |
], |
'sockets' => { |
'interrupt_cpu' => { |
'connection_num' => 'single connection', |
'value' => 1, |
'nums' => { |
'0' => { |
'name' => 'int_cpu' |
} |
}, |
'type' => 'num' |
}, |
'interrupt_peripheral' => { |
'connection_num' => 'single connection', |
'value' => 'INT_NUM', |
'nums' => { |
'0' => { |
'name' => 'int_periph' |
} |
}, |
'type' => 'param' |
} |
}, |
'module_name' => 'int_ctrl', |
'category' => 'interrupt', |
'module' => 'int_ctrl' |
}, |
'altera_jtag_uart0' => { |
'instance_name' => 'uart', |
'altera_jtag_uart0' => {}, |
'plugs' => { |
'reset' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'connect_socket_num' => '0', |
'connect_id' => 'clk_source0', |
'name' => 'reset', |
'connect_socket' => 'reset' |
} |
}, |
'type' => 'num' |
}, |
'interrupt_peripheral' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'connect_socket_num' => undef, |
'connect_id' => 'NC', |
'name' => 'interrupt_peripheral', |
'connect_socket' => undef |
} |
}, |
'type' => 'num' |
}, |
'clk' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'connect_socket_num' => '0', |
'connect_id' => 'clk_source0', |
'name' => 'clk', |
'connect_socket' => 'clk' |
} |
}, |
'type' => 'num' |
}, |
'wb_slave' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'base' => 2415919104, |
'width' => 5, |
'connect_socket_num' => '3', |
'name' => 'wb_slave', |
'end' => 2415919135, |
'connect_socket' => 'wb_slave', |
'connect_id' => 'wishbone_bus0', |
'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller' |
} |
}, |
'type' => 'num' |
} |
}, |
'parameters_order' => [], |
'sockets' => {}, |
'module_name' => 'altera_jtag_uart_wb', |
'category' => 'Jtag', |
'module' => 'altera_jtag_uart' |
}, |
'Altera_single_port_ram0' => { |
'instance_name' => 'ram', |
'Altera_single_port_ram0' => {}, |
'plugs' => { |
'reset' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'connect_socket_num' => '0', |
'connect_id' => 'clk_source0', |
'name' => 'reset', |
'connect_socket' => 'reset' |
} |
}, |
'type' => 'num' |
}, |
'clk' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'connect_socket_num' => '0', |
'connect_id' => 'clk_source0', |
'name' => 'clk', |
'connect_socket' => 'clk' |
} |
}, |
'type' => 'num' |
}, |
'wb_slave' => { |
'connection_num' => undef, |
'value' => 1, |
'nums' => { |
'0' => { |
'base' => 0, |
'width' => 'WBAw', |
'connect_socket_num' => '1', |
'name' => 'wb_slave', |
'end' => 16383, |
'connect_socket' => 'wb_slave', |
'connect_id' => 'wishbone_bus0', |
'addr' => '0x0000_0000 0x3fff_ffff RAM' |
} |
}, |
'type' => 'num' |
} |
}, |
'parameters' => { |
'RAM_TAG_STRING' => { |
'value' => 'i2s(CORE_ID)' |
}, |
'SELw' => { |
'value' => '4' |
}, |
'Dw' => { |
'value' => '32' |
}, |
'WBAw' => { |
'value' => 'Aw+2' |
}, |
'BTEw' => { |
'value' => '2' |
}, |
'Aw' => { |
'value' => 12 |
}, |
'TAGw' => { |
'value' => '3' |
}, |
'CTIw' => { |
'value' => '3' |
} |
}, |
'parameters_order' => [ |
'Dw', |
'Aw', |
'TAGw', |
'SELw', |
'CTIw', |
'BTEw', |
'RAM_TAG_STRING', |
'WBAw' |
], |
'sockets' => {}, |
'module_name' => 'Altera_single_port_ram', |
'category' => 'RAM', |
'module' => 'Altera_single_port_ram' |
}, |
'ethmac_1000' => { |
'instance_name' => 'ethmac', |
'plugs' => { |
'wb_master' => { |
'connection_num' => undef, |
'value' => 1, |
'type' => 'num', |
'nums' => { |
'0' => { |
'connect_id' => 'wishbone_bus0', |
'connect_socket_num' => '2', |
'name' => 'wb_master', |
'connect_socket' => 'wb_master' |
} |
} |
}, |
'clk' => { |
'connection_num' => undef, |
'value' => 1, |
'type' => 'num', |
'nums' => { |
'0' => { |
'connect_id' => 'clk_source0', |
'connect_socket_num' => '0', |
'name' => 'clk', |
'connect_socket' => 'clk' |
} |
} |
}, |
'interrupt_peripheral' => { |
'connection_num' => undef, |
'value' => 1, |
'type' => 'num', |
'nums' => { |
'0' => { |
'connect_id' => 'int_ctrl0', |
'connect_socket_num' => '0', |
'name' => 'interrupt_peripheral', |
'connect_socket' => 'interrupt_peripheral' |
} |
} |
}, |
'reset' => { |
'connection_num' => undef, |
'value' => 1, |
'type' => 'num', |
'nums' => { |
'0' => { |
'connect_id' => 'clk_source0', |
'connect_socket_num' => '0', |
'name' => 'reset', |
'connect_socket' => 'reset' |
} |
} |
}, |
'wb_slave' => { |
'connection_num' => undef, |
'value' => 1, |
'type' => 'num', |
'nums' => { |
'0' => { |
'connect_socket_num' => '0', |
'width' => 11, |
'base' => 2449473536, |
'name' => 'wb_slave', |
'connect_socket' => 'wb_slave', |
'end' => 2449475583, |
'connect_id' => 'wishbone_bus0', |
'addr' => '0x9200_0000 0x92ff_ffff Ethernet Controller' |
} |
} |
} |
}, |
'parameters' => { |
'RX_FIFO_DEPTH' => { |
'value' => ' 16' |
}, |
'TX_FIFO_DATA_WIDTH' => { |
'value' => ' 32' |
}, |
'RX_FIFO_DATA_WIDTH' => { |
'value' => ' 32' |
}, |
'RX_FIFO_CNT_WIDTH' => { |
'value' => ' 5' |
}, |
'TX_FIFO_CNT_WIDTH' => { |
'value' => ' 5' |
}, |
'TX_FIFO_DEPTH' => { |
'value' => ' 16' |
} |
}, |
'parameters_order' => [ |
'TX_FIFO_DATA_WIDTH', |
'TX_FIFO_DEPTH', |
'TX_FIFO_CNT_WIDTH', |
'RX_FIFO_DATA_WIDTH', |
'RX_FIFO_DEPTH', |
'RX_FIFO_CNT_WIDTH' |
], |
'sockets' => {}, |
'module_name' => 'ethtop', |
'ethmac_1000' => {}, |
'category' => 'eth', |
'module' => 'ethmac_100' |
} |
}, |
'instance_order' => [ |
'aeMB0', |
'clk_source0', |
'wishbone_bus0', |
'Altera_single_port_ram0', |
'int_ctrl0', |
'altera_jtag_uart0', |
'ethmac_1000' |
] |
}, 'soc' ); |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/eth_test/eth_test.qsf
0,0 → 1,1324
# -------------------------------------------------------------------------- # |
# |
# Copyright (C) 1991-2013 Altera Corporation |
# Your use of Altera Corporation's design tools, logic functions |
# and other software and tools, and its AMPP partner logic |
# functions, and any output files from any of the foregoing |
# (including device programming or simulation files), and any |
# associated documentation or information are expressly subject |
# to the terms and conditions of the Altera Program License |
# Subscription Agreement, Altera MegaCore Function License |
# Agreement, or other applicable license agreement, including, |
# without limitation, that your use is for the sole purpose of |
# programming logic devices manufactured by Altera and sold by |
# Altera or its authorized distributors. Please refer to the |
# applicable agreement for further details. |
# |
# -------------------------------------------------------------------------- # |
# |
# Quartus II 64-Bit |
# Version 13.0.0 Build 156 04/24/2013 SJ Full Version |
# Date created = 18:19:48 May 05, 2016 |
# |
# -------------------------------------------------------------------------- # |
# |
# Notes: |
# |
# 1) The default values for assignments are stored in the file: |
# eth_test_assignment_defaults.qdf |
# If this file doesn't exist, see file: |
# assignment_defaults.qdf |
# |
# 2) Altera recommends that you do not modify this file. This |
# file is updated automatically by the Quartus II software |
# and any changes you make may be lost or overwritten. |
# |
# -------------------------------------------------------------------------- # |
|
#============================================================ |
# Build by Altera University Program |
#============================================================ |
set_global_assignment -name FAMILY "Cyclone IV E" |
set_global_assignment -name DEVICE EP4CE115F29C8 |
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga |
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" |
|
#============================================================ |
# CLOCK |
#============================================================ |
set_location_assignment PIN_Y2 -to CLOCK_50 |
set_location_assignment PIN_AG14 -to CLOCK2_50 |
set_location_assignment PIN_AG15 -to CLOCK3_50 |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50 |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50 |
|
|
#============================================================ |
# Sma |
#============================================================ |
set_location_assignment PIN_AH14 -to SMA_CLKIN |
set_location_assignment PIN_AE23 -to SMA_CLKOUT |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKIN |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKOUT |
|
#============================================================ |
# LED |
#============================================================ |
set_location_assignment PIN_E21 -to LEDG[0] |
set_location_assignment PIN_E22 -to LEDG[1] |
set_location_assignment PIN_E25 -to LEDG[2] |
set_location_assignment PIN_E24 -to LEDG[3] |
set_location_assignment PIN_H21 -to LEDG[4] |
set_location_assignment PIN_G20 -to LEDG[5] |
set_location_assignment PIN_G22 -to LEDG[6] |
set_location_assignment PIN_G21 -to LEDG[7] |
set_location_assignment PIN_F17 -to LEDG[8] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[0] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[1] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[2] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[3] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[4] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[5] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[6] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[7] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[8] |
|
set_location_assignment PIN_G19 -to LEDR[0] |
set_location_assignment PIN_E19 -to LEDR[2] |
set_location_assignment PIN_F19 -to LEDR[1] |
set_location_assignment PIN_F21 -to LEDR[3] |
set_location_assignment PIN_F18 -to LEDR[4] |
set_location_assignment PIN_E18 -to LEDR[5] |
set_location_assignment PIN_J19 -to LEDR[6] |
set_location_assignment PIN_H19 -to LEDR[7] |
set_location_assignment PIN_J17 -to LEDR[8] |
set_location_assignment PIN_G17 -to LEDR[9] |
set_location_assignment PIN_J15 -to LEDR[10] |
set_location_assignment PIN_H16 -to LEDR[11] |
set_location_assignment PIN_J16 -to LEDR[12] |
set_location_assignment PIN_H17 -to LEDR[13] |
set_location_assignment PIN_F15 -to LEDR[14] |
set_location_assignment PIN_G15 -to LEDR[15] |
set_location_assignment PIN_G16 -to LEDR[16] |
set_location_assignment PIN_H15 -to LEDR[17] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[0] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[1] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[3] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[4] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[5] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[6] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[7] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[8] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[9] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[10] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[11] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[12] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[13] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[14] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[15] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[16] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[17] |
|
#============================================================ |
# KEY |
#============================================================ |
set_location_assignment PIN_M23 -to KEY[0] |
set_location_assignment PIN_M21 -to KEY[1] |
set_location_assignment PIN_N21 -to KEY[2] |
set_location_assignment PIN_R24 -to KEY[3] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[0] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[1] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[2] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[3] |
|
#============================================================ |
# SW |
#============================================================ |
set_location_assignment PIN_AB28 -to SW[0] |
set_location_assignment PIN_AC28 -to SW[1] |
set_location_assignment PIN_AC27 -to SW[2] |
set_location_assignment PIN_AD27 -to SW[3] |
set_location_assignment PIN_AB27 -to SW[4] |
set_location_assignment PIN_AC26 -to SW[5] |
set_location_assignment PIN_AD26 -to SW[6] |
set_location_assignment PIN_AB26 -to SW[7] |
set_location_assignment PIN_AC25 -to SW[8] |
set_location_assignment PIN_AB25 -to SW[9] |
set_location_assignment PIN_AC24 -to SW[10] |
set_location_assignment PIN_AB24 -to SW[11] |
set_location_assignment PIN_AB23 -to SW[12] |
set_location_assignment PIN_AA24 -to SW[13] |
set_location_assignment PIN_AA23 -to SW[14] |
set_location_assignment PIN_AA22 -to SW[15] |
set_location_assignment PIN_Y24 -to SW[16] |
set_location_assignment PIN_Y23 -to SW[17] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[4] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[5] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[6] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[7] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[8] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[9] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[10] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[11] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[12] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[13] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[14] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[15] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[16] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[17] |
|
#============================================================ |
# SEG7 |
#============================================================ |
set_location_assignment PIN_G18 -to HEX0[0] |
set_location_assignment PIN_F22 -to HEX0[1] |
set_location_assignment PIN_E17 -to HEX0[2] |
set_location_assignment PIN_L26 -to HEX0[3] |
set_location_assignment PIN_L25 -to HEX0[4] |
set_location_assignment PIN_J22 -to HEX0[5] |
set_location_assignment PIN_H22 -to HEX0[6] |
set_location_assignment PIN_M24 -to HEX1[0] |
set_location_assignment PIN_Y22 -to HEX1[1] |
set_location_assignment PIN_W21 -to HEX1[2] |
set_location_assignment PIN_W22 -to HEX1[3] |
set_location_assignment PIN_W25 -to HEX1[4] |
set_location_assignment PIN_U23 -to HEX1[5] |
set_location_assignment PIN_U24 -to HEX1[6] |
set_location_assignment PIN_AA25 -to HEX2[0] |
set_location_assignment PIN_AA26 -to HEX2[1] |
set_location_assignment PIN_Y25 -to HEX2[2] |
set_location_assignment PIN_W26 -to HEX2[3] |
set_location_assignment PIN_Y26 -to HEX2[4] |
set_location_assignment PIN_W27 -to HEX2[5] |
set_location_assignment PIN_W28 -to HEX2[6] |
set_location_assignment PIN_V21 -to HEX3[0] |
set_location_assignment PIN_U21 -to HEX3[1] |
set_location_assignment PIN_AB20 -to HEX3[2] |
set_location_assignment PIN_AA21 -to HEX3[3] |
set_location_assignment PIN_AD24 -to HEX3[4] |
set_location_assignment PIN_AF23 -to HEX3[5] |
set_location_assignment PIN_Y19 -to HEX3[6] |
set_location_assignment PIN_AB19 -to HEX4[0] |
set_location_assignment PIN_AA19 -to HEX4[1] |
set_location_assignment PIN_AG21 -to HEX4[2] |
set_location_assignment PIN_AH21 -to HEX4[3] |
set_location_assignment PIN_AE19 -to HEX4[4] |
set_location_assignment PIN_AF19 -to HEX4[5] |
set_location_assignment PIN_AE18 -to HEX4[6] |
set_location_assignment PIN_AD18 -to HEX5[0] |
set_location_assignment PIN_AC18 -to HEX5[1] |
set_location_assignment PIN_AB18 -to HEX5[2] |
set_location_assignment PIN_AH19 -to HEX5[3] |
set_location_assignment PIN_AG19 -to HEX5[4] |
set_location_assignment PIN_AF18 -to HEX5[5] |
set_location_assignment PIN_AH18 -to HEX5[6] |
set_location_assignment PIN_AA17 -to HEX6[0] |
set_location_assignment PIN_AB16 -to HEX6[1] |
set_location_assignment PIN_AA16 -to HEX6[2] |
set_location_assignment PIN_AB17 -to HEX6[3] |
set_location_assignment PIN_AB15 -to HEX6[4] |
set_location_assignment PIN_AA15 -to HEX6[5] |
set_location_assignment PIN_AC17 -to HEX6[6] |
set_location_assignment PIN_AD17 -to HEX7[0] |
set_location_assignment PIN_AE17 -to HEX7[1] |
set_location_assignment PIN_AG17 -to HEX7[2] |
set_location_assignment PIN_AH17 -to HEX7[3] |
set_location_assignment PIN_AF17 -to HEX7[4] |
set_location_assignment PIN_AG18 -to HEX7[5] |
set_location_assignment PIN_AA14 -to HEX7[6] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[0] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[1] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[2] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[3] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[4] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[5] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[6] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[0] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[1] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[2] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[3] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[4] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[5] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[6] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[0] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[1] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[2] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[3] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[4] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[5] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[6] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[0] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[2] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[3] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[4] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[5] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[6] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[2] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[3] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[4] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[5] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[6] |
|
#============================================================ |
# LCD |
#============================================================ |
set_location_assignment PIN_L6 -to LCD_BLON |
set_location_assignment PIN_M5 -to LCD_DATA[7] |
set_location_assignment PIN_M3 -to LCD_DATA[6] |
set_location_assignment PIN_K2 -to LCD_DATA[5] |
set_location_assignment PIN_K1 -to LCD_DATA[4] |
set_location_assignment PIN_K7 -to LCD_DATA[3] |
set_location_assignment PIN_L2 -to LCD_DATA[2] |
set_location_assignment PIN_L1 -to LCD_DATA[1] |
set_location_assignment PIN_L3 -to LCD_DATA[0] |
set_location_assignment PIN_L4 -to LCD_EN |
set_location_assignment PIN_M1 -to LCD_RW |
set_location_assignment PIN_M2 -to LCD_RS |
set_location_assignment PIN_L5 -to LCD_ON |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_ON |
|
#============================================================ |
# RS232 |
#============================================================ |
set_location_assignment PIN_G9 -to UART_TXD |
set_location_assignment PIN_G12 -to UART_RXD |
set_location_assignment PIN_G14 -to UART_CTS |
set_location_assignment PIN_J13 -to UART_RTS |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS |
|
#============================================================ |
# PS2 |
#============================================================ |
set_location_assignment PIN_G6 -to PS2_KBCLK |
set_location_assignment PIN_H5 -to PS2_KBDAT |
set_location_assignment PIN_G5 -to PS2_MSCLK |
set_location_assignment PIN_F5 -to PS2_MSDAT |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_MSCLK |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_MSDAT |
|
#============================================================ |
# SDCARD |
#============================================================ |
set_location_assignment PIN_AE14 -to SD_DAT[0] |
set_location_assignment PIN_AF13 -to SD_DAT[1] |
set_location_assignment PIN_AB14 -to SD_DAT[2] |
set_location_assignment PIN_AC14 -to SD_DAT[3] |
set_location_assignment PIN_AE13 -to SD_CLK |
set_location_assignment PIN_AD14 -to SD_CMD |
set_location_assignment PIN_AF14 -to SD_WP_N |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[2] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[3] |
|
#============================================================ |
# VGA |
#============================================================ |
set_location_assignment PIN_D12 -to VGA_B[7] |
set_location_assignment PIN_D11 -to VGA_B[6] |
set_location_assignment PIN_C12 -to VGA_B[5] |
set_location_assignment PIN_A11 -to VGA_B[4] |
set_location_assignment PIN_B11 -to VGA_B[3] |
set_location_assignment PIN_C11 -to VGA_B[2] |
set_location_assignment PIN_A10 -to VGA_B[1] |
set_location_assignment PIN_B10 -to VGA_B[0] |
set_location_assignment PIN_C9 -to VGA_G[7] |
set_location_assignment PIN_F10 -to VGA_G[6] |
set_location_assignment PIN_B8 -to VGA_G[5] |
set_location_assignment PIN_C8 -to VGA_G[4] |
set_location_assignment PIN_H12 -to VGA_G[3] |
set_location_assignment PIN_F8 -to VGA_G[2] |
set_location_assignment PIN_G11 -to VGA_G[1] |
set_location_assignment PIN_G8 -to VGA_G[0] |
set_location_assignment PIN_H10 -to VGA_R[7] |
set_location_assignment PIN_H8 -to VGA_R[6] |
set_location_assignment PIN_J12 -to VGA_R[5] |
set_location_assignment PIN_G10 -to VGA_R[4] |
set_location_assignment PIN_F12 -to VGA_R[3] |
set_location_assignment PIN_D10 -to VGA_R[2] |
set_location_assignment PIN_E11 -to VGA_R[1] |
set_location_assignment PIN_E12 -to VGA_R[0] |
set_location_assignment PIN_A12 -to VGA_CLK |
set_location_assignment PIN_F11 -to VGA_BLANK_N |
set_location_assignment PIN_C10 -to VGA_SYNC_N |
set_location_assignment PIN_G13 -to VGA_HS |
set_location_assignment PIN_C13 -to VGA_VS |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7] |
|
#============================================================ |
# Audio |
#============================================================ |
set_location_assignment PIN_D1 -to AUD_DACDAT |
set_location_assignment PIN_E3 -to AUD_DACLRCK |
set_location_assignment PIN_D2 -to AUD_ADCDAT |
set_location_assignment PIN_C2 -to AUD_ADCLRCK |
set_location_assignment PIN_E1 -to AUD_XCK |
set_location_assignment PIN_F2 -to AUD_BCLK |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK |
|
#============================================================ |
# I2C for EEPROM |
#============================================================ |
set_location_assignment PIN_D14 -to EEP_I2C_SCLK |
set_location_assignment PIN_E14 -to EEP_I2C_SDAT |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SCLK |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SDAT |
|
#============================================================ |
# I2C for Audioand Tv-Decode 1 and 2 |
#============================================================ |
set_location_assignment PIN_B7 -to I2C_SCLK |
set_location_assignment PIN_A8 -to I2C_SDAT |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT |
|
#============================================================ |
# Ethernet 0 |
#============================================================ |
set_location_assignment PIN_A17 -to ENET0_GTX_CLK |
set_location_assignment PIN_A21 -to ENET0_INT_N |
set_location_assignment PIN_C20 -to ENET0_MDC |
set_location_assignment PIN_B21 -to ENET0_MDIO |
set_location_assignment PIN_C19 -to ENET0_RESET_N |
set_location_assignment PIN_A15 -to ENET0_RX_CLK |
set_location_assignment PIN_E15 -to ENET0_RX_COL |
set_location_assignment PIN_D15 -to ENET0_RX_CRS |
set_location_assignment PIN_C16 -to ENET0_RX_DATA[0] |
set_location_assignment PIN_D16 -to ENET0_RX_DATA[1] |
set_location_assignment PIN_D17 -to ENET0_RX_DATA[2] |
set_location_assignment PIN_C15 -to ENET0_RX_DATA[3] |
set_location_assignment PIN_C17 -to ENET0_RX_DV |
set_location_assignment PIN_D18 -to ENET0_RX_ER |
set_location_assignment PIN_B17 -to ENET0_TX_CLK |
set_location_assignment PIN_C18 -to ENET0_TX_DATA[0] |
set_location_assignment PIN_D19 -to ENET0_TX_DATA[1] |
set_location_assignment PIN_A19 -to ENET0_TX_DATA[2] |
set_location_assignment PIN_B19 -to ENET0_TX_DATA[3] |
set_location_assignment PIN_A18 -to ENET0_TX_EN |
set_location_assignment PIN_B18 -to ENET0_TX_ER |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[0] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[0] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[1] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[1] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[2] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[3] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[3] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_GTX_CLK |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_EN |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_ER |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RESET_N |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DV |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_ER |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CRS |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_COL |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CLK |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_CLK |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDC |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDIO |
|
#============================================================ |
# Ethernet 1 |
#============================================================ |
set_location_assignment PIN_C23 -to ENET1_GTX_CLK |
set_location_assignment PIN_D24 -to ENET1_INT_N |
set_location_assignment PIN_D23 -to ENET1_MDC |
set_location_assignment PIN_D25 -to ENET1_MDIO |
set_location_assignment PIN_D22 -to ENET1_RESET_N |
set_location_assignment PIN_B15 -to ENET1_RX_CLK |
set_location_assignment PIN_B22 -to ENET1_RX_COL |
set_location_assignment PIN_D20 -to ENET1_RX_CRS |
set_location_assignment PIN_B23 -to ENET1_RX_DATA[0] |
set_location_assignment PIN_C21 -to ENET1_RX_DATA[1] |
set_location_assignment PIN_A23 -to ENET1_RX_DATA[2] |
set_location_assignment PIN_D21 -to ENET1_RX_DATA[3] |
set_location_assignment PIN_A22 -to ENET1_RX_DV |
set_location_assignment PIN_C24 -to ENET1_RX_ER |
set_location_assignment PIN_C22 -to ENET1_TX_CLK |
set_location_assignment PIN_C25 -to ENET1_TX_DATA[0] |
set_location_assignment PIN_A26 -to ENET1_TX_DATA[1] |
set_location_assignment PIN_B26 -to ENET1_TX_DATA[2] |
set_location_assignment PIN_C26 -to ENET1_TX_DATA[3] |
set_location_assignment PIN_B25 -to ENET1_TX_EN |
set_location_assignment PIN_A25 -to ENET1_TX_ER |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[0] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[0] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[1] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[1] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[2] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[2] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[3] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[3] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_GTX_CLK |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_EN |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_ER |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_INT_N |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RESET_N |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DV |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_ER |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CRS |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_COL |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CLK |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_CLK |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDC |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDIO |
|
set_location_assignment PIN_C14 -to ENET0_LINK100 |
set_location_assignment PIN_D13 -to ENET1_LINK100 |
set_location_assignment PIN_A14 -to ENETCLK_25 |
|
#============================================================ |
# TV Decoder |
#============================================================ |
set_location_assignment PIN_F7 -to TD_DATA[7] |
set_location_assignment PIN_E7 -to TD_DATA[6] |
set_location_assignment PIN_D6 -to TD_DATA[5] |
set_location_assignment PIN_D7 -to TD_DATA[4] |
set_location_assignment PIN_C7 -to TD_DATA[3] |
set_location_assignment PIN_D8 -to TD_DATA[2] |
set_location_assignment PIN_A7 -to TD_DATA[1] |
set_location_assignment PIN_E8 -to TD_DATA[0] |
set_location_assignment PIN_B14 -to TD_CLK27 |
set_location_assignment PIN_G7 -to TD_RESET_N |
set_location_assignment PIN_E4 -to TD_VS |
set_location_assignment PIN_E5 -to TD_HS |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27 |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7] |
|
#============================================================ |
# USB |
#============================================================ |
set_location_assignment PIN_D4 -to OTG_DACK_N[1] |
set_location_assignment PIN_C4 -to OTG_DACK_N[0] |
set_location_assignment PIN_A3 -to OTG_CS_N |
set_location_assignment PIN_B3 -to OTG_OE_N |
set_location_assignment PIN_B4 -to OTG_DREQ[1] |
set_location_assignment PIN_J1 -to OTG_DREQ[0] |
set_location_assignment PIN_A4 -to OTG_WE_N |
set_location_assignment PIN_H7 -to OTG_ADDR[0] |
set_location_assignment PIN_C3 -to OTG_ADDR[1] |
set_location_assignment PIN_C6 -to OTG_FSPEED |
set_location_assignment PIN_B6 -to OTG_LSPEED |
set_location_assignment PIN_D5 -to OTG_INT[1] |
set_location_assignment PIN_A6 -to OTG_INT[0] |
set_location_assignment PIN_C5 -to OTG_RST_N |
set_location_assignment PIN_J6 -to OTG_DATA[0] |
set_location_assignment PIN_K4 -to OTG_DATA[1] |
set_location_assignment PIN_J5 -to OTG_DATA[2] |
set_location_assignment PIN_K3 -to OTG_DATA[3] |
set_location_assignment PIN_J4 -to OTG_DATA[4] |
set_location_assignment PIN_J3 -to OTG_DATA[5] |
set_location_assignment PIN_J7 -to OTG_DATA[6] |
set_location_assignment PIN_H6 -to OTG_DATA[7] |
set_location_assignment PIN_H3 -to OTG_DATA[8] |
set_location_assignment PIN_H4 -to OTG_DATA[9] |
set_location_assignment PIN_G1 -to OTG_DATA[10] |
set_location_assignment PIN_G2 -to OTG_DATA[11] |
set_location_assignment PIN_G3 -to OTG_DATA[12] |
set_location_assignment PIN_F1 -to OTG_DATA[13] |
set_location_assignment PIN_F3 -to OTG_DATA[14] |
set_location_assignment PIN_G4 -to OTG_DATA[15] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[2] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[3] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[4] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[5] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[6] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[7] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[8] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[9] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[10] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[11] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[12] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[13] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[14] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[15] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_CS_N |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_WE_N |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_OE_N |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RST_N |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DACK_N[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DACK_N[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_FSPEED |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_LSPEED |
|
#============================================================ |
# IR Receiver |
#============================================================ |
set_location_assignment PIN_Y15 -to IRDA_RXD |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD |
|
#============================================================ |
# SDRAM |
#============================================================ |
set_location_assignment PIN_AE5 -to DRAM_CLK |
set_location_assignment PIN_U1 -to DRAM_DQ[31] |
set_location_assignment PIN_U4 -to DRAM_DQ[30] |
set_location_assignment PIN_T3 -to DRAM_DQ[29] |
set_location_assignment PIN_R3 -to DRAM_DQ[28] |
set_location_assignment PIN_R2 -to DRAM_DQ[27] |
set_location_assignment PIN_R1 -to DRAM_DQ[26] |
set_location_assignment PIN_R7 -to DRAM_DQ[25] |
set_location_assignment PIN_U5 -to DRAM_DQ[24] |
set_location_assignment PIN_M8 -to DRAM_DQ[16] |
set_location_assignment PIN_L8 -to DRAM_DQ[17] |
set_location_assignment PIN_P2 -to DRAM_DQ[18] |
set_location_assignment PIN_N3 -to DRAM_DQ[19] |
set_location_assignment PIN_N4 -to DRAM_DQ[20] |
set_location_assignment PIN_M4 -to DRAM_DQ[21] |
set_location_assignment PIN_M7 -to DRAM_DQ[22] |
set_location_assignment PIN_L7 -to DRAM_DQ[23] |
set_location_assignment PIN_Y3 -to DRAM_DQ[8] |
set_location_assignment PIN_Y4 -to DRAM_DQ[9] |
set_location_assignment PIN_AB1 -to DRAM_DQ[10] |
set_location_assignment PIN_AA3 -to DRAM_DQ[11] |
set_location_assignment PIN_AB2 -to DRAM_DQ[12] |
set_location_assignment PIN_AC1 -to DRAM_DQ[13] |
set_location_assignment PIN_AB3 -to DRAM_DQ[14] |
set_location_assignment PIN_AC2 -to DRAM_DQ[15] |
set_location_assignment PIN_W3 -to DRAM_DQ[0] |
set_location_assignment PIN_W2 -to DRAM_DQ[1] |
set_location_assignment PIN_V4 -to DRAM_DQ[2] |
set_location_assignment PIN_W1 -to DRAM_DQ[3] |
set_location_assignment PIN_V3 -to DRAM_DQ[4] |
set_location_assignment PIN_V2 -to DRAM_DQ[5] |
set_location_assignment PIN_V1 -to DRAM_DQ[6] |
set_location_assignment PIN_U3 -to DRAM_DQ[7] |
set_location_assignment PIN_W4 -to DRAM_DQM[1] |
set_location_assignment PIN_K8 -to DRAM_DQM[2] |
set_location_assignment PIN_U2 -to DRAM_DQM[0] |
set_location_assignment PIN_N8 -to DRAM_DQM[3] |
set_location_assignment PIN_U6 -to DRAM_RAS_N |
set_location_assignment PIN_V7 -to DRAM_CAS_N |
set_location_assignment PIN_AA6 -to DRAM_CKE |
set_location_assignment PIN_V6 -to DRAM_WE_N |
set_location_assignment PIN_T4 -to DRAM_CS_N |
set_location_assignment PIN_U7 -to DRAM_BA[0] |
set_location_assignment PIN_R4 -to DRAM_BA[1] |
set_location_assignment PIN_Y7 -to DRAM_ADDR[12] |
set_location_assignment PIN_AA5 -to DRAM_ADDR[11] |
set_location_assignment PIN_R5 -to DRAM_ADDR[10] |
set_location_assignment PIN_Y6 -to DRAM_ADDR[9] |
set_location_assignment PIN_Y5 -to DRAM_ADDR[8] |
set_location_assignment PIN_AA7 -to DRAM_ADDR[7] |
set_location_assignment PIN_W7 -to DRAM_ADDR[6] |
set_location_assignment PIN_W8 -to DRAM_ADDR[5] |
set_location_assignment PIN_V5 -to DRAM_ADDR[4] |
set_location_assignment PIN_P1 -to DRAM_ADDR[3] |
set_location_assignment PIN_U8 -to DRAM_ADDR[2] |
set_location_assignment PIN_V8 -to DRAM_ADDR[1] |
set_location_assignment PIN_R6 -to DRAM_ADDR[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[2] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[3] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[16] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[17] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[18] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[19] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[20] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[21] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[22] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[23] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[24] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[25] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[26] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[27] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[28] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[29] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[30] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[31] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] |
|
#============================================================ |
# SRAM |
#============================================================ |
set_location_assignment PIN_AG3 -to SRAM_DQ[15] |
set_location_assignment PIN_AF3 -to SRAM_DQ[14] |
set_location_assignment PIN_AE4 -to SRAM_DQ[13] |
set_location_assignment PIN_AE3 -to SRAM_DQ[12] |
set_location_assignment PIN_AE1 -to SRAM_DQ[11] |
set_location_assignment PIN_AE2 -to SRAM_DQ[10] |
set_location_assignment PIN_AD2 -to SRAM_DQ[9] |
set_location_assignment PIN_AD1 -to SRAM_DQ[8] |
set_location_assignment PIN_AF7 -to SRAM_DQ[7] |
set_location_assignment PIN_AH6 -to SRAM_DQ[6] |
set_location_assignment PIN_AG6 -to SRAM_DQ[5] |
set_location_assignment PIN_AF6 -to SRAM_DQ[4] |
set_location_assignment PIN_AH4 -to SRAM_DQ[3] |
set_location_assignment PIN_AG4 -to SRAM_DQ[2] |
set_location_assignment PIN_AF4 -to SRAM_DQ[1] |
set_location_assignment PIN_AH3 -to SRAM_DQ[0] |
set_location_assignment PIN_AC4 -to SRAM_UB_N |
set_location_assignment PIN_AD4 -to SRAM_LB_N |
set_location_assignment PIN_AF8 -to SRAM_CE_N |
set_location_assignment PIN_AD5 -to SRAM_OE_N |
set_location_assignment PIN_AE8 -to SRAM_WE_N |
set_location_assignment PIN_AE6 -to SRAM_ADDR[5] |
set_location_assignment PIN_AB5 -to SRAM_ADDR[6] |
set_location_assignment PIN_AC5 -to SRAM_ADDR[7] |
set_location_assignment PIN_AF5 -to SRAM_ADDR[8] |
set_location_assignment PIN_T7 -to SRAM_ADDR[9] |
set_location_assignment PIN_AF2 -to SRAM_ADDR[10] |
set_location_assignment PIN_AD3 -to SRAM_ADDR[11] |
set_location_assignment PIN_AB4 -to SRAM_ADDR[12] |
set_location_assignment PIN_AC3 -to SRAM_ADDR[13] |
set_location_assignment PIN_AA4 -to SRAM_ADDR[14] |
set_location_assignment PIN_AB7 -to SRAM_ADDR[0] |
set_location_assignment PIN_AD7 -to SRAM_ADDR[1] |
set_location_assignment PIN_AE7 -to SRAM_ADDR[2] |
set_location_assignment PIN_AC7 -to SRAM_ADDR[3] |
set_location_assignment PIN_AB6 -to SRAM_ADDR[4] |
set_location_assignment PIN_T8 -to SRAM_ADDR[19] |
set_location_assignment PIN_AB8 -to SRAM_ADDR[18] |
set_location_assignment PIN_AB9 -to SRAM_ADDR[17] |
set_location_assignment PIN_AC11 -to SRAM_ADDR[16] |
set_location_assignment PIN_AB11 -to SRAM_ADDR[15] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[2] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[3] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[4] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[5] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[6] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[7] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[8] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[9] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[10] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[11] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[12] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[13] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[14] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[15] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[16] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[17] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[18] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[19] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[2] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[3] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[4] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[5] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[6] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[7] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[8] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[9] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[10] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[11] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[12] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[13] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[14] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[15] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_UB_N |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_LB_N |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_CE_N |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_OE_N |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_WE_N |
|
#============================================================ |
# Flash |
#============================================================ |
set_location_assignment PIN_AF12 -to FL_DQ[7] |
set_location_assignment PIN_AH11 -to FL_DQ[6] |
set_location_assignment PIN_AG11 -to FL_DQ[5] |
set_location_assignment PIN_AF11 -to FL_DQ[4] |
set_location_assignment PIN_AH10 -to FL_DQ[3] |
set_location_assignment PIN_AG10 -to FL_DQ[2] |
set_location_assignment PIN_AF10 -to FL_DQ[1] |
set_location_assignment PIN_AH8 -to FL_DQ[0] |
set_location_assignment PIN_AG12 -to FL_ADDR[0] |
set_location_assignment PIN_AD11 -to FL_ADDR[22] |
set_location_assignment PIN_AD10 -to FL_ADDR[21] |
set_location_assignment PIN_AE10 -to FL_ADDR[20] |
set_location_assignment PIN_AD12 -to FL_ADDR[19] |
set_location_assignment PIN_AC12 -to FL_ADDR[18] |
set_location_assignment PIN_AH12 -to FL_ADDR[17] |
set_location_assignment PIN_AA8 -to FL_ADDR[16] |
set_location_assignment PIN_Y10 -to FL_ADDR[15] |
set_location_assignment PIN_AC8 -to FL_ADDR[14] |
set_location_assignment PIN_AD8 -to FL_ADDR[13] |
set_location_assignment PIN_AA10 -to FL_ADDR[12] |
set_location_assignment PIN_AF9 -to FL_ADDR[11] |
set_location_assignment PIN_AE9 -to FL_ADDR[10] |
set_location_assignment PIN_AB10 -to FL_ADDR[9] |
set_location_assignment PIN_AB12 -to FL_ADDR[8] |
set_location_assignment PIN_AB13 -to FL_ADDR[7] |
set_location_assignment PIN_AA12 -to FL_ADDR[6] |
set_location_assignment PIN_AA13 -to FL_ADDR[5] |
set_location_assignment PIN_Y12 -to FL_ADDR[4] |
set_location_assignment PIN_Y14 -to FL_ADDR[3] |
set_location_assignment PIN_Y13 -to FL_ADDR[2] |
set_location_assignment PIN_AH7 -to FL_ADDR[1] |
set_location_assignment PIN_AG7 -to FL_CE_N |
set_location_assignment PIN_AG8 -to FL_OE_N |
set_location_assignment PIN_AC10 -to FL_WE_N |
set_location_assignment PIN_AE11 -to FL_RESET_N |
set_location_assignment PIN_AE12 -to FL_WP_N |
set_location_assignment PIN_Y1 -to FL_RY |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[22] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RESET_N |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N |
|
#============================================================ |
# GPIO, GPIO connect to GPIO Default |
#============================================================ |
set_location_assignment PIN_AB22 -to GPIO[0] |
set_location_assignment PIN_AC15 -to GPIO[1] |
set_location_assignment PIN_AB21 -to GPIO[2] |
set_location_assignment PIN_Y17 -to GPIO[3] |
set_location_assignment PIN_AC21 -to GPIO[4] |
set_location_assignment PIN_Y16 -to GPIO[5] |
set_location_assignment PIN_AD21 -to GPIO[6] |
set_location_assignment PIN_AE16 -to GPIO[7] |
set_location_assignment PIN_AD15 -to GPIO[8] |
set_location_assignment PIN_AE15 -to GPIO[9] |
set_location_assignment PIN_AC19 -to GPIO[10] |
set_location_assignment PIN_AF16 -to GPIO[11] |
set_location_assignment PIN_AD19 -to GPIO[12] |
set_location_assignment PIN_AF15 -to GPIO[13] |
set_location_assignment PIN_AF24 -to GPIO[14] |
set_location_assignment PIN_AE21 -to GPIO[15] |
set_location_assignment PIN_AF25 -to GPIO[16] |
set_location_assignment PIN_AC22 -to GPIO[17] |
set_location_assignment PIN_AE22 -to GPIO[18] |
set_location_assignment PIN_AF21 -to GPIO[19] |
set_location_assignment PIN_AF22 -to GPIO[20] |
set_location_assignment PIN_AD22 -to GPIO[21] |
set_location_assignment PIN_AG25 -to GPIO[22] |
set_location_assignment PIN_AD25 -to GPIO[23] |
set_location_assignment PIN_AH25 -to GPIO[24] |
set_location_assignment PIN_AE25 -to GPIO[25] |
set_location_assignment PIN_AG22 -to GPIO[26] |
set_location_assignment PIN_AE24 -to GPIO[27] |
set_location_assignment PIN_AH22 -to GPIO[28] |
set_location_assignment PIN_AF26 -to GPIO[29] |
set_location_assignment PIN_AE20 -to GPIO[30] |
set_location_assignment PIN_AG23 -to GPIO[31] |
set_location_assignment PIN_AF20 -to GPIO[32] |
set_location_assignment PIN_AH26 -to GPIO[33] |
set_location_assignment PIN_AH23 -to GPIO[34] |
set_location_assignment PIN_AG26 -to GPIO[35] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] |
|
#============================================================ |
# HSMC, HSMC connect to HSMC Default |
#============================================================ |
set_location_assignment PIN_J27 -to HSMC_CLKIN_P1 |
set_location_assignment PIN_J28 -to HSMC_CLKIN_N1 |
set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2 |
set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2 |
set_location_assignment PIN_D27 -to HSMC_TX_D_P[0] |
set_location_assignment PIN_D28 -to HSMC_TX_D_N[0] |
set_location_assignment PIN_F24 -to HSMC_RX_D_P[0] |
set_location_assignment PIN_F25 -to HSMC_RX_D_N[0] |
set_location_assignment PIN_E27 -to HSMC_TX_D_P[1] |
set_location_assignment PIN_C27 -to HSMC_RX_D_N[1] |
set_location_assignment PIN_E28 -to HSMC_TX_D_N[1] |
set_location_assignment PIN_D26 -to HSMC_RX_D_P[1] |
set_location_assignment PIN_F27 -to HSMC_TX_D_P[2] |
set_location_assignment PIN_F28 -to HSMC_TX_D_N[2] |
set_location_assignment PIN_F26 -to HSMC_RX_D_P[2] |
set_location_assignment PIN_E26 -to HSMC_RX_D_N[2] |
set_location_assignment PIN_G27 -to HSMC_TX_D_P[3] |
set_location_assignment PIN_G28 -to HSMC_TX_D_N[3] |
set_location_assignment PIN_G25 -to HSMC_RX_D_P[3] |
set_location_assignment PIN_G26 -to HSMC_RX_D_N[3] |
set_location_assignment PIN_K27 -to HSMC_TX_D_P[4] |
set_location_assignment PIN_K28 -to HSMC_TX_D_N[4] |
set_location_assignment PIN_H25 -to HSMC_RX_D_P[4] |
set_location_assignment PIN_H26 -to HSMC_RX_D_N[4] |
set_location_assignment PIN_M27 -to HSMC_TX_D_P[5] |
set_location_assignment PIN_M28 -to HSMC_TX_D_N[5] |
set_location_assignment PIN_K25 -to HSMC_RX_D_P[5] |
set_location_assignment PIN_K26 -to HSMC_RX_D_N[5] |
set_location_assignment PIN_K21 -to HSMC_TX_D_P[6] |
set_location_assignment PIN_K22 -to HSMC_TX_D_N[6] |
set_location_assignment PIN_L23 -to HSMC_RX_D_P[6] |
set_location_assignment PIN_L24 -to HSMC_RX_D_N[6] |
set_location_assignment PIN_H23 -to HSMC_TX_D_P[7] |
set_location_assignment PIN_H24 -to HSMC_TX_D_N[7] |
set_location_assignment PIN_M25 -to HSMC_RX_D_P[7] |
set_location_assignment PIN_M26 -to HSMC_RX_D_N[7] |
set_location_assignment PIN_J23 -to HSMC_TX_D_P[8] |
set_location_assignment PIN_J24 -to HSMC_TX_D_N[8] |
set_location_assignment PIN_R25 -to HSMC_RX_D_P[8] |
set_location_assignment PIN_R26 -to HSMC_RX_D_N[8] |
set_location_assignment PIN_P27 -to HSMC_TX_D_P[9] |
set_location_assignment PIN_P28 -to HSMC_TX_D_N[9] |
set_location_assignment PIN_T25 -to HSMC_RX_D_P[9] |
set_location_assignment PIN_T26 -to HSMC_RX_D_N[9] |
set_location_assignment PIN_J25 -to HSMC_TX_D_P[10] |
set_location_assignment PIN_J26 -to HSMC_TX_D_N[10] |
set_location_assignment PIN_U25 -to HSMC_RX_D_P[10] |
set_location_assignment PIN_U26 -to HSMC_RX_D_N[10] |
set_location_assignment PIN_L27 -to HSMC_TX_D_P[11] |
set_location_assignment PIN_L28 -to HSMC_TX_D_N[11] |
set_location_assignment PIN_L21 -to HSMC_RX_D_P[11] |
set_location_assignment PIN_L22 -to HSMC_RX_D_N[11] |
set_location_assignment PIN_V25 -to HSMC_TX_D_P[12] |
set_location_assignment PIN_V26 -to HSMC_TX_D_N[12] |
set_location_assignment PIN_N25 -to HSMC_RX_D_P[12] |
set_location_assignment PIN_N26 -to HSMC_RX_D_N[12] |
set_location_assignment PIN_R27 -to HSMC_TX_D_P[13] |
set_location_assignment PIN_R28 -to HSMC_TX_D_N[13] |
set_location_assignment PIN_P25 -to HSMC_RX_D_P[13] |
set_location_assignment PIN_P26 -to HSMC_RX_D_N[13] |
set_location_assignment PIN_U27 -to HSMC_TX_D_P[14] |
set_location_assignment PIN_U28 -to HSMC_TX_D_N[14] |
set_location_assignment PIN_P21 -to HSMC_RX_D_P[14] |
set_location_assignment PIN_R21 -to HSMC_RX_D_N[14] |
set_location_assignment PIN_V27 -to HSMC_TX_D_P[15] |
set_location_assignment PIN_V28 -to HSMC_TX_D_N[15] |
set_location_assignment PIN_R22 -to HSMC_RX_D_P[15] |
set_location_assignment PIN_R23 -to HSMC_RX_D_N[15] |
set_location_assignment PIN_U22 -to HSMC_TX_D_P[16] |
set_location_assignment PIN_V22 -to HSMC_TX_D_N[16] |
set_location_assignment PIN_T21 -to HSMC_RX_D_P[16] |
set_location_assignment PIN_T22 -to HSMC_RX_D_N[16] |
set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2 |
set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2 |
set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1 |
set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1 |
set_location_assignment PIN_AD28 -to HSMC_CLKOUT0 |
set_location_assignment PIN_AE26 -to HSMC_D[0] |
set_location_assignment PIN_AE28 -to HSMC_D[1] |
set_location_assignment PIN_AE27 -to HSMC_D[2] |
set_location_assignment PIN_AF27 -to HSMC_D[3] |
set_location_assignment PIN_AH15 -to HSMC_CLKIN0 |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT0 |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[0] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[1] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[2] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[3] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P1 |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N1 |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[12] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[12] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[12] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[12] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[13] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[13] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[13] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[13] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[14] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[14] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[14] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[14] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[15] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[15] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[15] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[15] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[16] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[16] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[16] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[16] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P2 |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N2 |
|
#============================================================ |
# HSMC, HSMC connect to HSMC Default |
#============================================================ |
set_location_assignment PIN_J10 -to EXT_IO[0] |
set_location_assignment PIN_J14 -to EXT_IO[1] |
set_location_assignment PIN_H13 -to EXT_IO[2] |
set_location_assignment PIN_H14 -to EXT_IO[3] |
set_location_assignment PIN_F14 -to EXT_IO[4] |
set_location_assignment PIN_E10 -to EXT_IO[5] |
set_location_assignment PIN_D9 -to EXT_IO[6] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_IO[0] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_IO[1] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_IO[2] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_IO[3] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_IO[4] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_IO[5] |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_IO[6] |
|
#============================================================ |
# End of pin assignments by Altera University Program |
#============================================================ |
|
|
|
|
|
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[2] |
set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_INT_N |
set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[2] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[8] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[9] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[10] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[11] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[8] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[9] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[10] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[11] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[8] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[9] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[10] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[11] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[7] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[8] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[9] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[10] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[11] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P2 |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N2 |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[0] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[1] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[2] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[3] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[4] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[5] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[6] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[7] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[0] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[1] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[2] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[3] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[4] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[5] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[6] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[7] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[0] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[1] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[2] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[3] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[4] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[5] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[6] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[7] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[0] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[1] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[2] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[3] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[4] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[5] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[6] |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P1 |
set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N1 |
set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSMC_CLKIN0 |
|
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET0_LINK100 |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET1_LINK100 |
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENETCLK_25 |
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA |
set_global_assignment -name USE_CONFIGURATION_DEVICE ON |
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS64 |
|
|
|
set_global_assignment -name TOP_LEVEL_ENTITY eth_test_top |
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0 |
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:19:48 MAY 05, 2016" |
set_global_assignment -name LAST_QUARTUS_VERSION 13.0 |
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files |
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" |
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation |
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 |
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 |
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 780 |
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 |
|
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" |
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" |
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top |
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top |
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top |
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX2 |
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX0 |
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX1 |
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to KEY |
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to SW |
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX3[1] |
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX3[0] |
set_instance_assignment -name FAST_INPUT_REGISTER ON -to * |
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to * |
set_instance_assignment -name TSU_REQUIREMENT "10 ns" -from * -to * |
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" |
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" |
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" |
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation |
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testbench -section_id eda_simulation |
set_global_assignment -name EDA_TEST_BENCH_NAME testbench -section_id eda_simulation |
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id testbench |
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench -section_id testbench |
set_global_assignment -name EDA_TEST_BENCH_FILE src_verilog/testbench.v -section_id testbench |
set_global_assignment -name VERILOG_FILE src_verilog/lib/ethtop.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/altera_jtag_uart_wb.v |
set_global_assignment -name VERILOG_FILE src_verilog/reset_jtag.v |
set_global_assignment -name VERILOG_FILE src_verilog/eth_test_top.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/general_dual_port_ram.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/general_single_port_ram.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/xilinx_dist_ram_16x32.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/wishbone_bus.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/timescale.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/main_comp.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/int_ctrl.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/ethmac_defines.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/ethmac.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_wishbone.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_txstatem.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_txethmac.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_txcounters.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_transmitcontrol.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_top.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_spram_256x32.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_shiftreg.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_rxstatem.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_rxethmac.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_rxcounters.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_rxaddrcheck.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_registers.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_register.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_receivecontrol.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_random.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_outputcontrol.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_miim.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_macstatus.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_maccontrol.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_fifo.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_crc.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_cop.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/eth_clockgen.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/clk_source.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/arbiter.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/Altera_single_port_ram.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/altera_reset_synchronizer.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB_xecu.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB_sim.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB_regf.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB_ibuf.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB_edk32.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB_ctrl.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB_core.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB_bpcu.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_xslif.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_tpsram.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_spsram.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_sparam.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_sim.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_regs.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_pipe.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_mult.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_memif.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_iwbif.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_intu.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_iche.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_gprf.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_exec.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_edk63.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_edk62.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_dwbif.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_dparam.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_ctrl.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_bsft.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_brcc.v |
set_global_assignment -name VERILOG_FILE src_verilog/lib/aemb.v |
set_global_assignment -name VERILOG_FILE src_verilog/eth_test.v |
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/eth_test/sw/main.c
0,0 → 1,63
|
#include "eth_test.h" |
|
void aemb_enable_interrupt () |
{ |
int msr, tmp; |
asm volatile ("mfs %0, rmsr;" |
"ori %1, %0, 0x02;" |
"mts rmsr, %1;" |
: "=r"(msr) |
: "r" (tmp) |
); |
} |
|
|
|
// a simple delay function |
void delay ( unsigned int num ){ |
|
while (num>0){ |
num--; |
asm volatile ("nop"); |
} |
return; |
|
} |
|
void myISR( void ) __attribute__ ((interrupt_handler)); |
|
void myISR( void ) |
{ |
|
if( int_ctrl_IPR & ETHMAC_INT ) ethmac_interrupt(); |
int_ctrl_IAR = ETHMAC_INT; // Acknowledge Interrupts |
} |
|
|
int main(){ |
//delay(15500000); |
ethmac_init(); |
xil_printf("start\n"); |
ethmac_tx_data[0] = 0xFF; |
ethmac_tx_data[1] = 0x2B; |
ethmac_tx_data[2] = 0x40; |
ethmac_tx_data[3] = 0x50; |
|
|
|
int_ctrl_IER= ETHMAC_INT; |
int_ctrl_MER= 0x3; |
|
aemb_enable_interrupt (); |
|
while(1){ |
ethmac_send(4); |
delay(500000); |
//xil_printf("sent\n"); |
|
} |
|
return 0; |
} |
|
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/eth_test/src_verilog/eth_test_top.v
0,0 → 1,125
module eth_test_top( |
//////////// CLOCK ////////// |
CLOCK_50, |
|
//////////// KEY ////////// |
KEY, |
|
LEDG, |
|
|
//////////// Ethernet 0 ////////// |
ENET0_GTX_CLK, |
ENET0_INT_N, |
ENET0_LINK100, |
ENET0_MDC, |
ENET0_MDIO, |
ENET0_RESET_N, |
ENET0_RX_CLK, |
ENET0_RX_COL, |
ENET0_RX_CRS, |
ENET0_RX_DATA, |
ENET0_RX_DV, |
ENET0_RX_ER, |
ENET0_TX_CLK, |
ENET0_TX_DATA, |
ENET0_TX_EN, |
ENET0_TX_ER, |
ENETCLK_25 |
|
|
|
); |
|
|
|
|
//////////// CLOCK ////////// |
input CLOCK_50; |
|
|
output [0:0] LEDG; |
input [0:0] KEY; |
|
|
|
//////////// Ethernet 0 ////////// |
output ENET0_GTX_CLK; // GMII Transmit Clock |
input ENET0_INT_N; // Interrupt open drain output |
input ENET0_LINK100; // Parallel LED output of 100BASE-TX link |
output ENET0_MDC; // Management data clock reference |
inout ENET0_MDIO; // Management Data |
output ENET0_RESET_N; // Hardware reset Signal |
input ENET0_RX_CLK; // GMII/MII Receive clock |
input ENET0_RX_COL; // GMII/MII Collision |
input ENET0_RX_CRS; // GMII/MII Carrier sense |
input [3:0] ENET0_RX_DATA; // GMII/MII Receive data |
input ENET0_RX_DV; // GMII/MII Receive data valid |
input ENET0_RX_ER; // GMII/MII Receive error |
input ENET0_TX_CLK; // MII Transmit Clock |
output [3:0] ENET0_TX_DATA; // MII Transmit Data |
output ENET0_TX_EN; // GMII/MII Transmit enable |
output ENET0_TX_ER; // GMII/MII Transmit error |
|
input ENETCLK_25; // Internal Clock (SHARED) 25MHZ |
|
|
|
|
//======================================================= |
// REG/WIRE declarations |
//======================================================= |
|
|
|
|
|
wire reset_in,jtag_reset,reset; |
|
assign reset_in = ~KEY[0]; |
assign LEDG[0] = reset; |
assign reset = (jtag_reset | reset_in); |
|
// a reset source which can be controled using altera in-system source editor |
|
reset_jtag the_reset( |
.probe(), |
.source(jtag_reset) |
); |
|
|
wire md_we, md_out,md_in; |
|
eth_test soc( |
.aeMB_sys_ena_i(1'b1), |
.ss_clk_in(CLOCK_50), |
.ss_reset_in(reset), |
.ethmac_mcoll_pad_i(ENET0_RX_COL), |
.ethmac_mcrs_pad_i(ENET0_RX_CRS), |
.ethmac_md_pad_i(md_in), |
.ethmac_md_pad_o(md_out), |
.ethmac_md_padoe_o(md_we), |
.ethmac_mdc_pad_o(ENET0_MDC), |
.ethmac_mrx_clk_pad_i(ENET0_RX_CLK), |
.ethmac_mrxd_pad_i(ENET0_RX_DATA), |
.ethmac_mrxdv_pad_i(ENET0_RX_DV), |
.ethmac_mrxerr_pad_i(ENET0_RX_ER), |
.ethmac_mtx_clk_pad_i(ENET0_TX_CLK), |
.ethmac_mtxd_pad_o(ENET0_TX_DATA), |
.ethmac_mtxen_pad_o(ENET0_TX_EN), |
.ethmac_mtxerr_pad_o(ENET0_TX_ER), |
.uart_dataavailable(), |
.uart_readyfordata() |
|
); |
|
//convert tristate pin to two separate lines: |
|
assign ENET0_MDIO = md_we? md_out:1'bz; |
assign md_in = ENET0_MDIO; |
assign ENET0_RESET_N = ~reset; |
|
|
|
endmodule |
|
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/eth_test/src_verilog/reset_jtag.v
0,0 → 1,107
// megafunction wizard: %In-System Sources and Probes% |
// GENERATION: STANDARD |
// VERSION: WM1.0 |
// MODULE: altsource_probe |
|
// ============================================================ |
// File Name: reset_jtag.v |
// Megafunction Name(s): |
// altsource_probe |
// |
// Simulation Library Files(s): |
// altera_mf |
// ============================================================ |
// ************************************************************ |
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! |
// |
// 13.0.0 Build 156 04/24/2013 SJ Full Version |
// ************************************************************ |
|
|
//Copyright (C) 1991-2013 Altera Corporation |
//Your use of Altera Corporation's design tools, logic functions |
//and other software and tools, and its AMPP partner logic |
//functions, and any output files from any of the foregoing |
//(including device programming or simulation files), and any |
//associated documentation or information are expressly subject |
//to the terms and conditions of the Altera Program License |
//Subscription Agreement, Altera MegaCore Function License |
//Agreement, or other applicable license agreement, including, |
//without limitation, that your use is for the sole purpose of |
//programming logic devices manufactured by Altera and sold by |
//Altera or its authorized distributors. Please refer to the |
//applicable agreement for further details. |
|
|
// synopsys translate_off |
`timescale 1 ps / 1 ps |
// synopsys translate_on |
module reset_jtag ( |
probe, |
source); |
|
input [0:0] probe; |
output [0:0] source; |
|
wire [0:0] sub_wire0; |
wire [0:0] source = sub_wire0[0:0]; |
|
altsource_probe altsource_probe_component ( |
.probe (probe), |
.source (sub_wire0) |
// synopsys translate_off |
, |
.clrn (), |
.ena (), |
.ir_in (), |
.ir_out (), |
.jtag_state_cdr (), |
.jtag_state_cir (), |
.jtag_state_e1dr (), |
.jtag_state_sdr (), |
.jtag_state_tlr (), |
.jtag_state_udr (), |
.jtag_state_uir (), |
.raw_tck (), |
.source_clk (), |
.source_ena (), |
.tdi (), |
.tdo (), |
.usr1 () |
// synopsys translate_on |
); |
defparam |
altsource_probe_component.enable_metastability = "NO", |
altsource_probe_component.instance_id = "RST", |
altsource_probe_component.probe_width = 1, |
altsource_probe_component.sld_auto_instance_index = "NO", |
altsource_probe_component.sld_instance_index = 127, |
altsource_probe_component.source_initial_value = " 0", |
altsource_probe_component.source_width = 1; |
|
|
endmodule |
|
// ============================================================ |
// CNX file retrieval info |
// ============================================================ |
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" |
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all |
// Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "NO" |
// Retrieval info: CONSTANT: INSTANCE_ID STRING "RST" |
// Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "1" |
// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "NO" |
// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "127" |
// Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 0" |
// Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "1" |
// Retrieval info: USED_PORT: probe 0 0 1 0 INPUT NODEFVAL "probe[0..0]" |
// Retrieval info: USED_PORT: source 0 0 1 0 OUTPUT NODEFVAL "source[0..0]" |
// Retrieval info: CONNECT: @probe 0 0 1 0 probe 0 0 1 0 |
// Retrieval info: CONNECT: source 0 0 1 0 @source 0 0 1 0 |
// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag.v TRUE |
// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag.inc FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag.cmp FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag.bsf FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag_inst.v FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag_bb.v TRUE |
// Retrieval info: LIB_FILE: altera_mf |
an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/eth_test/src_verilog/reset_jtag.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/lcd_test/lcd_test.SOC
===================================================================
--- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/lcd_test/lcd_test.SOC (nonexistent)
+++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/lcd_test/lcd_test.SOC (revision 24)
@@ -0,0 +1,658 @@
+$lcd_test = bless( {
+ 'hdl_files' => undef,
+ 'modules' => {},
+ 'soc_name' => 'lcd_test',
+ 'top_ip' => bless( {
+ 'ports' => {
+ 'lcd_lcd_rs' => {
+ 'intfc_port' => 'IO',
+ 'intfc_name' => 'IO',
+ 'instance_name' => 'lcd_2x160',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'lcd_lcd_rw' => {
+ 'intfc_port' => 'IO',
+ 'intfc_name' => 'IO',
+ 'instance_name' => 'lcd_2x160',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'lcd_lcd_en' => {
+ 'intfc_port' => 'IO',
+ 'intfc_name' => 'IO',
+ 'instance_name' => 'lcd_2x160',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'ss_reset_in' => {
+ 'intfc_port' => 'reset_i',
+ 'intfc_name' => 'plug:reset[0]',
+ 'instance_name' => 'clk_source0',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'ss_clk_in' => {
+ 'intfc_port' => 'clk_i',
+ 'intfc_name' => 'plug:clk[0]',
+ 'instance_name' => 'clk_source0',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'lcd_lcd_data' => {
+ 'intfc_port' => 'IO',
+ 'intfc_name' => 'IO',
+ 'instance_name' => 'lcd_2x160',
+ 'range' => ' 7: 0',
+ 'type' => 'inout'
+ },
+ 'aeMB_sys_ena_i' => {
+ 'intfc_port' => 'enable_i',
+ 'intfc_name' => 'plug:enable[0]',
+ 'instance_name' => 'aeMB0',
+ 'range' => '',
+ 'type' => 'input'
+ }
+ },
+ 'interface' => {
+ 'plug:enable[0]' => {
+ 'ports' => {
+ 'aeMB_sys_ena_i' => {
+ 'intfc_port' => 'enable_i',
+ 'instance_name' => 'aeMB0',
+ 'range' => '',
+ 'type' => 'input'
+ }
+ }
+ },
+ 'IO' => {
+ 'ports' => {
+ 'lcd_lcd_rs' => {
+ 'intfc_port' => 'IO',
+ 'instance_name' => 'lcd_2x160',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'lcd_lcd_rw' => {
+ 'intfc_port' => 'IO',
+ 'instance_name' => 'lcd_2x160',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'lcd_lcd_en' => {
+ 'intfc_port' => 'IO',
+ 'instance_name' => 'lcd_2x160',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'lcd_lcd_data' => {
+ 'intfc_port' => 'IO',
+ 'instance_name' => 'lcd_2x160',
+ 'range' => ' 7: 0',
+ 'type' => 'inout'
+ }
+ }
+ },
+ 'plug:clk[0]' => {
+ 'ports' => {
+ 'ss_clk_in' => {
+ 'intfc_port' => 'clk_i',
+ 'instance_name' => 'clk_source0',
+ 'range' => '',
+ 'type' => 'input'
+ }
+ }
+ },
+ 'plug:reset[0]' => {
+ 'ports' => {
+ 'ss_reset_in' => {
+ 'intfc_port' => 'reset_i',
+ 'instance_name' => 'clk_source0',
+ 'range' => '',
+ 'type' => 'input'
+ }
+ }
+ }
+ },
+ 'instance_ids' => {
+ 'aeMB0' => {
+ 'ports' => {
+ 'aeMB_sys_ena_i' => {
+ 'intfc_port' => 'enable_i',
+ 'intfc_name' => 'plug:enable[0]',
+ 'range' => '',
+ 'type' => 'input'
+ }
+ },
+ 'module_name' => 'aeMB_top',
+ 'category' => 'Processor',
+ 'instance' => 'aeMB',
+ 'module' => 'aeMB'
+ },
+ 'clk_source0' => {
+ 'ports' => {
+ 'ss_reset_in' => {
+ 'intfc_port' => 'reset_i',
+ 'intfc_name' => 'plug:reset[0]',
+ 'range' => '',
+ 'type' => 'input'
+ },
+ 'ss_clk_in' => {
+ 'intfc_port' => 'clk_i',
+ 'intfc_name' => 'plug:clk[0]',
+ 'range' => '',
+ 'type' => 'input'
+ }
+ },
+ 'module_name' => 'clk_source',
+ 'category' => 'source',
+ 'instance' => 'ss',
+ 'module' => 'clk_source'
+ },
+ 'wishbone_bus0' => {
+ 'module_name' => 'wishbone_bus',
+ 'category' => 'bus',
+ 'instance' => 'bus',
+ 'module' => 'wishbone_bus'
+ },
+ 'lcd_2x160' => {
+ 'ports' => {
+ 'lcd_lcd_rs' => {
+ 'intfc_port' => 'IO',
+ 'intfc_name' => 'IO',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'lcd_lcd_rw' => {
+ 'intfc_port' => 'IO',
+ 'intfc_name' => 'IO',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'lcd_lcd_en' => {
+ 'intfc_port' => 'IO',
+ 'intfc_name' => 'IO',
+ 'range' => '',
+ 'type' => 'output'
+ },
+ 'lcd_lcd_data' => {
+ 'intfc_port' => 'IO',
+ 'intfc_name' => 'IO',
+ 'range' => ' 7: 0',
+ 'type' => 'inout'
+ }
+ },
+ 'module_name' => 'lcd_2x16',
+ 'category' => 'Display',
+ 'instance' => 'lcd',
+ 'module' => 'lcd_2x16'
+ },
+ 'Altera_single_port_ram0' => {
+ 'parameters' => {
+ 'ram_Dw' => {
+ 'info' => undef,
+ 'deafult' => '32',
+ 'global_param' => 1,
+ 'content' => '8,1024,1',
+ 'redefine_param' => 1,
+ 'type' => 'Spin-button'
+ },
+ 'ram_Aw' => {
+ 'info' => undef,
+ 'deafult' => 12,
+ 'global_param' => 1,
+ 'content' => '4,31,1',
+ 'redefine_param' => 1,
+ 'type' => 'Spin-button'
+ }
+ },
+ 'module_name' => 'Altera_single_port_ram',
+ 'category' => 'RAM',
+ 'instance' => 'ram',
+ 'module' => 'Altera_single_port_ram'
+ }
+ }
+ }, 'ip_gen' ),
+ 'instances' => {
+ 'aeMB0' => {
+ 'aeMB0' => {},
+ 'instance_name' => 'aeMB',
+ 'plugs' => {
+ 'wb_master' => {
+ 'connection_num' => undef,
+ 'value' => 2,
+ 'nums' => {
+ '1' => {
+ 'connect_socket_num' => '1',
+ 'connect_id' => 'wishbone_bus0',
+ 'name' => 'dwb',
+ 'connect_socket' => 'wb_master'
+ },
+ '0' => {
+ 'connect_socket_num' => '0',
+ 'connect_id' => 'wishbone_bus0',
+ 'name' => 'iwb',
+ 'connect_socket' => 'wb_master'
+ }
+ },
+ 'type' => 'num'
+ },
+ 'interrupt_cpu' => {
+ 'connection_num' => undef,
+ 'value' => 1,
+ 'nums' => {
+ '0' => {
+ 'connect_socket_num' => undef,
+ 'connect_id' => 'NC',
+ 'name' => 'intrp',
+ 'connect_socket' => undef
+ }
+ },
+ 'type' => 'num'
+ },
+ 'enable' => {
+ 'connection_num' => undef,
+ 'value' => 1,
+ 'nums' => {
+ '0' => {
+ 'connect_socket_num' => undef,
+ 'connect_id' => 'IO',
+ 'name' => 'enable',
+ 'connect_socket' => undef
+ }
+ },
+ 'type' => 'num'
+ },
+ 'reset' => {
+ 'connection_num' => undef,
+ 'value' => 1,
+ 'nums' => {
+ '0' => {
+ 'connect_socket_num' => '0',
+ 'connect_id' => 'clk_source0',
+ 'name' => 'reset',
+ 'connect_socket' => 'reset'
+ }
+ },
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'connection_num' => undef,
+ 'value' => 1,
+ 'nums' => {
+ '0' => {
+ 'connect_socket_num' => '0',
+ 'connect_id' => 'clk_source0',
+ 'name' => 'clk',
+ 'connect_socket' => 'clk'
+ }
+ },
+ 'type' => 'num'
+ }
+ },
+ 'parameters' => {
+ 'AEMB_XWB' => {
+ 'value' => ' 7'
+ },
+ 'AEMB_IDX' => {
+ 'value' => ' 6'
+ },
+ 'AEMB_MUL' => {
+ 'value' => ' 1'
+ },
+ 'AEMB_IWB' => {
+ 'value' => ' 32'
+ },
+ 'AEMB_BSF' => {
+ 'value' => ' 1'
+ },
+ 'AEMB_ICH' => {
+ 'value' => ' 11'
+ },
+ 'AEMB_DWB' => {
+ 'value' => ' 32'
+ }
+ },
+ 'parameters_order' => [
+ 'AEMB_IWB',
+ 'AEMB_DWB',
+ 'AEMB_XWB',
+ 'AEMB_ICH',
+ 'AEMB_IDX',
+ 'AEMB_BSF',
+ 'AEMB_MUL'
+ ],
+ 'sockets' => {},
+ 'module_name' => 'aeMB_top',
+ 'category' => 'Processor',
+ 'module' => 'aeMB'
+ },
+ 'clk_source0' => {
+ 'instance_name' => 'ss',
+ 'plugs' => {
+ 'reset' => {
+ 'connection_num' => undef,
+ 'value' => 1,
+ 'nums' => {
+ '0' => {
+ 'connect_socket_num' => undef,
+ 'connect_id' => 'IO',
+ 'name' => 'reset',
+ 'connect_socket' => undef
+ }
+ },
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'connection_num' => undef,
+ 'value' => 1,
+ 'nums' => {
+ '0' => {
+ 'connect_socket_num' => undef,
+ 'connect_id' => 'IO',
+ 'name' => 'clk',
+ 'connect_socket' => undef
+ }
+ },
+ 'type' => 'num'
+ }
+ },
+ 'parameters' => {},
+ 'clk_source0' => {},
+ 'parameters_order' => [],
+ 'sockets' => {
+ 'reset' => {
+ 'connection_num' => 'multi connection',
+ 'value' => 1,
+ 'nums' => {
+ '0' => {
+ 'name' => 'reset'
+ }
+ },
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'connection_num' => 'multi connection',
+ 'value' => 1,
+ 'nums' => {
+ '0' => {
+ 'name' => 'clk'
+ }
+ },
+ 'type' => 'num'
+ }
+ },
+ 'module_name' => 'clk_source',
+ 'category' => 'source',
+ 'module' => 'clk_source'
+ },
+ 'lcd_2x160' => {
+ 'instance_name' => 'lcd',
+ 'plugs' => {
+ 'reset' => {
+ 'connection_num' => undef,
+ 'value' => 1,
+ 'nums' => {
+ '0' => {
+ 'connect_socket_num' => '0',
+ 'connect_id' => 'clk_source0',
+ 'name' => 'reset',
+ 'connect_socket' => 'reset'
+ }
+ },
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'connection_num' => undef,
+ 'value' => 1,
+ 'nums' => {
+ '0' => {
+ 'connect_socket_num' => '0',
+ 'connect_id' => 'clk_source0',
+ 'name' => 'clk',
+ 'connect_socket' => 'clk'
+ }
+ },
+ 'type' => 'num'
+ },
+ 'wb_slave' => {
+ 'connection_num' => undef,
+ 'value' => 1,
+ 'nums' => {
+ '0' => {
+ 'base' => 2432696320,
+ 'width' => 5,
+ 'connect_socket_num' => '1',
+ 'name' => 'wb_slave',
+ 'end' => 2432696351,
+ 'connect_socket' => 'wb_slave',
+ 'connect_id' => 'wishbone_bus0',
+ 'addr' => '0x9100_0000 0x91ff_ffff General-Purpose I/O'
+ }
+ },
+ 'type' => 'num'
+ }
+ },
+ 'parameters' => {
+ 'Aw' => {
+ 'value' => ' 2'
+ },
+ 'Dw' => {
+ 'value' => ' 8'
+ },
+ 'CLK_MHZ' => {
+ 'value' => 50
+ }
+ },
+ 'parameters_order' => [
+ 'Dw',
+ 'Aw',
+ 'CLK_MHZ'
+ ],
+ 'sockets' => {},
+ 'lcd_2x160' => {},
+ 'module_name' => 'lcd_2x16',
+ 'category' => 'Display',
+ 'module' => 'lcd_2x16'
+ },
+ 'wishbone_bus0' => {
+ 'wishbone_bus0' => {},
+ 'instance_name' => 'bus',
+ 'plugs' => {
+ 'reset' => {
+ 'connection_num' => undef,
+ 'value' => 1,
+ 'nums' => {
+ '0' => {
+ 'connect_socket_num' => '0',
+ 'connect_id' => 'clk_source0',
+ 'name' => 'reset',
+ 'connect_socket' => 'reset'
+ }
+ },
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'connection_num' => undef,
+ 'value' => 1,
+ 'nums' => {
+ '0' => {
+ 'connect_socket_num' => '0',
+ 'connect_id' => 'clk_source0',
+ 'name' => 'clk',
+ 'connect_socket' => 'clk'
+ }
+ },
+ 'type' => 'num'
+ }
+ },
+ 'parameters' => {
+ 'S' => {
+ 'value' => 2
+ },
+ 'SELw' => {
+ 'value' => 'Dw/8'
+ },
+ 'Dw' => {
+ 'value' => '32'
+ },
+ 'BTEw' => {
+ 'value' => '2 '
+ },
+ 'Aw' => {
+ 'value' => '32'
+ },
+ 'M' => {
+ 'value' => 2
+ },
+ 'TAGw' => {
+ 'value' => '3'
+ },
+ 'CTIw' => {
+ 'value' => '3'
+ }
+ },
+ 'parameters_order' => [
+ 'M',
+ 'S',
+ 'Dw',
+ 'Aw',
+ 'SELw',
+ 'TAGw',
+ 'CTIw',
+ 'BTEw'
+ ],
+ 'sockets' => {
+ 'wb_master' => {
+ 'connection_num' => 'single connection',
+ 'value' => 'M',
+ 'nums' => {
+ '0' => {
+ 'name' => 'wb_master'
+ }
+ },
+ 'type' => 'param'
+ },
+ 'wb_addr_map' => {
+ 'connection_num' => 'single connection',
+ 'value' => 1,
+ 'nums' => {
+ '0' => {
+ 'name' => 'wb_addr_map'
+ }
+ },
+ 'type' => 'num'
+ },
+ 'wb_slave' => {
+ 'connection_num' => 'single connection',
+ 'value' => 'S',
+ 'nums' => {
+ '0' => {
+ 'name' => 'wb_slave'
+ }
+ },
+ 'type' => 'param'
+ }
+ },
+ 'module_name' => 'wishbone_bus',
+ 'category' => 'bus',
+ 'module' => 'wishbone_bus'
+ },
+ 'Altera_single_port_ram0' => {
+ 'instance_name' => 'ram',
+ 'Altera_single_port_ram0' => {},
+ 'plugs' => {
+ 'reset' => {
+ 'connection_num' => undef,
+ 'value' => 1,
+ 'nums' => {
+ '0' => {
+ 'connect_socket_num' => '0',
+ 'connect_id' => 'clk_source0',
+ 'name' => 'reset',
+ 'connect_socket' => 'reset'
+ }
+ },
+ 'type' => 'num'
+ },
+ 'clk' => {
+ 'connection_num' => undef,
+ 'value' => 1,
+ 'nums' => {
+ '0' => {
+ 'connect_socket_num' => '0',
+ 'connect_id' => 'clk_source0',
+ 'name' => 'clk',
+ 'connect_socket' => 'clk'
+ }
+ },
+ 'type' => 'num'
+ },
+ 'wb_slave' => {
+ 'connection_num' => undef,
+ 'value' => 1,
+ 'nums' => {
+ '0' => {
+ 'base' => 0,
+ 'width' => 'WBAw',
+ 'connect_socket_num' => '0',
+ 'name' => 'wb_slave',
+ 'end' => 16383,
+ 'connect_socket' => 'wb_slave',
+ 'connect_id' => 'wishbone_bus0',
+ 'addr' => '0x0000_0000 0x3fff_ffff RAM'
+ }
+ },
+ 'type' => 'num'
+ }
+ },
+ 'parameters' => {
+ 'RAM_TAG_STRING' => {
+ 'value' => 'i2s(CORE_ID)'
+ },
+ 'SELw' => {
+ 'value' => '4'
+ },
+ 'Dw' => {
+ 'value' => '32'
+ },
+ 'WBAw' => {
+ 'value' => 'Aw+2'
+ },
+ 'BTEw' => {
+ 'value' => '2'
+ },
+ 'Aw' => {
+ 'value' => 12
+ },
+ 'TAGw' => {
+ 'value' => '3'
+ },
+ 'CTIw' => {
+ 'value' => '3'
+ }
+ },
+ 'parameters_order' => [
+ 'Dw',
+ 'Aw',
+ 'TAGw',
+ 'SELw',
+ 'CTIw',
+ 'BTEw',
+ 'RAM_TAG_STRING',
+ 'WBAw'
+ ],
+ 'sockets' => {},
+ 'module_name' => 'Altera_single_port_ram',
+ 'category' => 'RAM',
+ 'module' => 'Altera_single_port_ram'
+ }
+ },
+ 'instance_order' => [
+ 'aeMB0',
+ 'Altera_single_port_ram0',
+ 'wishbone_bus0',
+ 'clk_source0',
+ 'lcd_2x160'
+ ]
+ }, 'soc' );
an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/lcd_test/lcd_test.SOC
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/lcd_test/lcd_test.qpf
===================================================================
--- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/lcd_test/lcd_test.qpf (nonexistent)
+++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/lcd_test/lcd_test.qpf (revision 24)
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.0 Build 156 04/24/2013 SJ Full Version
+# Date created = 10:13:20 April 18, 2016
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "10:13:20 April 18, 2016"
+
+# Revisions
+
+PROJECT_REVISION = "lcd_test"
Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/lcd_test/sw/main.c
===================================================================
--- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/lcd_test/sw/main.c (nonexistent)
+++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/lcd_test/sw/main.c (revision 24)
@@ -0,0 +1,27 @@
+#define lcd_TEST_ENABLE
+#include "lcd_test.h"
+
+
+// a simple delay function
+void delay ( unsigned int num ){
+
+ while (num>0){
+ num--;
+ asm volatile ("nop");
+ }
+ return;
+
+}
+
+int main(){
+
+ lcd_test();
+ while(1){
+
+
+
+ }
+
+return 0;
+}
+
Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/lcd_test/lcd_test.qsf
===================================================================
--- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/lcd_test/lcd_test.qsf (nonexistent)
+++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/lcd_test/lcd_test.qsf (revision 24)
@@ -0,0 +1,1301 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.0 Build 156 04/24/2013 SJ Full Version
+# Date created = 10:13:20 April 18, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# lcd_test_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+#============================================================
+# Build by Altera University Program
+#============================================================
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE115F29C8
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+#============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_Y2 -to CLOCK_50
+set_location_assignment PIN_AG14 -to CLOCK2_50
+set_location_assignment PIN_AG15 -to CLOCK3_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50
+
+
+#============================================================
+# Sma
+#============================================================
+set_location_assignment PIN_AH14 -to SMA_CLKIN
+set_location_assignment PIN_AE23 -to SMA_CLKOUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKIN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKOUT
+
+#============================================================
+# LED
+#============================================================
+set_location_assignment PIN_E21 -to LEDG[0]
+set_location_assignment PIN_E22 -to LEDG[1]
+set_location_assignment PIN_E25 -to LEDG[2]
+set_location_assignment PIN_E24 -to LEDG[3]
+set_location_assignment PIN_H21 -to LEDG[4]
+set_location_assignment PIN_G20 -to LEDG[5]
+set_location_assignment PIN_G22 -to LEDG[6]
+set_location_assignment PIN_G21 -to LEDG[7]
+set_location_assignment PIN_F17 -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[8]
+
+set_location_assignment PIN_G19 -to LEDR[0]
+set_location_assignment PIN_E19 -to LEDR[2]
+set_location_assignment PIN_F19 -to LEDR[1]
+set_location_assignment PIN_F21 -to LEDR[3]
+set_location_assignment PIN_F18 -to LEDR[4]
+set_location_assignment PIN_E18 -to LEDR[5]
+set_location_assignment PIN_J19 -to LEDR[6]
+set_location_assignment PIN_H19 -to LEDR[7]
+set_location_assignment PIN_J17 -to LEDR[8]
+set_location_assignment PIN_G17 -to LEDR[9]
+set_location_assignment PIN_J15 -to LEDR[10]
+set_location_assignment PIN_H16 -to LEDR[11]
+set_location_assignment PIN_J16 -to LEDR[12]
+set_location_assignment PIN_H17 -to LEDR[13]
+set_location_assignment PIN_F15 -to LEDR[14]
+set_location_assignment PIN_G15 -to LEDR[15]
+set_location_assignment PIN_G16 -to LEDR[16]
+set_location_assignment PIN_H15 -to LEDR[17]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[10]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[11]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[12]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[13]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[14]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[15]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[16]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[17]
+
+#============================================================
+# KEY
+#============================================================
+set_location_assignment PIN_M23 -to KEY[0]
+set_location_assignment PIN_M21 -to KEY[1]
+set_location_assignment PIN_N21 -to KEY[2]
+set_location_assignment PIN_R24 -to KEY[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[3]
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_AB28 -to SW[0]
+set_location_assignment PIN_AC28 -to SW[1]
+set_location_assignment PIN_AC27 -to SW[2]
+set_location_assignment PIN_AD27 -to SW[3]
+set_location_assignment PIN_AB27 -to SW[4]
+set_location_assignment PIN_AC26 -to SW[5]
+set_location_assignment PIN_AD26 -to SW[6]
+set_location_assignment PIN_AB26 -to SW[7]
+set_location_assignment PIN_AC25 -to SW[8]
+set_location_assignment PIN_AB25 -to SW[9]
+set_location_assignment PIN_AC24 -to SW[10]
+set_location_assignment PIN_AB24 -to SW[11]
+set_location_assignment PIN_AB23 -to SW[12]
+set_location_assignment PIN_AA24 -to SW[13]
+set_location_assignment PIN_AA23 -to SW[14]
+set_location_assignment PIN_AA22 -to SW[15]
+set_location_assignment PIN_Y24 -to SW[16]
+set_location_assignment PIN_Y23 -to SW[17]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[7]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[8]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[9]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[10]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[11]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[12]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[13]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[14]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[15]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[16]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[17]
+
+#============================================================
+# SEG7
+#============================================================
+set_location_assignment PIN_G18 -to HEX0[0]
+set_location_assignment PIN_F22 -to HEX0[1]
+set_location_assignment PIN_E17 -to HEX0[2]
+set_location_assignment PIN_L26 -to HEX0[3]
+set_location_assignment PIN_L25 -to HEX0[4]
+set_location_assignment PIN_J22 -to HEX0[5]
+set_location_assignment PIN_H22 -to HEX0[6]
+set_location_assignment PIN_M24 -to HEX1[0]
+set_location_assignment PIN_Y22 -to HEX1[1]
+set_location_assignment PIN_W21 -to HEX1[2]
+set_location_assignment PIN_W22 -to HEX1[3]
+set_location_assignment PIN_W25 -to HEX1[4]
+set_location_assignment PIN_U23 -to HEX1[5]
+set_location_assignment PIN_U24 -to HEX1[6]
+set_location_assignment PIN_AA25 -to HEX2[0]
+set_location_assignment PIN_AA26 -to HEX2[1]
+set_location_assignment PIN_Y25 -to HEX2[2]
+set_location_assignment PIN_W26 -to HEX2[3]
+set_location_assignment PIN_Y26 -to HEX2[4]
+set_location_assignment PIN_W27 -to HEX2[5]
+set_location_assignment PIN_W28 -to HEX2[6]
+set_location_assignment PIN_V21 -to HEX3[0]
+set_location_assignment PIN_U21 -to HEX3[1]
+set_location_assignment PIN_AB20 -to HEX3[2]
+set_location_assignment PIN_AA21 -to HEX3[3]
+set_location_assignment PIN_AD24 -to HEX3[4]
+set_location_assignment PIN_AF23 -to HEX3[5]
+set_location_assignment PIN_Y19 -to HEX3[6]
+set_location_assignment PIN_AB19 -to HEX4[0]
+set_location_assignment PIN_AA19 -to HEX4[1]
+set_location_assignment PIN_AG21 -to HEX4[2]
+set_location_assignment PIN_AH21 -to HEX4[3]
+set_location_assignment PIN_AE19 -to HEX4[4]
+set_location_assignment PIN_AF19 -to HEX4[5]
+set_location_assignment PIN_AE18 -to HEX4[6]
+set_location_assignment PIN_AD18 -to HEX5[0]
+set_location_assignment PIN_AC18 -to HEX5[1]
+set_location_assignment PIN_AB18 -to HEX5[2]
+set_location_assignment PIN_AH19 -to HEX5[3]
+set_location_assignment PIN_AG19 -to HEX5[4]
+set_location_assignment PIN_AF18 -to HEX5[5]
+set_location_assignment PIN_AH18 -to HEX5[6]
+set_location_assignment PIN_AA17 -to HEX6[0]
+set_location_assignment PIN_AB16 -to HEX6[1]
+set_location_assignment PIN_AA16 -to HEX6[2]
+set_location_assignment PIN_AB17 -to HEX6[3]
+set_location_assignment PIN_AB15 -to HEX6[4]
+set_location_assignment PIN_AA15 -to HEX6[5]
+set_location_assignment PIN_AC17 -to HEX6[6]
+set_location_assignment PIN_AD17 -to HEX7[0]
+set_location_assignment PIN_AE17 -to HEX7[1]
+set_location_assignment PIN_AG17 -to HEX7[2]
+set_location_assignment PIN_AH17 -to HEX7[3]
+set_location_assignment PIN_AF17 -to HEX7[4]
+set_location_assignment PIN_AG18 -to HEX7[5]
+set_location_assignment PIN_AA14 -to HEX7[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[6]
+
+#============================================================
+# LCD
+#============================================================
+set_location_assignment PIN_L6 -to LCD_BLON
+set_location_assignment PIN_M5 -to LCD_DATA[7]
+set_location_assignment PIN_M3 -to LCD_DATA[6]
+set_location_assignment PIN_K2 -to LCD_DATA[5]
+set_location_assignment PIN_K1 -to LCD_DATA[4]
+set_location_assignment PIN_K7 -to LCD_DATA[3]
+set_location_assignment PIN_L2 -to LCD_DATA[2]
+set_location_assignment PIN_L1 -to LCD_DATA[1]
+set_location_assignment PIN_L3 -to LCD_DATA[0]
+set_location_assignment PIN_L4 -to LCD_EN
+set_location_assignment PIN_M1 -to LCD_RW
+set_location_assignment PIN_M2 -to LCD_RS
+set_location_assignment PIN_L5 -to LCD_ON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_ON
+
+#============================================================
+# RS232
+#============================================================
+set_location_assignment PIN_G9 -to UART_TXD
+set_location_assignment PIN_G12 -to UART_RXD
+set_location_assignment PIN_G14 -to UART_CTS
+set_location_assignment PIN_J13 -to UART_RTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+
+#============================================================
+# PS2
+#============================================================
+set_location_assignment PIN_G6 -to PS2_KBCLK
+set_location_assignment PIN_H5 -to PS2_KBDAT
+set_location_assignment PIN_G5 -to PS2_MSCLK
+set_location_assignment PIN_F5 -to PS2_MSDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_MSCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_MSDAT
+
+#============================================================
+# SDCARD
+#============================================================
+set_location_assignment PIN_AE14 -to SD_DAT[0]
+set_location_assignment PIN_AF13 -to SD_DAT[1]
+set_location_assignment PIN_AB14 -to SD_DAT[2]
+set_location_assignment PIN_AC14 -to SD_DAT[3]
+set_location_assignment PIN_AE13 -to SD_CLK
+set_location_assignment PIN_AD14 -to SD_CMD
+set_location_assignment PIN_AF14 -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[3]
+
+#============================================================
+# VGA
+#============================================================
+set_location_assignment PIN_D12 -to VGA_B[7]
+set_location_assignment PIN_D11 -to VGA_B[6]
+set_location_assignment PIN_C12 -to VGA_B[5]
+set_location_assignment PIN_A11 -to VGA_B[4]
+set_location_assignment PIN_B11 -to VGA_B[3]
+set_location_assignment PIN_C11 -to VGA_B[2]
+set_location_assignment PIN_A10 -to VGA_B[1]
+set_location_assignment PIN_B10 -to VGA_B[0]
+set_location_assignment PIN_C9 -to VGA_G[7]
+set_location_assignment PIN_F10 -to VGA_G[6]
+set_location_assignment PIN_B8 -to VGA_G[5]
+set_location_assignment PIN_C8 -to VGA_G[4]
+set_location_assignment PIN_H12 -to VGA_G[3]
+set_location_assignment PIN_F8 -to VGA_G[2]
+set_location_assignment PIN_G11 -to VGA_G[1]
+set_location_assignment PIN_G8 -to VGA_G[0]
+set_location_assignment PIN_H10 -to VGA_R[7]
+set_location_assignment PIN_H8 -to VGA_R[6]
+set_location_assignment PIN_J12 -to VGA_R[5]
+set_location_assignment PIN_G10 -to VGA_R[4]
+set_location_assignment PIN_F12 -to VGA_R[3]
+set_location_assignment PIN_D10 -to VGA_R[2]
+set_location_assignment PIN_E11 -to VGA_R[1]
+set_location_assignment PIN_E12 -to VGA_R[0]
+set_location_assignment PIN_A12 -to VGA_CLK
+set_location_assignment PIN_F11 -to VGA_BLANK_N
+set_location_assignment PIN_C10 -to VGA_SYNC_N
+set_location_assignment PIN_G13 -to VGA_HS
+set_location_assignment PIN_C13 -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7]
+
+#============================================================
+# Audio
+#============================================================
+set_location_assignment PIN_D1 -to AUD_DACDAT
+set_location_assignment PIN_E3 -to AUD_DACLRCK
+set_location_assignment PIN_D2 -to AUD_ADCDAT
+set_location_assignment PIN_C2 -to AUD_ADCLRCK
+set_location_assignment PIN_E1 -to AUD_XCK
+set_location_assignment PIN_F2 -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK
+
+#============================================================
+# I2C for EEPROM
+#============================================================
+set_location_assignment PIN_D14 -to EEP_I2C_SCLK
+set_location_assignment PIN_E14 -to EEP_I2C_SDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SDAT
+
+#============================================================
+# I2C for Audioand Tv-Decode 1 and 2
+#============================================================
+set_location_assignment PIN_B7 -to I2C_SCLK
+set_location_assignment PIN_A8 -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT
+
+#============================================================
+# Ethernet 0
+#============================================================
+set_location_assignment PIN_A17 -to ENET0_GTX_CLK
+set_location_assignment PIN_A21 -to ENET0_INT_N
+set_location_assignment PIN_C20 -to ENET0_MDC
+set_location_assignment PIN_B21 -to ENET0_MDIO
+set_location_assignment PIN_C19 -to ENET0_RESET_N
+set_location_assignment PIN_A15 -to ENET0_RX_CLK
+set_location_assignment PIN_E15 -to ENET0_RX_COL
+set_location_assignment PIN_D15 -to ENET0_RX_CRS
+set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
+set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
+set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
+set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
+set_location_assignment PIN_C17 -to ENET0_RX_DV
+set_location_assignment PIN_D18 -to ENET0_RX_ER
+set_location_assignment PIN_B17 -to ENET0_TX_CLK
+set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
+set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
+set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
+set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
+set_location_assignment PIN_A18 -to ENET0_TX_EN
+set_location_assignment PIN_B18 -to ENET0_TX_ER
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_GTX_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_EN
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_ER
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RESET_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DV
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_ER
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CRS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_COL
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDC
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDIO
+
+#============================================================
+# Ethernet 1
+#============================================================
+set_location_assignment PIN_C23 -to ENET1_GTX_CLK
+set_location_assignment PIN_D24 -to ENET1_INT_N
+set_location_assignment PIN_D23 -to ENET1_MDC
+set_location_assignment PIN_D25 -to ENET1_MDIO
+set_location_assignment PIN_D22 -to ENET1_RESET_N
+set_location_assignment PIN_B15 -to ENET1_RX_CLK
+set_location_assignment PIN_B22 -to ENET1_RX_COL
+set_location_assignment PIN_D20 -to ENET1_RX_CRS
+set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
+set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
+set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
+set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
+set_location_assignment PIN_A22 -to ENET1_RX_DV
+set_location_assignment PIN_C24 -to ENET1_RX_ER
+set_location_assignment PIN_C22 -to ENET1_TX_CLK
+set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
+set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
+set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
+set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
+set_location_assignment PIN_B25 -to ENET1_TX_EN
+set_location_assignment PIN_A25 -to ENET1_TX_ER
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_GTX_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_EN
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_ER
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_INT_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RESET_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DV
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_ER
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CRS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_COL
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDC
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDIO
+
+set_location_assignment PIN_C14 -to ENET0_LINK100
+set_location_assignment PIN_D13 -to ENET1_LINK100
+set_location_assignment PIN_A14 -to ENETCLK_25
+
+#============================================================
+# TV Decoder
+#============================================================
+set_location_assignment PIN_F7 -to TD_DATA[7]
+set_location_assignment PIN_E7 -to TD_DATA[6]
+set_location_assignment PIN_D6 -to TD_DATA[5]
+set_location_assignment PIN_D7 -to TD_DATA[4]
+set_location_assignment PIN_C7 -to TD_DATA[3]
+set_location_assignment PIN_D8 -to TD_DATA[2]
+set_location_assignment PIN_A7 -to TD_DATA[1]
+set_location_assignment PIN_E8 -to TD_DATA[0]
+set_location_assignment PIN_B14 -to TD_CLK27
+set_location_assignment PIN_G7 -to TD_RESET_N
+set_location_assignment PIN_E4 -to TD_VS
+set_location_assignment PIN_E5 -to TD_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7]
+
+#============================================================
+# USB
+#============================================================
+set_location_assignment PIN_D4 -to OTG_DACK_N[1]
+set_location_assignment PIN_C4 -to OTG_DACK_N[0]
+set_location_assignment PIN_A3 -to OTG_CS_N
+set_location_assignment PIN_B3 -to OTG_OE_N
+set_location_assignment PIN_B4 -to OTG_DREQ[1]
+set_location_assignment PIN_J1 -to OTG_DREQ[0]
+set_location_assignment PIN_A4 -to OTG_WE_N
+set_location_assignment PIN_H7 -to OTG_ADDR[0]
+set_location_assignment PIN_C3 -to OTG_ADDR[1]
+set_location_assignment PIN_C6 -to OTG_FSPEED
+set_location_assignment PIN_B6 -to OTG_LSPEED
+set_location_assignment PIN_D5 -to OTG_INT[1]
+set_location_assignment PIN_A6 -to OTG_INT[0]
+set_location_assignment PIN_C5 -to OTG_RST_N
+set_location_assignment PIN_J6 -to OTG_DATA[0]
+set_location_assignment PIN_K4 -to OTG_DATA[1]
+set_location_assignment PIN_J5 -to OTG_DATA[2]
+set_location_assignment PIN_K3 -to OTG_DATA[3]
+set_location_assignment PIN_J4 -to OTG_DATA[4]
+set_location_assignment PIN_J3 -to OTG_DATA[5]
+set_location_assignment PIN_J7 -to OTG_DATA[6]
+set_location_assignment PIN_H6 -to OTG_DATA[7]
+set_location_assignment PIN_H3 -to OTG_DATA[8]
+set_location_assignment PIN_H4 -to OTG_DATA[9]
+set_location_assignment PIN_G1 -to OTG_DATA[10]
+set_location_assignment PIN_G2 -to OTG_DATA[11]
+set_location_assignment PIN_G3 -to OTG_DATA[12]
+set_location_assignment PIN_F1 -to OTG_DATA[13]
+set_location_assignment PIN_F3 -to OTG_DATA[14]
+set_location_assignment PIN_G4 -to OTG_DATA[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DACK_N[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DACK_N[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_FSPEED
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_LSPEED
+
+#============================================================
+# IR Receiver
+#============================================================
+set_location_assignment PIN_Y15 -to IRDA_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD
+
+#============================================================
+# SDRAM
+#============================================================
+set_location_assignment PIN_AE5 -to DRAM_CLK
+set_location_assignment PIN_U1 -to DRAM_DQ[31]
+set_location_assignment PIN_U4 -to DRAM_DQ[30]
+set_location_assignment PIN_T3 -to DRAM_DQ[29]
+set_location_assignment PIN_R3 -to DRAM_DQ[28]
+set_location_assignment PIN_R2 -to DRAM_DQ[27]
+set_location_assignment PIN_R1 -to DRAM_DQ[26]
+set_location_assignment PIN_R7 -to DRAM_DQ[25]
+set_location_assignment PIN_U5 -to DRAM_DQ[24]
+set_location_assignment PIN_M8 -to DRAM_DQ[16]
+set_location_assignment PIN_L8 -to DRAM_DQ[17]
+set_location_assignment PIN_P2 -to DRAM_DQ[18]
+set_location_assignment PIN_N3 -to DRAM_DQ[19]
+set_location_assignment PIN_N4 -to DRAM_DQ[20]
+set_location_assignment PIN_M4 -to DRAM_DQ[21]
+set_location_assignment PIN_M7 -to DRAM_DQ[22]
+set_location_assignment PIN_L7 -to DRAM_DQ[23]
+set_location_assignment PIN_Y3 -to DRAM_DQ[8]
+set_location_assignment PIN_Y4 -to DRAM_DQ[9]
+set_location_assignment PIN_AB1 -to DRAM_DQ[10]
+set_location_assignment PIN_AA3 -to DRAM_DQ[11]
+set_location_assignment PIN_AB2 -to DRAM_DQ[12]
+set_location_assignment PIN_AC1 -to DRAM_DQ[13]
+set_location_assignment PIN_AB3 -to DRAM_DQ[14]
+set_location_assignment PIN_AC2 -to DRAM_DQ[15]
+set_location_assignment PIN_W3 -to DRAM_DQ[0]
+set_location_assignment PIN_W2 -to DRAM_DQ[1]
+set_location_assignment PIN_V4 -to DRAM_DQ[2]
+set_location_assignment PIN_W1 -to DRAM_DQ[3]
+set_location_assignment PIN_V3 -to DRAM_DQ[4]
+set_location_assignment PIN_V2 -to DRAM_DQ[5]
+set_location_assignment PIN_V1 -to DRAM_DQ[6]
+set_location_assignment PIN_U3 -to DRAM_DQ[7]
+set_location_assignment PIN_W4 -to DRAM_DQM[1]
+set_location_assignment PIN_K8 -to DRAM_DQM[2]
+set_location_assignment PIN_U2 -to DRAM_DQM[0]
+set_location_assignment PIN_N8 -to DRAM_DQM[3]
+set_location_assignment PIN_U6 -to DRAM_RAS_N
+set_location_assignment PIN_V7 -to DRAM_CAS_N
+set_location_assignment PIN_AA6 -to DRAM_CKE
+set_location_assignment PIN_V6 -to DRAM_WE_N
+set_location_assignment PIN_T4 -to DRAM_CS_N
+set_location_assignment PIN_U7 -to DRAM_BA[0]
+set_location_assignment PIN_R4 -to DRAM_BA[1]
+set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
+set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
+set_location_assignment PIN_R5 -to DRAM_ADDR[10]
+set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
+set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
+set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
+set_location_assignment PIN_W7 -to DRAM_ADDR[6]
+set_location_assignment PIN_W8 -to DRAM_ADDR[5]
+set_location_assignment PIN_V5 -to DRAM_ADDR[4]
+set_location_assignment PIN_P1 -to DRAM_ADDR[3]
+set_location_assignment PIN_U8 -to DRAM_ADDR[2]
+set_location_assignment PIN_V8 -to DRAM_ADDR[1]
+set_location_assignment PIN_R6 -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+
+#============================================================
+# SRAM
+#============================================================
+set_location_assignment PIN_AG3 -to SRAM_DQ[15]
+set_location_assignment PIN_AF3 -to SRAM_DQ[14]
+set_location_assignment PIN_AE4 -to SRAM_DQ[13]
+set_location_assignment PIN_AE3 -to SRAM_DQ[12]
+set_location_assignment PIN_AE1 -to SRAM_DQ[11]
+set_location_assignment PIN_AE2 -to SRAM_DQ[10]
+set_location_assignment PIN_AD2 -to SRAM_DQ[9]
+set_location_assignment PIN_AD1 -to SRAM_DQ[8]
+set_location_assignment PIN_AF7 -to SRAM_DQ[7]
+set_location_assignment PIN_AH6 -to SRAM_DQ[6]
+set_location_assignment PIN_AG6 -to SRAM_DQ[5]
+set_location_assignment PIN_AF6 -to SRAM_DQ[4]
+set_location_assignment PIN_AH4 -to SRAM_DQ[3]
+set_location_assignment PIN_AG4 -to SRAM_DQ[2]
+set_location_assignment PIN_AF4 -to SRAM_DQ[1]
+set_location_assignment PIN_AH3 -to SRAM_DQ[0]
+set_location_assignment PIN_AC4 -to SRAM_UB_N
+set_location_assignment PIN_AD4 -to SRAM_LB_N
+set_location_assignment PIN_AF8 -to SRAM_CE_N
+set_location_assignment PIN_AD5 -to SRAM_OE_N
+set_location_assignment PIN_AE8 -to SRAM_WE_N
+set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
+set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
+set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
+set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
+set_location_assignment PIN_T7 -to SRAM_ADDR[9]
+set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
+set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
+set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
+set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
+set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
+set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
+set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
+set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
+set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
+set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
+set_location_assignment PIN_T8 -to SRAM_ADDR[19]
+set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
+set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
+set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
+set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_UB_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_LB_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_WE_N
+
+#============================================================
+# Flash
+#============================================================
+set_location_assignment PIN_AF12 -to FL_DQ[7]
+set_location_assignment PIN_AH11 -to FL_DQ[6]
+set_location_assignment PIN_AG11 -to FL_DQ[5]
+set_location_assignment PIN_AF11 -to FL_DQ[4]
+set_location_assignment PIN_AH10 -to FL_DQ[3]
+set_location_assignment PIN_AG10 -to FL_DQ[2]
+set_location_assignment PIN_AF10 -to FL_DQ[1]
+set_location_assignment PIN_AH8 -to FL_DQ[0]
+set_location_assignment PIN_AG12 -to FL_ADDR[0]
+set_location_assignment PIN_AD11 -to FL_ADDR[22]
+set_location_assignment PIN_AD10 -to FL_ADDR[21]
+set_location_assignment PIN_AE10 -to FL_ADDR[20]
+set_location_assignment PIN_AD12 -to FL_ADDR[19]
+set_location_assignment PIN_AC12 -to FL_ADDR[18]
+set_location_assignment PIN_AH12 -to FL_ADDR[17]
+set_location_assignment PIN_AA8 -to FL_ADDR[16]
+set_location_assignment PIN_Y10 -to FL_ADDR[15]
+set_location_assignment PIN_AC8 -to FL_ADDR[14]
+set_location_assignment PIN_AD8 -to FL_ADDR[13]
+set_location_assignment PIN_AA10 -to FL_ADDR[12]
+set_location_assignment PIN_AF9 -to FL_ADDR[11]
+set_location_assignment PIN_AE9 -to FL_ADDR[10]
+set_location_assignment PIN_AB10 -to FL_ADDR[9]
+set_location_assignment PIN_AB12 -to FL_ADDR[8]
+set_location_assignment PIN_AB13 -to FL_ADDR[7]
+set_location_assignment PIN_AA12 -to FL_ADDR[6]
+set_location_assignment PIN_AA13 -to FL_ADDR[5]
+set_location_assignment PIN_Y12 -to FL_ADDR[4]
+set_location_assignment PIN_Y14 -to FL_ADDR[3]
+set_location_assignment PIN_Y13 -to FL_ADDR[2]
+set_location_assignment PIN_AH7 -to FL_ADDR[1]
+set_location_assignment PIN_AG7 -to FL_CE_N
+set_location_assignment PIN_AG8 -to FL_OE_N
+set_location_assignment PIN_AC10 -to FL_WE_N
+set_location_assignment PIN_AE11 -to FL_RESET_N
+set_location_assignment PIN_AE12 -to FL_WP_N
+set_location_assignment PIN_Y1 -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RESET_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+
+#============================================================
+# GPIO, GPIO connect to GPIO Default
+#============================================================
+set_location_assignment PIN_AB22 -to GPIO[0]
+set_location_assignment PIN_AC15 -to GPIO[1]
+set_location_assignment PIN_AB21 -to GPIO[2]
+set_location_assignment PIN_Y17 -to GPIO[3]
+set_location_assignment PIN_AC21 -to GPIO[4]
+set_location_assignment PIN_Y16 -to GPIO[5]
+set_location_assignment PIN_AD21 -to GPIO[6]
+set_location_assignment PIN_AE16 -to GPIO[7]
+set_location_assignment PIN_AD15 -to GPIO[8]
+set_location_assignment PIN_AE15 -to GPIO[9]
+set_location_assignment PIN_AC19 -to GPIO[10]
+set_location_assignment PIN_AF16 -to GPIO[11]
+set_location_assignment PIN_AD19 -to GPIO[12]
+set_location_assignment PIN_AF15 -to GPIO[13]
+set_location_assignment PIN_AF24 -to GPIO[14]
+set_location_assignment PIN_AE21 -to GPIO[15]
+set_location_assignment PIN_AF25 -to GPIO[16]
+set_location_assignment PIN_AC22 -to GPIO[17]
+set_location_assignment PIN_AE22 -to GPIO[18]
+set_location_assignment PIN_AF21 -to GPIO[19]
+set_location_assignment PIN_AF22 -to GPIO[20]
+set_location_assignment PIN_AD22 -to GPIO[21]
+set_location_assignment PIN_AG25 -to GPIO[22]
+set_location_assignment PIN_AD25 -to GPIO[23]
+set_location_assignment PIN_AH25 -to GPIO[24]
+set_location_assignment PIN_AE25 -to GPIO[25]
+set_location_assignment PIN_AG22 -to GPIO[26]
+set_location_assignment PIN_AE24 -to GPIO[27]
+set_location_assignment PIN_AH22 -to GPIO[28]
+set_location_assignment PIN_AF26 -to GPIO[29]
+set_location_assignment PIN_AE20 -to GPIO[30]
+set_location_assignment PIN_AG23 -to GPIO[31]
+set_location_assignment PIN_AF20 -to GPIO[32]
+set_location_assignment PIN_AH26 -to GPIO[33]
+set_location_assignment PIN_AH23 -to GPIO[34]
+set_location_assignment PIN_AG26 -to GPIO[35]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35]
+
+#============================================================
+# HSMC, HSMC connect to HSMC Default
+#============================================================
+set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
+set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
+set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
+set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
+set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
+set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
+set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
+set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
+set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
+set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
+set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
+set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
+set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
+set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
+set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
+set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
+set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
+set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
+set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
+set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
+set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
+set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
+set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
+set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
+set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
+set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
+set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
+set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
+set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
+set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
+set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
+set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
+set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
+set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
+set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
+set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
+set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
+set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
+set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
+set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
+set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
+set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
+set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
+set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
+set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
+set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
+set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
+set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
+set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
+set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
+set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
+set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
+set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
+set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
+set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
+set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
+set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
+set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
+set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
+set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
+set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
+set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
+set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
+set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
+set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
+set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
+set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
+set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
+set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
+set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
+set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
+set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
+set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
+set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
+set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
+set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
+set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
+set_location_assignment PIN_AE26 -to HSMC_D[0]
+set_location_assignment PIN_AE28 -to HSMC_D[1]
+set_location_assignment PIN_AE27 -to HSMC_D[2]
+set_location_assignment PIN_AF27 -to HSMC_D[3]
+set_location_assignment PIN_AH15 -to HSMC_CLKIN0
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT0
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[3]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P1
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N1
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[12]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[12]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[12]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[12]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[13]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[13]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[13]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[13]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[14]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[14]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[14]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[14]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[15]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[15]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[15]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[15]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[16]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[16]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[16]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[16]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P2
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N2
+
+#============================================================
+# HSMC, HSMC connect to HSMC Default
+#============================================================
+set_location_assignment PIN_J10 -to EXT_IO[0]
+set_location_assignment PIN_J14 -to EXT_IO[1]
+set_location_assignment PIN_H13 -to EXT_IO[2]
+set_location_assignment PIN_H14 -to EXT_IO[3]
+set_location_assignment PIN_F14 -to EXT_IO[4]
+set_location_assignment PIN_E10 -to EXT_IO[5]
+set_location_assignment PIN_D9 -to EXT_IO[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_IO[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_IO[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_IO[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_IO[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_IO[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_IO[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EXT_IO[6]
+
+#============================================================
+# End of pin assignments by Altera University Program
+#============================================================
+
+
+
+
+
+
+
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_INT_N
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[8]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[9]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[10]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[11]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[8]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[9]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[10]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[11]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[8]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[9]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[10]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[11]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[7]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[8]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[9]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[10]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[11]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P2
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N2
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[0]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[1]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[2]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[3]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[4]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[5]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[6]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[7]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[0]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[1]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[2]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[3]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[4]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[5]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[6]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[7]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[0]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[1]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[2]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[3]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[4]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[5]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[6]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[7]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[0]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[1]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[2]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[3]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[4]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[5]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[6]
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P1
+set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N1
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSMC_CLKIN0
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET0_LINK100
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET1_LINK100
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENETCLK_25
+
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS64
+
+
+
+
+
+
+
+
+set_global_assignment -name TOP_LEVEL_ENTITY lcd_test_top
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:13:20 APRIL 18, 2016"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 780
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX2
+set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX0
+set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX1
+set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to KEY
+set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to SW
+set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX3[1]
+set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX3[0]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to *
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to *
+set_instance_assignment -name TSU_REQUIREMENT "10 ns" -from * -to *
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VERILOG_FILE src_verilog/reset_jtag.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/wishbone_bus.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/main_comp.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/lcd_2x16.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/clk_source.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/arbiter.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/Altera_single_port_ram.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/altera_reset_synchronizer.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB_xecu.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB_sim.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB_regf.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB_ibuf.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB_edk32.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB_ctrl.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB_core.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB_bpcu.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_xslif.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_tpsram.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_spsram.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_sparam.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_sim.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_regs.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_pipe.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_mult.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_memif.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_iwbif.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_intu.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_iche.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_gprf.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_exec.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_edk63.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_edk62.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_dwbif.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_dparam.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_ctrl.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_bsft.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aeMB2_brcc.v
+set_global_assignment -name VERILOG_FILE src_verilog/lib/aemb.v
+set_global_assignment -name VERILOG_FILE src_verilog/lcd_test.v
+set_global_assignment -name VERILOG_FILE src_verilog/lcd_test_tio.v
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testbench -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_NAME testbench -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id testbench
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench -section_id testbench
+set_global_assignment -name EDA_TEST_BENCH_FILE src_verilog/testbench.v -section_id testbench
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/lcd_test/src_verilog/lcd_test_top.v
===================================================================
--- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/lcd_test/src_verilog/lcd_test_top.v (nonexistent)
+++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/lcd_test/src_verilog/lcd_test_top.v (revision 24)
@@ -0,0 +1,52 @@
+module lcd_test_top (
+
+ output [0:0]LEDR,
+ output [0:0]LEDG,
+ input [0:0]KEY,
+ input CLOCK_50,
+
+ //////////// LCD //////////
+ output LCD_BLON,
+ inout [7:0] LCD_DATA,
+ output LCD_EN,
+ output LCD_ON,
+ output LCD_RS,
+ output LCD_RW
+ );
+ wire reset_in,jtag_reset,reset;
+
+ assign reset_in = ~KEY[0];
+ assign LEDG[0] = reset;
+ assign reset = (jtag_reset | reset_in);
+
+ // a reset source which can be controled using altera in-system source editor
+ reset_jtag the_reset(
+ .probe(),
+ .source(jtag_reset)
+ );
+
+
+
+
+
+ lcd_test top (
+ .aeMB_sys_ena_i(1'b1),
+ .ss_clk_in(CLOCK_50),
+ .ss_reset_in(reset),
+ .lcd_lcd_data(LCD_DATA),
+ .lcd_lcd_en(LCD_EN),
+ .lcd_lcd_rs(LCD_RS),
+ .lcd_lcd_rw(LCD_RW)
+);
+
+///////////////////////////////////////////
+// LCD config
+assign LCD_BLON = 1'b0; // not supported
+assign LCD_ON = 1'b1; // alwasy on
+
+
+
+
+
+endmodule
+
Index: an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/lcd_test/src_verilog/reset_jtag.v
===================================================================
--- an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/lcd_test/src_verilog/reset_jtag.v (nonexistent)
+++ an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/lcd_test/src_verilog/reset_jtag.v (revision 24)
@@ -0,0 +1,107 @@
+// megafunction wizard: %In-System Sources and Probes%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsource_probe
+
+// ============================================================
+// File Name: reset_jtag.v
+// Megafunction Name(s):
+// altsource_probe
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.0.0 Build 156 04/24/2013 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module reset_jtag (
+ probe,
+ source);
+
+ input [0:0] probe;
+ output [0:0] source;
+
+ wire [0:0] sub_wire0;
+ wire [0:0] source = sub_wire0[0:0];
+
+ altsource_probe altsource_probe_component (
+ .probe (probe),
+ .source (sub_wire0)
+ // synopsys translate_off
+ ,
+ .clrn (),
+ .ena (),
+ .ir_in (),
+ .ir_out (),
+ .jtag_state_cdr (),
+ .jtag_state_cir (),
+ .jtag_state_e1dr (),
+ .jtag_state_sdr (),
+ .jtag_state_tlr (),
+ .jtag_state_udr (),
+ .jtag_state_uir (),
+ .raw_tck (),
+ .source_clk (),
+ .source_ena (),
+ .tdi (),
+ .tdo (),
+ .usr1 ()
+ // synopsys translate_on
+ );
+ defparam
+ altsource_probe_component.enable_metastability = "NO",
+ altsource_probe_component.instance_id = "RST",
+ altsource_probe_component.probe_width = 1,
+ altsource_probe_component.sld_auto_instance_index = "NO",
+ altsource_probe_component.sld_instance_index = 127,
+ altsource_probe_component.source_initial_value = " 0",
+ altsource_probe_component.source_width = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "NO"
+// Retrieval info: CONSTANT: INSTANCE_ID STRING "RST"
+// Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "NO"
+// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "127"
+// Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 0"
+// Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "1"
+// Retrieval info: USED_PORT: probe 0 0 1 0 INPUT NODEFVAL "probe[0..0]"
+// Retrieval info: USED_PORT: source 0 0 1 0 OUTPUT NODEFVAL "source[0..0]"
+// Retrieval info: CONNECT: @probe 0 0 1 0 probe 0 0 1 0
+// Retrieval info: CONNECT: source 0 0 1 0 @source 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL reset_jtag_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/mpsoc/perl_gui/examples/lcd_test/src_verilog/reset_jtag.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property