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URL https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk

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/axi4_tlm_bfm/trunk/rtl/axi4-stream-bfm-master.vhdl
56,12 → 56,12
-- axiSlave_out:buffer tAxi4Transactor_s2m;
symbolsPerTransfer:in i_transactor.t_cnt;
outstandingTransactions:in i_transactor.t_cnt
outstandingTransactions:in i_transactor.t_cnt;
/* Debug ports. */
-- dbg_cnt:out unsigned(9 downto 0);
-- dbg_axiRxFsm:out axiBfmStatesRx:=idle;
-- dbg_axiTxFsm:out axiBfmStatesTx:=idle
dbg_axiTxFsm:out axiBfmStatesTx:=idle
);
end entity axiBfmMaster;
 
138,4 → 138,5
end if;
end process;
dbg_axiTxFSM<=axiTxState;
end architecture rtl;
/axi4_tlm_bfm/trunk/rtl/user.vhdl
44,22 → 44,25
library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
/* synthesis translate_on */
 
--library altera; use altera.stp;
 
 
entity user is port(
/* Comment-out for simulation. */
-- clk,nReset:in std_ulogic;
-- clk,reset:in std_ulogic;
/* AXI Master interface */
-- axiMaster_in:in t_axi4StreamTransactor_s2m;
axiMaster_out:buffer t_axi4StreamTransactor_m2s
axiMaster_out:buffer t_axi4StreamTransactor_m2s;
/* Debug ports. */
selTxn:in unsigned(3 downto 0):=x"0"
);
end entity user;
 
architecture rtl of user is
signal reset:std_ulogic:='0';
signal i_reset:std_ulogic:='0';
signal porCnt:unsigned(3 downto 0);
signal trigger:boolean;
/* Global counters. */
constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
70,26 → 73,24
signal readRequest,writeRequest:i_transactor.t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
signal readResponse,writeResponse:i_transactor.t_bfm;
type txStates is (idle,transmitting);
signal txFSM,i_txFSM:txStates;
/* Tester signals. */
/* synthesis translate_off */
signal clk,nReset:std_ulogic:='0';
signal clk,reset:std_ulogic:='0';
attribute period:time; attribute period of clk:signal is 10 ps;
/* synthesis translate_on */
signal dbg_axiTxFSM:axiBfmStatesTx;
signal anlysr_dataIn:std_logic_vector(255 downto 0);
signal anlysr_trigger:std_ulogic;
signal axiMaster_in:t_axi4StreamTransactor_s2m;
signal irq_write:std_ulogic; -- clock gating.
signal prbs:i_transactor.t_msg;
begin
/* Bus functional models. */
axiMaster: entity tauhop.axiBfmMaster(rtl)
--axiMaster: entity work.axiBfmMaster(simulation)
port map(
aclk=>irq_write, n_areset=>not reset,
aclk=>irq_write, n_areset=>not i_reset,
readRequest=>readRequest, writeRequest=>writeRequest,
readResponse=>readResponse, writeResponse=>writeResponse,
97,256 → 98,43
axiMaster_out=>axiMaster_out,
symbolsPerTransfer=>symbolsPerTransfer,
outstandingTransactions=>outstandingTransactions
outstandingTransactions=>outstandingTransactions,
dbg_axiTxFSM=>dbg_axiTxFSM
);
/* Interrupt-request generator. */
trigger<=txFSM/=i_txFSM or writeResponse.trigger;
irq_write<=clk when not reset else '0';
/* Simulation Tester. */
/* synthesis translate_off */
clk<=not clk after clk'period/2;
process is begin
nReset<='1'; wait for 1 ps;
nReset<='0'; wait for 500 ps;
nReset<='1';
wait;
end process;
/* synthesis translate_on */
/* Hardware tester. */
/* Clocks and reset. */
/* Power-on Reset circuitry. */
por: process(nReset,clk) is begin
if not nReset then reset<='1'; porCnt<=(others=>'1');
por: process(reset,clk) is begin
if reset then i_reset<='1'; porCnt<=(others=>'1');
elsif rising_edge(clk) then
reset<='0';
i_reset<='0';
if porCnt>0 then reset<='1'; porCnt<=porCnt-1; end if;
if porCnt>0 then i_reset<='1'; porCnt<=porCnt-1; end if;
end if;
end process por;
/*
process is
alias trigger is <<signal axiMaster.trigger:boolean>>;
alias axiTxState is <<signal axiMaster.next_axiTxState:axiBfmStatesTx>>;
begin
-- Remove this assertion once request queue has been implemented.
if trigger then
assert axiTxState=idle or axiTxState=payload report "[Error]: Trigger occurs when FSM is not in IDLE or PAYLOAD state." severity error;
end if;
wait for clk'period/10;
end process;
*/
/* Stimuli sequencer. TODO move to tester/stimuli.
This emulates the AXI4-Stream Slave.
*/
/* Simulation-only stimuli sequencer. */
/* synthesis translate_off */
clk<=not clk after clk'period/2;
process is begin
report "Performing fast read..." severity note;
/* Fast read. */
while not axiMaster_out.tLast loop
/* Wait for tValid to assert. */
while not axiMaster_out.tValid loop
wait until falling_edge(clk);
end loop;
axiMaster_in.tReady<=true;
wait until falling_edge(clk);
axiMaster_in.tReady<=false;
end loop;
report "Completed fast read..." severity note;
wait until falling_edge(clk);
report "Performing normal read..." severity note;
/* Normal read. */
while not axiMaster_out.tLast loop
/* Wait for tValid to assert. */
while not axiMaster_out.tValid loop
wait until falling_edge(clk);
end loop;
wait until falling_edge(clk);
axiMaster_in.tReady<=true;
wait until falling_edge(clk);
axiMaster_in.tReady<=false;
wait until falling_edge(clk);
end loop;
report "Completed normal read." severity note;
wait until falling_edge(clk);
report "Performing slow read..." severity note;
/* Slow read. */
while not axiMaster_out.tLast loop
/* Wait for tValid to assert. */
while not axiMaster_out.tValid loop
wait until falling_edge(clk);
end loop;
wait until falling_edge(clk);
wait until falling_edge(clk);
axiMaster_in.tReady<=true;
wait until falling_edge(clk);
axiMaster_in.tReady<=false;
wait until falling_edge(clk);
end loop;
report "Completed slow read." severity note;
for i in 0 to 10 loop
wait until falling_edge(clk);
end loop;
report "Performing one-shot read..." severity note;
/* One-shot read. */
axiMaster_in.tReady<=true;
wait until falling_edge(clk);
axiMaster_in.tReady<=false;
report "Completed one-shot read." severity note;
reset<='0'; wait for 1 ps;
reset<='1'; wait for 500 ps;
reset<='0';
wait;
end process;
/* synthesis translate_on */
/* Synthesisable stimuli sequencer. */
/* Simulation Tester. */
/* Data transmitter. */
i_prbs: entity tauhop.prbs31(rtl)
generic map(
isParallelLoad=>true,
tapVector=>(
/* Example polynomial from Wikipedia:
http://en.wikipedia.org/wiki/Computation_of_cyclic_redundancy_checks
*/
0|3|31=>true, 1|2|30 downto 4=>false
)
)
port map(
/* Comment-out for simulation. */
clk=>irq_write, reset=>reset,
en=>trigger,
seed=>32x"ace1", --9x"57",
prbs=>prbs
);
sequencer_ns: process(all) is begin
txFSM<=i_txFSM;
if reset then txFSM<=idle;
else
case i_txFSM is
when idle=>
if outstandingTransactions>0 then txFSM<=transmitting; end if;
when transmitting=>
if axiMaster_out.tLast then
txFSM<=idle;
end if;
when others=> null;
end case;
end if;
end process sequencer_ns;
sequencer_op: process(reset,irq_write) is
/* Local procedures to map BFM signals with the package procedure. */
procedure read(address:in i_transactor.t_addr) is begin
i_transactor.read(readRequest,address);
end procedure read;
procedure write(data:in i_transactor.t_msg) is begin
i_transactor.write(request=>writeRequest, address=>(others=>'-'), data=>data);
end procedure write;
variable isPktError:boolean;
/* Tester variables. */
/* Synthesis-only randomisation. */
/* Simulation-only randomisation. */
/* synthesis translate_off */
variable rv0:RandomPType;
/* synthesis translate_on */
begin
-- if reset then
/* simulation only. */
/* synthesis translate_off */
-- rv0.InitSeed(rv0'instance_name);
/* synthesis translate_on */
-- elsif falling_edge(irq_write) then
if falling_edge(irq_write) then
case txFSM is
when transmitting=>
if trigger then
/* synthesis translate_off */
-- write(rv0.RandSigned(axiMaster_out.tData'length));
/* synthesis translate_on */
write(prbs);
end if;
when others=>null;
end case;
end if;
end process sequencer_op;
sequencer_regs: process(irq_write) is begin
if falling_edge(irq_write) then
i_txFSM<=txFSM;
end if;
end process sequencer_regs;
/* Transaction counter. */
process(reset,symbolsPerTransfer,irq_write) is begin
if reset then outstandingTransactions<=symbolsPerTransfer;
elsif rising_edge(irq_write) then
if not axiMaster_out.tLast then
if outstandingTransactions<1 then
outstandingTransactions<=symbolsPerTransfer;
report "No more pending transactions." severity note;
elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
end if;
end if;
/* Use synchronous reset for outstandingTransactions to meet timing because it is a huge register set. */
if reset then outstandingTransactions<=symbolsPerTransfer; end if;
end if;
end process;
/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
process(reset,irq_write) is
/* synthesis translate_off */
variable rv0:RandomPType;
/* synthesis translate_on */
begin
if reset then
/* synthesis translate_off */
rv0.InitSeed(rv0'instance_name);
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note;
/* synthesis translate_on */
elsif rising_edge(irq_write) then
if axiMaster_out.tLast then
/* synthesis translate_off */
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note;
/* synthesis translate_on */
end if;
end if;
end process;
/* Hardware tester. */
bist: entity work.tester(rtl) port map(
clk=>clk, reset=>i_reset,
axiMaster_in=>axiMaster_in,
axiMaster_out=>axiMaster_out,
readRequest=>readRequest, writeRequest=>writeRequest,
readResponse=>readResponse, writeResponse=>writeResponse,
irq_write=>irq_write,
symbolsPerTransfer=>symbolsPerTransfer,
outstandingTransactions=>outstandingTransactions,
selTxn=>selTxn
);
end architecture rtl;
/axi4_tlm_bfm/trunk/rtl/packages/pkg-axi-tlm.vhdl
156,12 → 156,25
-- cActive:
-- end record tAxiTransactor_lp;
-- type axiBfmStatesTx is (idle,sendAddr,startOfPacket,payload,endOfPacket,endOfTx);
type t_fsm is (idle,sendAddr,startOfPacket,payload,endOfPacket,endOfTx);
type axiBfmStatesTx is (idle,payload,endOfTx);
type axiBfmStatesRx is (idle,checkAddr,startOfPacket,payload);
function to_std_logic_vector(fsm:axiBfmStatesTx) return std_logic_vector;
end package axiTLM;
 
package body axiTLM is
function to_std_logic_vector(fsm:axiBfmStatesTx) return std_logic_vector is
variable r:std_logic_vector(1 downto 0);
begin
case fsm is
when idle=> r:=2x"0";
when payload=> r:=2x"1";
when endOfTx=> r:=2x"2";
when others=> null;
end case;
return r;
end function to_std_logic_vector;
end package body axiTLM;
 
 
/axi4_tlm_bfm/trunk/tester/questa/waves.do File deleted
axi4_tlm_bfm/trunk/tester/questa/waves.do Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: axi4_tlm_bfm/trunk/tester/questa/simulate.sh =================================================================== --- axi4_tlm_bfm/trunk/tester/questa/simulate.sh (revision 23) +++ axi4_tlm_bfm/trunk/tester/questa/simulate.sh (nonexistent) @@ -1,65 +0,0 @@ -#!/bin/bash -# -# Example bash script for Mentor Graphics QuestaSim/ModelSim simulation. -# -# Author(s): -# - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com -# -# Copyright (C) 2012-2013 Authors and OPENCORES.ORG -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# This notice and disclaimer must be retained as part of this text at all times. -# -# @dependencies: -# @designer: Daniel C.K. Kho [daniel.kho@gmail.com] | [daniel.kho@tauhop.com] -# @history: @see Mercurial log for full list of changes. -# -# @Description: -# - -#read -p "press Enter to run full simulation now, or Ctrl-C to exit: "; -echo $(date "+[%Y-%m-%d %H:%M:%S]: Removing previously-generated files and folders..."); -rm -rf modelsim.ini ./simulate.log ./work ./altera ./osvvm ./tauhop; - -echo $(date "+[%Y-%m-%d %H:%M:%S]: Remove successful."); -echo $(date "+[%Y-%m-%d %H:%M:%S]: Compiling project..."); -vlib work; vmap work work; -vlib osvvm; vmap osvvm osvvm; -vlib tauhop; vmap tauhop tauhop; - -vcom -2008 -work osvvm ../../../rtl/packages/os-vvm/SortListPkg_int.vhd \ - ../../../rtl/packages/os-vvm/RandomBasePkg.vhd \ - ../../../rtl/packages/os-vvm/RandomPkg.vhd \ - ../../../rtl/packages/os-vvm/CoveragePkg.vhd \ - | tee -ai ./simulate.log; - -vcom -2008 -work tauhop ../../../rtl/packages/pkg-tlm.vhdl \ - ../../../rtl/packages/pkg-axi-tlm.vhdl \ - ../../../rtl/packages/pkg-types.vhdl \ - ../../../rtl/axi4-stream-bfm-master.vhdl \ - ../../../rtl/galois-lfsr.vhdl \ - ../../../rtl/prbs-31.vhdl \ - | tee -ai ./simulate.log; - -vcom -2008 -work work ../../../rtl/user.vhdl \ - | tee -ai ./simulate.log; - -errorStr=`grep "\*\* Error: " ./simulate.log` -if [ `echo ${#errorStr}` -gt 0 ] -then echo "Errors exist. Refer simulate.log for more details. Exiting."; exit; -else - vsim -t ps -do ./waves.do -voptargs="+acc" "work.user(rtl)"; - echo $(date "+[%Y-%m-%d %H:%M:%S]: simulation loaded."); -fi
axi4_tlm_bfm/trunk/tester/questa/simulate.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: axi4_tlm_bfm/trunk/tester/tester.vhdl =================================================================== --- axi4_tlm_bfm/trunk/tester/tester.vhdl (nonexistent) +++ axi4_tlm_bfm/trunk/tester/tester.vhdl (revision 24) @@ -0,0 +1,386 @@ +/* + This file is part of the AXI4 Transactor and Bus Functional Model + (axi4_tlm_bfm) project: + http://www.opencores.org/project,axi4_tlm_bfm + + Description + Synthesisable use case for AXI4 on-chip messaging. + + To Do: + + Author(s): + - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com + + Copyright (C) 2012-2013 Authors and OPENCORES.ORG + + This source file may be used and distributed without + restriction provided that this copyright statement is not + removed from the file and that any derivative work contains + the original copyright notice and the associated disclaimer. + + This source file is free software; you can redistribute it + and/or modify it under the terms of the GNU Lesser General + Public License as published by the Free Software Foundation; + either version 2.1 of the License, or (at your option) any + later version. + + This source is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + PURPOSE. See the GNU Lesser General Public License for more + details. + + You should have received a copy of the GNU Lesser General + Public License along with this source; if not, download it + from http://www.opencores.org/lgpl.shtml. +*/ +library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all; +library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all; --TODO just use axiTransactor here as transactor should already be wrapped up. + +/* TODO remove once generic packages are supported. */ +--library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all; + +/* synthesis translate_off */ +library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all; +/* synthesis translate_on */ + +--library altera; use altera.stp; + + +entity tester is port( + /* Comment-out for simulation. */ + clk,reset:in std_ulogic; + + /* AXI Master interface */ + axiMaster_in:buffer t_axi4StreamTransactor_s2m; + axiMaster_out:in t_axi4StreamTransactor_m2s; + + /* BFM signalling. */ +-- readRequest,writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false); +-- readResponse,writeResponse:t_bfm; + readRequest,writeRequest:buffer t_bfm; + readResponse,writeResponse:in t_bfm; + + irq_write:buffer std_ulogic; -- clock gating. + + symbolsPerTransfer:buffer t_cnt; + outstandingTransactions:buffer t_cnt; + + /* Debug ports. */ +-- dataIn:in t_msg; + selTxn:in unsigned(3 downto 0) +); +end entity tester; + +architecture rtl of tester is +-- signal reset:std_ulogic:='0'; + signal locked:std_ulogic; + signal porCnt:unsigned(3 downto 0); + signal trigger:boolean; + + /* Global counters. */ + constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width. +-- signal symbolsPerTransfer:t_cnt; +-- signal outstandingTransactions:t_cnt; + +-- /* BFM signalling. */ +-- signal readRequest,writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false); +-- signal readResponse,writeResponse:t_bfm; + + type txStates is (idle,transmitting); + signal txFSM,i_txFSM:txStates; + + /* Tester signals. */ + /* synthesis translate_off */ +-- signal clk,nReset:std_ulogic:='0'; + attribute period:time; attribute period of clk:signal is 10 ps; + /* synthesis translate_on */ + + signal testerClk:std_ulogic; + signal dbg_axiTxFSM:axiBfmStatesTx; + signal anlysr_dataIn:std_logic_vector(127 downto 0); + signal anlysr_trigger:std_ulogic; + +-- signal axiMaster_in:t_axi4StreamTransactor_s2m; +-- signal irq_write:std_ulogic; -- clock gating. + + signal prbs:t_msg; + +begin + /* PLL to generate tester's clock. */ +/* f100MHz: entity altera.pll(syn) port map( + areset=>'0', --not nReset, + inclk0=>clk, + c0=>testerClk, + locked=>locked + ); +*/ + /* Interrupt-request generator. */ + trigger<=txFSM/=i_txFSM or writeResponse.trigger; + irq_write<=clk when not reset else '0'; + + /* SignalTap II embedded logic analyser. Included as part of BiST architecture. */ + --anlysr_trigger<='1' when writeRequest.trigger else '0'; + anlysr_trigger<='1' when reset else '0'; + + /* Disable this for synthesis as this is not currently synthesisable. + Pull the framerFSM statemachine signal from lower down the hierarchy to this level instead. + */ + /* synthesis translate_off */ + --framerFSM<=to_unsigned(<>,framerFSM'length); + /* synthesis translate_on */ + + anlysr_dataIn(7 downto 0)<=std_logic_vector(symbolsPerTransfer(7 downto 0)); + anlysr_dataIn(15 downto 8)<=std_logic_vector(outstandingTransactions(7 downto 0)); + --anlysr_dataIn(2 downto 0) <= <>; + anlysr_dataIn(17 downto 16)<=to_std_logic_vector(dbg_axiTxFSM); + anlysr_dataIn(18)<='1' when clk else '0'; + anlysr_dataIn(19)<='1' when reset else '0'; + anlysr_dataIn(20)<='1' when irq_write else '0'; + anlysr_dataIn(21)<='1' when axiMaster_in.tReady else '0'; + anlysr_dataIn(22)<='1' when axiMaster_out.tValid else '0'; + anlysr_dataIn(54 downto 23)<=std_logic_vector(axiMaster_out.tData); + anlysr_dataIn(86 downto 55)<=std_logic_vector(prbs); + --anlysr_dataIn(90 downto 87)<=std_logic_vector(axiMaster_out.tStrb); + --anlysr_dataIn(94 downto 91)<=std_logic_vector(axiMaster_out.tKeep); + anlysr_dataIn(95)<='1' when axiMaster_out.tLast else '0'; + anlysr_dataIn(96)<='1' when writeRequest.trigger else '0'; + anlysr_dataIn(97)<='1' when writeResponse.trigger else '0'; + anlysr_dataIn(99 downto 98)<=to_std_logic_vector(dbg_axiTxFSM); + anlysr_dataIn(101 downto 98)<=std_logic_vector(porCnt); +-- anlysr_dataIn(102)<='1' when locked else '0'; +-- anlysr_dataIn(102)<=locked; + + anlysr_dataIn(anlysr_dataIn'high downto 102)<=(others=>'0'); + + + /* Simulate only if you have compiled Altera's simulation libraries. */ +/* i_bist_logicAnalyser: entity altera.stp(syn) port map( + acq_clk=>testerClk, + acq_data_in=>anlysr_dataIn, + acq_trigger_in=>"1", + trigger_in=>anlysr_trigger + ); +*/ + + + /* Stimuli sequencer. TODO move to tester/stimuli. + This emulates the AXI4-Stream Slave. + */ + /* Simulation-only stimuli sequencer. */ + /* synthesis translate_off */ + process is begin + report "Performing fast read..." severity note; + + /* Fast read. */ + while not axiMaster_out.tLast loop + /* Wait for tValid to assert. */ + while not axiMaster_out.tValid loop + wait until falling_edge(clk); + end loop; + + axiMaster_in.tReady<=true; + + wait until falling_edge(clk); + axiMaster_in.tReady<=false; + end loop; + + wait until falling_edge(clk); + report "Performing normal read..." severity note; + + /* Normal read. */ + while not axiMaster_out.tLast loop + /* Wait for tValid to assert. */ + while not axiMaster_out.tValid loop + wait until falling_edge(clk); + end loop; + + wait until falling_edge(clk); + wait until falling_edge(clk); + axiMaster_in.tReady<=true; + + wait until falling_edge(clk); + axiMaster_in.tReady<=false; + + wait until falling_edge(clk); + end loop; + + report "Completed normal read." severity note; + + for i in 0 to 10 loop + wait until falling_edge(clk); + end loop; + + /* One-shot read. */ + axiMaster_in.tReady<=true; + + wait until falling_edge(clk); + axiMaster_in.tReady<=false; + + report "Completed one-shot read." severity note; + + wait; + end process; + /* synthesis translate_on */ + + /* Synthesisable stimuli sequencer. */ +/* process(clk) is begin + if falling_edge(clk) then + axiMaster_in.tReady<=false; + --if axiMaster_out.tValid and not axiMaster_out.tLast then + if not axiMaster_in.tReady and axiMaster_out.tValid and not axiMaster_out.tLast then + axiMaster_in.tReady<=true; + end if; + end if; + end process; +*/ + + /* Data transmitter. */ + i_prbs: entity tauhop.prbs31(rtl) + generic map( + isParallelLoad=>true, + tapVector=>( + /* Example polynomial from Wikipedia: + http://en.wikipedia.org/wiki/Computation_of_cyclic_redundancy_checks + */ + 0|3|31=>true, 1|2|30 downto 4=>false + ) + ) + port map( + /* Comment-out for simulation. */ + clk=>irq_write, reset=>reset, + en=>trigger, + seed=>32x"ace1", --9x"57", + prbs=>prbs + ); + + sequencer_ns: process(all) is begin + txFSM<=i_txFSM; + if reset then txFSM<=idle; + else + case i_txFSM is + when idle=> + if outstandingTransactions>0 then txFSM<=transmitting; end if; + when transmitting=> + if axiMaster_out.tLast then + txFSM<=idle; + end if; + when others=> null; + end case; + end if; + end process sequencer_ns; + + sequencer_op: process(reset,irq_write) is + /* Local procedures to map BFM signals with the package procedure. */ + procedure read(address:in t_addr) is begin + read(readRequest,address); + end procedure read; + + procedure write(data:in t_msg) is begin + write(request=>writeRequest, address=>(others=>'-'), data=>data); + end procedure write; + + variable isPktError:boolean; + + /* Tester variables. */ + /* Synthesis-only randomisation. */ + + /* Simulation-only randomisation. */ + /* synthesis translate_off */ + variable rv0:RandomPType; + /* synthesis translate_on */ + +-- variable trigger:boolean; + begin +-- if reset then + /* simulation only. */ + /* synthesis translate_off */ +-- rv0.InitSeed(rv0'instance_name); + /* synthesis translate_on */ + if falling_edge(irq_write) then + case txFSM is + when transmitting=> + if trigger then + /* Pseudorandom stimuli generation using OS-VVM. */ + /* synthesis translate_off */ + write(rv0.RandSigned(axiMaster_out.tData'length)); + /* synthesis translate_on */ + + /* Pseudorandom stimuli generation using LFSR. */ + /* + case selTxn is + when x"1"=> write(32x"12ab34cd"); + when x"2"=> write(32x"12345678"); + when x"3"=> write(32x"87654321"); + when x"4"=> write(32x"abcd1234"); + when others=> write(prbs); + end case; + */ + end if; + when others=>null; + end case; + end if; + end process sequencer_op; + + sequencer_regs: process(irq_write) is begin + if falling_edge(irq_write) then + i_txFSM<=txFSM; + end if; + end process sequencer_regs; + + /* Transaction counter. */ + process(reset,symbolsPerTransfer,irq_write) is begin + /* TODO close timing for asynchronous reset. */ + if reset then outstandingTransactions<=symbolsPerTransfer; + elsif rising_edge(irq_write) then + if not axiMaster_out.tLast then + if outstandingTransactions<1 then + outstandingTransactions<=symbolsPerTransfer; + report "No more pending transactions." severity note; + elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1; + end if; + end if; + + /* Use synchronous reset for outstandingTransactions to meet timing because it is a huge register set. */ + if reset then outstandingTransactions<=symbolsPerTransfer; end if; + end if; + end process; + + /* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */ + process(reset,irq_write) is + /* synthesis translate_off */ + variable rv0:RandomPType; + /* synthesis translate_on */ + begin + if reset then + /* synthesis translate_off */ + rv0.InitSeed(rv0'instance_name); + symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8); + report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note; + /* synthesis translate_on */ + + symbolsPerTransfer<=128x"fc"; + elsif rising_edge(irq_write) then + if axiMaster_out.tLast then + /* synthesis only. */ + /* Testcase 1: number of symbols per transfer becomes 0 after first stream transfer. */ + --symbolsPerTransfer<=(others=>'0'); + + /* Testcase 2: number of symbols per transfer is randomised. */ + --uniform(seed0,seed1,rand0); + --symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8); --symbolsPerTransfer'length + --report "symbols per transfer = " & ieee.numeric_std.to_hstring(to_unsigned(integer(rand0 * 2.0**8),8)); --axiMaster_out.tData'length)); + + + /* synthesis translate_off */ + symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8); + report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note; + /* synthesis translate_on */ + + symbolsPerTransfer<=128x"0f"; --128x"ffffffff_ffffffff_ffffffff_ffffffff"; + end if; + end if; + end process; + +-- outstandingTransactions<=128x"fc"; --symbolsPerTransfer; +end architecture rtl;
axi4_tlm_bfm/trunk/tester/tester.vhdl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: axi4_tlm_bfm/trunk/tester/stimuli/prbs-31.vhdl =================================================================== --- axi4_tlm_bfm/trunk/tester/stimuli/prbs-31.vhdl (nonexistent) +++ axi4_tlm_bfm/trunk/tester/stimuli/prbs-31.vhdl (revision 24) @@ -0,0 +1,128 @@ +/* + This file is part of the Galois Linear Feedback Shift Register + (galois_lfsr) project: + http://www.opencores.org/project,galois_lfsr + + Description + Synthesisable use case for Galois LFSR. + This example is a CRC generator that uses a Galois LFSR. + + ToDo: + + Author(s): + - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com + + Copyright (C) 2012-2013 Authors and OPENCORES.ORG + + This source file may be used and distributed without + restriction provided that this copyright statement is not + removed from the file and that any derivative work contains + the original copyright notice and the associated disclaimer. + + This source file is free software; you can redistribute it + and/or modify it under the terms of the GNU Lesser General + Public License as published by the Free Software Foundation; + either version 2.1 of the License, or (at your option) any + later version. + + This source is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + PURPOSE. See the GNU Lesser General Public License for more + details. + + You should have received a copy of the GNU Lesser General + Public License along with this source; if not, download it + from http://www.opencores.org/lgpl.shtml. +*/ +library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all; +/* Enable for synthesis; comment out for simulation. + For this design, we just need boolean_vector. This is already included in Questa/ModelSim, + but Quartus doesn't yet support this. +*/ +library tauhop; use tauhop.types.all, tauhop.axiTransactor.all; + +entity prbs31 is + generic( + isParallelLoad:boolean:=false; + tapVector:boolean_vector:=( + /* Example polynomial from Wikipedia: + http://en.wikipedia.org/wiki/Computation_of_cyclic_redundancy_checks + */ + --0|1|2|8=>true, 7 downto 3=>false + 0|3|31=>true, 1|2|30 downto 4=>false + ) + ); + port( + /* Comment-out for simulation. */ + clk,reset:in std_ulogic; + en:in boolean; +-- seed:in unsigned(tapVector'high downto 0); +-- prbs:out unsigned(31 downto 0):=(others=>'0') + seed:in i_transactor.t_msg; + prbs:out i_transactor.t_msg + ); +end entity prbs31; + +architecture rtl of prbs31 is + signal n,c:natural; + + /* Tester signals. */ + signal d:std_ulogic; + /* synthesis translate_off */ +-- signal clk,reset:std_ulogic:='0'; + /* synthesis translate_on */ + + signal loadEn:std_ulogic; -- clock gating. + signal load:boolean; +-- signal loadEn,computeClk:std_ulogic; -- clock gating. + signal loaded,i_loaded:boolean; +-- signal computed,i_computed:boolean; + +begin +-- loadEn<=clk when reset='0' and not i_computed else '0'; + loadEn<=clk when reset='0' and en else '0'; + + /* Galois LFSR instance. */ + i_lfsr: entity tauhop.lfsr(rtl) + generic map(taps=>tapVector) + /*generic map(taps => ( + 0|1|2|8=>true, + 7 downto 3=>false + ))*/ + port map(nReset=>not reset, clk=>loadEn, +-- load=>isParallelLoad, + load=>load, + seed=>seed, + d=>d, + q=>prbs(prbs'range) + ); + + /* Load message into LFSR. */ + process(reset,loadEn) is begin + if reset then loaded<=false; n<=seed'length-1; d<='0'; +-- if reset then loaded<=false; n<=seed'length-1; + elsif rising_edge(loadEn) then + d<='0'; + + /* for parallel mode, LFSR automatically loads the seed in parallel. */ + if isParallelLoad then loaded<=true; + else + if not loaded then d<=seed(n); end if; + + if n>0 then n<=n-1; + else loaded<=true; + end if; + end if; + end if; + end process; + + load<=(loaded xor i_loaded) and isParallelLoad and reset='0'; + + /* Register pipelines. */ + process(clk) is begin + if rising_edge(clk) then + i_loaded<=loaded; + end if; + end process; +end architecture rtl;
axi4_tlm_bfm/trunk/tester/stimuli/prbs-31.vhdl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: axi4_tlm_bfm/trunk/tester/stimuli/prbs-15.vhdl =================================================================== --- axi4_tlm_bfm/trunk/tester/stimuli/prbs-15.vhdl (nonexistent) +++ axi4_tlm_bfm/trunk/tester/stimuli/prbs-15.vhdl (revision 24) @@ -0,0 +1,117 @@ +/* + This file is part of the Galois Linear Feedback Shift Register + (galois_lfsr) project: + http://www.opencores.org/project,galois_lfsr + + Description + Synthesisable use case for Galois LFSR. + This example is a CRC generator that uses a Galois LFSR. + + ToDo: + + Author(s): + - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com + + Copyright (C) 2012-2013 Authors and OPENCORES.ORG + + This source file may be used and distributed without + restriction provided that this copyright statement is not + removed from the file and that any derivative work contains + the original copyright notice and the associated disclaimer. + + This source file is free software; you can redistribute it + and/or modify it under the terms of the GNU Lesser General + Public License as published by the Free Software Foundation; + either version 2.1 of the License, or (at your option) any + later version. + + This source is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + PURPOSE. See the GNU Lesser General Public License for more + details. + + You should have received a copy of the GNU Lesser General + Public License along with this source; if not, download it + from http://www.opencores.org/lgpl.shtml. +*/ +library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all; +/* Enable for synthesis; comment out for simulation. + For this design, we just need boolean_vector. This is already included in Questa/ModelSim, + but Quartus doesn't yet support this. +*/ +library tauhop; use tauhop.types.all; + +entity prbs15 is + generic( + parallelLoad:boolean:=false; + tapVector:boolean_vector:=( + /* Example polynomial from Wikipedia: + http://en.wikipedia.org/wiki/Computation_of_cyclic_redundancy_checks + */ + --0|1|2|8=>true, 7 downto 3=>false + 0|1|15=>true, 14 downto 2=>false + ) + ); + port( + /* Comment-out for simulation. */ + clk,reset:in std_ulogic; + seed:in unsigned(tapVector'high downto 0):=16x"ace1"; --9x"57"; + prbs:out unsigned(15 downto 0):=(others=>'0') + ); +end entity prbs15; + +architecture rtl of prbs15 is + signal n,c:natural; + + /* Tester signals. */ + signal d:std_ulogic; + /* synthesis translate_off */ +-- signal clk,reset:std_ulogic:='0'; + /* synthesis translate_on */ + + signal loadEn:std_ulogic; -- clock gating. +-- signal loadEn,computeClk:std_ulogic; -- clock gating. + signal loaded:boolean; +-- signal computed,i_computed:boolean; + +begin +-- loadEn<=clk when reset='0' and not i_computed else '0'; + loadEn<=clk when reset='0' else '0'; + + /* Galois LFSR instance. */ + i_lfsr: entity work.lfsr(rtl) + generic map(taps=>tapVector) + /*generic map(taps => ( + 0|1|2|8=>true, + 7 downto 3=>false + ))*/ + port map(nReset=>not reset, clk=>loadEn, + load=>parallelLoad, + seed=>seed, + d=>d, + q=>prbs(prbs'range) + ); + + /* Load message into LFSR. */ + process(reset,loadEn) is begin + if reset then loaded<=false; n<=seed'length-1; d<='0'; +-- if reset then loaded<=false; n<=seed'length-1; + elsif rising_edge(loadEn) then + d<='0'; + + /* for parallel mode, LFSR automatically loads the seed in parallel. */ + if parallelLoad then d<='0'; loaded<=true; +-- if parallelLoad then loaded<=true; + else + if not loaded then d<=seed(n); end if; + + if n>0 then n<=n-1; + else loaded<=true; + end if; + end if; + end if; + end process; + +-- d<=seed(n) when rising_edge(loadEn); +end architecture rtl;
axi4_tlm_bfm/trunk/tester/stimuli/prbs-15.vhdl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: axi4_tlm_bfm/trunk/tester/stimuli/galois-lfsr.vhdl =================================================================== --- axi4_tlm_bfm/trunk/tester/stimuli/galois-lfsr.vhdl (nonexistent) +++ axi4_tlm_bfm/trunk/tester/stimuli/galois-lfsr.vhdl (revision 24) @@ -0,0 +1,100 @@ +/* + This file is part of the Galois-type linear-feedback shift register + (galois_lfsr) project: + http://www.opencores.org/project,galois_lfsr + + Description + Synthesisable use case for Galois LFSR. + This example is a CRC generator that uses a Galois LFSR. + Example applications include: + * serial or parallel PRBS generation. + * CRC computation. + * digital scramblers/descramblers. + + ToDo: + + Author(s): + - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com + + Copyright (C) 2012-2013 Authors and OPENCORES.ORG + + This source file may be used and distributed without + restriction provided that this copyright statement is not + removed from the file and that any derivative work contains + the original copyright notice and the associated disclaimer. + + This source file is free software; you can redistribute it + and/or modify it under the terms of the GNU Lesser General + Public License as published by the Free Software Foundation; + either version 2.1 of the License, or (at your option) any + later version. + + This source is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + PURPOSE. See the GNU Lesser General Public License for more + details. + + You should have received a copy of the GNU Lesser General + Public License along with this source; if not, download it + from http://www.opencores.org/lgpl.shtml. +*/ +library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; +/* Enable for synthesis; comment out for simulation. + For this design, we just need boolean_vector. This is already included in Questa/ModelSim, + but Quartus doesn't yet support this. +*/ +library tauhop; use tauhop.types.all, tauhop.axiTransactor.all; + +entity lfsr is generic( + /* + * Tap vector: a TRUE means that position is tapped, otherwise that position is untapped. + */ + taps:boolean_vector + ); + + port(nReset,clk:in std_ulogic:='0'; + load:in boolean; +-- seed:in unsigned(taps'high downto 0); + seed:in i_transactor.t_msg; + + d:in std_ulogic; +-- q:out unsigned(taps'high downto 0) + q:out i_transactor.t_msg + ); +end entity lfsr; + +architecture rtl of lfsr is +-- signal i_d,i_q:unsigned(taps'high downto 0); +-- signal x:unsigned(taps'high-1 downto 0); + signal i_d,i_q:i_transactor.t_msg; + signal x:i_transactor.t_msg; + +begin +-- /* [begin]: Simulation testbench stimuli. Do not remove. +-- TODO migrate to separate testbench when more testcases are developed. +-- */ +-- /* synthesis translate_off */ +-- clk<=not clk after 1 ns; +-- /* synthesis translate_on */ +-- /* [end]: simulation stimuli. */ + + + /* Receives a vector of taps; generates LFSR structure with correct XOR positionings. */ + tapGenr: for i in 0 to taps'high-1 generate + i_d(i+1)<=x(i) when taps(i) else i_q(i); + x(i)<=i_q(i) xor i_q(taps'high); + end generate; + + process(nReset,load,seed,clk) is begin + if nReset='0' then i_q<=(others=>'0'); + elsif load then i_q<=seed; + elsif rising_edge(clk) then + i_q<=i_d; + end if; + end process; + + i_d(0)<=d; + q<=i_d; + +end architecture rtl;
axi4_tlm_bfm/trunk/tester/stimuli/galois-lfsr.vhdl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: axi4_tlm_bfm/trunk/workspace/quartus/axi4-tlm.qpf =================================================================== --- axi4_tlm_bfm/trunk/workspace/quartus/axi4-tlm.qpf (revision 23) +++ axi4_tlm_bfm/trunk/workspace/quartus/axi4-tlm.qpf (nonexistent) @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2012 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 32-bit -# Version 12.1 Build 177 11/07/2012 SJ Full Version -# Date created = 23:27:13 September 06, 2013 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "12.1" -DATE = "23:27:13 September 06, 2013" - -# Revisions - -PROJECT_REVISION = "axi4-tlm" Index: axi4_tlm_bfm/trunk/workspace/quartus/axi4-tlm.sdc =================================================================== --- axi4_tlm_bfm/trunk/workspace/quartus/axi4-tlm.sdc (revision 23) +++ axi4_tlm_bfm/trunk/workspace/quartus/axi4-tlm.sdc (nonexistent) @@ -1,13 +0,0 @@ -create_clock -period 100MHz -name clk [get_ports {clk}] -#derive_pll_clocks -create_base_clock -derive_clock_uncertainty - -set_false_path -from [get_keepers *por*] -to [get_keepers *por*] -set_false_path -from [get_keepers *reset*] - -#if {$::quartus(nameofexecutable) == "quartus_fit"} { -#set_max_delay -from *symbolsPerTransfer* -to *i1_outstandingTransactions* -10.000 -#set_min_delay -from *symbolsPerTransfer* -to *i1_outstandingTransactions* -10.000 - -##set_max_delay -to [get_clocks clk] 20 -#} Index: axi4_tlm_bfm/trunk/workspace/quartus/synthesise.sh =================================================================== --- axi4_tlm_bfm/trunk/workspace/quartus/synthesise.sh (revision 23) +++ axi4_tlm_bfm/trunk/workspace/quartus/synthesise.sh (nonexistent) @@ -1,50 +0,0 @@ -#!/bin/bash -# -# Example bash script for Quartus synthesis, place-and-route, and design -# assembly. -# -# Author(s): -# - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com -# -# Copyright (C) 2012-2013 Authors and OPENCORES.ORG -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# This notice and disclaimer must be retained as part of this text at all times. -# -# @dependencies: -# @designer: Daniel C.K. Kho [daniel.kho@gmail.com] | [daniel.kho@tauhop.com] -# @history: @see Mercurial log for full list of changes. -# -# @Description: -# - -quartus_sh --flow compile axi4-tlm; - -errorStr=`grep 'Error (' ./output_files/*.rpt` -if [ `echo ${#errorStr}` -gt 0 ] -then echo "Build error(s) exist. Refer to report files in the output_files directory for more details. Exiting."; exit; -else - echo $(date "+[%Y-%m-%d %H:%M:%S]: Configuring device..."); - quartus_pgm -c 'USB-Blaster [1-1.1]' -m jtag -o 'p;./output_files/axi4-tlm.sof'; - -fi - -errorStr=`grep 'Error (' ./output_files/*.rpt` -if [ `echo ${#errorStr}` -gt 0 ] -then echo "Configuration error(s) exist. Refer to report files in the output_files directory for more details. Exiting."; exit; -else - echo $(date "+[%Y-%m-%d %H:%M:%S]: Loading waveform session..."); - quartus_stpw ./waves.stp & -fi
axi4_tlm_bfm/trunk/workspace/quartus/synthesise.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: axi4_tlm_bfm/trunk/workspace/quartus/axi4-tlm.qsf =================================================================== --- axi4_tlm_bfm/trunk/workspace/quartus/axi4-tlm.qsf (revision 23) +++ axi4_tlm_bfm/trunk/workspace/quartus/axi4-tlm.qsf (nonexistent) @@ -1,80 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2012 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 32-bit -# Version 12.1 Build 177 11/07/2012 SJ Full Version -# Date created = 23:27:13 September 06, 2013 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# axi4-tlm_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY "Cyclone IV E" -set_global_assignment -name DEVICE EP4CE22F17C7 -set_global_assignment -name TOP_LEVEL_ENTITY "user" -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:27:13 SEPTEMBER 06, 2013" -set_global_assignment -name LAST_QUARTUS_VERSION 12.1 -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation -set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF - -# NEEK kit: -#set_location_assignment PIN_M23 -to nReset -#set_location_assignment PIN_Y2 -to clk -# -# BeMicro kit: -set_location_assignment PIN_R7 -to reset -set_location_assignment PIN_E1 -to clk - - -set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - -set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-types.vhdl" -set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-tlm.vhdl" -set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-axi-tlm.vhdl" -set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl" -set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pll.vhd" -set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/stp.vhd" -set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/prbs-31.vhdl" -set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/galois-lfsr.vhdl" -set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/tester.vhdl" -set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/axi4-interface.vhdl" -#set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/user-hw-tlm-paper.vhdl" -set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/user.vhdl" - -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top Index: axi4_tlm_bfm/trunk/workspace/quartus/waves.stp =================================================================== --- axi4_tlm_bfm/trunk/workspace/quartus/waves.stp (revision 23) +++ axi4_tlm_bfm/trunk/workspace/quartus/waves.stp (nonexistent) @@ -1,986 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

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