OpenCores
URL https://opencores.org/ocsvn/wb4pb/wb4pb/trunk

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Rev 23 → Rev 24

/wb4pb/trunk/impl/avnet_sp3a_eval_gpio_vhd.xise
0,0 → 1,398
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
 
<header>
<!-- ISE source project file created by Project Navigator. -->
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<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
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<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
 
<version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/>
 
<files>
<file xil_pn:name="avnet_sp3a_eval_gpio.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="avnet_sp3a_eval_gpio_vhd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../rtl/wbs_gpio.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../rtl/kcpsm3.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../rtl/wbm_picoblaze.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../asm/PBWBGPIO.VHD" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
</files>
 
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<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s400a" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="avnet_sp3a_eval_gpio_vhd_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="avnet_sp3a_eval_gpio_vhd_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="avnet_sp3a_eval_gpio_vhd_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="avnet_sp3a_eval_gpio_vhd_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="avnet_sp3a_eval_gpio_vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="avnet_sp3a_eval_gpio_vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-03-19T14:22:30" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="B8418BCFDEB343439CF021473882CE0A" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
 
<bindings/>
 
<libraries/>
 
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
 
</project>
/wb4pb/trunk/impl/avnet_sp3a_eval_uart_vlog.v
0,0 → 1,203
////////////////////////////////////////////////////////////////////////////////
// This sourcecode is released under BSD license.
// Please see http://www.opensource.org/licenses/bsd-license.php for details!
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2011, Stefan Fischer <Ste.Fis@OpenCores.org>
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
// * Neither the name of the author nor the names of his contributors may be
// used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
////////////////////////////////////////////////////////////////////////////////
// filename: avnet_sp3a_eval_uart_vlog.v
// description: synthesizable PicoBlaze (TM) uart example using wishbone /
// AVNET (R) Sp3A-Eval-Kit version
// todo4user: add other modules as needed
// version: 0.0.0
// changelog: - 0.0.0, initial release
// - ...
////////////////////////////////////////////////////////////////////////////////
 
 
module avnet_sp3a_eval_uart_vlog (
FPGA_RESET,
CLK_16MHZ,
UART_TXD,
UART_RXD,
LED1
);
 
input FPGA_RESET;
wire FPGA_RESET;
input CLK_16MHZ;
wire CLK_16MHZ;
input UART_TXD;
wire UART_TXD;
output UART_RXD;
wire UART_RXD;
 
output LED1;
wire LED1;
 
reg rst;
wire clk;
wire wb_cyc;
wire wb_stb;
wire wb_we;
wire[7:0] wb_adr;
wire[7:0] wb_dat_m2s;
wire[7:0] wb_dat_s2m;
wire wb_ack;
wire pb_write_strobe;
wire pb_read_strobe;
wire[7:0] pb_port_id;
wire[7:0] pb_in_port;
wire[7:0] pb_out_port;
wire[17:0] instruction;
wire[9:0] address;
wire interrupt;
wire interrupt_ack;
reg[23:0] timer;
wire dcm_locked;
// 50 mhz clock generation
DCM_SP # (
.CLK_FEEDBACK("NONE"),
.CLKDV_DIVIDE(2.0),
.CLKFX_DIVIDE(8),
.CLKFX_MULTIPLY(25),
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(62.500),
.CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE")
)
DCM_SP_INST (
.CLKFB(1'B0),
.CLKIN(CLK_16MHZ),
.DSSEN(1'B0),
.PSCLK(1'B0),
.PSEN(1'B0),
.PSINCDEC(1'B0),
.RST(FPGA_RESET),
.CLKDV(),
.CLKFX(clk),
.CLKFX180(),
.CLK0(),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(dcm_locked),
.PSDONE(),
.STATUS()
);
// reset synchronisation
always@(clk)
rst <= ! dcm_locked;
// module instances
///////////////////
kcpsm3 inst_kcpsm3 (
.address(address),
.instruction(instruction),
.port_id(pb_port_id),
.write_strobe(pb_write_strobe),
.out_port(pb_out_port),
.read_strobe(pb_read_strobe),
.in_port(pb_in_port),
.interrupt(interrupt),
.interrupt_ack(interrupt_ack),
.reset(rst),
.clk(clk)
);
 
pbwbuart inst_pbwbuart (
.address(address),
.instruction(instruction),
.clk(clk)
);
 
wbm_picoblaze inst_wbm_picoblaze (
.rst(rst),
.clk(clk),
.wbm_cyc_o(wb_cyc),
.wbm_stb_o(wb_stb),
.wbm_we_o(wb_we),
.wbm_adr_o(wb_adr),
.wbm_dat_m2s_o(wb_dat_m2s),
.wbm_dat_s2m_i(wb_dat_s2m),
.wbm_ack_i(wb_ack),
.pb_port_id_i(pb_port_id),
.pb_write_strobe_i(pb_write_strobe),
.pb_out_port_i(pb_out_port),
.pb_read_strobe_i(pb_read_strobe),
.pb_in_port_o(pb_in_port)
);
 
wbs_uart inst_wbs_uart (
.rst(rst),
.clk(clk),
.wbs_cyc_i(wb_cyc),
.wbs_stb_i(wb_stb),
.wbs_we_i(wb_we),
.wbs_adr_i(wb_adr),
.wbs_dat_m2s_i(wb_dat_m2s),
.wbs_dat_s2m_o(wb_dat_s2m),
.wbs_ack_o(wb_ack),
.uart_rx_si_i(UART_TXD),
.uart_tx_so_o(UART_RXD)
);
assign LED1 = timer[23];
always@(posedge clk) begin : led_blinker
timer <= timer + 1;
if (rst)
timer <= {24{1'b0}};
end
endmodule
/wb4pb/trunk/impl/avnet_sp3a_eval_uart.ucf
0,0 → 1,26
INST DCM_SP_INST CLK_FEEDBACK = NONE;
INST DCM_SP_INST CLKDV_DIVIDE = 2.0;
INST DCM_SP_INST CLKFX_DIVIDE = 8;
INST DCM_SP_INST CLKFX_MULTIPLY = 25;
INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE;
INST DCM_SP_INST CLKIN_PERIOD = 62.500;
INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE;
INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW;
INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW;
INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE;
INST DCM_SP_INST FACTORY_JF = C080;
INST DCM_SP_INST PHASE_SHIFT = 0;
INST DCM_SP_INST STARTUP_WAIT = FALSE;
 
NET CLK_16MHZ TNM_NET = CLK_16MHZ;
TIMESPEC TS_CLK_16MHZ = PERIOD CLK_16MHZ 62.50 ns;
 
NET CLK_16MHZ LOC = C10 | IOSTANDARD = LVCMOS33 ;
 
NET FPGA_RESET LOC = H4 | IOSTANDARD = LVCMOS33 ;
 
NET LED1 LOC = D14 | IOSTANDARD = LVCMOS33 ;
 
NET UART_RXD LOC = B3 | IOSTANDARD = LVCMOS33 ;
NET UART_TXD LOC = A3 | IOSTANDARD = LVCMOS33 ;
/wb4pb/trunk/impl/avnet_sp3a_eval_gpio_vlog.v
0,0 → 1,193
////////////////////////////////////////////////////////////////////////////////
// This sourcecode is released under BSD license.
// Please see http://www.opensource.org/licenses/bsd-license.php for details!
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2011, Stefan Fischer <Ste.Fis@OpenCores.org>
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
// * Neither the name of the author nor the names of his contributors may be
// used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
////////////////////////////////////////////////////////////////////////////////
// filename: avnet_sp3a_eval_gpio_vlog.v
// description: synthesizable PicoBlaze (TM) general purpose i/o example using
// wishbone / AVNET (R) Sp3A-Eval-Kit version
// todo4user: add other modules as needed
// version: 0.0.0
// changelog: - 0.0.0, initial release
// - ...
////////////////////////////////////////////////////////////////////////////////
 
 
module avnet_sp3a_eval_gpio_vlog (
FPGA_RESET,
CLK_16MHZ,
FPGA_PUSH_A,
FPGA_PUSH_B,
FPGA_PUSH_C,
LED1,
LED2,
LED3,
LED4
);
 
input FPGA_RESET;
wire FPGA_RESET;
input CLK_16MHZ;
wire CLK_16MHZ;
input FPGA_PUSH_A;
wire FPGA_PUSH_A;
input FPGA_PUSH_B;
wire FPGA_PUSH_B;
input FPGA_PUSH_C;
wire FPGA_PUSH_C;
output LED1;
wire LED1;
output LED2;
wire LED2;
output LED3;
wire LED3;
output LED4;
wire LED4;
reg rst;
wire clk;
wire wb_cyc;
wire wb_stb;
wire wb_we;
wire[7:0] wb_adr;
wire[7:0] wb_dat_m2s;
wire[7:0] wb_dat_s2m;
wire wb_ack;
wire pb_write_strobe;
wire pb_read_strobe;
wire[7:0] pb_port_id;
wire[7:0] pb_in_port;
wire[7:0] pb_out_port;
wire[17:0] instruction;
wire[9:0] address;
wire interrupt;
wire interrupt_ack;
wire[7:0] gpio_in;
wire[7:0] gpio_out;
wire[7:0] gpio_oe;
reg[23:0] timer;
// reset synchronisation
always@(clk)
rst <= FPGA_RESET;
assign clk = CLK_16MHZ;
// module instances
///////////////////
kcpsm3 inst_kcpsm3 (
.address(address),
.instruction(instruction),
.port_id(pb_port_id),
.write_strobe(pb_write_strobe),
.out_port(pb_out_port),
.read_strobe(pb_read_strobe),
.in_port(pb_in_port),
.interrupt(interrupt),
.interrupt_ack(interrupt_ack),
.reset(rst),
.clk(clk)
);
 
pbwbgpio inst_pbwbgpio (
.address(address),
.instruction(instruction),
.clk(clk)
);
 
wbm_picoblaze inst_wbm_picoblaze (
.rst(rst),
.clk(clk),
.wbm_cyc_o(wb_cyc),
.wbm_stb_o(wb_stb),
.wbm_we_o(wb_we),
.wbm_adr_o(wb_adr),
.wbm_dat_m2s_o(wb_dat_m2s),
.wbm_dat_s2m_i(wb_dat_s2m),
.wbm_ack_i(wb_ack),
.pb_port_id_i(pb_port_id),
.pb_write_strobe_i(pb_write_strobe),
.pb_out_port_i(pb_out_port),
.pb_read_strobe_i(pb_read_strobe),
.pb_in_port_o(pb_in_port)
);
 
wbs_gpio inst_wbs_gpio (
.rst(rst),
.clk(clk),
.wbs_cyc_i(wb_cyc),
.wbs_stb_i(wb_stb),
.wbs_we_i(wb_we),
.wbs_adr_i(wb_adr),
.wbs_dat_m2s_i(wb_dat_m2s),
.wbs_dat_s2m_o(wb_dat_s2m),
.wbs_ack_o(wb_ack),
.gpio_in_i(gpio_in),
.gpio_out_o(gpio_out),
.gpio_oe_o(gpio_oe)
);
// i/o buffer generation
assign gpio_in = {
1'b0,
FPGA_PUSH_C,
FPGA_PUSH_B,
FPGA_PUSH_A,
{4{1'b0}}
};
assign LED1 = gpio_out[0];
assign LED2 = gpio_out[1];
assign LED3 = gpio_out[2];
assign LED4 = timer[23];
always@(posedge clk) begin : led_blinker
timer <= timer + 1;
if (rst)
timer <= {24{1'b0}};
end
endmodule
/wb4pb/trunk/impl/avnet_sp3a_eval_uart_vhd.bit Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/wb4pb/trunk/impl/avnet_sp3a_eval_uart_vhd.bit
wb4pb/trunk/impl/avnet_sp3a_eval_uart_vhd.bit Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: wb4pb/trunk/impl/avnet_sp3a_eval_uart_vlog.xise =================================================================== --- wb4pb/trunk/impl/avnet_sp3a_eval_uart_vlog.xise (nonexistent) +++ wb4pb/trunk/impl/avnet_sp3a_eval_uart_vlog.xise (revision 24) @@ -0,0 +1,381 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: wb4pb/trunk/impl/avnet_sp3a_eval_gpio.ucf =================================================================== --- wb4pb/trunk/impl/avnet_sp3a_eval_gpio.ucf (nonexistent) +++ wb4pb/trunk/impl/avnet_sp3a_eval_gpio.ucf (revision 24) @@ -0,0 +1,14 @@ +NET CLK_16MHZ TNM_NET = CLK_16MHZ; +TIMESPEC TS_CLK_16MHZ = PERIOD CLK_16MHZ 62.50 ns; + +NET CLK_16MHZ LOC = C10 | IOSTANDARD = LVCMOS33 ; + +NET FPGA_RESET LOC = H4 | IOSTANDARD = LVCMOS33 ; +NET FPGA_PUSH_A LOC = K3 | IOSTANDARD = LVCMOS33 ; +NET FPGA_PUSH_B LOC = H5 | IOSTANDARD = LVCMOS33 ; +NET FPGA_PUSH_C LOC = L3 | IOSTANDARD = LVCMOS33 ; + +NET LED1 LOC = D14 | IOSTANDARD = LVCMOS33 ; +NET LED2 LOC = C16 | IOSTANDARD = LVCMOS33 ; +NET LED3 LOC = C15 | IOSTANDARD = LVCMOS33 ; +NET LED4 LOC = B15 | IOSTANDARD = LVCMOS33 ; Index: wb4pb/trunk/impl/avnet_sp3a_eval_gpio_vhd.bit =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: wb4pb/trunk/impl/avnet_sp3a_eval_gpio_vhd.bit =================================================================== --- wb4pb/trunk/impl/avnet_sp3a_eval_gpio_vhd.bit (nonexistent) +++ wb4pb/trunk/impl/avnet_sp3a_eval_gpio_vhd.bit (revision 24)
wb4pb/trunk/impl/avnet_sp3a_eval_gpio_vhd.bit Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: wb4pb/trunk/impl/avnet_sp3a_eval_gpio_vlog.xise =================================================================== --- wb4pb/trunk/impl/avnet_sp3a_eval_gpio_vlog.xise (nonexistent) +++ wb4pb/trunk/impl/avnet_sp3a_eval_gpio_vlog.xise (revision 24) @@ -0,0 +1,360 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: wb4pb/trunk/impl/avnet_sp3a_eval_uart_vhd.vhd =================================================================== --- wb4pb/trunk/impl/avnet_sp3a_eval_uart_vhd.vhd (nonexistent) +++ wb4pb/trunk/impl/avnet_sp3a_eval_uart_vhd.vhd (revision 24) @@ -0,0 +1,290 @@ +-------------------------------------------------------------------------------- +-- This sourcecode is released under BSD license. +-- Please see http://www.opensource.org/licenses/bsd-license.php for details! +-------------------------------------------------------------------------------- +-- +-- Copyright (c) 2011, Stefan Fischer +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- * Neither the name of the author nor the names of his contributors may be +-- used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-------------------------------------------------------------------------------- +-- filename: avnet_sp3a_eval_uart_vhd.vhd +-- description: synthesizable PicoBlaze (TM) uart example using wishbone / +-- AVNET (R) Sp3A-Eval-Kit version +-- todo4user: add other modules as needed +-- version: 0.0.0 +-- changelog: - 0.0.0, initial release +-- - ... +-------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library unisim; +use unisim.vcomponents.all; + + +entity avnet_sp3a_eval_uart_vhd is + port + ( + FPGA_RESET : in std_logic; + CLK_16MHZ : in std_logic; + + UART_TXD : in std_logic; + UART_RXD : out std_logic; + + LED1 : out std_logic + ); +end avnet_sp3a_eval_uart_vhd; + + +architecture rtl of avnet_sp3a_eval_uart_vhd is + + component kcpsm3 is + port + ( + address : out std_logic_vector(9 downto 0); + instruction : in std_logic_vector(17 downto 0); + port_id : out std_logic_vector(7 downto 0); + write_strobe : out std_logic; + out_port : out std_logic_vector(7 downto 0); + read_strobe : out std_logic; + in_port : in std_logic_vector(7 downto 0); + interrupt : in std_logic; + interrupt_ack : out std_logic; + reset : in std_logic; + clk : in std_logic + ); + end component; + + component pbwbuart is + port + ( + address : in std_logic_vector(9 downto 0); + instruction : out std_logic_vector(17 downto 0); + clk : in std_logic + ); + end component; + + component wbm_picoblaze is + port + ( + rst : in std_logic; + clk : in std_logic; + + wbm_cyc_o : out std_logic; + wbm_stb_o : out std_logic; + wbm_we_o : out std_logic; + wbm_adr_o : out std_logic_vector(7 downto 0); + wbm_dat_m2s_o : out std_logic_vector(7 downto 0); + wbm_dat_s2m_i : in std_logic_vector(7 downto 0); + wbm_ack_i : in std_logic; + + pb_port_id_i : in std_logic_vector(7 downto 0); + pb_write_strobe_i : in std_logic; + pb_out_port_i : in std_logic_vector(7 downto 0); + pb_read_strobe_i : in std_logic; + pb_in_port_o : out std_logic_vector(7 downto 0) + ); + end component; + + component wbs_uart is + port + ( + rst : in std_logic; + clk : in std_logic; + + wbs_cyc_i : in std_logic; + wbs_stb_i : in std_logic; + wbs_we_i : in std_logic; + wbs_adr_i : in std_logic_vector(7 downto 0); + wbs_dat_m2s_i : in std_logic_vector(7 downto 0); + wbs_dat_s2m_o : out std_logic_vector(7 downto 0); + wbs_ack_o : out std_logic; + + uart_rx_si_i : in std_logic; + uart_tx_so_o : out std_logic + ); + end component; + + signal rst : std_logic := '1'; + signal clk : std_logic := '1'; + + signal wb_cyc : std_logic := '0'; + signal wb_stb : std_logic := '0'; + signal wb_we : std_logic := '0'; + signal wb_adr : std_logic_vector(7 downto 0) := (others => '0'); + signal wb_dat_m2s : std_logic_vector(7 downto 0) := (others => '0'); + signal wb_dat_s2m : std_logic_vector(7 downto 0) := (others => '0'); + signal wb_ack : std_logic := '0'; + + signal pb_write_strobe : std_logic := '0'; + signal pb_read_strobe : std_logic := '0'; + signal pb_port_id : std_logic_vector(7 downto 0) := (others => '0'); + signal pb_in_port : std_logic_vector(7 downto 0) := (others => '0'); + signal pb_out_port : std_logic_vector(7 downto 0) := (others => '0'); + + signal instruction : std_logic_vector(17 downto 0) := (others => '0'); + signal address : std_logic_vector(9 downto 0) := (others => '0'); + + signal interrupt : std_logic := '0'; + signal interrupt_ack : std_logic := '0'; + + signal timer : unsigned(23 downto 0) := (others => '0'); + + signal dcm_locked : std_logic := '0'; + +begin + + -- 50 mhz clock generation + DCM_SP_INST : DCM_SP + generic map + ( + CLK_FEEDBACK => "NONE", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 8, + CLKFX_MULTIPLY => 25, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 62.500, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE + ) + port map + ( + CLKFB => '0', + CLKIN => CLK_16MHZ, + DSSEN => '0', + PSCLK => '0', + PSEN => '0', + PSINCDEC => '0', + RST => FPGA_RESET, + CLKDV => open, + CLKFX => clk, + CLKFX180 => open, + CLK0 => open, + CLK2X => open, + CLK2X180 => open, + CLK90 => open, + CLK180 => open, + CLK270 => open, + LOCKED => dcm_locked, + PSDONE => open, + STATUS => open + ); + + -- reset synchronisation + process(clk) + begin + rst <= not dcm_locked; + end process; + + -- module instances + ------------------- + + inst_kcpsm3 : kcpsm3 + port map + ( + address => address, + instruction => instruction, + port_id => pb_port_id, + write_strobe => pb_write_strobe, + out_port => pb_out_port, + read_strobe => pb_read_strobe, + in_port => pb_in_port, + interrupt => interrupt, + interrupt_ack => interrupt_ack, + reset => rst, + clk => clk + ); + + inst_pbwbuart : pbwbuart + port map + ( + address => address, + instruction => instruction, + clk => clk + ); + + inst_wbm_picoblaze : wbm_picoblaze + port map + ( + rst => rst, + clk => clk, + + wbm_cyc_o => wb_cyc, + wbm_stb_o => wb_stb, + wbm_we_o => wb_we, + wbm_adr_o => wb_adr, + wbm_dat_m2s_o => wb_dat_m2s, + wbm_dat_s2m_i => wb_dat_s2m, + wbm_ack_i => wb_ack, + + pb_port_id_i => pb_port_id, + pb_write_strobe_i => pb_write_strobe, + pb_out_port_i => pb_out_port, + pb_read_strobe_i => pb_read_strobe, + pb_in_port_o => pb_in_port + ); + + inst_wbs_uart : wbs_uart + port map + ( + rst => rst, + clk => clk, + + wbs_cyc_i => wb_cyc, + wbs_stb_i => wb_stb, + wbs_we_i => wb_we, + wbs_adr_i => wb_adr, + wbs_dat_m2s_i => wb_dat_m2s, + wbs_dat_s2m_o => wb_dat_s2m, + wbs_ack_o => wb_ack, + + uart_rx_si_i => UART_TXD, + uart_tx_so_o => UART_RXD + ); + + LED1 <= timer(23); + + led_blinker : process(clk) + begin + if rising_edge(clk) then + timer <= timer + 1; + if rst = '1' then + timer <= (others => '0'); + end if; + end if; + end process; + +end rtl; \ No newline at end of file Index: wb4pb/trunk/impl/avnet_sp3a_eval_gpio_vhd.vhd =================================================================== --- wb4pb/trunk/impl/avnet_sp3a_eval_gpio_vhd.vhd (nonexistent) +++ wb4pb/trunk/impl/avnet_sp3a_eval_gpio_vhd.vhd (revision 24) @@ -0,0 +1,266 @@ +-------------------------------------------------------------------------------- +-- This sourcecode is released under BSD license. +-- Please see http://www.opensource.org/licenses/bsd-license.php for details! +-------------------------------------------------------------------------------- +-- +-- Copyright (c) 2011, Stefan Fischer +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- * Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- * Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- * Neither the name of the author nor the names of his contributors may be +-- used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-------------------------------------------------------------------------------- +-- filename: avnet_sp3a_eval_gpio_vhd.vhd +-- description: synthesizable PicoBlaze (TM) general purpose i/o example using +-- wishbone / AVNET (R) Sp3A-Eval-Kit version +-- todo4user: add other modules as needed +-- version: 0.0.0 +-- changelog: - 0.0.0, initial release +-- - ... +-------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity avnet_sp3a_eval_gpio_vhd is + port + ( + FPGA_RESET : in std_logic; + CLK_16MHZ : in std_logic; + + FPGA_PUSH_A : in std_logic; + FPGA_PUSH_B : in std_logic; + FPGA_PUSH_C : in std_logic; + + LED1 : out std_logic; + LED2 : out std_logic; + LED3 : out std_logic; + LED4 : out std_logic + ); +end avnet_sp3a_eval_gpio_vhd; + + +architecture rtl of avnet_sp3a_eval_gpio_vhd is + + component kcpsm3 is + port + ( + address : out std_logic_vector(9 downto 0); + instruction : in std_logic_vector(17 downto 0); + port_id : out std_logic_vector(7 downto 0); + write_strobe : out std_logic; + out_port : out std_logic_vector(7 downto 0); + read_strobe : out std_logic; + in_port : in std_logic_vector(7 downto 0); + interrupt : in std_logic; + interrupt_ack : out std_logic; + reset : in std_logic; + clk : in std_logic + ); + end component; + + component pbwbgpio is + port + ( + address : in std_logic_vector(9 downto 0); + instruction : out std_logic_vector(17 downto 0); + clk : in std_logic + ); + end component; + + component wbm_picoblaze is + port + ( + rst : in std_logic; + clk : in std_logic; + + wbm_cyc_o : out std_logic; + wbm_stb_o : out std_logic; + wbm_we_o : out std_logic; + wbm_adr_o : out std_logic_vector(7 downto 0); + wbm_dat_m2s_o : out std_logic_vector(7 downto 0); + wbm_dat_s2m_i : in std_logic_vector(7 downto 0); + wbm_ack_i : in std_logic; + + pb_port_id_i : in std_logic_vector(7 downto 0); + pb_write_strobe_i : in std_logic; + pb_out_port_i : in std_logic_vector(7 downto 0); + pb_read_strobe_i : in std_logic; + pb_in_port_o : out std_logic_vector(7 downto 0) + ); + end component; + + component wbs_gpio is + port + ( + rst : in std_logic; + clk : in std_logic; + + wbs_cyc_i : in std_logic; + wbs_stb_i : in std_logic; + wbs_we_i : in std_logic; + wbs_adr_i : in std_logic_vector(7 downto 0); + wbs_dat_m2s_i : in std_logic_vector(7 downto 0); + wbs_dat_s2m_o : out std_logic_vector(7 downto 0); + wbs_ack_o : out std_logic; + + gpio_in_i : in std_logic_vector(7 downto 0); + gpio_out_o : out std_logic_vector(7 downto 0); + gpio_oe_o : out std_logic_vector(7 downto 0) + ); + end component; + + signal rst : std_logic := '1'; + signal clk : std_logic := '1'; + + signal wb_cyc : std_logic := '0'; + signal wb_stb : std_logic := '0'; + signal wb_we : std_logic := '0'; + signal wb_adr : std_logic_vector(7 downto 0) := (others => '0'); + signal wb_dat_m2s : std_logic_vector(7 downto 0) := (others => '0'); + signal wb_dat_s2m : std_logic_vector(7 downto 0) := (others => '0'); + signal wb_ack : std_logic := '0'; + + signal pb_write_strobe : std_logic := '0'; + signal pb_read_strobe : std_logic := '0'; + signal pb_port_id : std_logic_vector(7 downto 0) := (others => '0'); + signal pb_in_port : std_logic_vector(7 downto 0) := (others => '0'); + signal pb_out_port : std_logic_vector(7 downto 0) := (others => '0'); + + signal instruction : std_logic_vector(17 downto 0) := (others => '0'); + signal address : std_logic_vector(9 downto 0) := (others => '0'); + + signal interrupt : std_logic := '0'; + signal interrupt_ack : std_logic := '0'; + + signal gpio_in : std_logic_vector(7 downto 0) := (others => '0'); + signal gpio_out : std_logic_vector(7 downto 0) := (others => '0'); + signal gpio_oe : std_logic_vector(7 downto 0) := (others => '0'); + + signal timer : unsigned(23 downto 0) := (others => '0'); + +begin + + -- reset synchronisation + process(clk) + begin + rst <= FPGA_RESET; + end process; + clk <= CLK_16MHZ; + + -- module instances + ------------------- + + inst_kcpsm3 : kcpsm3 + port map + ( + address => address, + instruction => instruction, + port_id => pb_port_id, + write_strobe => pb_write_strobe, + out_port => pb_out_port, + read_strobe => pb_read_strobe, + in_port => pb_in_port, + interrupt => interrupt, + interrupt_ack => interrupt_ack, + reset => rst, + clk => clk + ); + + inst_pbwbgpio : pbwbgpio + port map + ( + address => address, + instruction => instruction, + clk => clk + ); + + inst_wbm_picoblaze : wbm_picoblaze + port map + ( + rst => rst, + clk => clk, + + wbm_cyc_o => wb_cyc, + wbm_stb_o => wb_stb, + wbm_we_o => wb_we, + wbm_adr_o => wb_adr, + wbm_dat_m2s_o => wb_dat_m2s, + wbm_dat_s2m_i => wb_dat_s2m, + wbm_ack_i => wb_ack, + + pb_port_id_i => pb_port_id, + pb_write_strobe_i => pb_write_strobe, + pb_out_port_i => pb_out_port, + pb_read_strobe_i => pb_read_strobe, + pb_in_port_o => pb_in_port + ); + + inst_wbs_gpio : wbs_gpio + port map + ( + rst => rst, + clk => clk, + + wbs_cyc_i => wb_cyc, + wbs_stb_i => wb_stb, + wbs_we_i => wb_we, + wbs_adr_i => wb_adr, + wbs_dat_m2s_i => wb_dat_m2s, + wbs_dat_s2m_o => wb_dat_s2m, + wbs_ack_o => wb_ack, + + gpio_in_i => gpio_in, + gpio_out_o => gpio_out, + gpio_oe_o => gpio_oe + ); + + -- i/o buffer generation + + gpio_in <= ( + 4 => FPGA_PUSH_A, + 5 => FPGA_PUSH_B, + 6 => FPGA_PUSH_C, + others => '0' + ); + + LED1 <= gpio_out(0); + LED2 <= gpio_out(1); + LED3 <= gpio_out(2); + LED4 <= timer(23); + + led_blinker : process(clk) + begin + if rising_edge(clk) then + timer <= timer + 1; + if rst = '1' then + timer <= (others => '0'); + end if; + end if; + end process; + +end rtl; Index: wb4pb/trunk/impl/avnet_sp3a_eval_uart_vlog.bit =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: wb4pb/trunk/impl/avnet_sp3a_eval_uart_vlog.bit =================================================================== --- wb4pb/trunk/impl/avnet_sp3a_eval_uart_vlog.bit (nonexistent) +++ wb4pb/trunk/impl/avnet_sp3a_eval_uart_vlog.bit (revision 24)
wb4pb/trunk/impl/avnet_sp3a_eval_uart_vlog.bit Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: wb4pb/trunk/impl/avnet_sp3a_eval_gpio_vlog.bit =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: wb4pb/trunk/impl/avnet_sp3a_eval_gpio_vlog.bit =================================================================== --- wb4pb/trunk/impl/avnet_sp3a_eval_gpio_vlog.bit (nonexistent) +++ wb4pb/trunk/impl/avnet_sp3a_eval_gpio_vlog.bit (revision 24)
wb4pb/trunk/impl/avnet_sp3a_eval_gpio_vlog.bit Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: wb4pb/trunk/impl/avnet_sp3a_eval_uart_vhd.xise =================================================================== --- wb4pb/trunk/impl/avnet_sp3a_eval_uart_vhd.xise (nonexistent) +++ wb4pb/trunk/impl/avnet_sp3a_eval_uart_vhd.xise (revision 24) @@ -0,0 +1,381 @@ + + + +
+ + + + + + + + +
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