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URL https://opencores.org/ocsvn/uart16750/uart16750/trunk

Subversion Repositories uart16750

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    from Rev 24 to Rev 25
    Reverse comparison

Rev 24 → Rev 25

/uart16750/trunk/bench/vhdl/uart_package.vhd
23,6 → 23,7
 
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
use std.textio.all;
 
use work.txt_util.all;
71,6 → 72,13
-- Compare two std_logig_vectors (handles don't-care)
function compare (d1 : std_logic_vector; d2 : std_logic_vector) return boolean;
 
-- Send serial data to UART
procedure uart_send (signal sout : out std_logic;
baud : in time;
wl : in integer;
count : in integer;
file log : TEXT
);
end uart_package;
 
package body uart_package is
132,5 → 140,37
return true;
end compare;
 
-- Send serial data to UART
procedure uart_send (signal sout : out std_logic;
baud : in time;
wl : in integer;
count : in integer;
file log : TEXT
) is
variable data : unsigned(7 downto 0);
begin
print (log, "UART send: Sending " & integer'image(count) & " symbols with " & integer'image(wl) & " bits");
 
data := (others => '0');
 
for i in 0 to count loop
 
-- Start bit
sout <= '0';
wait for baud;
 
for i in 0 to wl loop
sout <= data(i);
wait for baud;
end loop;
 
-- Stop bit
sout <= '1';
wait for baud;
 
data := data + 1;
end loop;
 
end uart_send;
end uart_package;
 
/uart16750/trunk/bench/vhdl/uart_transactor.vhd
29,8 → 29,8
 
entity uart_transactor is
generic (
stim_file : string := "uart_stim.dat"; -- Stimulus input file
log_file : string := "uart_log.txt" -- Log file
stim_file : string := "sim/uart_stim.dat"; -- Stimulus input file
log_file : string := "sim/uart_log.txt" -- Log file
);
end uart_transactor;
 
199,6 → 199,9
else
print (log, time'image(now) & ": " & "UART outputs: " & str(data(4 downto 0)));
end if;
elsif (s(1 to 4) = "#EUS") then -- Send serial data from external UART to DUT
uart_send (SOUT, 8.68 us, integer'value (s(6 to 7)), integer'value (s(9 to 11)), log);
--uart_send (SOUT, 3.33 ms, 8, integer'value (s(8 to 10)), log);
else
print ("Unknown command: " & s);
end if;
/uart16750/trunk/sim/rtl_sim/bin/uart_test_stim.pl
37,6 → 37,7
sub uart_write($$); # Address, Data
sub uart_read($$); # Address, Expected data
sub uart_setbaudrate($); # Baudrate
sub uart_eu_send($); # Send serial data from external UART
 
##################################################################
# Main process
800,8 → 801,6
if (TEST_AFC) {
uart_check_afc ();
}
 
logmessage ("UART: Test end");
 
##################################################################
# End main process
932,3 → 931,9
}
}
 
# Send serial data from external UART
sub uart_eu_send($)
{
printf ("#EUS 8 %d\n", $_[0]);
}
 

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