URL
https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk
Subversion Repositories versatile_fifo
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- This comparison shows the changes necessary to convert path
/
- from Rev 24 to Rev 25
- ↔ Reverse comparison
Rev 24 → Rev 25
/versatile_fifo/trunk/rtl/verilog/versatile_fifo_async_cmp.v
58,7 → 58,8
output fifo_full; |
input wclk, rclk, rst; |
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reg direction, direction_set, direction_clr; |
wire direction; |
reg direction_set, direction_clr; |
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wire async_empty, async_full; |
wire fifo_full2; |
/versatile_fifo/trunk/rtl/verilog/dff_sr.v
0,0 → 1,59
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Versatile counter //// |
//// //// |
//// Description //// |
//// Versatile counter, a reconfigurable binary, gray or LFSR //// |
//// counter //// |
//// //// |
//// To Do: //// |
//// - add LFSR with more taps //// |
//// //// |
//// Author(s): //// |
//// - Michael Unneback, unneback@opencores.org //// |
//// ORSoC AB //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
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module dff_sr ( aclr, aset, clock, data, q); |
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input aclr; |
input aset; |
input clock; |
input data; |
output reg q; |
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always @ (posedge clock or posedge aclr or posedge aset) |
if (aclr) |
q <= 1'b0; |
else if (aset) |
q <= 1'b1; |
else |
q <= data; |
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endmodule |