URL
https://opencores.org/ocsvn/ion/ion/trunk
Subversion Repositories ion
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- This comparison shows the changes necessary to convert path
/
- from Rev 241 to Rev 242
- ↔ Reverse comparison
Rev 241 → Rev 242
/ion/trunk/vhdl/SoC/mips_soc.vhdl
140,6 → 140,7
signal cpu_data_wr : t_word; |
signal cpu_byte_we : std_logic_vector(3 downto 0); |
signal cpu_mem_wait : std_logic; |
signal cpu_cache_ready : std_logic; |
signal cpu_ic_invalidate : std_logic; |
signal cpu_cache_enable : std_logic; |
signal unmapped_access : std_logic; |
196,6 → 197,7
byte_we => cpu_byte_we, |
|
mem_wait => cpu_mem_wait, |
cache_ready => cpu_cache_ready, |
cache_enable=> cpu_cache_enable, |
ic_invalidate=>cpu_ic_invalidate, |
|
225,6 → 227,7
data_wr => cpu_data_wr, |
|
mem_wait => cpu_mem_wait, |
cache_ready => cpu_cache_ready, |
cache_enable => cpu_cache_enable, |
ic_invalidate => cpu_ic_invalidate, |
unmapped => unmapped_access, |
/ion/trunk/vhdl/mips_cache.vhdl
206,6 → 206,7
data_wr : in std_logic_vector(31 downto 0); |
|
mem_wait : out std_logic; |
cache_ready : out std_logic; |
cache_enable : in std_logic; |
ic_invalidate : in std_logic; |
unmapped : out std_logic; |
260,6 → 261,7
-- State machine ---------------------------------------------------- |
|
type t_cache_state is ( |
cache_reset, -- Between reset and 1st code refill, |
idle, -- Cache is hitting, control machine idle |
|
-- Code refill -------------------------------------------------- |
389,6 → 391,7
-- '1' when the I-cache state machine stalls the pipeline (mem_wait) |
signal code_wait : std_logic; |
|
|
-- D-cache ---------------------------------------------------------- |
|
subtype t_data_tag is std_logic_vector(DATA_TAG_SIZE+1-1 downto 0); |
468,7 → 471,7
begin |
if clk'event and clk='1' then |
if reset='1' then |
ps <= idle; |
ps <= cache_reset; |
else |
ps <= ns; |
end if; |
485,7 → 488,13
write_pending, read_pending) |
begin |
case ps is |
when idle => |
|
-- The cache will remain in 'cache_reset' state until the first code miss, |
-- at which time the state machine proceeds as usual. |
-- The only difference between states idle and cache_reset is that in |
-- cache_reset the output cache_ready is '0', which will prevent the CPU |
-- from loading its IR with the cache output -- which is known invalid. |
when idle | cache_reset => |
if code_miss='1' then |
case code_rd_attr.mem_type is |
when MT_BRAM => ns <= code_refill_bram_0; |
1418,4 → 1427,11
read_pending or write_pending when others; |
|
|
-- The cache will be ready only after the first code refill. |
-- This will prevent the CPU from loading junk into the IR. |
with ps select cache_ready <= |
'0' when cache_reset, |
'1' when others; |
|
|
end architecture direct; |
/ion/trunk/vhdl/mips_cpu.vhdl
96,7 → 96,8
cache_enable : out std_logic; |
ic_invalidate : out std_logic; |
|
mem_wait : in std_logic |
mem_wait : in std_logic; |
cache_ready : in std_logic |
); |
end; --entity mips_cpu |
|
563,7 → 564,16
if reset='1' then |
p1_ir_reg <= (others => '0'); |
elsif stall_pipeline='0' then |
p1_ir_reg <= code_rd; |
-- Load the IR with whatever the cache is giving us, UNLESS the |
-- cache is not ready (has not yet completed the first code refill |
-- after reset), in which case... |
if cache_ready='1' then |
p1_ir_reg <= code_rd; |
else |
-- ... load the IR with something innocuous so that the |
-- instruction decoder does not derail. |
p1_ir_reg <= (others => '0'); |
end if; |
end if; |
end if; |
end process instruction_register; |