Subversion Repositories dmt_tx

/dmt_tx/trunk/myhdl/test/test_flipSign.py

dmt_tx/trunk/myhdl/test/test_flipSign.py Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: dmt_tx/trunk/myhdl/test/test_cmath.py =================================================================== --- dmt_tx/trunk/myhdl/test/test_cmath.py (nonexistent) +++ dmt_tx/trunk/myhdl/test/test_cmath.py (revision 27) @@ -0,0 +1,157 @@ + +import unittest + +from myhdl import * + + +from rtl.cmath import cadd, csub + +class TestCplxMath(unittest.TestCase): + + def test_cadd(self): + + def bench(): + width = 4 + m = 2**(width-1) + a_re, a_im, b_re, b_im, y_re, y_im = [ + Signal(intbv(0,min=-m, max=m)) for i in range(6)] + overflow = Signal(bool(0)) + + cadd_inst = cadd(a_re,a_im,b_re,b_im,y_re,y_im, overflow, width) + + @instance + def stimulus(): + a_im.next = 1 + b_re.next = 1 + b_im.next = 1 + overflow.next = False + + for ar in range(-m,m): + for br in range(-m,m): + a_re.next = ar + b_re.next = br + yield delay(10) + + yield delay(10) + + raise StopSimulation + + + @instance + def verify(): + yield delay(5) + + while True: + yre_exp = a_re + b_re + yim_exp = a_im + b_im + txt = "got: %s at: %d"%(overflow, now()) + if yre_exp >= m: + ovfl_re = True + yre_exp = m-1 + elif yre_exp < -m: + ovfl_re = True + yre_exp = -m + else: + ovfl_re = False + + self.assertEqual(y_re, yre_exp) + + if yim_exp >= m: + ovfl_im = True + yim_exp = m-1 + elif yim_exp < -m: + ovfl_im = True + yim_exp = -m + else: + ovfl_im = False + + self.assertEqual(y_im, yim_exp) + + ovfl_exp = ovfl_re or ovfl_im + + self.assertEqual(ovfl_exp, overflow, txt) + + yield delay(10) + + return instances() + + tb = bench() + #tb = traceSignals(bench) + sim = Simulation(tb) + sim.run() + + + def test_csub(self): + + def bench(): + width = 4 + m = 2**(width-1) + a_re, a_im, b_re, b_im, y_re, y_im = [ + Signal(intbv(0,min=-m, max=m)) for i in range(6)] + overflow = Signal(bool(0)) + + csub_inst = csub(a_re,a_im,b_re,b_im,y_re,y_im, overflow, width) + + @instance + def stimulus(): + a_im.next = 1 + b_im.next = 1 + overflow.next = False + + for ar in range(-m,m): + for br in range(-m,m): + a_re.next = ar + b_re.next = br + yield delay(10) + + yield delay(10) + + raise StopSimulation + + + @instance + def verify(): + yield delay(5) + + while True: + yre_exp = a_re - b_re + yim_exp = a_im - b_im + txt = "got: %s at: %d"%(overflow, now()) + if yre_exp >= m: + ovfl_re = True + yre_exp = m-1 + elif yre_exp < -m: + ovfl_re = True + yre_exp = -m + else: + ovfl_re = False + + self.assertEqual(y_re, yre_exp) + + if yim_exp >= m: + ovfl_im = True + yim_exp = m-1 + elif yim_exp < -m: + ovfl_im = True + yim_exp = -m + else: + ovfl_im = False + + self.assertEqual(y_im, yim_exp) + + ovfl_exp = ovfl_re or ovfl_im + + self.assertEqual(ovfl_exp, overflow, txt) + + yield delay(10) + + return instances() + + tb = bench() + #tb = traceSignals(bench) + sim = Simulation(tb) + sim.run() + + + def test_cmult(self): + pass Index: dmt_tx/trunk/myhdl/test/__init__.py =================================================================== Index: dmt_tx/trunk/myhdl/rtl/flipSign.py =================================================================== --- dmt_tx/trunk/myhdl/rtl/flipSign.py (nonexistent) +++ dmt_tx/trunk/myhdl/rtl/flipSign.py (revision 27) @@ -0,0 +1,36 @@ + +from myhdl import * + + +def flipSign(in_data, out_data, overflow, width): + '''Flip the sign of the input value. + The min value will cause an overflow and will be saturated to the max + value when flipping its sign + + I/O Signals + =========== + in_data : signal with the input data + out_data : signal having input data with flipped sign + overflow : signal whether an overflow occured. That only happens for + min value, as the max value = abs(min) - 1 + + Parameter + ========= + width : input width + ''' + + min = -2**(width-1) + max = 2**(width-1)-1 + + @always_comb + def rtl(): + + if in_data == min: + out_data.next = max + overflow.next = True + else: + out_data.next = -in_data + overflow.next = False + + return instances() + Index: dmt_tx/trunk/myhdl/rtl/cmath.py =================================================================== --- dmt_tx/trunk/myhdl/rtl/cmath.py (nonexistent) +++ dmt_tx/trunk/myhdl/rtl/cmath.py (revision 27) @@ -0,0 +1,91 @@ + +from myhdl import * + +def cadd(a_re, a_im, b_re, b_im, y_re, y_im, overflow, width=8): + '''Complex add + + I/O pins: + ========= + a : input a + b : input b + y : output a + b + overflow : signal overflow + + parameter: + ========== + width : data width for input and output + ''' + @always_comb + def logic(): + m = 2**(width-1) + + # + # Real value calculation + if (a_re + b_re) >= m: + y_re.next = m-1 + ovfl_re = True + + elif (a_re + b_re) < -m: + y_re.next = -m + ovfl_re = True + + else: + y_re.next = a_re + b_re + ovfl_re = False + + # + # Imaginary add + if (a_im + b_im) >= m: + y_im.next = m-1 + ovfl_im = True + + elif (a_im + b_im) < -m: + y_im.next = -m + ovfl_im = True + + else: + y_im.next = a_im + b_im + ovfl_im = False + + overflow.next = ovfl_re or ovfl_im + + return instances() + + +def csub(a_re, a_im, b_re, b_im, y_re, y_im, overflow, width=8): + + @always_comb + def logic(): + m = 2**(width-1) + + # + # Real value calculation + if (a_re - b_re) >= m: + y_re.next = m-1 + ovfl_re = True + + elif (a_re - b_re) < -m: + y_re.next = -m + ovfl_re = True + + else: + y_re.next = a_re - b_re + ovfl_re = False + + # + # Imaginary add + if (a_im - b_im) >= m: + y_im.next = m-1 + ovfl_im = True + + elif (a_im - b_im) < -m: + y_im.next = -m + ovfl_im = True + + else: + y_im.next = a_im - b_im + ovfl_im = False + + overflow.next = ovfl_re or ovfl_im + + return instances() Index: dmt_tx/trunk/myhdl/rtl/__init__.py =================================================================== Index: dmt_tx/trunk/myhdl/adsl_main.py =================================================================== --- dmt_tx/trunk/myhdl/adsl_main.py (nonexistent) +++ dmt_tx/trunk/myhdl/adsl_main.py (revision 27) @@ -0,0 +1,39 @@ +#!/usr/bin/env python + +######################################################################## +# +# Main program that runs all the test +# +# +# +# +######################################################################## + +import unittest + + +import test.test_flipSign, test.test_cmath + +mL = [test.test_flipSign] +mL.append(test.test_cmath) + +tl = unittest.defaultTestLoader +def suite(): + alltests = unittest.TestSuite() + for m in mL: + alltests.addTest(tl.loadTestsFromModule(m)) + return alltests + +def main(): + unittest.main(defaultTest='suite', + testRunner=unittest.TextTestRunner(verbosity=2)) + + + + + +######################################################################## +# main +# +if __name__ == '__main__': + main()

dmt_tx/trunk/myhdl/adsl_main.py Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property