/tags/STEP1_2b/doc/Multiprocessor interconnection based on DMA for FPGA.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/tags/STEP1_2b/doc/Multiprocessor interconnection based on DMA for FPGA.pdf

tags/STEP1_2b/doc/Multiprocessor interconnection based on DMA for FPGA.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/STEP1_2b/system.log =================================================================== --- tags/STEP1_2b/system.log (nonexistent) +++ tags/STEP1_2b/system.log (revision 27) @@ -0,0 +1,35 @@ +Xilinx Platform Studio (XPS) +Xilinx EDK 7.1.2 Build EDK_H.12.5.1 + +Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. + +At Local date and time: Mon Oct 23 18:18:40 2006 +Command xbash -q -c "cd /cygdrive/d/mpdma/; /usr/bin/make -f system.make clean; exit;" Started... +rm -f implementation/system.ngc +rm -f implementation/system.bmm +rm -f implementation/system.bit +rm -f implementation/system.ncd +rm -f implementation/system_bd.bmm +rm -rf implementation synthesis xst hdl +rm -rf xst.srp system.srp +rm -rf microblaze_0/lib/ +rm -rf microblaze_1/lib/ +rm -rf microblaze_2/lib/ +rm -rf microblaze_3/lib/ +rm -f mb-bmp2jpg/executable.elf +rm -f mb-dct/executable.elf +rm -f mb-vlc/executable.elf +rm -f mb-cc/executable.elf +rm -rf simulation/behavioral +rm -rf virtualplatform +rm -f _impact.cmd +Done. +No changes to be saved in XMP file +Xilinx Platform Studio (XPS) +Xilinx EDK 7.1.2 Build EDK_H.12.5.1 + +Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. + +No changes to be saved in XMP file +Project Opened. +No changes to be saved in XMP file Index: tags/STEP1_2b/system.mss =================================================================== --- tags/STEP1_2b/system.mss (nonexistent) +++ tags/STEP1_2b/system.mss (revision 27) @@ -0,0 +1,206 @@ + + PARAMETER VERSION = 2.2.0 + + +BEGIN OS + PARAMETER OS_NAME = standalone + PARAMETER OS_VER = 1.00.a + PARAMETER PROC_INSTANCE = microblaze_0 + PARAMETER STDIN = RS232_Uart_1 + PARAMETER STDOUT = RS232_Uart_1 +END + +BEGIN OS + PARAMETER OS_NAME = standalone + PARAMETER OS_VER = 1.00.a + PARAMETER PROC_INSTANCE = microblaze_2 +END + +BEGIN OS + PARAMETER OS_NAME = standalone + PARAMETER OS_VER = 1.00.a + PARAMETER PROC_INSTANCE = microblaze_3 +END + +BEGIN OS + PARAMETER OS_NAME = standalone + PARAMETER OS_VER = 1.00.a + PARAMETER PROC_INSTANCE = microblaze_1 +END + + +BEGIN PROCESSOR + PARAMETER DRIVER_NAME = cpu + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = microblaze_0 + PARAMETER COMPILER = mb-gcc + PARAMETER ARCHIVER = mb-ar + PARAMETER XMDSTUB_PERIPHERAL = debug_module +END + +BEGIN PROCESSOR + PARAMETER DRIVER_NAME = cpu + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = microblaze_2 + PARAMETER COMPILER = mb-gcc + PARAMETER ARCHIVER = mb-ar +END + +BEGIN PROCESSOR + PARAMETER DRIVER_NAME = cpu + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = microblaze_3 + PARAMETER COMPILER = mb-gcc + PARAMETER ARCHIVER = mb-ar +END + +BEGIN PROCESSOR + PARAMETER DRIVER_NAME = cpu + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = microblaze_1 + PARAMETER COMPILER = mb-gcc + PARAMETER ARCHIVER = mb-ar +END + + +BEGIN DRIVER + PARAMETER DRIVER_NAME = opbarb + PARAMETER DRIVER_VER = 1.02.a + PARAMETER HW_INSTANCE = mb_opb +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = uartlite + PARAMETER DRIVER_VER = 1.00.b + PARAMETER HW_INSTANCE = debug_module +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = bram + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = dlmb_cntlr0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = bram + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = ilmb_cntlr0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = uartlite + PARAMETER DRIVER_VER = 1.00.b + PARAMETER HW_INSTANCE = RS232_Uart_1 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = sysace + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = SysACE_CompactFlash +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = ddr + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = DDR_256MB_32MX64_rank1_row13_col10_cl2_5 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = sysclk_inv +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = clk90_inv +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = ddr_clk90_inv +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = dcm_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = dcm_1 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = bram + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = dlmb_cntlr2 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = bram + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = ilmb_cntlr2 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = fifo01 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = fifo23 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = bram + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = dlmb_cntlr3 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = bram + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = ilmb_cntlr3 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = fifo30 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = bram + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = dlmb_cntlr1 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = bram + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = ilmb_cntlr1 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = fifo12 +END + + +BEGIN LIBRARY + PARAMETER LIBRARY_NAME = xilfatfs + PARAMETER LIBRARY_VER = 1.00.a + PARAMETER CONFIG_WRITE = true + PARAMETER CONFIG_MAXFILES = 2 + PARAMETER CONFIG_BUFCACHE_SIZE = 2560 +END + Index: tags/STEP1_2b/system.xmp =================================================================== --- tags/STEP1_2b/system.xmp (nonexistent) +++ tags/STEP1_2b/system.xmp (revision 27) @@ -0,0 +1,150 @@ +#Please do not modify this file by hand +XmpVersion: 7.1 +IntStyle: default +ModuleSearchPath: D:/XilinxXUP/lib/ +MHS File: system.mhs +MSS File: system.mss +NPL File: projnav/system.ise +Architecture: virtex2p +Device: xc2vp30 +Package: ff896 +SpeedGrade: -7 +UseProjNav: 0 +AddToNPL: 0 +PNImportBitFile: +PNImportBmmFile: +UserCmd1: +UserCmd1Type: 0 +UserCmd2: +UserCmd2Type: 0 +SynProj: xst +ReloadPbde: 0 +MainMhsEditor: 0 +InsertNoPads: 0 +HdlLang: VHDL +Simulator: mti +SimModel: BEHAVIORAL +SimXLib: +SimEdkLib: +MixLangSim: 1 +UcfFile: data/system.ucf +Processor: microblaze_0 +BootLoop: 0 +XmdStub: 0 +Processor: microblaze_1 +BootLoop: 0 +XmdStub: 0 +Processor: microblaze_2 +BootLoop: 0 +XmdStub: 0 +Processor: microblaze_3 +BootLoop: 0 +XmdStub: 0 +SwProj: TestApp_Memory +Processor: microblaze_0 +Executable: TestApp_Memory/executable.elf +Source: TestApp_Memory/src/TestApp_Memory.c +DefaultInit: EXECUTABLE +InitBram: 1 +Active: 0 +CompilerOptLevel: 2 +GlobPtrOpt: 0 +DebugSym: 1 +AsmOpt: +LinkOpt: +ProgStart: +StackSize: +HeapSize: +LinkerScript: TestApp_Memory/src/TestApp_Memory_LinkScr +ProgCCFlags: +SwProj: mb-bmp2jpg +Processor: microblaze_0 +Executable: mb-bmp2jpg/executable.elf +Source: mb-bmp2jpg/bmp2jpg_mb.c +Source: mb-bmp2jpg/ColorConversion.c +Source: mb-bmp2jpg/dct.c +Source: mb-bmp2jpg/huffman.c +Source: mb-bmp2jpg/zzq.c +Header: mb-bmp2jpg/dct.h +Header: mb-bmp2jpg/ejpgl.h +Header: mb-bmp2jpg/huffman.h +Header: mb-bmp2jpg/io.h +Header: mb-bmp2jpg/mb.h +Header: mb-bmp2jpg/weights.h +Header: mb-bmp2jpg/zzq.h +DefaultInit: EXECUTABLE +InitBram: 1 +Active: 1 +CompilerOptLevel: 2 +GlobPtrOpt: 0 +DebugSym: 1 +AsmOpt: +LinkOpt: +ProgStart: +StackSize: +HeapSize: +LinkerScript: mb-bmp2jpg_linker_script +ProgCCFlags: -D__MICROBLAZE +SwProj: mb-dct +Processor: microblaze_2 +Executable: mb-dct/executable.elf +Source: mb-dct/mb-dct.c +Header: mb-dct/ejpgl.h +Header: mb-dct/fifo_link.h +Header: mb-dct/mb-dct.h +Header: mb-dct/mb-weights.h +DefaultInit: EXECUTABLE +InitBram: 1 +Active: 1 +CompilerOptLevel: 2 +GlobPtrOpt: 0 +DebugSym: 1 +AsmOpt: +LinkOpt: +ProgStart: +StackSize: +HeapSize: +LinkerScript: +ProgCCFlags: -D__MICROBLAZE +SwProj: mb-vlc +Processor: microblaze_3 +Executable: mb-vlc/executable.elf +Source: mb-vlc/mb-huffman.c +Source: mb-vlc/mb-zzq.c +Header: mb-vlc/ejpgl.h +Header: mb-vlc/fifo_link.h +Header: mb-vlc/mb-huffman.h +Header: mb-vlc/mb-zzq.h +DefaultInit: EXECUTABLE +InitBram: 1 +Active: 1 +CompilerOptLevel: 2 +GlobPtrOpt: 0 +DebugSym: 1 +AsmOpt: +LinkOpt: +ProgStart: +StackSize: +HeapSize: +LinkerScript: +ProgCCFlags: -D__MICROBLAZE +SwProj: mb-cc +Processor: microblaze_1 +Executable: mb-cc/executable.elf +Source: mb-cc/mb-cc.c +Header: mb-cc/ejpgl.h +Header: mb-cc/fifo_link.h +Header: mb-cc/io.h +DefaultInit: EXECUTABLE +InitBram: 1 +Active: 1 +CompilerOptLevel: 2 +GlobPtrOpt: 0 +DebugSym: 1 +AsmOpt: +LinkOpt: +ProgStart: +StackSize: +HeapSize: +LinkerScript: +ProgCCFlags: -D__MICROBLAZE Index: tags/STEP1_2b/system.mhs =================================================================== --- tags/STEP1_2b/system.mhs (nonexistent) +++ tags/STEP1_2b/system.mhs (revision 27) @@ -0,0 +1,543 @@ +# ############################################################################## +# Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build EDK_H.12.5.1 +# Thu Oct 19 14:57:41 2006 +# Target Board: Xilinx XUP Virtex-II Pro Development System Rev C +# Family: virtex2p +# Device: xc2vp30 +# Package: ff896 +# Speed Grade: -7 +# Processor: Microblaze +# System clock frequency: 100.000000 MHz +# Debug interface: On-Chip HW Debug Module +# On Chip Memory : 64 KB +# Total Off Chip Memory : 256 MB +# - DDR_SDRAM_32Mx64 Single Rank = 256 MB +# ############################################################################## + + + PARAMETER VERSION = 2.1.0 + + + PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = INPUT + PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = OUTPUT + PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = INPUT + PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, VEC = [6:0], DIR = OUTPUT + PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, VEC = [15:0], DIR = INOUT + PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = OUTPUT + PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = OUTPUT + PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = OUTPUT + PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = INPUT + PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk, VEC = [0:2], DIR = OUTPUT + PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn, VEC = [0:2], DIR = OUTPUT + PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr, VEC = [0:12], DIR = OUTPUT + PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr, VEC = [0:1], DIR = OUTPUT + PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn, DIR = OUTPUT + PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn, DIR = OUTPUT + PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn, DIR = OUTPUT + PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM, VEC = [0:7], DIR = OUTPUT + PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS, VEC = [0:7], DIR = INOUT + PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ, VEC = [0:63], DIR = INOUT + PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE, DIR = OUTPUT + PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn, DIR = OUTPUT + PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = INPUT + PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = OUTPUT + PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK + PORT sys_rst_pin = sys_rst_s, DIR = INPUT + + +BEGIN microblaze + PARAMETER INSTANCE = microblaze_0 + PARAMETER HW_VER = 4.00.a + PARAMETER C_DEBUG_ENABLED = 1 + PARAMETER C_NUMBER_OF_PC_BRK = 2 + PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1 + PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1 + PARAMETER C_FSL_LINKS = 1 + BUS_INTERFACE DLMB = dlmb0 + BUS_INTERFACE ILMB = ilmb0 + BUS_INTERFACE DOPB = mb_opb + BUS_INTERFACE IOPB = mb_opb + BUS_INTERFACE MFSL0 = fsl0m + BUS_INTERFACE SFSL0 = fsl0s + PORT CLK = sys_clk_s + PORT DBG_CAPTURE = DBG_CAPTURE_s + PORT DBG_CLK = DBG_CLK_s + PORT DBG_REG_EN = DBG_REG_EN_s + PORT DBG_TDI = DBG_TDI_s + PORT DBG_TDO = DBG_TDO_s + PORT DBG_UPDATE = DBG_UPDATE_s +END + +BEGIN microblaze + PARAMETER INSTANCE = microblaze_1 + PARAMETER HW_VER = 4.00.a + PARAMETER C_DEBUG_ENABLED = 1 + PARAMETER C_NUMBER_OF_PC_BRK = 2 + PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1 + PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1 + PARAMETER C_FSL_LINKS = 1 + BUS_INTERFACE DLMB = dlmb1 + BUS_INTERFACE ILMB = ilmb1 + BUS_INTERFACE DOPB = mb_opb + BUS_INTERFACE IOPB = mb_opb + BUS_INTERFACE SFSL0 = fsl1s + BUS_INTERFACE MFSL0 = fsl1m +END + +BEGIN microblaze + PARAMETER INSTANCE = microblaze_2 + PARAMETER HW_VER = 4.00.a + PARAMETER C_DEBUG_ENABLED = 1 + PARAMETER C_NUMBER_OF_PC_BRK = 2 + PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1 + PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1 + PARAMETER C_FSL_LINKS = 1 + BUS_INTERFACE DLMB = dlmb2 + BUS_INTERFACE ILMB = ilmb2 + BUS_INTERFACE DOPB = mb_opb + BUS_INTERFACE IOPB = mb_opb + BUS_INTERFACE SFSL0 = fsl2s + BUS_INTERFACE MFSL0 = fsl2m + PORT CLK = sys_clk_s +END + +BEGIN microblaze + PARAMETER INSTANCE = microblaze_3 + PARAMETER HW_VER = 4.00.a + PARAMETER C_FSL_LINKS = 1 + BUS_INTERFACE DOPB = mb_opb + BUS_INTERFACE IOPB = mb_opb + BUS_INTERFACE DLMB = dlmb3 + BUS_INTERFACE ILMB = ilmb3 + BUS_INTERFACE SFSL0 = fsl3s + BUS_INTERFACE MFSL0 = fsl3m +END + +BEGIN opb_v20 + PARAMETER INSTANCE = mb_opb + PARAMETER HW_VER = 1.10.c + PARAMETER C_EXT_RESET_HIGH = 0 + PORT SYS_Rst = sys_rst_s + PORT OPB_Clk = sys_clk_s +END + +BEGIN opb_mdm + PARAMETER INSTANCE = debug_module + PARAMETER HW_VER = 2.00.a + PARAMETER C_MB_DBG_PORTS = 1 + PARAMETER C_USE_UART = 1 + PARAMETER C_UART_WIDTH = 8 + PARAMETER C_BASEADDR = 0x41400000 + PARAMETER C_HIGHADDR = 0x4140ffff + BUS_INTERFACE SOPB = mb_opb + PORT OPB_Clk = sys_clk_s + PORT DBG_CAPTURE_0 = DBG_CAPTURE_s + PORT DBG_CLK_0 = DBG_CLK_s + PORT DBG_REG_EN_0 = DBG_REG_EN_s + PORT DBG_TDI_0 = DBG_TDI_s + PORT DBG_TDO_0 = DBG_TDO_s + PORT DBG_UPDATE_0 = DBG_UPDATE_s +END + +BEGIN lmb_v10 + PARAMETER INSTANCE = ilmb0 + PARAMETER HW_VER = 1.00.a + PARAMETER C_EXT_RESET_HIGH = 0 + PORT SYS_Rst = sys_rst_s + PORT LMB_Clk = sys_clk_s +END + +BEGIN lmb_v10 + PARAMETER INSTANCE = dlmb0 + PARAMETER HW_VER = 1.00.a + PARAMETER C_EXT_RESET_HIGH = 0 + PORT SYS_Rst = sys_rst_s + PORT LMB_Clk = sys_clk_s +END + +BEGIN lmb_v10 + PARAMETER INSTANCE = ilmb1 + PARAMETER HW_VER = 1.00.a + PARAMETER C_EXT_RESET_HIGH = 0 + PORT SYS_Rst = sys_rst_s + PORT LMB_Clk = sys_clk_s +END + +BEGIN lmb_v10 + PARAMETER INSTANCE = dlmb1 + PARAMETER HW_VER = 1.00.a + PARAMETER C_EXT_RESET_HIGH = 0 + PORT SYS_Rst = sys_rst_s + PORT LMB_Clk = sys_clk_s +END + +BEGIN lmb_v10 + PARAMETER INSTANCE = ilmb2 + PARAMETER HW_VER = 1.00.a + PARAMETER C_EXT_RESET_HIGH = 0 + PORT SYS_Rst = sys_rst_s + PORT LMB_Clk = sys_clk_s +END + +BEGIN lmb_v10 + PARAMETER INSTANCE = dlmb2 + PARAMETER HW_VER = 1.00.a + PARAMETER C_EXT_RESET_HIGH = 0 + PORT SYS_Rst = sys_rst_s + PORT LMB_Clk = sys_clk_s +END + +BEGIN lmb_v10 + PARAMETER INSTANCE = ilmb3 + PARAMETER HW_VER = 1.00.a + PARAMETER C_EXT_RESET_HIGH = 0 + PORT SYS_Rst = sys_rst_s + PORT LMB_Clk = sys_clk_s +END + +BEGIN lmb_v10 + PARAMETER INSTANCE = dlmb3 + PARAMETER HW_VER = 1.00.a + PARAMETER C_EXT_RESET_HIGH = 0 + PORT SYS_Rst = sys_rst_s + PORT LMB_Clk = sys_clk_s +END + +BEGIN fsl_v20 + PARAMETER INSTANCE = fsl0m + PARAMETER HW_VER = 2.00.a + PARAMETER C_EXT_RESET_HIGH = 0 + PARAMETER C_FSL_DEPTH = 128 + PORT FSL_Clk = sys_clk_s + PORT SYS_Rst = sys_rst_s +END + +BEGIN fsl_v20 + PARAMETER INSTANCE = fsl0s + PARAMETER HW_VER = 2.00.a + PARAMETER C_EXT_RESET_HIGH = 0 + PARAMETER C_FSL_DEPTH = 128 + PORT FSL_Clk = sys_clk_s + PORT SYS_Rst = sys_rst_s +END + +BEGIN fsl_v20 + PARAMETER INSTANCE = fsl1m + PARAMETER HW_VER = 2.00.a + PARAMETER C_EXT_RESET_HIGH = 0 + PARAMETER C_FSL_DEPTH = 128 + PORT FSL_Clk = sys_clk_s + PORT SYS_Rst = sys_rst_s +END + +BEGIN fsl_v20 + PARAMETER INSTANCE = fsl1s + PARAMETER HW_VER = 2.00.a + PARAMETER C_EXT_RESET_HIGH = 0 + PARAMETER C_FSL_DEPTH = 128 + PORT FSL_Clk = sys_clk_s + PORT SYS_Rst = sys_rst_s +END + +BEGIN fsl_v20 + PARAMETER INSTANCE = fsl2m + PARAMETER HW_VER = 2.00.a + PARAMETER C_EXT_RESET_HIGH = 0 + PARAMETER C_FSL_DEPTH = 128 + PORT FSL_Clk = sys_clk_s + PORT SYS_Rst = sys_rst_s +END + +BEGIN fsl_v20 + PARAMETER INSTANCE = fsl2s + PARAMETER HW_VER = 2.00.a + PARAMETER C_EXT_RESET_HIGH = 0 + PARAMETER C_FSL_DEPTH = 128 + PORT FSL_Clk = sys_clk_s + PORT SYS_Rst = sys_rst_s +END + +BEGIN fsl_v20 + PARAMETER INSTANCE = fsl3m + PARAMETER HW_VER = 2.00.a + PARAMETER C_EXT_RESET_HIGH = 0 + PARAMETER C_FSL_DEPTH = 128 + PORT FSL_Clk = sys_clk_s + PORT SYS_Rst = sys_rst_s +END + +BEGIN fsl_v20 + PARAMETER INSTANCE = fsl3s + PARAMETER HW_VER = 2.00.a + PARAMETER C_EXT_RESET_HIGH = 0 + PARAMETER C_FSL_DEPTH = 128 + PORT FSL_Clk = sys_clk_s + PORT SYS_Rst = sys_rst_s +END + +BEGIN lmb_bram_if_cntlr + PARAMETER INSTANCE = dlmb_cntlr0 + PARAMETER HW_VER = 1.00.b + PARAMETER C_BASEADDR = 0x00000000 + PARAMETER C_HIGHADDR = 0x0000ffff + BUS_INTERFACE SLMB = dlmb0 + BUS_INTERFACE BRAM_PORT = dlmb_port0 +END + +BEGIN lmb_bram_if_cntlr + PARAMETER INSTANCE = ilmb_cntlr0 + PARAMETER HW_VER = 1.00.b + PARAMETER C_BASEADDR = 0x00000000 + PARAMETER C_HIGHADDR = 0x0000ffff + BUS_INTERFACE SLMB = ilmb0 + BUS_INTERFACE BRAM_PORT = ilmb_port0 +END + +BEGIN bram_block + PARAMETER INSTANCE = lmb_bram0 + PARAMETER HW_VER = 1.00.a + BUS_INTERFACE PORTA = ilmb_port0 + BUS_INTERFACE PORTB = dlmb_port0 +END + +BEGIN lmb_bram_if_cntlr + PARAMETER INSTANCE = dlmb_cntlr1 + PARAMETER HW_VER = 1.00.b + PARAMETER C_BASEADDR = 0x00000000 + PARAMETER C_HIGHADDR = 0x00001fff + BUS_INTERFACE SLMB = dlmb1 + BUS_INTERFACE BRAM_PORT = dmb_port1 +END + +BEGIN lmb_bram_if_cntlr + PARAMETER INSTANCE = ilmb_cntlr1 + PARAMETER HW_VER = 1.00.b + PARAMETER C_BASEADDR = 0x00000000 + PARAMETER C_HIGHADDR = 0x00001fff + BUS_INTERFACE SLMB = ilmb1 + BUS_INTERFACE BRAM_PORT = ilmb_port1 +END + +BEGIN bram_block + PARAMETER INSTANCE = lmb_bram1 + PARAMETER HW_VER = 1.00.a + BUS_INTERFACE PORTA = ilmb_port1 + BUS_INTERFACE PORTB = dmb_port1 +END + +BEGIN lmb_bram_if_cntlr + PARAMETER INSTANCE = dlmb_cntlr2 + PARAMETER HW_VER = 1.00.b + PARAMETER C_BASEADDR = 0x00000000 + PARAMETER C_HIGHADDR = 0x00001fff + BUS_INTERFACE SLMB = dlmb2 + BUS_INTERFACE BRAM_PORT = dlmb_port2 +END + +BEGIN lmb_bram_if_cntlr + PARAMETER INSTANCE = ilmb_cntlr2 + PARAMETER HW_VER = 1.00.b + PARAMETER C_BASEADDR = 0x00000000 + PARAMETER C_HIGHADDR = 0x00001fff + BUS_INTERFACE SLMB = ilmb2 + BUS_INTERFACE BRAM_PORT = ilmb_port2 +END + +BEGIN bram_block + PARAMETER INSTANCE = lmb_bram2 + PARAMETER HW_VER = 1.00.a + BUS_INTERFACE PORTA = ilmb_port2 + BUS_INTERFACE PORTB = dlmb_port2 +END + +BEGIN lmb_bram_if_cntlr + PARAMETER INSTANCE = dlmb_cntlr3 + PARAMETER HW_VER = 1.00.b + PARAMETER C_BASEADDR = 0x00000000 + PARAMETER C_HIGHADDR = 0x00001fff + BUS_INTERFACE BRAM_PORT = dlmb_port3 + BUS_INTERFACE SLMB = dlmb3 +END + +BEGIN lmb_bram_if_cntlr + PARAMETER INSTANCE = ilmb_cntlr3 + PARAMETER HW_VER = 1.00.b + PARAMETER C_BASEADDR = 0x00000000 + PARAMETER C_HIGHADDR = 0x00001fff + BUS_INTERFACE BRAM_PORT = ilmb_port3 + BUS_INTERFACE SLMB = ilmb3 +END + +BEGIN bram_block + PARAMETER INSTANCE = lmb_bram3 + PARAMETER HW_VER = 1.00.a + BUS_INTERFACE PORTA = ilmb_port3 + BUS_INTERFACE PORTB = dlmb_port3 +END + +BEGIN opb_uartlite + PARAMETER INSTANCE = RS232_Uart_1 + PARAMETER HW_VER = 1.00.b + PARAMETER C_BAUDRATE = 9600 + PARAMETER C_DATA_BITS = 8 + PARAMETER C_ODD_PARITY = 0 + PARAMETER C_USE_PARITY = 0 + PARAMETER C_CLK_FREQ = 100000000 + PARAMETER C_BASEADDR = 0x40600000 + PARAMETER C_HIGHADDR = 0x4060ffff + BUS_INTERFACE SOPB = mb_opb + PORT OPB_Clk = sys_clk_s + PORT RX = fpga_0_RS232_Uart_1_RX + PORT TX = fpga_0_RS232_Uart_1_TX +END + +BEGIN opb_sysace + PARAMETER INSTANCE = SysACE_CompactFlash + PARAMETER HW_VER = 1.00.c + PARAMETER C_MEM_WIDTH = 16 + PARAMETER C_BASEADDR = 0x41800000 + PARAMETER C_HIGHADDR = 0x4180ffff + BUS_INTERFACE SOPB = mb_opb + PORT OPB_Clk = sys_clk_s + PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK + PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA + PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD + PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN + PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN + PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN + PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ +END + +BEGIN opb_ddr + PARAMETER INSTANCE = DDR_256MB_32MX64_rank1_row13_col10_cl2_5 + PARAMETER HW_VER = 2.00.b + PARAMETER C_OPB_CLK_PERIOD_PS = 10000 + PARAMETER C_NUM_BANKS_MEM = 1 + PARAMETER C_NUM_CLK_PAIRS = 4 + PARAMETER C_REG_DIMM = 0 + PARAMETER C_DDR_TMRD = 20000 + PARAMETER C_DDR_TWR = 20000 + PARAMETER C_DDR_TRAS = 60000 + PARAMETER C_DDR_TRC = 90000 + PARAMETER C_DDR_TRFC = 100000 + PARAMETER C_DDR_TRCD = 30000 + PARAMETER C_DDR_TRRD = 20000 + PARAMETER C_DDR_TRP = 30000 + PARAMETER C_DDR_TREFC = 70300000 + PARAMETER C_DDR_AWIDTH = 13 + PARAMETER C_DDR_COL_AWIDTH = 10 + PARAMETER C_DDR_BANK_AWIDTH = 2 + PARAMETER C_DDR_DWIDTH = 64 + PARAMETER C_MEM0_BASEADDR = 0x30000000 + PARAMETER C_MEM0_HIGHADDR = 0x3fffffff + BUS_INTERFACE SOPB = mb_opb + PORT OPB_Clk = sys_clk_s + PORT DDR_Addr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr + PORT DDR_BankAddr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr + PORT DDR_CASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn + PORT DDR_CKE = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE + PORT DDR_CSn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn + PORT DDR_RASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn + PORT DDR_WEn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn + PORT DDR_DM = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM + PORT DDR_DQS = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS + PORT DDR_DQ = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ + PORT DDR_Clk = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk & ddr_clk_feedback_out_s + PORT DDR_Clkn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn & 0b0 + PORT Device_Clk90_in = clk_90_s + PORT Device_Clk90_in_n = clk_90_n_s + PORT Device_Clk = sys_clk_s + PORT Device_Clk_n = sys_clk_n_s + PORT DDR_Clk90_in = ddr_clk_90_s + PORT DDR_Clk90_in_n = ddr_clk_90_n_s +END + +BEGIN util_vector_logic + PARAMETER INSTANCE = sysclk_inv + PARAMETER HW_VER = 1.00.a + PARAMETER C_SIZE = 1 + PARAMETER C_OPERATION = not + PORT Op1 = sys_clk_s + PORT Res = sys_clk_n_s +END + +BEGIN util_vector_logic + PARAMETER INSTANCE = clk90_inv + PARAMETER HW_VER = 1.00.a + PARAMETER C_SIZE = 1 + PARAMETER C_OPERATION = not + PORT Op1 = clk_90_s + PORT Res = clk_90_n_s +END + +BEGIN util_vector_logic + PARAMETER INSTANCE = ddr_clk90_inv + PARAMETER HW_VER = 1.00.a + PARAMETER C_SIZE = 1 + PARAMETER C_OPERATION = not + PORT Op1 = ddr_clk_90_s + PORT Res = ddr_clk_90_n_s +END + +BEGIN dcm_module + PARAMETER INSTANCE = dcm_0 + PARAMETER HW_VER = 1.00.a + PARAMETER C_CLK0_BUF = TRUE + PARAMETER C_CLK90_BUF = TRUE + PARAMETER C_CLKIN_PERIOD = 10.000000 + PARAMETER C_CLK_FEEDBACK = 1X + PARAMETER C_EXT_RESET_HIGH = 1 + PORT CLKIN = dcm_clk_s + PORT CLK0 = sys_clk_s + PORT CLK90 = clk_90_s + PORT CLKFB = sys_clk_s + PORT RST = net_gnd + PORT LOCKED = dcm_0_lock +END + +BEGIN dcm_module + PARAMETER INSTANCE = dcm_1 + PARAMETER HW_VER = 1.00.a + PARAMETER C_CLK0_BUF = TRUE + PARAMETER C_CLK90_BUF = TRUE + PARAMETER C_CLKIN_PERIOD = 10.000000 + PARAMETER C_CLK_FEEDBACK = 1X + PARAMETER C_PHASE_SHIFT = 60 + PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED + PARAMETER C_EXT_RESET_HIGH = 0 + PORT CLKIN = ddr_feedback_s + PORT CLK90 = ddr_clk_90_s + PORT CLK0 = dcm_1_FB + PORT CLKFB = dcm_1_FB + PORT RST = dcm_0_lock + PORT LOCKED = dcm_1_lock +END + +BEGIN fifo_link + PARAMETER INSTANCE = fifo01 + PARAMETER HW_VER = 1.00.a + BUS_INTERFACE SFSL = fsl0m + BUS_INTERFACE MFSL = fsl1s +END + +BEGIN fifo_link + PARAMETER INSTANCE = fifo12 + PARAMETER HW_VER = 1.00.a + BUS_INTERFACE SFSL = fsl1m + BUS_INTERFACE MFSL = fsl2s +END + +BEGIN fifo_link + PARAMETER INSTANCE = fifo23 + PARAMETER HW_VER = 1.00.a + BUS_INTERFACE SFSL = fsl2m + BUS_INTERFACE MFSL = fsl3s +END + +BEGIN fifo_link + PARAMETER INSTANCE = fifo30 + PARAMETER HW_VER = 1.00.a + BUS_INTERFACE SFSL = fsl3m + BUS_INTERFACE MFSL = fsl0s +END + Index: tags/STEP1_2b/pcores/fifo_link_v1_00_a/hdl/vhdl/fifo_link.vhd =================================================================== --- tags/STEP1_2b/pcores/fifo_link_v1_00_a/hdl/vhdl/fifo_link.vhd (nonexistent) +++ tags/STEP1_2b/pcores/fifo_link_v1_00_a/hdl/vhdl/fifo_link.vhd (revision 27) @@ -0,0 +1,137 @@ +------------------------------------------------------------------------------ +-- fifo_link - entity/architecture pair +------------------------------------------------------------------------------ +-- +-- *************************************************************************** +-- ** Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. ** +-- ** ** +-- ** Xilinx, Inc. ** +-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** +-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** +-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** +-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** +-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** +-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** +-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** +-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** +-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** +-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** +-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** +-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** +-- ** FOR A PARTICULAR PURPOSE. ** +-- ** ** +-- ** YOU MAY COPY AND MODIFY THESE FILES FOR YOUR OWN INTERNAL USE SOLELY ** +-- ** WITH XILINX PROGRAMMABLE LOGIC DEVICES AND XILINX EDK SYSTEM OR ** +-- ** CREATE IP MODULES SOLELY FOR XILINX PROGRAMMABLE LOGIC DEVICES AND ** +-- ** XILINX EDK SYSTEM. NO RIGHTS ARE GRANTED TO DISTRIBUTE ANY FILES ** +-- ** UNLESS THEY ARE DISTRIBUTED IN XILINX PROGRAMMABLE LOGIC DEVICES. ** +-- ** ** +-- *************************************************************************** +-- +------------------------------------------------------------------------------ +-- Filename: fifo_link +-- Version: 1.00.a +-- Description: Example FSL core (VHDL). +-- Date: Fri Oct 06 17:25:29 2006 (by Create and Import Peripheral Wizard Wizard) +-- VHDL Standard: VHDL'93 +------------------------------------------------------------------------------ +-- Naming Conventions: +-- active low signals: "*_n" +-- clock signals: "clk", "clk_div#", "clk_#x" +-- reset signals: "rst", "rst_n" +-- generics: "C_*" +-- user defined types: "*_TYPE" +-- state machine next state: "*_ns" +-- state machine current state: "*_cs" +-- combinatorial signals: "*_com" +-- pipelined or register delay signals: "*_d#" +-- counter signals: "*cnt*" +-- clock enable signals: "*_ce" +-- internal version of output port: "*_i" +-- device pins: "*_pin" +-- ports: "- Names begin with Uppercase" +-- processes: "*_PROCESS" +-- component instantiations: "I_<#|FUNC>" +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +------------------------------------------------------------------------------------- +-- +-- +-- Definition of Ports +-- FSL_Clk : Synchronous clock +-- FSL_Rst : System reset, should always come from FSL bus +-- FSL_S_Clk : Slave asynchronous clock +-- FSL_S_Read : Read signal, requiring next available input to be read +-- FSL_S_Data : Input data +-- FSL_S_CONTROL : Control Bit, indicating the input data are control word +-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus +-- FSL_M_Clk : Master asynchronous clock +-- FSL_M_Write : Write signal, enabling writing to output FSL bus +-- FSL_M_Data : Output data +-- FSL_M_Control : Control Bit, indicating the output data are contol word +-- FSL_M_Full : Full Bit, indicating output FSL bus is full +-- +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------ +-- Entity Section +------------------------------------------------------------------------------ + +entity fifo_link is + port + ( + -- DO NOT EDIT BELOW THIS LINE --------------------- + -- Bus protocol ports, do not add or delete. + FSL_Clk : in std_logic; + FSL_Rst : in std_logic; + FSL_S_Clk : out std_logic; + FSL_S_Read : out std_logic; + FSL_S_Data : in std_logic_vector(0 to 31); + FSL_S_Control : in std_logic; + FSL_S_Exists : in std_logic; + FSL_M_Clk : out std_logic; + FSL_M_Write : out std_logic; + FSL_M_Data : out std_logic_vector(0 to 31); + FSL_M_Control : out std_logic; + FSL_M_Full : in std_logic + -- DO NOT EDIT ABOVE THIS LINE --------------------- + ); + +attribute SIGIS : string; +attribute SIGIS of FSL_Clk : signal is "Clk"; +attribute SIGIS of FSL_S_Clk : signal is "Clk"; +attribute SIGIS of FSL_M_Clk : signal is "Clk"; + +end fifo_link; + +------------------------------------------------------------------------------ +-- Architecture Section +------------------------------------------------------------------------------ + +-- In this section, we povide an example implementation of ENITY fifo_link +-- that does the following: +-- +-- 1. Read all inputs +-- 2. Add each input to the contents of register 'sum' which +-- acts as an accumulator +-- 3. After all the inputs have been read, write out the +-- content of 'sum' into the output FSL bus NUMBER_OF_OUTPUT_WORDS times +-- +-- You will need to modify this example or implement a new architecture for +-- ENTITY fifo_link to implement your coprocessor + +architecture EXAMPLE of fifo_link is + +begin + + FSL_M_Data <= FSL_S_Data; + FSL_M_Write <= FSL_S_Exists and (not FSL_M_Full); + + FSL_S_Read <= FSL_S_Exists and (not FSL_M_Full); + + +end architecture EXAMPLE; Index: tags/STEP1_2b/pcores/fifo_link_v1_00_a/data/fifo_link_v2_1_0.pao =================================================================== --- tags/STEP1_2b/pcores/fifo_link_v1_00_a/data/fifo_link_v2_1_0.pao (nonexistent) +++ tags/STEP1_2b/pcores/fifo_link_v1_00_a/data/fifo_link_v2_1_0.pao (revision 27) @@ -0,0 +1,21 @@ +############################################################################## +## +## *************************************************************************** +## ** ** +## ** Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. ** +## ** ** +## ** You may copy and modify these files for your own internal use solely ** +## ** with Xilinx programmable logic devices and Xilinx EDK system or ** +## ** create IP modules solely for Xilinx programmable logic devices and ** +## ** Xilinx EDK system. No rights are granted to distribute any files ** +## ** unless they are distributed in Xilinx programmable logic devices. ** +## ** ** +## *************************************************************************** +## +############################################################################## +## Filename: D:\mpdma\pcores\fifo_link_v1_00_a\data\fifo_link_v2_1_0.pao +## Description: Peripheral Analysis Order +## Date: Sun Oct 22 10:40:07 2006 (by Create and Import Peripheral Wizard) +############################################################################## + +lib fifo_link_v1_00_a fifo_link vhdl Index: tags/STEP1_2b/pcores/fifo_link_v1_00_a/data/fifo_link_v2_1_0.mpd =================================================================== --- tags/STEP1_2b/pcores/fifo_link_v1_00_a/data/fifo_link_v2_1_0.mpd (nonexistent) +++ tags/STEP1_2b/pcores/fifo_link_v1_00_a/data/fifo_link_v2_1_0.mpd (revision 27) @@ -0,0 +1,45 @@ +## Copyright (c) 2004 Xilinx, Inc. All Rights Reserved. +## You may copy and modify these files for your own internal use solely with +## Xilinx programmable logic devices and Xilinx EDK system or create IP +## modules solely for Xilinx programmable logic devices and Xilinx EDK system. +## No rights are granted to distribute any files unless they are distributed in +## Xilinx programmable logic devices. +################################################################### +## +## Name : fifo_link +## Desc : Microprocessor Peripheral Description +## : Automatically generated by PsfUtility +## +################################################################### + +BEGIN fifo_link + +## Peripheral Options +OPTION IPTYPE = PERIPHERAL +OPTION IMP_NETLIST = TRUE +OPTION HDL = VHDL +OPTION CORE_STATE = ACTIVE +OPTION IP_GROUP = MICROBLAZE:PPC:USER + + +## Bus Interfaces +BUS_INTERFACE BUS = SFSL, BUS_TYPE = SLAVE, BUS_STD = FSL +BUS_INTERFACE BUS = MFSL, BUS_TYPE = MASTER, BUS_STD = FSL + +## Generics for VHDL or Parameters for Verilog + +## Ports +PORT FSL_Clk = "", DIR = I, SIGIS = Clk, BUS = SFSL:MFSL +PORT FSL_Rst = OPB_Rst, DIR = I, BUS = SFSL:MFSL +PORT FSL_S_Clk = FSL_S_Clk, DIR = O, SIGIS = Clk, BUS = SFSL +PORT FSL_S_Read = FSL_S_Read, DIR = O, BUS = SFSL +PORT FSL_S_Data = FSL_S_Data, DIR = I, VEC = [0:31], BUS = SFSL +PORT FSL_S_Control = FSL_S_Control, DIR = I, BUS = SFSL +PORT FSL_S_Exists = FSL_S_Exists, DIR = I, BUS = SFSL +PORT FSL_M_Clk = FSL_M_Clk, DIR = O, SIGIS = Clk, BUS = MFSL +PORT FSL_M_Write = FSL_M_Write, DIR = O, BUS = MFSL +PORT FSL_M_Data = FSL_M_Data, DIR = O, VEC = [0:31], BUS = MFSL +PORT FSL_M_Control = FSL_M_Control, DIR = O, BUS = MFSL +PORT FSL_M_Full = FSL_M_Full, DIR = I, BUS = MFSL + +END Index: tags/STEP1_2b/pcores/fifo_link_v1_00_a/devl/ipwiz.log =================================================================== --- tags/STEP1_2b/pcores/fifo_link_v1_00_a/devl/ipwiz.log (nonexistent) +++ tags/STEP1_2b/pcores/fifo_link_v1_00_a/devl/ipwiz.log (revision 27) @@ -0,0 +1,47 @@ +HDL language for the peripheral (top level) design unit fifo_link is vhdl ... +INFO:MDT - Create temparary xst project file: D:\mpdma\pcores\fifo_link.prj +Compiling vhdl file +"D:/thesis/mb-diesel/pcores/fifo_link_v1_00_a/hdl/vhdl/fifo_link.vhd" in Library +fifo_link_v1_00_a. +Entity compiled. +Entity (Architecture ) compiled. + + +Analyzing HDL attributes ... +INFO:MDT - IPTYPE set to value : PERIPHERAL +INFO:MDT - IMP_NETLIST set to value : TRUE +INFO:MDT - HDL set to value : VHDL +INFO:MDT - NO SIGIS=RST specified for probable Reset signal FSL_Rst +INFO:MDT - NO SIGIS=RST specified for probable Reset signal FSL_Rst +INFO:MDT - Infer bus clock [FSL_Clk] for bus interface MFSL ... +INFO:MDT - Infer bus reset [FSL_Rst] for bus interface MFSL ... +INFO:MDT - Infer bus clock [FSL_Clk] for bus interface SFSL ... +INFO:MDT - Infer bus reset [FSL_Rst] for bus interface SFSL ... +Copying file fifo_link.vhd to D:\mpdma\pcores\fifo_link_v1_00_a\hdl\vhdl\ ... + +Summary: + + Logical library : fifo_link_v1_00_a + Version : 1.00.a + Bus interface(s) : SFSL MFSL + +The following sub-directories will be created in the pcores repository in your +project: + +- fifo_link_v1_00_a\data +- fifo_link_v1_00_a\hdl +- fifo_link_v1_00_a\hdl\vhdl + + +The following HDL source files will be copied into the +fifo_link_v1_00_a\hdl\vhdl directory: + +- fifo_link.vhd + +The following files will be created under the fifo_link_v1_00_a\data directory: + +- fifo_link_v2_1_0.mpd +- fifo_link_v2_1_0.pao + +Thank you for using this Import Peripheral Wizard! + Index: tags/STEP1_2b/mb-bmp2jpg_linker_script =================================================================== --- tags/STEP1_2b/mb-bmp2jpg_linker_script (nonexistent) +++ tags/STEP1_2b/mb-bmp2jpg_linker_script (revision 27) @@ -0,0 +1,100 @@ +/*******************************************************************/ +/* */ +/* This file is automatically generated by linker script generator.*/ +/* */ +/* Version: Xilinx EDK 7.1.2EDK_H.12.5.1 */ +/* */ +/* Copyright (c) 2004 Xilinx, Inc. All rights reserved. */ +/* */ +/* Description : MicroBlaze Linker Script */ +/* */ +/*******************************************************************/ + +_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x1000; +_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x400; + +/* Define Memories in the system */ + +MEMORY +{ + DDR_256MB_32MX64_rank1_row13_col10_cl2_5_C_MEM0_BASEADDR : ORIGIN = 0x30000000, LENGTH = 0x0FFFFFFF + ilmb_cntlr_dlmb_cntlr : ORIGIN = 0x00000000, LENGTH = 0x0000FFFF +} + +/* Specify the default entry point to the program */ + +ENTRY(_start) + +/* Define the sections, and where they are mapped in memory */ + +SECTIONS +{ +.text : { + __text_start = .; + *(.text) + *(.text.*) + *(.gnu.linkonce.t*) + __text_end = .; +} > ilmb_cntlr_dlmb_cntlr + +.rodata : { + __rodata_start = .; + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r*) + __rodata_end = .; +} > ilmb_cntlr_dlmb_cntlr + +.sdata2 : { + . = ALIGN(8); + __sdata2_start = .; + *(.sdata2) + . = ALIGN(8); + __sdata2_end = .; +} > ilmb_cntlr_dlmb_cntlr + +.data : { + . = ALIGN(4); + __data_start = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + __data_end = .; +} > ilmb_cntlr_dlmb_cntlr + +.sbss : { + . = ALIGN(4); + __sbss_start = .; + *(.sbss) + . = ALIGN(8); + __sbss_end = .; +} > ilmb_cntlr_dlmb_cntlr + +.bss : { + . = ALIGN(4); + __bss_start = .; + *(.bss) + *(COMMON) + . = ALIGN(4); + __bss_end = .; +} > ilmb_cntlr_dlmb_cntlr + +PROVIDE (_SDA_BASE_ = (__sbss_end - __sbss_start / 2 )); + +PROVIDE (_SDA2_BASE_ = (__sdata2_end - __sdata2_start / 2 )); + +/* Generate Stack and Heap definitions */ + +bss_stack : { + . = ALIGN(8); + _heap = .; + _heap_start = _heap; + . += _HEAP_SIZE; + . += _STACK_SIZE; + . = ALIGN(8); + _stack = .; + __stack = _stack; +} > ilmb_cntlr_dlmb_cntlr + +} + Index: tags/STEP1_2b/mb-cc/mb-cc.c =================================================================== --- tags/STEP1_2b/mb-cc/mb-cc.c (nonexistent) +++ tags/STEP1_2b/mb-cc/mb-cc.c (revision 27) @@ -0,0 +1,91 @@ +#include "xutil.h" +#include "mb_interface.h" +#include "fifo_link.h" + +#include "ejpgl.h" +#include "io.h" + +#define XPAR_FSL_FIFO_LINK_0_INPUT_SLOT_ID 0 +#define XPAR_FSL_FIFO_LINK_0_OUTPUT_SLOT_ID 0 + + +#define RGB2Y(r, g, b) (((66*r + 129*g + 25*b + 128)>>8)+128) +#define RGB2Cr(r, g, b) (((-38*r - 74*g + 112*b + 128)>>8)+128) +#define RGB2Cb(r, g, b) (((112*r - 94*g - 18*b + 128)>>8)+128) + +void RGB2YCrCb(signed char pixelmatrix[MACRO_BLOCK_SIZE][MACRO_BLOCK_SIZE*3],signed char YMatrix[MATRIX_SIZE][MATRIX_SIZE],signed char CrMatrix[MATRIX_SIZE][MATRIX_SIZE],signed char CbMatrix[MATRIX_SIZE][MATRIX_SIZE], unsigned int sample) +{ + unsigned int row, col, rowoffset, coloffset, xoffset, yoffset; + for(row = 0;row < MATRIX_SIZE; row++) { + for(col = 0; col < MATRIX_SIZE; col++) { + coloffset = (sample&0x01)*8; + rowoffset = (sample&0x02)*4; + YMatrix[row][col] = RGB2Y(pixelmatrix[row+rowoffset][(col+coloffset)*3+2],pixelmatrix[row+rowoffset][(col+coloffset)*3+1],pixelmatrix[row+rowoffset][(col+coloffset)*3]) - 128; + if (col%2==0) { + yoffset = (sample&0x01)*4; + xoffset = (sample&0x02)*2; + if (row%2==0) { + CrMatrix[xoffset+(row>>1)][yoffset+(col>>1)] = RGB2Cr(pixelmatrix[row+rowoffset][(col+coloffset)*3+2],pixelmatrix[row+rowoffset][(col+coloffset)*3+1],pixelmatrix[row+rowoffset][(col+coloffset)*3]) - 128; + } else { + CbMatrix[xoffset+((row)>>2)][yoffset+(col>>2)] = RGB2Cb(pixelmatrix[row+rowoffset][(col+coloffset)*3+2],pixelmatrix[row+rowoffset][(col+coloffset)*3+1],pixelmatrix[row+rowoffset][(col+coloffset)*3]) - 128; + } + } + } + } +} + +signed char pixelmatrix[MACRO_BLOCK_SIZE][MACRO_BLOCK_SIZE*3]; +signed char YMatrix[MATRIX_SIZE][MATRIX_SIZE]; +signed char CrMatrix[MATRIX_SIZE][MATRIX_SIZE]; +signed char CbMatrix[MATRIX_SIZE][MATRIX_SIZE]; + +main() { + unsigned int i,j; + int result; + int sample; + int color; + int msg; + + for (;;) { + read_from_fsl(msg, XPAR_FSL_FIFO_LINK_0_INPUT_SLOT_ID); + if (msg == 0xff) { + write_into_fsl(color, XPAR_FSL_FIFO_LINK_0_OUTPUT_SLOT_ID); + continue; + } + + for (i=0; i +#include "ejpgl.h" + +typedef struct { + unsigned int size; /* Header size in bytes */ + int width,height; /* Width and height of image */ + unsigned short int planes; /* Number of colour planes */ + unsigned short int bits; /* Bits per pixel */ + unsigned int compression; /* Compression type */ + unsigned int imagesize; /* Image size in bytes */ + int xresolution,yresolution; /* Pixels per meter */ + unsigned int ncolours; /* Number of colours */ + unsigned int importantcolours; /* Important colours */ + unsigned char palette[1024]; /* Storage for palette */ +} INFOHEADER; + +typedef struct { + int restofheader; //TODO + INFOHEADER info; /* Information header */ +} BMPHEADER; + +typedef struct { + unsigned int row; /* Width and height of image */ + unsigned int col; /* Width and height of image */ +} BLOCKINFO; + +typedef struct { + unsigned char QTMarker[2]; + unsigned char Length[2]; + unsigned char QTInfo[130]; //bit 0..3: number of QT (0..3, otherwise error) + // bit 4..7: precision of QT, 0 = 8 bit, otherwise 16 bit + // unsigned char ValuesQT[]; //max 192 values. 64*(precision+1) bytes +} QTINFO; + +typedef struct { + unsigned char HTMarker[2]; + unsigned char Length[2]; + unsigned char HuffmanInfo[416]; //Array containing ALL huffman information + //For each color component holds: + //First byte is used as info byte, followed by 16 bytes with values used + //for counting the different huffman codes, finally the corresponding + //huffman codes will follow. This sequence can repeat it self for + //different Huffman tables, both DC or AC tables. + + //The structure of the information byte is as follows: + //bit 0..3 : number of HT (0..3, otherwise error) + //bit 4 : type of HT, 0 = DC table, 1 = AC table + //bit 5..7 : not used, must be 0 (Used for progressive scan JPEG) +} HTINFO; + + +typedef struct { + unsigned char APP0Marker[2]; + unsigned char Length[2]; + unsigned char Identifier[5]; + unsigned char Version[2]; + unsigned char Units; + unsigned char XDensity[2]; + unsigned char YDensity[2]; + unsigned char ThumbWidth; + unsigned char ThumbHeight; +} APP0INFO; + +typedef struct { + unsigned char SOF0Marker[2]; + unsigned char Length[2]; + unsigned char DataPrecision; //This is in bits/sample, usually 8 (12 and 16 not supported by most software). + unsigned char ImageHeight[2]; + unsigned char ImageWidth[2]; + unsigned char Components; //Usually 1 = grey scaled, 3 = color YcbCr or YIQ 4 = color CMYK + unsigned char ComponentInfo[3][3]; //Read each component data of 3 bytes. It contains, + //(component Id(1byte)(1 = Y, 2 = Cb, 3 = Cr, 4 = I, 5 = Q), + //sampling factors (1byte) (bit 0-3 vertical., 4-7 horizontal.), + //quantization table number (1 byte)). +} SOF0INFO; + +typedef struct { + unsigned char SOSMarker[2]; + unsigned char Length[2]; //This must be equal to 6+2*(number of components in scan). + unsigned char ComponentCount; //This must be >= 1 and <=4 (otherwise error), usually 1 or 3 + unsigned char Component[3][2]; // For each component, read 2 bytes. It contains, + //1 byte Component Id (1=Y, 2=Cb, 3=Cr, 4=I, 5=Q), + //1 byte Huffman table to use : + //bit 0..3 : AC table (0..3) + //bit 4..7 : DC table (0..3) + unsigned char Ignore[3]; //We have to skip 3 bytes +} SOSINFO; + +typedef struct { + unsigned char DRIMarker[2]; + unsigned char Length[2]; + unsigned char RestartInteral[2]; // Interval of the restart markers +} DRIINFO; + +typedef struct { + unsigned char SOIMarker[2]; //Start of image marker + APP0INFO app0; + QTINFO qt; + SOF0INFO sof0; + HTINFO ht; +// DRIINFO dri; + SOSINFO sos; +} JPEGHEADER; + +/* + * Read BMP header and return it in header, for now only the width and height + * are returned, since the other values are of no use. + */ +int getbmpheader(FILE * file, INFOHEADER *header); + +int getjpegheader(FILE * file, JPEGHEADER *header); + +void writebmpheader(FILE * file, BMPHEADER *header); + +void writejpegheader(FILE * file, INFOHEADER *header); + +void writejpegfooter(FILE * file); + +/* + * Read BMP to retrieve 8*8 block starting at horizontal position mcol*8, and + * vertical position mrow*8 in the image. This block is returned in pixelmatrix. + * + */ +void RGB2YCrCb(signed char pixelmatrix[MACRO_BLOCK_SIZE][MACRO_BLOCK_SIZE*3],signed char YMatrix[MATRIX_SIZE][MATRIX_SIZE],signed char CrMatrix[MATRIX_SIZE][MATRIX_SIZE],signed char CbMatrix[MATRIX_SIZE][MATRIX_SIZE], unsigned int sample); + +void readjpegfile(FILE * file, unsigned char bitstream[]); + +void writebmpfile(FILE * file, unsigned char pixelmatrix[MATRIX_SIZE][MATRIX_SIZE], unsigned int mrow, unsigned int mcol, unsigned int width); + +void writejpegfile(FILE * file, unsigned char bitstream[]); +#else +#error "ERROR file io.h multiple times included" +#endif /* --- _IO_H --- */ + Index: tags/STEP1_2b/mb-dct/mb-dct.c =================================================================== --- tags/STEP1_2b/mb-dct/mb-dct.c (nonexistent) +++ tags/STEP1_2b/mb-dct/mb-dct.c (revision 27) @@ -0,0 +1,118 @@ +#include "xparameters.h" +#include "xutil.h" +#include "mb_interface.h" +#include "fifo_link.h" + +#include "ejpgl.h" +#include "mb-dct.h" +#include "mb-weights.h" + +signed short dctresult[MATRIX_SIZE][MATRIX_SIZE]; + +#define XPAR_FSL_FIFO_LINK_0_INPUT_SLOT_ID 0 +#define XPAR_FSL_FIFO_LINK_0_OUTPUT_SLOT_ID 0 + +int dct_init_start() { + + return 0; + +} + +/* + Function Name: dct + + Operation: Find the 8x8 DCT of an array using separable DCT + First, finds 1-d DCT along rows, storing the result in inter[][] + Then, 1-d DCT along columns of inter[][] is found + + Input: pixels is the 8x8 input array + + Output: dct is the 8x8 output array +*/ + +void dct(signed char pixels[8][8], int color) +{ + FILE * file; + int inr, inc; /* rows and columns of input image */ + int intr, intc; /* rows and columns of intermediate image */ + int outr, outc; /* rows and columns of dct */ + int f_val; /* cumulative sum */ + int inter[8][8]; /* stores intermediate result */ + int i,j,k; + k=0; + // file = fopen("weights.h","w+"); + // fprintf(file,"double weights1[512] = {"); + /* find 1-d dct along rows */ + for (intr=0; intr<8; intr++) + for (intc=0; intc<8; intc++) { + for (i=0,f_val=0; i<8; i++) { + + f_val += (pixels[intr][i]* weights[k]);//cos((double)(2*i+1)*(double)intc*PI/16); + k++; + // fprintf(file, "\n%.0f,",cos((double)(2*i+1)*(double)intc*PI/16)*16384); + } + if (intc!=0) + inter[intr][intc] = f_val>>15; + else + inter[intr][intc] = (11585*(f_val>>14))>>15; + + } + // fprintf(file,"\n};"); + // fclose(file); + k=0; + /* find 1-d dct along columns */ + for (outc=0; outc<8; outc++) + for (outr=0; outr<8; outr++) { + for (i=0,f_val=0; i<8; i++) { + f_val += (inter[i][outc] *weights[k]); + k++; + } + if (outr!=0) + dctresult[outr][outc] = f_val>>15; + else + dctresult[outr][outc] = (11585*(f_val>>14)>>15); + } + +} + + + +/***************************************************************** + UNCOMMENT THIS SECTION TO TEST 2D DCT +*****************************************************************/ + +signed char ipixels[8][8]; + +main() +{ + + unsigned int i,j; + int result; + int color; + + dct_init_start(); + + for (;;) { + read_from_fsl(color, XPAR_FSL_FIFO_LINK_0_INPUT_SLOT_ID); + + if (color==0xff) { + write_into_fsl(color, XPAR_FSL_FIFO_LINK_0_OUTPUT_SLOT_ID); + } + else { + for (i=0; i<64; i++) { + read_from_fsl(result, XPAR_FSL_FIFO_LINK_0_INPUT_SLOT_ID); + ((signed char*)ipixels)[i]=result; + } + + dct(ipixels, color); + + write_into_fsl(color, XPAR_FSL_FIFO_LINK_0_OUTPUT_SLOT_ID); + + for (i=0; i<64; i++) { + write_into_fsl(((short*)dctresult)[i], XPAR_FSL_FIFO_LINK_0_OUTPUT_SLOT_ID); + } + } + + } + +} Index: tags/STEP1_2b/mb-dct/fifo_link.h =================================================================== --- tags/STEP1_2b/mb-dct/fifo_link.h (nonexistent) +++ tags/STEP1_2b/mb-dct/fifo_link.h (revision 27) @@ -0,0 +1,91 @@ +////////////////////////////////////////////////////////////////////////////// +// +// *************************************************************************** +// ** ** +// ** Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. ** +// ** ** +// ** You may copy and modify these files for your own internal use solely ** +// ** with Xilinx programmable logic devices and Xilinx EDK system or ** +// ** create IP modules solely for Xilinx programmable logic devices and ** +// ** Xilinx EDK system. No rights are granted to distribute any files ** +// ** unless they are distributed in Xilinx programmable logic devices. ** +// ** ** +// *************************************************************************** +// +////////////////////////////////////////////////////////////////////////////// +// Filename: D:\thesis\FIFO1\drivers\fifo_link_v1_00_a\src\\fifo_link.h +// Version: 1.00.a +// Description: fifo_link (FIFO link) Driver Header File +// Date: Fri Oct 06 17:25:29 2006 (by Create and Import Peripheral Wizard) +////////////////////////////////////////////////////////////////////////////// + +#ifndef FIFO_LINK_H +#define FIFO_LINK_H + +#ifdef __MICROBLAZE__ + #include "mb_interface.h" + #define write_into_fsl(val, id) microblaze_bwrite_datafsl(val, id) + #define read_from_fsl(val, id) microblaze_bread_datafsl(val, id) +#else + #include "xpseudo_asm_gcc.h" + #define write_into_fsl(val, id) putfsl(val, id) + #define read_from_fsl(val, id) getfsl(val, id) +#endif + +/* +* A macro for accessing FSL peripheral. +* +* This example driver writes all the data in the input arguments +* into the input FSL bus through blocking wrties. FSL peripheral will +* automatically read from the FSL bus. Once all the inputs +* have been written, the output from the FSL peripheral is read +* into output arguments through blocking reads. +* +* Arguments: +* output_slot_id +* Compile time constant indicating FSL slot from +* which output data is read. Defined in +* xparameters.h . +* input_slot_id +* Compile time constant indicating FSL slot into +* which input data is written. Defined in +* xparameters.h . +* input_0 An array of unsigned integers. Array size is 1 +* output_0 An array of unsigned integers. Array size is 1 +* +* Caveats: +* The output_slot_id and input_slot_id arguments must be +* constants available at compile time. Do not pass +* variables for these arguments. +* +* Since this is a macro, using it too many times will +* increase the size of your application. In such cases, +* or when this macro is too simplistic for your +* application you may want to create your own instance +* specific driver function (not a macro) using the +* macros defined in this file and the slot +* identifiers defined in xparameters.h . Please see the +* example code (fifo_link_app.c) for details. +*/ + +#define fifo_link(\ + input_slot_id,\ + output_slot_id,\ + input_0, \ + output_0 \ + )\ +{\ + int i;\ +\ + for (i=0; i<1; i++)\ + {\ + write_into_fsl(input_0[i], input_slot_id);\ + }\ +\ + for (i=0; i<1; i++)\ + {\ + read_from_fsl(output_0[i], output_slot_id);\ + }\ +} + +#endif Index: tags/STEP1_2b/mb-dct/ejpgl.h =================================================================== --- tags/STEP1_2b/mb-dct/ejpgl.h (nonexistent) +++ tags/STEP1_2b/mb-dct/ejpgl.h (revision 27) @@ -0,0 +1,10 @@ +#ifndef _EJPGL_H +#define _EJPGL_H + +#define MATRIX_SIZE 8 +#define MACRO_BLOCK_SIZE 16 + +int idct8x8(int* fblock, char* sblock); + +#endif + Index: tags/STEP1_2b/mb-dct/mb-dct.h =================================================================== --- tags/STEP1_2b/mb-dct/mb-dct.h (nonexistent) +++ tags/STEP1_2b/mb-dct/mb-dct.h (revision 27) @@ -0,0 +1,20 @@ + + +#include + +/* + Function Name: dct + + Operation: Find the 8x8 DCT of an array using separable DCT + First, finds 1-d DCT along rows, storing the result in inter[][] + Then, 1-d DCT along columns of inter[][] is found + + Input: pixels is the 8x8 input array + + Output: dct is the 8x8 output array +*/ + + + +void dct(signed char pixels[8][8], int color); + Index: tags/STEP1_2b/mb-dct/mb-weights.h =================================================================== --- tags/STEP1_2b/mb-dct/mb-weights.h (nonexistent) +++ tags/STEP1_2b/mb-dct/mb-weights.h (revision 27) @@ -0,0 +1,514 @@ +signed int weights[512] = { +16384, +16384, +16384, +16384, +16384, +16384, +16384, +16384, +16069, +13623, +9102, +3196, +-3196, +-9102, +-13623, +-16069, +15137, +6270, +-6270, +-15137, +-15137, +-6270, +6270, +15137, +13623, +-3196, +-16069, +-9103, +9102, +16069, +3196, +-13623, +11585, +-11585, +-11585, +11585, +11585, +-11585, +-11585, +11585, +9102, +-16069, +3196, +13623, +-13623, +-3197, +16069, +-9102, +6270, +-15137, +15137, +-6270, +-6270, +15137, +-15137, +6270, +3196, +-9103, +13623, +-16069, +16069, +-13623, +9102, +-3196, +16384, +16384, +16384, +16384, +16384, +16384, +16384, +16384, +16069, +13623, +9102, +3196, +-3196, +-9102, +-13623, +-16069, +15137, +6270, +-6270, +-15137, +-15137, +-6270, +6270, +15137, +13623, +-3196, +-16069, +-9103, +9102, +16069, +3196, +-13623, +11585, +-11585, +-11585, +11585, +11585, +-11585, +-11585, +11585, +9102, +-16069, +3196, +13623, +-13623, +-3197, +16069, +-9102, +6270, +-15137, +15137, +-6270, +-6270, +15137, +-15137, +6270, +3196, +-9103, +13623, +-16069, +16069, +-13623, +9102, +-3196, +16384, +16384, +16384, +16384, +16384, +16384, +16384, +16384, +16069, +13623, +9102, +3196, +-3196, +-9102, +-13623, +-16069, +15137, +6270, +-6270, +-15137, +-15137, +-6270, +6270, +15137, +13623, +-3196, +-16069, +-9103, +9102, +16069, +3196, +-13623, +11585, +-11585, +-11585, +11585, +11585, +-11585, +-11585, +11585, +9102, +-16069, +3196, +13623, +-13623, +-3197, +16069, +-9102, +6270, +-15137, +15137, +-6270, +-6270, +15137, +-15137, +6270, +3196, +-9103, +13623, +-16069, +16069, +-13623, +9102, +-3196, +16384, +16384, +16384, +16384, +16384, +16384, +16384, +16384, +16069, +13623, +9102, +3196, +-3196, +-9102, +-13623, +-16069, +15137, +6270, +-6270, +-15137, +-15137, +-6270, +6270, +15137, +13623, +-3196, +-16069, +-9103, +9102, +16069, +3196, +-13623, +11585, +-11585, +-11585, +11585, +11585, +-11585, +-11585, +11585, +9102, +-16069, +3196, +13623, +-13623, +-3197, +16069, +-9102, +6270, +-15137, +15137, +-6270, +-6270, +15137, +-15137, +6270, +3196, +-9103, +13623, +-16069, +16069, +-13623, +9102, +-3196, +16384, +16384, +16384, +16384, +16384, +16384, +16384, +16384, +16069, +13623, +9102, +3196, +-3196, +-9102, +-13623, +-16069, +15137, +6270, +-6270, +-15137, +-15137, +-6270, +6270, +15137, +13623, +-3196, +-16069, +-9103, +9102, +16069, +3196, +-13623, +11585, +-11585, +-11585, +11585, +11585, +-11585, +-11585, +11585, +9102, +-16069, +3196, +13623, +-13623, +-3197, +16069, +-9102, +6270, +-15137, +15137, +-6270, +-6270, +15137, +-15137, +6270, +3196, +-9103, +13623, +-16069, +16069, +-13623, +9102, +-3196, +16384, +16384, +16384, +16384, +16384, +16384, +16384, +16384, +16069, +13623, +9102, +3196, +-3196, +-9102, +-13623, +-16069, +15137, +6270, +-6270, +-15137, +-15137, +-6270, +6270, +15137, +13623, +-3196, +-16069, +-9103, +9102, +16069, +3196, +-13623, +11585, +-11585, +-11585, +11585, +11585, +-11585, +-11585, +11585, +9102, +-16069, +3196, +13623, +-13623, +-3197, +16069, +-9102, +6270, +-15137, +15137, +-6270, +-6270, +15137, +-15137, +6270, +3196, +-9103, +13623, +-16069, +16069, +-13623, +9102, +-3196, +16384, +16384, +16384, +16384, +16384, +16384, +16384, +16384, +16069, +13623, +9102, +3196, +-3196, +-9102, +-13623, +-16069, +15137, +6270, +-6270, +-15137, +-15137, +-6270, +6270, +15137, +13623, +-3196, +-16069, +-9103, +9102, +16069, +3196, +-13623, +11585, +-11585, +-11585, +11585, +11585, +-11585, +-11585, +11585, +9102, +-16069, +3196, +13623, +-13623, +-3197, +16069, +-9102, +6270, +-15137, +15137, +-6270, +-6270, +15137, +-15137, +6270, +3196, +-9103, +13623, +-16069, +16069, +-13623, +9102, +-3196, +16384, +16384, +16384, +16384, +16384, +16384, +16384, +16384, +16069, +13623, +9102, +3196, +-3196, +-9102, +-13623, +-16069, +15137, +6270, +-6270, +-15137, +-15137, +-6270, +6270, +15137, +13623, +-3196, +-16069, +-9103, +9102, +16069, +3196, +-13623, +11585, +-11585, +-11585, +11585, +11585, +-11585, +-11585, +11585, +9102, +-16069, +3196, +13623, +-13623, +-3197, +16069, +-9102, +6270, +-15137, +15137, +-6270, +-6270, +15137, +-15137, +6270, +3196, +-9103, +13623, +-16069, +16069, +-13623, +9102, +-3196 +}; Index: tags/STEP1_2b/mb-vlc/mb-huffman.c =================================================================== --- tags/STEP1_2b/mb-vlc/mb-huffman.c (nonexistent) +++ tags/STEP1_2b/mb-vlc/mb-huffman.c (revision 27) @@ -0,0 +1,792 @@ +#pragma argsused +/* +Only encoder +This version works correctly, it is tested with testcase.jpg +The translation into real huffman codes works. +Changed: If huffman wants to send 0xFFxx (FF in one byte) than there must be 0x00 inserted between FF and xx +possible fault in finish send: +-must it be filled up with zeros? YES +-must it be filled up to one bye? or 2 byte? --> in this code there is filled up to 2 bytes, but I (joris) thinks this must be filled up to 1 byte. + still dont know +- 24-11-05 code clean up +- 24-11-05 tables added for color + + + +Block numbers: +Y = 0 +cb =1 +cr= 2 +*/ +//--------------------------------------------------------------------------- +#include "xparameters.h" +#include "xutil.h" +#include "mb_interface.h" +#include "fifo_link.h" + +#include "ejpgl.h" + + +#define XPAR_FSL_FIFO_LINK_0_INPUT_SLOT_ID 0 +#define XPAR_FSL_FIFO_LINK_0_OUTPUT_SLOT_ID 0 + + +static unsigned int vlc_remaining; +static unsigned char vlc_amount_remaining; +static unsigned char dcvalue[4]; // 3 is enough + +int vlc_init_start() { + + vlc_remaining=0x00; + vlc_amount_remaining=0x00; + memset(dcvalue, 0, 4); + return 0; + +} + +#if 0 +#define vlc_output_byte(c) put_char(c) +#endif + +void vlc_output_byte(unsigned char c) { + unsigned long result; + + result = c; + write_into_fsl(result, XPAR_FSL_FIFO_LINK_0_OUTPUT_SLOT_ID); + return; + +} + +#ifdef __MULTI_TASK + +void vlc_task() { + + +} + +#endif + +#ifdef __MULTI_PROCESSOR + +int main() { + + for (;;) { + + + } + +} + +#endif + +static unsigned char convertDCMagnitudeCLengthTable[16] = { + 0x02, 0x02, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x00, 0x00, 0x00, 0x00 +}; + +static unsigned short convertDCMagnitudeCOutTable[16] = { + 0x0000, 0x0001, 0x0002, 0x0006, 0x000e, 0x001e, 0x003e, 0x007e, + 0x00fe, 0x01fe, 0x03fe, 0x07fe, 0x0000, 0x0000, 0x0000, 0x0000 +}; + +void ConvertDCMagnitudeC(unsigned char magnitude,unsigned short int *out, unsigned short int *lenght) +{ + unsigned char len; + + if ((magnitude>16) || ((len=convertDCMagnitudeCLengthTable[magnitude])==0)) { +#ifndef __MICROBLAZE + printf("WAARDE STAAT NIET IN TABEL!!!!!!!!!!!!!!!!!!!!\n"); +#endif + } + *lenght = len; + *out = convertDCMagnitudeCOutTable[magnitude]; + +#if 0 + switch (magnitude) { + case 0x00 : *out=0x0000; *lenght=2; break; + case 0x01 : *out=0x0001; *lenght=2; break; + case 0x02 : *out=0x0002; *lenght=2; break; + case 0x03 : *out=0x0006; *lenght=3; break; + case 0x04 : *out=0x000e; *lenght=4; break; + case 0x05 : *out=0x001e; *lenght=5; break; + case 0x06 : *out=0x003e; *lenght=6; break; + case 0x07 : *out=0x007e; *lenght=7; break; + case 0x08 : *out=0x00fe; *lenght=8; break; + case 0x09 : *out=0x01fe; *lenght=9; break; + case 0x0a : *out=0x03fe; *lenght=10; break; + case 0x0b : *out=0x07fe; *lenght=11; break; + } +#endif + +} + +static unsigned char convertACMagnitudeCLengthTable[256] = { +0x02, 0x02, 0x03, 0x04, 0x05, 0x05, 0x06, 0x07, 0x09, 0x0a, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, // 00 - 0f +0x00, 0x04, 0x06, 0x08, 0x09, 0x0b, 0x0c, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 10 - 1f +0x00, 0x05, 0x08, 0x0a, 0x0c, 0x0f, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 20 - 2f +0x00, 0x05, 0x08, 0x0a, 0x0c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 30 - 3f +0x00, 0x06, 0x09, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 40 - 4f +0x00, 0x06, 0x0a, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 50 - 5f +0x00, 0x07, 0x0b, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 60 - 6f +0x00, 0x07, 0x0b, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 70 - 7f +0x00, 0x08, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 80 - 8f +0x00, 0x09, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 90 - 9f +0x00, 0x09, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // a0 - af +0x00, 0x09, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // b0 - bf +0x00, 0x09, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // c0 - cf +0x00, 0x0b, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // d0 - df +0x00, 0x0e, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // e0 - ef +0x0a, 0x0f, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +static unsigned short convertACMagnitudeCOutTable[256] = { +0x0000, 0x0001, 0x0004, 0x000a, 0x0018, 0x0019, 0x0038, 0x0078, 0x01f4, 0x03f6, 0x0ff4, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 00 - 0f +0x0000, 0x000b, 0x0039, 0x00f6, 0x01f5, 0x07f6, 0x0ff5, 0xff88, 0xff89, 0xff8a, 0xff8b, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 10 - 1f +0x0000, 0x001a, 0x00f7, 0x03f7, 0x0ff6, 0x7fc2, 0xff8c, 0xff8d, 0xff8e, 0xff8f, 0xff90, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 20 - 2f +0x0000, 0x001b, 0x00f8, 0x03f8, 0x0ff7, 0xff91, 0xff92, 0xff93, 0xff94, 0xff95, 0xff96, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 30 - 3f +0x0000, 0x003a, 0x01f6, 0xff97, 0xff98, 0xff99, 0xff9a, 0xff9b, 0xff9c, 0xff9d, 0xff9e, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 40 - 4f +0x0000, 0x003b, 0x03f9, 0xff9f, 0xffa0, 0xffa1, 0xFFA2, 0xFFA3, 0xFFA4, 0xFFA5, 0xFFA6, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 50 - 5f +0x0000, 0x0079, 0x07f7, 0xffa7, 0xffa8, 0xffa9, 0xffaa, 0xffab, 0xFFAc, 0xFFAf, 0xFFAe, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 60 - 6f +0x0000, 0x007a, 0x07f8, 0xffaf, 0xffb0, 0xFFB1, 0xFFB2, 0xFFB3, 0xFFB4, 0xFFB5, 0xFFB6, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 70 - 7f +0x0000, 0x00f9, 0xffb7, 0xFFB8, 0xFFB9, 0xFFBa, 0xFFBb, 0xFFBc, 0xFFBd, 0xFFBe, 0xFFBf, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 80 - 8f +0x0000, 0x01f7, 0xffc0, 0xffc1, 0xFFC2, 0xFFC3, 0xFFC4, 0xFFC5, 0xFFC6, 0xFFC7, 0xFFC8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 90 - 9f +0x0000, 0x01f8, 0xffc9, 0xFFCa, 0xFFCb, 0xFFCc, 0xFFCd, 0xFFCe, 0xFFCf, 0xFFd0, 0xFFd1, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // a0 - af +0x0000, 0x01f9, 0xFFD2, 0xFFD3, 0xFFD4, 0xFFD5, 0xFFD6, 0xFFD7, 0xFFD8, 0xFFD9, 0xFFDa, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // b0 - bf +0x0000, 0x01fa, 0xFFDb, 0xFFDc, 0xFFDd, 0xFFDe, 0xFFDf, 0xFFe0, 0xFFe1, 0xFFe2, 0xFFe3, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // c0 - cf +0x0000, 0x07f9, 0xFFE4, 0xFFE5, 0xFFE6, 0xFFE7, 0xFFE8, 0xFFE9, 0xFFEa, 0xFFEb, 0xFFEc, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // d0 - df +0x0000, 0x3fe0, 0xffed, 0xFFEe, 0xFFEf, 0xFFf0, 0xFFF1, 0xFFF2, 0xFFF3, 0xFFF4, 0xFFF5, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // e0 - ef +0x03fa, 0x7fc3, 0xFFF6, 0xFFF7, 0xFFF8, 0xFFF9, 0xFFFA, 0xFFFB, 0xFFFC, 0xFFFD, 0xFFFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 +}; + +//=========================================================================== +void ConvertACMagnitudeC(unsigned char magnitude,unsigned short int *out, unsigned short int *lenght) +{ + unsigned char len; + + len = convertACMagnitudeCLengthTable[magnitude]; + if (!len) { +#ifndef __MICROBLAZE + printf("WAARDE STAAT NIET IN TABEL!!!!!!!!!!!!!!!!!!!!\n"); +#endif + } + *lenght = len; + *out = convertACMagnitudeCOutTable[magnitude]; + +#if 0 + switch (magnitude) { +case 0x00 : *lenght=0x02; *out=0x0000; break; //1010 +case 0x01 : *lenght=0x02; *out=0x0001; break; //00 +case 0x02 : *lenght=0x03; *out=0x0004; break; //01 +case 0x03 : *lenght=0x04; *out=0x000a; break; //100 +case 0x04 : *lenght=0x05; *out=0x0018; break; //1011 +case 0x05 : *lenght=0x05; *out=0x0019; break; //11010 +case 0x06 : *lenght=0x06; *out=0x0038; break; //1111000 +case 0x07 : *lenght=0x07; *out=0x0078; break; //11111000 +case 0x08 : *lenght=0x09; *out=0x01f4; break; //1111110110 +case 0x09 : *lenght=0x0a; *out=0x03f6; break; //1111111110000010 +case 0x0A : *lenght=0x0c; *out=0x0ff4; break; //1111111110000011 +case 0x11 : *lenght=0x04; *out=0x000b; break; //1100 +case 0x12 : *lenght=0x06; *out=0x0039; break; //11011 +case 0x13 : *lenght=0x08; *out=0x00f6; break; //1111001 +case 0x14 : *lenght=0x09; *out=0x01f5; break; //111110110 +case 0x15 : *lenght=0x0b; *out=0x07f6; break; //11111110110 +case 0x16 : *lenght=0x0c; *out=0x0ff5; break; //1111111110000100 +case 0x17 : *lenght=0x10; *out=0xff88; break; //1111111110000101 +case 0x18 : *lenght=0x10; *out=0xff89; break; //1111111110000110 +case 0x19 : *lenght=0x10; *out=0xff8a; break; //1111111110000111 +case 0x1A : *lenght=0x10; *out=0xff8b; break; //1111111110001000 +case 0x21 : *lenght=0x05; *out=0x001a; break; //11100 +case 0x22 : *lenght=0x08; *out=0x00f7; break; //11111001 +case 0x23 : *lenght=0x0a; *out=0x03f7; break; //1111110111 +case 0x24 : *lenght=0x0c; *out=0x0ff6; break; //111111110100 +case 0x25 : *lenght=0x0f; *out=0x7fc2; break; //1111111110001001 +case 0x26 : *lenght=0x10; *out=0xff8c; break; //1111111110001010 +case 0x27 : *lenght=0x10; *out=0xff8d; break; //1111111110001011 +case 0x28 : *lenght=0x10; *out=0xff8e; break; //1111111110001100 +case 0x29 : *lenght=0x10; *out=0xff8f; break; //1111111110001101 +case 0x2A : *lenght=0x10; *out=0xff90; break; //1111111110001110 +case 0x31 : *lenght=0x05; *out=0x001b; break; //111010 +case 0x32 : *lenght=0x08; *out=0x00f8; break; //111110111 +case 0x33 : *lenght=0x0a; *out=0x03f8; break; //111111110101 +case 0x34 : *lenght=0x0c; *out=0x0ff7; break; //1111111110001111 +case 0x35 : *lenght=0x10; *out=0xff91; break; //1111111110010000 +case 0x36 : *lenght=0x10; *out=0xff92; break; //1111111110010001 +case 0x37 : *lenght=0x10; *out=0xff93; break; //1111111110010010 +case 0x38 : *lenght=0x10; *out=0xff94; break; //1111111110010011 +case 0x39 : *lenght=0x10; *out=0xff95; break; //1111111110010100 +case 0x3A : *lenght=0x10; *out=0xff96; break; //1111111110010101 +case 0x41 : *lenght=0x06; *out=0x003a; break; //111011 +case 0x42 : *lenght=0x09; *out=0x01f6; break; //1111111000 +case 0x43 : *lenght=0x10; *out=0xff97; break; //1111111110010110 +case 0x44 : *lenght=0x10; *out=0xff98; break; //1111111110010111 +case 0x45 : *lenght=0x10; *out=0xff99; break; //1111111110011000 +case 0x46 : *lenght=0x10; *out=0xff9a; break; //1111111110011001 +case 0x47 : *lenght=0x10; *out=0xff9b; break; //1111111110011010 +case 0x48 : *lenght=0x10; *out=0xff9c; break; //1111111110011011 +case 0x49 : *lenght=0x10; *out=0xff9d; break; //1111111110011100 +case 0x4A : *lenght=0x10; *out=0xff9e; break; //1111111110011101 +case 0x51 : *lenght=0x06; *out=0x003b; break; //1111010 +case 0x52 : *lenght=0x0a; *out=0x03f9; break; //11111110111 +case 0x53 : *lenght=0x10; *out=0xff9f; break; //1111111110011110 +case 0x54 : *lenght=0x10; *out=0xffa0; break; //1111111110011111 +case 0x55 : *lenght=0x10; *out=0xffa1; break; //1111111110100000 +case 0x56 : *lenght=0x10; *out=0xFFA2; break; //1111111110100001 +case 0x57 : *lenght=0x10; *out=0xFFA3; break; //1111111110100010 +case 0x58 : *lenght=0x10; *out=0xFFA4; break; //1111111110100011 +case 0x59 : *lenght=0x10; *out=0xFFA5; break; //1111111110100100 +case 0x5A : *lenght=0x10; *out=0xFFA6; break; //1111111110100101 +case 0x61 : *lenght=0x07; *out=0x0079; break; //1111011 +case 0x62 : *lenght=0x0b; *out=0x07f7; break; //111111110110 +case 0x63 : *lenght=0x10; *out=0xffa7; break; //1111111110100110 +case 0x64 : *lenght=0x10; *out=0xffa8; break; //1111111110100111 +case 0x65 : *lenght=0x10; *out=0xffa9; break; //1111111110101000 +case 0x66 : *lenght=0x10; *out=0xffaa; break; //1111111110101001 +case 0x67 : *lenght=0x10; *out=0xffab; break; //1111111110101010 +case 0x68 : *lenght=0x10; *out=0xFFAc; break; //1111111110101011 +case 0x69 : *lenght=0x10; *out=0xFFAf; break; //1111111110101100 +case 0x6A : *lenght=0x10; *out=0xFFAe; break; //1111111110101101 +case 0x71 : *lenght=0x07; *out=0x007a; break; //11111010 +case 0x72 : *lenght=0x0b; *out=0x07f8; break; //111111110111 +case 0x73 : *lenght=0x10; *out=0xffaf; break; //1111111110101110 +case 0x74 : *lenght=0x10; *out=0xffb0; break; //1111111110101111 +case 0x75 : *lenght=0x10; *out=0xFFB1; break; //1111111110110000 +case 0x76 : *lenght=0x10; *out=0xFFB2; break; //111111110110001 +case 0x77 : *lenght=0x10; *out=0xFFB3; break; //111111110110010 +case 0x78 : *lenght=0x10; *out=0xFFB4; break; //111111110110011 +case 0x79 : *lenght=0x10; *out=0xFFB5; break; //1111111110110100 +case 0x7A : *lenght=0x10; *out=0xFFB6; break; //1111111110110101 +case 0x81 : *lenght=0x08; *out=0x00f9; break; //111111000 +case 0x82 : *lenght=0x10; *out=0xffb7; break; //111111111000000 +case 0x83 : *lenght=0x10; *out=0xFFB8; break; //1111111110110110 +case 0x84 : *lenght=0x10; *out=0xFFB9; break; //1111111110110111 +case 0x85 : *lenght=0x10; *out=0xFFBa; break; //1111111110111000 +case 0x86 : *lenght=0x10; *out=0xFFBb; break; //1111111110111001 +case 0x87 : *lenght=0x10; *out=0xFFBc; break; //1111111110111010 +case 0x88 : *lenght=0x10; *out=0xFFBd; break; //1111111110111011 +case 0x89 : *lenght=0x10; *out=0xFFBe; break; //1111111110111100 +case 0x8A : *lenght=0x10; *out=0xFFBf; break; //1111111110111101 +case 0x91 : *lenght=0x09; *out=0x01f7; break; //111111001 +case 0x92 : *lenght=0x10; *out=0xffc0; break; //1111111110111110 +case 0x93 : *lenght=0x10; *out=0xffc1; break; //1111111110111111 +case 0x94 : *lenght=0x10; *out=0xFFC2; break; //1111111111000000 +case 0x95 : *lenght=0x10; *out=0xFFC3; break; //1111111111000001 +case 0x96 : *lenght=0x10; *out=0xFFC4; break; //1111111111000010 +case 0x97 : *lenght=0x10; *out=0xFFC5; break; //1111111111000011 +case 0x98 : *lenght=0x10; *out=0xFFC6; break; //1111111111000100 +case 0x99 : *lenght=0x10; *out=0xFFC7; break; //1111111111000101 +case 0x9A : *lenght=0x10; *out=0xFFC8; break; //1111111111000110 +case 0xA1 : *lenght=0x09; *out=0x01f8; break; //111111010 +case 0xA2 : *lenght=0x10; *out=0xffc9; break; //1111111111000111 +case 0xA3 : *lenght=0x10; *out=0xFFCa; break; //1111111111001000 +case 0xA4 : *lenght=0x10; *out=0xFFCb; break; //1111111111001001 +case 0xA5 : *lenght=0x10; *out=0xFFCc; break; //1111111111001010 +case 0xA6 : *lenght=0x10; *out=0xFFCd; break; //1111111111001011 +case 0xA7 : *lenght=0x10; *out=0xFFCe; break; //1111111111001100 +case 0xA8 : *lenght=0x10; *out=0xFFCf; break; //1111111111001101 +case 0xA9 : *lenght=0x10; *out=0xFFd0; break; //1111111111001110 +case 0xAA : *lenght=0x10; *out=0xFFd1; break; //1111111111001111 +case 0xB1 : *lenght=0x09; *out=0x01f9; break; //1111111001 +case 0xB2 : *lenght=0x10; *out=0xFFD2; break; //1111111111010000 +case 0xB3 : *lenght=0x10; *out=0xFFD3; break; //1111111111010001 +case 0xB4 : *lenght=0x10; *out=0xFFD4; break; //1111111111010010 +case 0xB5 : *lenght=0x10; *out=0xFFD5; break; //1111111111010011 +case 0xB6 : *lenght=0x10; *out=0xFFD6; break; //1111111111010100 +case 0xB7 : *lenght=0x10; *out=0xFFD7; break; //1111111111010101 +case 0xB8 : *lenght=0x10; *out=0xFFD8; break; //1111111111010110 +case 0xB9 : *lenght=0x10; *out=0xFFD9; break; //1111111111010111 +case 0xBA : *lenght=0x10; *out=0xFFDa; break; //1111111111011000 +case 0xC1 : *lenght=0x09; *out=0x01fa; break; //1111111010 +case 0xC2 : *lenght=0x10; *out=0xFFDb; break; //1111111111011001 +case 0xC3 : *lenght=0x10; *out=0xFFDc; break; //1111111111011010 +case 0xC4 : *lenght=0x10; *out=0xFFDd; break; //1111111111011011 +case 0xC5 : *lenght=0x10; *out=0xFFDe; break; //1111111111011100 +case 0xC6 : *lenght=0x10; *out=0xFFDf; break; //1111111111011101 +case 0xC7 : *lenght=0x10; *out=0xFFe0; break; //1111111111011110 +case 0xC8 : *lenght=0x10; *out=0xFFe1; break; //1111111111011111 +case 0xC9 : *lenght=0x10; *out=0xFFe2; break; //1111111111100000 +case 0xCA : *lenght=0x10; *out=0xFFe3; break; //1111111111100001 +case 0xD1 : *lenght=0x0b; *out=0x07f9; break; //11111111000 +case 0xD2 : *lenght=0x10; *out=0xFFE4; break; //1111111111100010 +case 0xD3 : *lenght=0x10; *out=0xFFE5; break; //1111111111100011 +case 0xD4 : *lenght=0x10; *out=0xFFE6; break; //1111111111100100 +case 0xD5 : *lenght=0x10; *out=0xFFE7; break; //1111111111100101 +case 0xD6 : *lenght=0x10; *out=0xFFE8; break; //1111111111100110 +case 0xD7 : *lenght=0x10; *out=0xFFE9; break; //1111111111100111 +case 0xD8 : *lenght=0x10; *out=0xFFEa; break; //1111111111101000 +case 0xD9 : *lenght=0x10; *out=0xFFEb; break; //1111111111101001 +case 0xDA : *lenght=0x10; *out=0xFFEc; break; //1111111111101010 +case 0xE1 : *lenght=0x0e; *out=0x3fe0; break; //1111111111101011 +case 0xE2 : *lenght=0x10; *out=0xffed; break; //1111111111101100 +case 0xE3 : *lenght=0x10; *out=0xFFEe; break; //1111111111101101 +case 0xE4 : *lenght=0x10; *out=0xFFEf; break; //1111111111101110 +case 0xE5 : *lenght=0x10; *out=0xFFf0; break; //1111111111101111 +case 0xE6 : *lenght=0x10; *out=0xFFF1; break; //1111111111110000 +case 0xE7 : *lenght=0x10; *out=0xFFF2; break; //1111111111110001 +case 0xE8 : *lenght=0x10; *out=0xFFF3; break; //1111111111110010 +case 0xE9 : *lenght=0x10; *out=0xFFF4; break; //1111111111110011 +case 0xEA : *lenght=0x10; *out=0xFFF5; break; //1111111111110100 +case 0xF0 : *lenght=0x0a; *out=0x03fa; break; //11111111001 +case 0xF1 : *lenght=0x0f; *out=0x7fc3; break; //1111111111110101 +case 0xF2 : *lenght=0x10; *out=0xFFF6; break; //1111111111110110 +case 0xF3 : *lenght=0x10; *out=0xFFF7; break; //1111111111110111 +case 0xF4 : *lenght=0x10; *out=0xFFF8; break; //1111111111111000 +case 0xF5 : *lenght=0x10; *out=0xFFF9; break; //1111111111111001 +case 0xF6 : *lenght=0x10; *out=0xFFFA; break; //1111111111111010 +case 0xF7 : *lenght=0x10; *out=0xFFFB; break; //1111111111111011 +case 0xF8 : *lenght=0x10; *out=0xFFFC; break; //1111111111111100 +case 0xF9 : *lenght=0x10; *out=0xFFFD; break; //1111111111111101 +case 0xFA : *lenght=0x10; *out=0xFFFE; break; //1111111111111110 +#ifndef __MICROBLAZE +default : printf("WAARDE STAAT NIET IN TABEL!!!!!!!!!!!!!!!!!!!!\n");break; +#endif + } + // printf("magnitude= %x out= %x lenght= %d \n",magnitude,*out,*lenght); + return; +#endif + + +} + +static unsigned char convertDCMagnitudeYLengthTable[16] = { +0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x04, 0x05, +0x06, 0x07, 0x08, 0x09, 0x00, 0x00, 0x00, 0x00 +}; + +static unsigned short convertDCMagnitudeYOutTable[16] = { +0x0000, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x000e, 0x001e, +0x003e, 0x007e, 0x00fe, 0x01fe, 0x0000, 0x0000, 0x0000, 0x0000 +}; + +//=========================================================================== +void ConvertDCMagnitudeY(unsigned char magnitude,unsigned short int *out, unsigned short int *lenght) +{ + unsigned char len; + + if ((magnitude>16) || ((len=convertDCMagnitudeYLengthTable[magnitude])==0)) { +#ifndef __MICROBLAZE + printf("WAARDE STAAT NIET IN TABEL!!!!!!!!!!!!!!!!!!!!\n"); +#endif + } + *lenght = len; + *out = convertDCMagnitudeYOutTable[magnitude]; +#if 0 + switch (magnitude) { + case 0x00 : *out=0x0000; *lenght=2; break; + case 0x01 : *out=0x0002; *lenght=3; break; + case 0x02 : *out=0x0003; *lenght=3; break; + case 0x03 : *out=0x0004; *lenght=3; break; + case 0x04 : *out=0x0005; *lenght=3; break; + case 0x05 : *out=0x0006; *lenght=3; break; + case 0x06 : *out=0x000e; *lenght=4; break; + case 0x07 : *out=0x001e; *lenght=5; break; + case 0x08 : *out=0x003e; *lenght=6; break; + case 0x09 : *out=0x007e; *lenght=7; break; + case 0x0a : *out=0x00fe; *lenght=8; break; + case 0x0b : *out=0x01fe; *lenght=9; break; + } +#endif +} + +static unsigned char convertACMagnitudeYLength[256] = { +0x04, 0x02, 0x02, 0x03, 0x04, 0x05, 0x07, 0x08, 0x0a, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 00 - 0f +0x00, 0x04, 0x05, 0x07, 0x09, 0x0b, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 10 - 1f +0x00, 0x05, 0x08, 0x0a, 0x0c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 20 - 2f +0x00, 0x06, 0x09, 0x0c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 30 - 3f +0x00, 0x06, 0x0a, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 40 - 4f +0x00, 0x07, 0x0b, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 50 - 5f +0x00, 0x07, 0x0c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 60 - 6f +0x00, 0x08, 0x0c, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 70 - 7f +0x00, 0x09, 0x0f, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 80 - 8f +0x00, 0x09, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 90 - 9f +0x00, 0x09, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // a0 - af +0x00, 0x0a, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // b0 - bf +0x00, 0x0a, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // c0 - cf +0x00, 0x0b, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // d0 - df +0x00, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // e0 - ef +0x0b, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +static unsigned short convertACMagnitudeYOut[256] = { +0xFFFA, 0xFFF0, 0xFFF1, 0xFFF4, 0xFFFB, 0xFFFA, 0xFFF8, 0xFFF8, 0xFFF6, 0xFF82, 0xFF83, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 00 - 0f +0x0000, 0xFFFC, 0xFFFB, 0xFFF9, 0xFFF6, 0xFFF6, 0xFF84, 0xFF85, 0xFF86, 0xFF87, 0xFF88, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 10 - 1f +0x0000, 0xFFFC, 0xFFF9, 0xFFF7, 0xFFF4, 0xFF89, 0xFF8A, 0xFF8B, 0xFF8C, 0xFF8D, 0xFF8E, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 20 - 2f +0x0000, 0xFFFA, 0xFFF7, 0xFFF5, 0xFF8F, 0xFF90, 0xFF91, 0xFF92, 0xFF93, 0xFF94, 0xFF95, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 30 - 3f +0x0000, 0xFFFB, 0xFFF8, 0xFF96, 0xFF97, 0xFF98, 0xFF99, 0xFF9A, 0xFF9B, 0xFF9C, 0xFF9D, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 40 - 4f +0x0000, 0xFFFA, 0xFFF7, 0xFF9E, 0xFF9F, 0xFFA0, 0xFFA1, 0xFFA2, 0xFFA3, 0xFFA4, 0xFFA5, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 50 - 5f +0x0000, 0xFFFB, 0xFFF6, 0xFFA6, 0xFFA7, 0xFFA8, 0xFFA9, 0xFFAA, 0xFFAB, 0xFFAC, 0xFFAD, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 60 - 6f +0x0000, 0xFFFA, 0xFFF7, 0xFFAE, 0xFFAF, 0xFFB0, 0xFFB1, 0xFFB2, 0xFFB3, 0xFFB4, 0xFFB5, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 70 - 7f +0x0000, 0xFFF8, 0xFFC0, 0xFFB6, 0xFFB7, 0xFFB8, 0xFFB9, 0xFFBA, 0xFFBB, 0xFFBC, 0xFFBD, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 80 - 8f +0x0000, 0xFFF9, 0xFFBE, 0xFFBF, 0xFFC0, 0xFFC1, 0xFFC2, 0xFFC3, 0xFFC4, 0xFFC5, 0xFFC6, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 90 - 9f +0x0000, 0xFFFA, 0xFFC7, 0xFFC8, 0xFFC9, 0xFFCA, 0xFFCB, 0xFFCC, 0xFFCD, 0xFFCE, 0xFFCF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // a0 - af +0x0000, 0xFFF9, 0xFFD0, 0xFFD1, 0xFFD2, 0xFFD3, 0xFFD4, 0xFFD5, 0xFFD6, 0xFFD7, 0xFFD8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // b0 - bf +0x0000, 0xFFFA, 0xFFD9, 0xFFDA, 0xFFDB, 0xFFDC, 0xFFDD, 0xFFDE, 0xFFDF, 0xFFE0, 0xFFE1, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // c0 - cf +0x0000, 0xFFF8, 0xFFE2, 0xFFE3, 0xFFE4, 0xFFE5, 0xFFE6, 0xFFE7, 0xFFE8, 0xFFE9, 0xFFEA, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // d0 - df +0x0000, 0xFFEB, 0xFFEC, 0xFFED, 0xFFEE, 0xFFEF, 0xFFF0, 0xFFF1, 0xFFF2, 0xFFF3, 0xFFF4, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // e0 - ef +0xFFF9, 0xFFF5, 0xFFF6, 0xFFF7, 0xFFF8, 0xFFF9, 0xFFFA, 0xFFFB, 0xFFFC, 0xFFFD, 0xFFFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 +}; + +//=========================================================================== +void ConvertACMagnitudeY(unsigned char magnitude,unsigned short int *out, unsigned short int *lenght) +{ + unsigned char len; + + len = convertACMagnitudeYLength[magnitude]; + if (!len) { +#ifndef __MICROBLAZE + printf("WAARDE STAAT NIET IN TABEL!!!!!!!!!!!!!!!!!!!!\n"); +#endif + } + *lenght = len; + *out = convertACMagnitudeYOut[magnitude]; + +#if 0 + switch (magnitude) { +case 0x00 : *lenght=4; *out=0xFFFA; break; //1010 +case 0x01 : *lenght=2; *out=0xFFF0; break; //00 +case 0x02 : *lenght=2; *out=0xFFF1; break; //01 +case 0x03 : *lenght=3; *out=0xFFF4; break; //100 +case 0x04 : *lenght=4; *out=0xFFFB; break; //1011 +case 0x05 : *lenght=5; *out=0xFFFA; break; //11010 +case 0x06 : *lenght=7; *out=0xFFF8; break; //1111000 +case 0x07 : *lenght=8; *out=0xFFF8; break; //11111000 +case 0x08 : *lenght=10; *out=0xFFF6; break; //1111110110 +case 0x09 : *lenght=16; *out=0xFF82; break; //1111111110000010 +case 0x0A : *lenght=16; *out=0xFF83; break; //1111111110000011 +case 0x11 : *lenght=4; *out=0xFFFC; break; //1100 +case 0x12 : *lenght=5; *out=0xFFFB; break; //11011 +case 0x13 : *lenght=7; *out=0xFFF9; break; //1111001 +case 0x14 : *lenght=9; *out=0xFFF6; break; //111110110 +case 0x15 : *lenght=11; *out=0xFFF6; break; //11111110110 +case 0x16 : *lenght=16; *out=0xFF84; break; //1111111110000100 +case 0x17 : *lenght=16; *out=0xFF85; break; //1111111110000101 +case 0x18 : *lenght=16; *out=0xFF86; break; //1111111110000110 +case 0x19 : *lenght=16; *out=0xFF87; break; //1111111110000111 +case 0x1A : *lenght=16; *out=0xFF88; break; //1111111110001000 +case 0x21 : *lenght=5; *out=0xFFFC; break; //11100 +case 0x22 : *lenght=8; *out=0xFFF9; break; //11111001 +case 0x23 : *lenght=10; *out=0xFFF7; break; //1111110111 +case 0x24 : *lenght=12; *out=0xFFF4; break; //111111110100 +case 0x25 : *lenght=16; *out=0xFF89; break; //1111111110001001 +case 0x26 : *lenght=16; *out=0xFF8A; break; //1111111110001010 +case 0x27 : *lenght=16; *out=0xFF8B; break; //1111111110001011 +case 0x28 : *lenght=16; *out=0xFF8C; break; //1111111110001100 +case 0x29 : *lenght=16; *out=0xFF8D; break; //1111111110001101 +case 0x2A : *lenght=16; *out=0xFF8E; break; //1111111110001110 +case 0x31 : *lenght=6; *out=0xFFFA; break; //111010 +case 0x32 : *lenght=9; *out=0xFFF7; break; //111110111 +case 0x33 : *lenght=12; *out=0xFFF5; break; //111111110101 +case 0x34 : *lenght=16; *out=0xFF8F; break; //1111111110001111 +case 0x35 : *lenght=16; *out=0xFF90; break; //1111111110010000 +case 0x36 : *lenght=16; *out=0xFF91; break; //1111111110010001 +case 0x37 : *lenght=16; *out=0xFF92; break; //1111111110010010 +case 0x38 : *lenght=16; *out=0xFF93; break; //1111111110010011 +case 0x39 : *lenght=16; *out=0xFF94; break; //1111111110010100 +case 0x3A : *lenght=16; *out=0xFF95; break; //1111111110010101 +case 0x41 : *lenght=6; *out=0xFFFB; break; //111011 +case 0x42 : *lenght=10; *out=0xFFF8; break; //1111111000 +case 0x43 : *lenght=16; *out=0xFF96; break; //1111111110010110 +case 0x44 : *lenght=16; *out=0xFF97; break; //1111111110010111 +case 0x45 : *lenght=16; *out=0xFF98; break; //1111111110011000 +case 0x46 : *lenght=16; *out=0xFF99; break; //1111111110011001 +case 0x47 : *lenght=16; *out=0xFF9A; break; //1111111110011010 +case 0x48 : *lenght=16; *out=0xFF9B; break; //1111111110011011 +case 0x49 : *lenght=16; *out=0xFF9C; break; //1111111110011100 +case 0x4A : *lenght=16; *out=0xFF9D; break; //1111111110011101 +case 0x51 : *lenght=7; *out=0xFFFA; break; //1111010 +case 0x52 : *lenght=11; *out=0xFFF7; break; //11111110111 +case 0x53 : *lenght=16; *out=0xFF9E; break; //1111111110011110 +case 0x54 : *lenght=16; *out=0xFF9F; break; //1111111110011111 +case 0x55 : *lenght=16; *out=0xFFA0; break; //1111111110100000 +case 0x56 : *lenght=16; *out=0xFFA1; break; //1111111110100001 +case 0x57 : *lenght=16; *out=0xFFA2; break; //1111111110100010 +case 0x58 : *lenght=16; *out=0xFFA3; break; //1111111110100011 +case 0x59 : *lenght=16; *out=0xFFA4; break; //1111111110100100 +case 0x5A : *lenght=16; *out=0xFFA5; break; //1111111110100101 +case 0x61 : *lenght=7; *out=0xFFFB; break; //1111011 +case 0x62 : *lenght=12; *out=0xFFF6; break; //111111110110 +case 0x63 : *lenght=16; *out=0xFFA6; break; //1111111110100110 +case 0x64 : *lenght=16; *out=0xFFA7; break; //1111111110100111 +case 0x65 : *lenght=16; *out=0xFFA8; break; //1111111110101000 +case 0x66 : *lenght=16; *out=0xFFA9; break; //1111111110101001 +case 0x67 : *lenght=16; *out=0xFFAA; break; //1111111110101010 +case 0x68 : *lenght=16; *out=0xFFAB; break; //1111111110101011 +case 0x69 : *lenght=16; *out=0xFFAC; break; //1111111110101100 +case 0x6A : *lenght=16; *out=0xFFAD; break; //1111111110101101 +case 0x71 : *lenght=8; *out=0xFFFA; break; //11111010 +case 0x72 : *lenght=12; *out=0xFFF7; break; //111111110111 +case 0x73 : *lenght=16; *out=0xFFAE; break; //1111111110101110 +case 0x74 : *lenght=16; *out=0xFFAF; break; //1111111110101111 +case 0x75 : *lenght=16; *out=0xFFB0; break; //1111111110110000 +case 0x76 : *lenght=16; *out=0xFFB1; break; //111111110110001 +case 0x77 : *lenght=16; *out=0xFFB2; break; //111111110110010 +case 0x78 : *lenght=16; *out=0xFFB3; break; //111111110110011 +case 0x79 : *lenght=16; *out=0xFFB4; break; //1111111110110100 +case 0x7A : *lenght=16; *out=0xFFB5; break; //1111111110110101 +case 0x81 : *lenght=9; *out=0xFFF8; break; //111111000 +case 0x82 : *lenght=15; *out=0xFFC0; break; //111111111000000 +case 0x83 : *lenght=16; *out=0xFFB6; break; //1111111110110110 +case 0x84 : *lenght=16; *out=0xFFB7; break; //1111111110110111 +case 0x85 : *lenght=16; *out=0xFFB8; break; //1111111110111000 +case 0x86 : *lenght=16; *out=0xFFB9; break; //1111111110111001 +case 0x87 : *lenght=16; *out=0xFFBA; break; //1111111110111010 +case 0x88 : *lenght=16; *out=0xFFBB; break; //1111111110111011 +case 0x89 : *lenght=16; *out=0xFFBC; break; //1111111110111100 +case 0x8A : *lenght=16; *out=0xFFBD; break; //1111111110111101 +case 0x91 : *lenght=9; *out=0xFFF9; break; //111111001 +case 0x92 : *lenght=16; *out=0xFFBE; break; //1111111110111110 +case 0x93 : *lenght=16; *out=0xFFBF; break; //1111111110111111 +case 0x94 : *lenght=16; *out=0xFFC0; break; //1111111111000000 +case 0x95 : *lenght=16; *out=0xFFC1; break; //1111111111000001 +case 0x96 : *lenght=16; *out=0xFFC2; break; //1111111111000010 +case 0x97 : *lenght=16; *out=0xFFC3; break; //1111111111000011 +case 0x98 : *lenght=16; *out=0xFFC4; break; //1111111111000100 +case 0x99 : *lenght=16; *out=0xFFC5; break; //1111111111000101 +case 0x9A : *lenght=16; *out=0xFFC6; break; //1111111111000110 +case 0xA1 : *lenght=9; *out=0xFFFA; break; //111111010 +case 0xA2 : *lenght=16; *out=0xFFC7; break; //1111111111000111 +case 0xA3 : *lenght=16; *out=0xFFC8; break; //1111111111001000 +case 0xA4 : *lenght=16; *out=0xFFC9; break; //1111111111001001 +case 0xA5 : *lenght=16; *out=0xFFCA; break; //1111111111001010 +case 0xA6 : *lenght=16; *out=0xFFCB; break; //1111111111001011 +case 0xA7 : *lenght=16; *out=0xFFCC; break; //1111111111001100 +case 0xA8 : *lenght=16; *out=0xFFCD; break; //1111111111001101 +case 0xA9 : *lenght=16; *out=0xFFCE; break; //1111111111001110 +case 0xAA : *lenght=16; *out=0xFFCF; break; //1111111111001111 +case 0xB1 : *lenght=10; *out=0xFFF9; break; //1111111001 +case 0xB2 : *lenght=16; *out=0xFFD0; break; //1111111111010000 +case 0xB3 : *lenght=16; *out=0xFFD1; break; //1111111111010001 +case 0xB4 : *lenght=16; *out=0xFFD2; break; //1111111111010010 +case 0xB5 : *lenght=16; *out=0xFFD3; break; //1111111111010011 +case 0xB6 : *lenght=16; *out=0xFFD4; break; //1111111111010100 +case 0xB7 : *lenght=16; *out=0xFFD5; break; //1111111111010101 +case 0xB8 : *lenght=16; *out=0xFFD6; break; //1111111111010110 +case 0xB9 : *lenght=16; *out=0xFFD7; break; //1111111111010111 +case 0xBA : *lenght=16; *out=0xFFD8; break; //1111111111011000 +case 0xC1 : *lenght=10; *out=0xFFFA; break; //1111111010 +case 0xC2 : *lenght=16; *out=0xFFD9; break; //1111111111011001 +case 0xC3 : *lenght=16; *out=0xFFDA; break; //1111111111011010 +case 0xC4 : *lenght=16; *out=0xFFDB; break; //1111111111011011 +case 0xC5 : *lenght=16; *out=0xFFDC; break; //1111111111011100 +case 0xC6 : *lenght=16; *out=0xFFDD; break; //1111111111011101 +case 0xC7 : *lenght=16; *out=0xFFDE; break; //1111111111011110 +case 0xC8 : *lenght=16; *out=0xFFDF; break; //1111111111011111 +case 0xC9 : *lenght=16; *out=0xFFE0; break; //1111111111100000 +case 0xCA : *lenght=16; *out=0xFFE1; break; //1111111111100001 +case 0xD1 : *lenght=11; *out=0xFFF8; break; //11111111000 +case 0xD2 : *lenght=16; *out=0xFFE2; break; //1111111111100010 +case 0xD3 : *lenght=16; *out=0xFFE3; break; //1111111111100011 +case 0xD4 : *lenght=16; *out=0xFFE4; break; //1111111111100100 +case 0xD5 : *lenght=16; *out=0xFFE5; break; //1111111111100101 +case 0xD6 : *lenght=16; *out=0xFFE6; break; //1111111111100110 +case 0xD7 : *lenght=16; *out=0xFFE7; break; //1111111111100111 +case 0xD8 : *lenght=16; *out=0xFFE8; break; //1111111111101000 +case 0xD9 : *lenght=16; *out=0xFFE9; break; //1111111111101001 +case 0xDA : *lenght=16; *out=0xFFEA; break; //1111111111101010 +case 0xE1 : *lenght=16; *out=0xFFEB; break; //1111111111101011 +case 0xE2 : *lenght=16; *out=0xFFEC; break; //1111111111101100 +case 0xE3 : *lenght=16; *out=0xFFED; break; //1111111111101101 +case 0xE4 : *lenght=16; *out=0xFFEE; break; //1111111111101110 +case 0xE5 : *lenght=16; *out=0xFFEF; break; //1111111111101111 +case 0xE6 : *lenght=16; *out=0xFFF0; break; //1111111111110000 +case 0xE7 : *lenght=16; *out=0xFFF1; break; //1111111111110001 +case 0xE8 : *lenght=16; *out=0xFFF2; break; //1111111111110010 +case 0xE9 : *lenght=16; *out=0xFFF3; break; //1111111111110011 +case 0xEA : *lenght=16; *out=0xFFF4; break; //1111111111110100 +case 0xF0 : *lenght=11; *out=0xFFF9; break; //11111111001 +case 0xF1 : *lenght=16; *out=0xFFF5; break; //1111111111110101 +case 0xF2 : *lenght=16; *out=0xFFF6; break; //1111111111110110 +case 0xF3 : *lenght=16; *out=0xFFF7; break; //1111111111110111 +case 0xF4 : *lenght=16; *out=0xFFF8; break; //1111111111111000 +case 0xF5 : *lenght=16; *out=0xFFF9; break; //1111111111111001 +case 0xF6 : *lenght=16; *out=0xFFFA; break; //1111111111111010 +case 0xF7 : *lenght=16; *out=0xFFFB; break; //1111111111111011 +case 0xF8 : *lenght=16; *out=0xFFFC; break; //1111111111111100 +case 0xF9 : *lenght=16; *out=0xFFFD; break; //1111111111111101 +case 0xFA : *lenght=16; *out=0xFFFE; break; //1111111111111110 +#ifndef __MICROBLAZE +default : printf("WAARDE STAAT NIET IN TABEL!!!!!!!!!!!!!!!!!!!!\n");break; +#endif + } + // printf("magnitude= %x out= %x lenght= %d \n",magnitude,*out,*lenght); + return; + #endif + +} +//=========================================================================== +char Extend (char additional, unsigned char magnitude) +{ + int vt= 1 << (magnitude-1); + if ( additional < vt ) return (additional + (-1 << magnitude) + 1); + else return additional; +} +//=========================================================================== +void ReverseExtend (char value, unsigned char *magnitude, unsigned char *bits) +{ + // printf("reverseextend value= %d\n",*magnitude); + if (value >=0) + { + *bits=value; + } + else + { + value=-value; + *bits=~value; + } + *magnitude=0; + while (value !=0) + { + value>>=1; + ++*magnitude; + } + // printf("reverseextend magnitude= %d bits= %d",magnitude,bits); + return; +} +//=========================================================================== +void WriteRawBits16(unsigned char amount_bits, unsigned int bits) //*remaining needs bo be more than 8 bits because 8 bits could be added and ther ecould already be up ot 7 bits in *remaining +// this function collects bits to send +// if there less than 16 bits collected, nothing is send and these bits are stored in *remaining. In *amount_remaining there is stated how much bits are stored in *remaining +// if more than 16 bits are collected, 16 bits are send and the remaining bits are stored again +{ + unsigned short int send; + unsigned int mask; + unsigned char send2; + int count; + mask=0x00; //init mask + vlc_remaining=(vlc_remaining<0; count--) mask=(mask<<1)|0x01; //create mask for adding bit + vlc_remaining=vlc_remaining | (bits&mask); //add bits + vlc_amount_remaining=vlc_amount_remaining + amount_bits; //change *amount_remaining to the correct new value + if (vlc_amount_remaining >= 16) //are there more than 16 bits in buffer, send 16 bits + { +#ifndef __MICROBLAZE +if (vlc_amount_remaining >= 32 ) printf("ERROR, more bits to send %d",vlc_amount_remaining); +#endif + send=vlc_remaining>>(vlc_amount_remaining-16); //this value can be send/stored (in art this can be dony by selecting bits) + send2=(send & 0xFF00) >>8; + vlc_output_byte(send2); +// fwrite(&send2,1,1,file); + if (send2==0xFF) + { + send2=0x00; + vlc_output_byte(send2); +// fwrite(&send2,1,1,file); + } + send2=send & 0xFF; + vlc_output_byte(send2); +// fwrite(&send2,1,1,file); + if (send2==0xFF) + { + send2=0x00; + vlc_output_byte(send2); +// fwrite(&send2,1,1,file); + } + vlc_amount_remaining=vlc_amount_remaining-16; //descrease by 16 because these are send + } + return; +} +//=========================================================================== +void HuffmanEncodeFinishSend() +// There are still some bits left to send at the end of the 8x8 matrix (or maybe the file), +// the remaining bits are filled up with ones and send +// possible fault: -must it be filled up with ones? +{ + unsigned short int send; + unsigned int mask; + int count; + mask=0x00; //init mask + if (vlc_amount_remaining >= 8) //2 bytes to send, send first byte + { + send=vlc_remaining>>(vlc_amount_remaining-8); //shift so that first byte is ready to send + vlc_output_byte(send&0xff); +// fwrite(&send,1,1,file); + if (send==0xFF) //is this still needed???? + { + send=0x00; + vlc_output_byte(send&0xff); +// fwrite(&send,1,1,file); + } + vlc_amount_remaining=vlc_amount_remaining -8; // lower the value to the amount of bits that still needs to be send + } + if (vlc_amount_remaining >= 0) //there is a last byte to send + { + send=vlc_remaining<<(8-vlc_amount_remaining); //shift the last bits to send to the front of the byte + mask=0x00; //init mask + for (count=(8-vlc_amount_remaining); count>0; count--) mask=(mask<<1)|0x01; //create mask to fill byte up with ones + send=send | mask; //add the ones to the byte + vlc_output_byte(send&0xff); +// fwrite(&send,1,1,file); + vlc_amount_remaining=0x00; //is this needed? + } + return; +} +//=========================================================================== +void HuffmanEncodeUsingDCTable(unsigned char magnitude) +// Translate magnitude into needed data (from table) and send it +{ + unsigned char send; + unsigned short int huffmancode, huffmanlengt; + ConvertDCMagnitudeY(magnitude, &huffmancode, &huffmanlengt); + WriteRawBits16(huffmanlengt,huffmancode); + //printf("Write DC magnitude= %2x \n",magnitude); + //WriteRawBits16(0x08,magnitude,remaining,amount_remaining, file); + return; +} +//=========================================================================== +void HuffmanEncodeUsingACTable(unsigned char mag) +// Translate magnitude into needed data (from table) and send it +{ + unsigned char send; + unsigned short int huffmancode, huffmanlengt; + ConvertACMagnitudeY(mag, &huffmancode, &huffmanlengt); + WriteRawBits16(huffmanlengt,huffmancode); + return; +} +//=========================================================================== +char EncodeDataUnit(char dataunit[64], unsigned int color) +{ + char difference; + unsigned char magnitude,zerorun,ii,ert; + unsigned int bits; + unsigned char bit_char; + char last_dc_value; + //init + // PrintMatrix(dataunit) ; + last_dc_value = dcvalue[color]; + difference = dataunit[0] - last_dc_value; + last_dc_value=dataunit[0]; + ReverseExtend(difference, &magnitude,&bit_char); + bits = bit_char; + HuffmanEncodeUsingDCTable(magnitude); + WriteRawBits16(magnitude,bits); + zerorun=0; + ii=1; + while ( ii < 64 ) + { + if (dataunit[ii] != 0 ) + { + while ( zerorun >= 16 ) + { + HuffmanEncodeUsingACTable(0xF0); + zerorun=zerorun-16; + // printf("16 zeros: %d\n",zerorun); + } + ReverseExtend(dataunit[ii],&magnitude,&bit_char); + bits=bit_char; + ert= ((int)zerorun *16); //ERROR !!!!!!!!!!! + ert=ert + magnitude; + HuffmanEncodeUsingACTable(ert); + WriteRawBits16(magnitude,bits); + zerorun=0; + } + else zerorun=zerorun+1; + ii++; + } + if ( zerorun != 0 ) + { + HuffmanEncodeUsingACTable(0x00); +// printf("NUL DE REST IS NUL\n"); + } + // HuffmanEncodeFinishSend(remaining,amount_remaining,file); + dcvalue[color] = last_dc_value; + return 0; +} Index: tags/STEP1_2b/mb-vlc/mb-zzq.c =================================================================== --- tags/STEP1_2b/mb-vlc/mb-zzq.c (nonexistent) +++ tags/STEP1_2b/mb-vlc/mb-zzq.c (revision 27) @@ -0,0 +1,118 @@ +#include "xparameters.h" +#include "xutil.h" +#include "mb_interface.h" +#include "fifo_link.h" + +#include "ejpgl.h" +#include "mb-zzq.h" + +#define XPAR_FSL_FIFO_LINK_0_INPUT_SLOT_ID 0 +#define XPAR_FSL_FIFO_LINK_0_OUTPUT_SLOT_ID 0 + + +unsigned char quantization_table[MATRIX_SIZE][MATRIX_SIZE] ={ + {4, 3, 3, 4, 4, 5, 6, 6}, + {3, 3, 4, 4, 5, 6, 6, 6}, + {4, 4, 4, 4, 5, 6, 6, 6}, + {4, 4, 4, 5, 6, 6, 6, 6}, + {4, 4, 5, 6, 6, 7, 7, 6}, + {4, 5, 6, 6, 6, 7, 7, 6}, + {6, 6, 6, 6, 7, 7, 7, 7}, + {6, 6, 6, 7, 7, 7, 7, 7} + }; + +signed char bitstream[NUMBER_OF_PIXELS] ; + +int zzq_encode_init_start(int compression) { + + return 0; + +} + +void zzq_encode(signed short pixelmatrix[MATRIX_SIZE][MATRIX_SIZE], int color) +{ + int i, x, y, jumped, deltax, deltay; + + x = y = deltax = deltay = jumped = 0; + + for(i=0;i0) + bitstream[i] = (pixelmatrix[y][x]>>quantization_table[y][x]); + else + bitstream[i] = -((-pixelmatrix[y][x])>>quantization_table[y][x]); + + if((y == 0) || (y == MATRIX_SIZE-1)) { //on top or bottom side of matrix + if(!jumped) { //first jump to element on the right + x++; + jumped = 1; + } else { //modify direction + if(i<(NUMBER_OF_PIXELS>>1)) { + deltax = -1; + deltay = 1; + } else { + deltax = 1; + deltay = -1; + } + x += deltax; + y += deltay; + jumped = 0; + } + } else if ((x == 0) || (x == MATRIX_SIZE-1)) { //on left or right side of matrix + if(!jumped) { //jump to element below + y++; + jumped = 1; + } else { //modify direction + if(i<(NUMBER_OF_PIXELS>>1)) { + deltax = 1; + deltay = -1; + } else { + deltax = -1; + deltay = 1; + } + x += deltax; + y += deltay; + jumped = 0; + } + } + else {//not on the edges of the matrix + x += deltax; + y += deltay; + } + } + + EncodeDataUnit(bitstream, color); + +} +//--------------------------------------------------------------------------- + +signed short dctresult[MATRIX_SIZE][MATRIX_SIZE]; + +int main() { + int i; + int result; + int color; + + zzq_encode_init_start(0); + vlc_init_start(0); + + for (;;) { + + read_from_fsl(color, XPAR_FSL_FIFO_LINK_0_INPUT_SLOT_ID); + + if (color == 0xff) { + HuffmanEncodeFinishSend(); + } + else { + for (i=0; i<64; i++){ + read_from_fsl(result, XPAR_FSL_FIFO_LINK_0_INPUT_SLOT_ID); + ((short*)dctresult)[i] = result; + } + + zzq_encode(dctresult, color); + } + + } + +} + Index: tags/STEP1_2b/mb-vlc/fifo_link.h =================================================================== --- tags/STEP1_2b/mb-vlc/fifo_link.h (nonexistent) +++ tags/STEP1_2b/mb-vlc/fifo_link.h (revision 27) @@ -0,0 +1,91 @@ +////////////////////////////////////////////////////////////////////////////// +// +// *************************************************************************** +// ** ** +// ** Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. ** +// ** ** +// ** You may copy and modify these files for your own internal use solely ** +// ** with Xilinx programmable logic devices and Xilinx EDK system or ** +// ** create IP modules solely for Xilinx programmable logic devices and ** +// ** Xilinx EDK system. No rights are granted to distribute any files ** +// ** unless they are distributed in Xilinx programmable logic devices. ** +// ** ** +// *************************************************************************** +// +////////////////////////////////////////////////////////////////////////////// +// Filename: D:\thesis\FIFO1\drivers\fifo_link_v1_00_a\src\\fifo_link.h +// Version: 1.00.a +// Description: fifo_link (FIFO link) Driver Header File +// Date: Fri Oct 06 17:25:29 2006 (by Create and Import Peripheral Wizard) +////////////////////////////////////////////////////////////////////////////// + +#ifndef FIFO_LINK_H +#define FIFO_LINK_H + +#ifdef __MICROBLAZE__ + #include "mb_interface.h" + #define write_into_fsl(val, id) microblaze_bwrite_datafsl(val, id) + #define read_from_fsl(val, id) microblaze_bread_datafsl(val, id) +#else + #include "xpseudo_asm_gcc.h" + #define write_into_fsl(val, id) putfsl(val, id) + #define read_from_fsl(val, id) getfsl(val, id) +#endif + +/* +* A macro for accessing FSL peripheral. +* +* This example driver writes all the data in the input arguments +* into the input FSL bus through blocking wrties. FSL peripheral will +* automatically read from the FSL bus. Once all the inputs +* have been written, the output from the FSL peripheral is read +* into output arguments through blocking reads. +* +* Arguments: +* output_slot_id +* Compile time constant indicating FSL slot from +* which output data is read. Defined in +* xparameters.h . +* input_slot_id +* Compile time constant indicating FSL slot into +* which input data is written. Defined in +* xparameters.h . +* input_0 An array of unsigned integers. Array size is 1 +* output_0 An array of unsigned integers. Array size is 1 +* +* Caveats: +* The output_slot_id and input_slot_id arguments must be +* constants available at compile time. Do not pass +* variables for these arguments. +* +* Since this is a macro, using it too many times will +* increase the size of your application. In such cases, +* or when this macro is too simplistic for your +* application you may want to create your own instance +* specific driver function (not a macro) using the +* macros defined in this file and the slot +* identifiers defined in xparameters.h . Please see the +* example code (fifo_link_app.c) for details. +*/ + +#define fifo_link(\ + input_slot_id,\ + output_slot_id,\ + input_0, \ + output_0 \ + )\ +{\ + int i;\ +\ + for (i=0; i<1; i++)\ + {\ + write_into_fsl(input_0[i], input_slot_id);\ + }\ +\ + for (i=0; i<1; i++)\ + {\ + read_from_fsl(output_0[i], output_slot_id);\ + }\ +} + +#endif Index: tags/STEP1_2b/mb-vlc/mb-huffman.h =================================================================== --- tags/STEP1_2b/mb-vlc/mb-huffman.h (nonexistent) +++ tags/STEP1_2b/mb-vlc/mb-huffman.h (revision 27) @@ -0,0 +1,13 @@ +#ifndef _HUFFMAN_H +#define _HUFFMAN_H 1 + +int vlc_init(); + +char EncodeDataUnit(char dataunit[NUMBER_OF_PIXELS], unsigned int component); + +void HuffmanEncodeFinishSend(); + +#else +#error "ERROR file huffman.h multiple times included" +#endif /* --- _HUFFMAN_H --- */ + Index: tags/STEP1_2b/mb-vlc/mb-zzq.h =================================================================== --- tags/STEP1_2b/mb-vlc/mb-zzq.h (nonexistent) +++ tags/STEP1_2b/mb-vlc/mb-zzq.h (revision 27) @@ -0,0 +1,18 @@ +#ifndef _ZZQ_H +#define _ZZQ_H 1 + +#define MATRIX_SIZE 8 +#define NUMBER_OF_PIXELS MATRIX_SIZE*MATRIX_SIZE + + + + +/* + * ZigZag order the pixelmatrix and quantify its values, if endode == 0 the + * inverse operation will be caried out. + */ +void zzq_encode(signed short pixelmatrix[MATRIX_SIZE][MATRIX_SIZE], int color); +#else +#error "ERROR file zzq.h multiple times included" +#endif /* --- _ZZQ_H --- */ + Index: tags/STEP1_2b/mb-vlc/ejpgl.h =================================================================== --- tags/STEP1_2b/mb-vlc/ejpgl.h (nonexistent) +++ tags/STEP1_2b/mb-vlc/ejpgl.h (revision 27) @@ -0,0 +1,10 @@ +#ifndef _EJPGL_H +#define _EJPGL_H + +#define MATRIX_SIZE 8 +#define MACRO_BLOCK_SIZE 16 + +int idct8x8(int* fblock, char* sblock); + +#endif + Index: tags/STEP1_2b/TestApp_Memory/src/TestApp_Memory.c =================================================================== --- tags/STEP1_2b/TestApp_Memory/src/TestApp_Memory.c (nonexistent) +++ tags/STEP1_2b/TestApp_Memory/src/TestApp_Memory.c (revision 27) @@ -0,0 +1,88 @@ +/* + * * Copyright (c) 2004 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +/* + * Xilinx EDK 7.1.2 EDK_H.12.5.1 + * + * This file is a sample test application + * + * This application is intended to test and/or illustrate some + * functionality of your system. The contents of this file may + * vary depending on the IP in your system and may use existing + * IP driver functions. These drivers will be generated in your + * XPS project when you run the "Generate Libraries" menu item + * in XPS. + * + * Your XPS project directory is at: + * D:\mpdma + */ + + +// Located in: microblaze_0/include/xparameters.h +#include "xparameters.h" + +#include "xutil.h" + +//==================================================== + +int main (void) { + + + xil_printf("-- Entering main() %s %s--\r\n", __DATE__, __TIME__); + + /* + * MemoryTest routine will not be run for the memory at + * 0x00000000 (dlmb_cntlr) + * because it is being used to hold a part of this application program + */ + + + /* Testing DDR Memory (DDR_256MB_32MX64_rank1_row13_col10_cl2_5)*/ + { + XStatus status; + + print("Starting MemoryTest for DDR_256MB_32MX64_rank1_row13_col10_cl2_5:\r\n"); + print(" Running 32-bit test..."); + status = XUtil_MemoryTest32((Xuint32*)XPAR_DDR_256MB_32MX64_RANK1_ROW13_COL10_CL2_5_MEM0_BASEADDR, 1024, 0xAAAA5555, XUT_ALLMEMTESTS); + if (status == XST_SUCCESS) { + print("PASSED!\r\n"); + } + else { + print("FAILED!\r\n"); + } + print(" Running 16-bit test..."); + status = XUtil_MemoryTest16((Xuint16*)XPAR_DDR_256MB_32MX64_RANK1_ROW13_COL10_CL2_5_MEM0_BASEADDR, 2048, 0xAA55, XUT_ALLMEMTESTS); + if (status == XST_SUCCESS) { + print("PASSED!\r\n"); + } + else { + print("FAILED!\r\n"); + } + print(" Running 8-bit test..."); + status = XUtil_MemoryTest8((Xuint8*)XPAR_DDR_256MB_32MX64_RANK1_ROW13_COL10_CL2_5_MEM0_BASEADDR, 4096, 0xA5, XUT_ALLMEMTESTS); + if (status == XST_SUCCESS) { + print("PASSED!\r\n"); + } + else { + print("FAILED!\r\n"); + } + } + + xil_printf("-- Exiting main() --\r\n"); + return 0; +} + Index: tags/STEP1_2b/TestApp_Memory/src/TestApp_Memory_LinkScr =================================================================== --- tags/STEP1_2b/TestApp_Memory/src/TestApp_Memory_LinkScr (nonexistent) +++ tags/STEP1_2b/TestApp_Memory/src/TestApp_Memory_LinkScr (revision 27) @@ -0,0 +1,99 @@ + +_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x1000; + +/* Define all the memory regions in the system */ +MEMORY +{ +ilmb_cntlr : ORIGIN = 0x00000000, LENGTH = 0xffff +} + +/* +* Specify the default entry point to the program +*/ +ENTRY(_start) + +/* +* Define the sections, and where they are mapped in memory +*/ +SECTIONS +{ + + .text : { + _ftext = .; + *(.text) + *(.text.*) + *(.gnu.linkonce.t*) + _etext = .; + } > ilmb_cntlr + + .rodata : { + _frodata = .; + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r*) + _erodata = .; + } > ilmb_cntlr + + /* Alignments by 8 to ensure that _SDA2_BASE_ on a word boundary */ + .sdata2 : { + . = ALIGN(8); + _sdata2_start = .; + *(.sdata2) + . = ALIGN(8); + _sdata2_end = .; + } > ilmb_cntlr + _sdata2_size = _sdata2_end - _sdata2_start; + PROVIDE (_SDA2_BASE_ = _sdata2_start + (_sdata2_size / 2 )); + + .data : { + . = ALIGN(4); + _fdata = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + _edata = .; + } > ilmb_cntlr + + .eh_frame : { + *(.eh_frame) + } > ilmb_cntlr + + /* Alignments by 8 to ensure that _SDA_BASE_ on a word boundary */ + /* Note that .sdata and .sbss must be contiguous */ + + .sdata : { + . = ALIGN(8); + _ssro = .; + *(.sdata) + } > ilmb_cntlr + .sbss : { + . = ALIGN(4); + PROVIDE (__sbss_start = .); + *(.sbss) + . = ALIGN(8); + _essro = .; + } > ilmb_cntlr + PROVIDE (__sbss_end = _essro); + _ssro_size = _essro - _ssro; + PROVIDE (_SDA_BASE_ = _ssro + (_ssro_size / 2 )); + + .bss : { + . = ALIGN(4); + PROVIDE (__bss_start = .); + *(.bss) + *(COMMON) + . = ALIGN(4); + PROVIDE (__bss_end = .); + } > ilmb_cntlr + + .bss_stack : { + . = ALIGN(8); + _heap = .; + _heap_start = _heap; + . += _STACK_SIZE; + . = ALIGN(8); + _stack = .; + __stack = _stack; + } > ilmb_cntlr +} + Index: tags/STEP1_2b/data/system.ucf =================================================================== --- tags/STEP1_2b/data/system.ucf (nonexistent) +++ tags/STEP1_2b/data/system.ucf (revision 27) @@ -0,0 +1,347 @@ +############################################################################ +## This system.ucf file is generated by Base System Builder based on the +## settings in the selected Xilinx Board Definition file. Please add other +## user constraints to this file based on customer design specifications. +############################################################################ + +Net sys_clk_pin LOC=AJ15; +Net sys_clk_pin IOSTANDARD = LVCMOS25; +Net sys_rst_pin LOC=AH5; +Net sys_rst_pin IOSTANDARD = LVTTL; +## System level constraints +Net sys_clk_pin TNM_NET = sys_clk_pin; +TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps; +Net sys_rst_pin TIG; + +## FPGA pin constraints +Net fpga_0_RS232_Uart_1_RX_pin LOC=AJ8; +Net fpga_0_RS232_Uart_1_RX_pin IOSTANDARD = LVCMOS25; +Net fpga_0_RS232_Uart_1_TX_pin LOC=AE7; +Net fpga_0_RS232_Uart_1_TX_pin IOSTANDARD = LVCMOS25; +Net fpga_0_RS232_Uart_1_TX_pin SLEW = SLOW; +Net fpga_0_RS232_Uart_1_TX_pin DRIVE = 12; +Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AH15; +Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin PERIOD = 30000 ps; +Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> LOC=AF21; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=AG21; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=AC19; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=AD19; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=AE22; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=AE21; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=AH22; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=AE15; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=AD15; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=AG14; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=AF14; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=AE14; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=AD14; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=AC15; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=AB15; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=AJ9; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=AH9; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=AE10; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=AE9; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=AD12; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=AC12; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=AG10; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=AF10; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=AB16; +Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=AD17; +Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=AC16; +Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin IOSTANDARD = LVCMOS25; +Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin SLEW = SLOW; +Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin DRIVE = 8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=AD16; +Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin IOSTANDARD = LVCMOS25; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<12> LOC=M25; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<12> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<11> LOC=N25; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<11> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<10> LOC=L26; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<10> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<9> LOC=M29; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<9> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<8> LOC=K30; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<8> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<7> LOC=G25; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<7> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<6> LOC=G26; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<6> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<5> LOC=D26; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<5> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<4> LOC=J24; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<4> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<3> LOC=K24; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<3> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<2> LOC=F28; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<2> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<1> LOC=F30; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<1> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<0> LOC=M24; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin<0> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin<1> LOC=M26; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin<0> LOC=K26; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin LOC=L27; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin LOC=R26; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin LOC=R24; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin LOC=N29; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin LOC=N26; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<7> LOC=U26; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<7> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<6> LOC=V29; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<6> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<5> LOC=W29; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<5> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<4> LOC=T22; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<4> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<3> LOC=W28; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<3> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<2> LOC=W27; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<2> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<1> LOC=W26; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<1> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<0> LOC=W25; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin<0> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<7> LOC=E30; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<7> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<6> LOC=J29; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<6> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<5> LOC=M30; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<5> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<4> LOC=P29; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<4> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<3> LOC=V23; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<3> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<2> LOC=AA25; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<2> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<1> LOC=AC25; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<1> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<0> LOC=AH26; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin<0> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<63> LOC=C27; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<63> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<62> LOC=D28; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<62> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<61> LOC=D29; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<61> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<60> LOC=D30; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<60> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<59> LOC=H25; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<59> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<58> LOC=H26; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<58> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<57> LOC=E27; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<57> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<56> LOC=E28; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<56> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<55> LOC=J26; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<55> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<54> LOC=G27; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<54> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<53> LOC=G28; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<53> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<52> LOC=G30; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<52> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<51> LOC=L23; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<51> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<50> LOC=L24; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<50> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<49> LOC=H27; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<49> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<48> LOC=H28; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<48> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<47> LOC=J27; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<47> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<46> LOC=J28; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<46> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<45> LOC=K29; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<45> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<44> LOC=L29; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<44> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<43> LOC=N23; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<43> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<42> LOC=N24; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<42> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<41> LOC=K27; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<41> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<40> LOC=K28; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<40> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<39> LOC=R22; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<39> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<38> LOC=M27; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<38> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<37> LOC=M28; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<37> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<36> LOC=P30; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<36> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<35> LOC=P23; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<35> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<34> LOC=P24; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<34> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<33> LOC=N27; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<33> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<32> LOC=N28; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<32> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<31> LOC=V27; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<31> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<30> LOC=Y30; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<30> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<29> LOC=U24; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<29> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<28> LOC=U23; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<28> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<27> LOC=V26; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<27> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<26> LOC=V25; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<26> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<25> LOC=Y29; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<25> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<24> LOC=AA29; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<24> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<23> LOC=Y26; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<23> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<22> LOC=AA28; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<22> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<21> LOC=AA27; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<21> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<20> LOC=W24; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<20> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<19> LOC=W23; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<19> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<18> LOC=AB28; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<18> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<17> LOC=AB27; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<17> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<16> LOC=AC29; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<16> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<15> LOC=AB25; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<15> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<14> LOC=AE29; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<14> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<13> LOC=AA24; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<13> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<12> LOC=AA23; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<12> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<11> LOC=AD28; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<11> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<10> LOC=AD27; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<10> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<9> LOC=AF30; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<9> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<8> LOC=AF29; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<8> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<7> LOC=AF25; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<7> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<6> LOC=AG30; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<6> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<5> LOC=AG29; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<5> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<4> LOC=AD26; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<4> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<3> LOC=AD25; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<3> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<2> LOC=AG28; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<2> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<1> LOC=AH27; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<1> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<0> LOC=AH29; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin<0> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<2> LOC=AC27; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<2> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<1> LOC=AD29; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<1> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<0> LOC=AB23; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin<0> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<2> LOC=AC28; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<2> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<1> LOC=AD30; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<1> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<0> LOC=AB24; +Net fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin<0> IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_CLK_FB LOC=C16; +Net fpga_0_DDR_CLK_FB IOSTANDARD = SSTL2_II; +Net fpga_0_DDR_CLK_FB_OUT LOC=G23; +Net fpga_0_DDR_CLK_FB_OUT IOSTANDARD = SSTL2_II; Index: tags/STEP1_2b/system.bsb =================================================================== --- tags/STEP1_2b/system.bsb (nonexistent) +++ tags/STEP1_2b/system.bsb (revision 27) @@ -0,0 +1 @@ +��Į��tt��@Dn\b\dDvE��Į��tt��@D��D@D��@��Z��@��@��@��D@D�Dv-��Į��tt��ʌ��@D��D@D��d�Dv+��Į��tt��ʌ��@D��D@D��d��f`Dv%��Į��tt��ʌ��@D��D@D��prlDv%��Į��tt��ʌ��@D��D@DZnDv"��Į��tt��Ƞ��@D��Dv=��Į��tt��ʆ��@D��D@D��D@Db``\``````Dv8��Į��tt��ʆ��@D��D@D��D@D��@��Dvf��Į��tt��ʆ��@D��D@D��@��D@D��jbd��lh��lh��d��bf��b`��d�jDv=��Į��tt��ʆ��@D��D@D��D@Db``\``````DvJ��Į��tt��ʆ��@D��D@D��D@D��Z��@��@��@��Dv<��Į��tt��ʆ��@D��D@D��@��D@DljjflDv>��Į��tt��ʆ��@D��D@D��D@Db``\``````Dv8��Į��tt��ʆ��@D��D@D��D@D`Dv4��Į��tt��Ƞ��@D��dfd��bD@D��ľ��Dv;��Į��tt��ʆ��@D��dfd��bD@D��D@Drl``Dv9��Į��tt��ʆ��@D��dfd��bD@D��D@DpDv:��Į��tt��ʆ��@D��dfd��bD@D��D@D`Dv:��Į��tt��ʆ��@D��dfd��bD@D��D@D`Dv>��Į��tt��ʆ��@D��dfd��bD@D��D@D��bDv9��Į��tt��Ƞ��@D��悆��D@D��ľ��DvG��Į��tt��ʆ��@D��悆��D@D��D@D��bDvK��Į��tt��Ƞ��@D��djl��fd��lh��b��bf��b`��d�jD@D��ľ��DvY��Į��tt��ʆ��@D��djl��fd��lh��b��bf��b`��d�jD@D��D@D��bDv.��Į��tt��ʦ�@D��D@D��Dv2��Į��tt��ʦ�@D��D@D��Dv+��Į��tt��ʦ�@D��D@D��dfd��bDv,��Į��tt��ʦ�@D��D@D��dfd��bDv=��Į��tt��ʦ�@D��D@D��ľ��D@D��ྚ��Dv=��Į��tt��ʦ�@D��D@D��D@D��ྚ��Dv@��Į��tt��ʦ�@D��D@D��ľ��D@D��ྚ��Dv@��Į��tt��ʦ�@D��D@D��D@D��ྚ��Dv>��Į��tt��ʦ�@D��D@D��ľ��D@D��ྚ��Dv>��Į��tt��ʦ�@D��D@D��D@D��ྚ��Dv \ No newline at end of file Index: tags/STEP1_2b/etc/bitgen.ut =================================================================== --- tags/STEP1_2b/etc/bitgen.ut (nonexistent) +++ tags/STEP1_2b/etc/bitgen.ut (revision 27) @@ -0,0 +1,21 @@ +-g ConfigRate:4 +-g CclkPin:PULLUP +-g TdoPin:PULLNONE +-g M1Pin:PULLDOWN +-g DonePin:PULLUP +-g DriveDone:No +-g StartUpClk:JTAGCLK +-g DONE_cycle:4 +-g GTS_cycle:5 +-g M0Pin:PULLUP +-g M2Pin:PULLUP +-g ProgPin:PULLUP +-g TckPin:PULLUP +-g TdiPin:PULLUP +-g TmsPin:PULLUP +-g DonePipe:No +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:NONE +-m +-g Persist:No Index: tags/STEP1_2b/etc/fast_runtime.opt =================================================================== --- tags/STEP1_2b/etc/fast_runtime.opt (nonexistent) +++ tags/STEP1_2b/etc/fast_runtime.opt (revision 27) @@ -0,0 +1,80 @@ +FLOWTYPE = FPGA; +############################################################### +## Filename: fast_runtime.opt +## +## Option File For Xilinx FPGA Implementation Flow for Fast +## Runtime. +## +## Version: 4.1.1 +############################################################### +# +# Options for Translator +# +# Type "ngdbuild -h" for a detailed list of ngdbuild command line options +# +Program ngdbuild +-p ; # Partname to use - picked from xflow commandline +-nt timestamp; # NGO File generation. Regenerate only when + # source netlist is newer than existing + # NGO file (default) +-bm .bmm # Block RAM memory map file +; # User design - pick from xflow command line +-uc .ucf; # ucf constraints +.ngd; # Name of NGD file. Filebase same as design filebase +End Program ngdbuild + +# +# Options for Mapper +# +# Type "map -h " for a detailed list of map command line options +# +Program map +-o _map.ncd; # Output Mapped ncd file +-pr b; # Pack internal FF/latches into IOBs +#-fp .mfp; # Floorplan file +.ngd; # Input NGD file +.pcf; # Physical constraints file +END Program map + +# +# Options for Post Map Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_map_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o _map.twr; # Output trace report file +-xml _map.twx; # Output XML version of the timing report +#-tsi _map.tsi; # Produce Timing Specification Interaction report +_map.ncd; # Input mapped ncd +.pcf; # Physical constraints file +END Program post_map_trce + +# +# Options for Place and Route +# +# Type "par -h" for a detailed list of par command line options +# +Program par +-w; # Overwrite existing placed and routed ncd +-ol high; # Overall effort level +_map.ncd; # Input mapped NCD file +.ncd; # Output placed and routed NCD +.pcf; # Input physical constraints file +END Program par + +# +# Options for Post Par Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_par_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o .twr; # Output trace report file +-xml .twx; # Output XML version of the timing report +#-tsi .tsi; # Produce Timing Specification Interaction report +.ncd; # Input placed and routed ncd +.pcf; # Physical constraints file +END Program post_par_trce + + Index: tags/STEP1_2b/etc/download.cmd =================================================================== --- tags/STEP1_2b/etc/download.cmd (nonexistent) +++ tags/STEP1_2b/etc/download.cmd (revision 27) @@ -0,0 +1,6 @@ +setMode -bscan +setCable -p auto +identify +assignfile -p 3 -file implementation/download.bit +program -p 3 +quit Index: tags/STEP1_2b/etc/bitgen_spartan3.ut =================================================================== --- tags/STEP1_2b/etc/bitgen_spartan3.ut (nonexistent) +++ tags/STEP1_2b/etc/bitgen_spartan3.ut (revision 27) @@ -0,0 +1,15 @@ +-g CclkPin:PULLUP +-g TdoPin:PULLNONE +-g M1Pin:PULLDOWN +-g DonePin:PULLUP +-g StartUpClk:JTAGCLK +-g M0Pin:PULLUP +-g M2Pin:PULLUP +-g ProgPin:PULLUP +-g TckPin:PULLUP +-g TdiPin:PULLUP +-g TmsPin:PULLUP +-g LCK_cycle:NoWait +-g Security:NONE +-m +-g Persist:No

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