URL
https://opencores.org/ocsvn/tinycpu/tinycpu/trunk
Subversion Repositories tinycpu
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- This comparison shows the changes necessary to convert path
/
- from Rev 26 to Rev 27
- ↔ Reverse comparison
Rev 26 → Rev 27
/tinycpu/trunk/testbench/core_tb.vhd
134,7 → 134,15
MemIn <= x"0025"; --mov r0,0x25 |
assert(DebugR0 = x"20" and DebugTR='0') report "moved to r0 conditional thought TR is 0" severity error; |
assert(MemAddr = x"0020" and MemWE='1' and MemWW='0' and MemOut=x"0050") report "Write to memory doesn't work" severity error; |
wait for 20 ns; --wait an extra cycle because of WaitForMemory state |
MemIn <= x"0235"; --mov r1,0x35 |
wait for 10 ns; |
MemIn <= "0011000000010000"; --compare greater than r0, r1 : TR=r0 > r1 |
wait for 10 ns; |
assert(DebugTR ='0') report "ALU compare is not correct for greater than" severity error; |
MemIn <= "0011000000010010"; --TR=r0 < r1 |
wait for 20 ns; |
assert(DebugTR='1') report "ALU compare is not correct for less than" severity error; |
--wait for 10 ns; --have to wait an extra cycle for memory |
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-- summary of testbench |
/tinycpu/trunk/src/registerfile.vhd
27,7 → 27,7
regs: for I in 0 to 15 generate |
process(WriteEnable(I), DataIn(I), Clock) |
begin |
if rising_edge(Clock) then |
if falling_edge(Clock) then --I really hope this one falling_edge component doesn't bite me in the ass later |
if(WriteEnable(I) = '1') then |
registers(I) <= DataIn(I); |
end if; |
/tinycpu/trunk/src/core.vhd
137,10 → 137,10
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signal fetcheraddress: std_logic_vector(15 downto 0); |
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--temporary signals |
signal tempreg1: std_logic_vector(3 downto 0); |
signal tempreg2: std_logic_vector(3 downto 0); |
signal tempreg3: std_logic_vector(3 downto 0); |
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signal bankreg1: std_logic_vector(3 downto 0); --these signals have register bank stuff baked in |
signal bankreg2: std_logic_vector(3 downto 0); |
signal bankreg3: std_logic_vector(3 downto 0); |
signal FetchMemAddr: std_logic_vector(15 downto 0); |
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197,8 → 197,8
opcond2 <= IR(7); |
opreg1 <= IR(11 downto 9); |
opreg3 <= IR(2 downto 0); |
opreg2 <= IR(5 downto 3); |
opseges <= IR(6); |
opreg2 <= IR(6 downto 4); |
opseges <= IR(3); |
--debug ports |
DebugCS <= regOut(REGCS); |
DebugIP <= regOut(REGIP); |
206,9 → 206,9
DebugIR <= IR; |
DebugTR <= TR; |
--register addresses with registerbank baked in |
tempreg1 <= ('1' & opreg1) when (regbank='1' and opreg1(2)='0') else '0' & opreg1; |
tempreg2 <= ('1' & opreg2) when (regbank='1' and opreg2(2)='0') else '0' & opreg2; |
tempreg3 <= ('1' & opreg3) when (regbank='1' and opreg3(2)='0') else '0' & opreg3; |
bankreg1 <= ('1' & opreg1) when (regbank='1' and opreg1(2)='0') else '0' & opreg1; |
bankreg2 <= ('1' & opreg2) when (regbank='1' and opreg2(2)='0') else '0' & opreg2; |
bankreg3 <= ('1' & opreg3) when (regbank='1' and opreg3(2)='0') else '0' & opreg3; |
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300,10 → 300,10
if opcond1='0' or (opcond1='1' and TR='1') then |
case opmain is |
when "0000" => --mov reg,imm |
regIn(to_integer(unsigned(tempreg1))) <= opimmd; |
regWE(to_integer(unsigned(tempreg1))) <= '1'; |
regIn(to_integer(unsigned(bankreg1))) <= opimmd; |
regWE(to_integer(unsigned(bankreg1))) <= '1'; |
when "0001" => --mov [reg],imm |
OpAddress <= regOut(REGDS) & regOut(to_integer(unsigned(tempreg1))); |
OpAddress <= regOut(REGDS) & regOut(to_integer(unsigned(bankreg1))); |
OpWE <= '1'; |
OpData <= x"00" & opimmd; |
OpWW <= '0'; |
310,6 → 310,17
state <= WaitForMemory; |
IPAddend <= x"00"; --disable all this because we have to wait a cycle to write memory |
FetchEN <= '0'; |
when "0011" => --group 3 comparisons |
AluOp <= "01" & opreg3; --nothing hard here, ALU does it all for us |
AluIn1 <= regOut(to_integer(unsigned(opreg1))); |
AluIn2 <= regOut(to_integer(unsigned(opreg2))); |
when "0100" => --group 4 bitwise operations |
AluOp <= "00" & opreg3; --nothing hard here, ALU does it all for us |
AluIn1 <= regOut(to_integer(unsigned(opreg1))); |
AluIn2 <= regOut(to_integer(unsigned(opreg2))); |
regIn(to_integer(unsigned(opreg1))) <= AluOut; |
regWE(to_integer(unsigned(opreg1))) <= '1'; |
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when others => |
--synthesis off |
report "Not implemented" severity error; |
/tinycpu/trunk/docs/design.md.txt
289,12 → 289,38
C = conditional portion |
s = segment register choice |
i = immediate data |
N = not used |
o = opcode choice (for groups) |
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0000 rrrC iiii iiii |
mov reg, immediate |
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0001 rrrC iiii iiii |
mov [reg], immediate |
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group 3 comparions |
0011 rrrC Crrr Nooo |
opcode choices |
000: is greater than reg1,reg2 (TR=reg1>reg2) |
001: is greater or equal to reg,reg |
010: is less than reg,reg |
011: is less than or equal to reg,reg |
100: is equal to reg,reg |
101: is not equal to reg,reg |
110: equals 0 reg |
111: not equals 0 reg |
|
group 4 bitwise |
0100 rrrC Crrr Nooo |
opcode choices |
000: and reg1,reg2 (reg1=reg1 and reg2) |
001: or reg, reg |
010: xor reg,reg |
011: not reg1,reg2 (reg1=not reg2) |
100: left shift reg,reg |
101: right shift reg,reg |
110: rotate right reg,reg |
111: rotate left reg,reg |
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