OpenCores
URL https://opencores.org/ocsvn/atlas_core/atlas_core/trunk

Subversion Repositories atlas_core

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    from Rev 27 to Rev 28
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Rev 27 → Rev 28

/atlas_core/trunk/asm/atlas_asm.exe Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/atlas_core/trunk/asm/src/main.cpp
42,7 → 42,7
int find_offset(char *input_label, int line);
int conv_imm(char *input, int max_val, int line);
void get_labels(const char *input_file);
int assemble(const char *input_file, const char *output_file, const char *bin_output_file);
int assemble(const char *input_file, const char *output_file, const char *bin_output_file, const char *boot_output_file);
int main(int argc, char *argv[]);
1214,9 → 1214,9
// *****************************************************************************************************************
// Assemble pre-processor file
// *****************************************************************************************************************
int assemble(const char *input_file, const char *output_file, const char *bin_output_file){
int assemble(const char *input_file, const char *output_file, const char *bin_output_file, const char *boot_output_file){
 
FILE *data_in, *data_out, *bin_data_out;
FILE *data_in, *data_out, *bin_data_out, *boot_out;
char line_input[512];
int index = 0;
int i = 0, j = 0;
1224,6 → 1224,7
char *cut_out;
char line_string[256];
char tmp_string[32];
char buf_string[32];
char arg[10][64];
int opcode;
int temp;
1236,18 → 1237,25
}
data_out = fopen(output_file, "w");
if(data_out == NULL){
printf("ASSEMBLE: Output file error_cnt!\n");
printf("ASSEMBLE: Output file error!\n");
exit(1);
}
bin_data_out = fopen(bin_output_file, "wb");
if(data_out == NULL){
printf("ASSEMBLE: Binary output file error_cnt!\n");
if(bin_data_out == NULL){
printf("ASSEMBLE: Binary output file error!\n");
exit(1);
}
boot_out = fopen(boot_output_file, "wb");
if(boot_out == NULL){
printf("ASSEMBLE: Boot output file error!\n");
exit(1);
}
 
// reserve memory for header (16 byte)
for (i=0; i<16; i++)
fputc(char(0), bin_data_out);
for (i=0; i<8; i++)
fputs("000000 => x\"0000\",\n", boot_out);
 
// get line
line = 1;
1833,6 → 1841,9
// binary data file output
fputc(char((opcode>>8)&255), bin_data_out);
fputc(char(opcode&255), bin_data_out);
// boot image output
sprintf(buf_string, "%06d => x\"%04x\",\n", line-1+8, opcode);
fputs(buf_string, boot_out);
// compute xor-checksum
xor_checksum = xor_checksum xor opcode;
xor_checksum = xor_checksum & (int)(pow(2, 16)-1);
1841,31 → 1852,43
line++;
}
 
if (error_cnt == 0)
if (error_cnt == 0){
fputs("others => x\"0000\" -- NOP", data_out);
fputs("others => x\"0000\"", boot_out);
}
 
// build header
rewind(bin_data_out);
rewind(boot_out);
 
// bootfile signature
fputc(char(((51966)>>8)&255), bin_data_out);
fputc(char((51966)&255), bin_data_out);
sprintf(buf_string, "000000 => x\"%04x\",\n", 51966); fputs(buf_string, boot_out);
 
// program size (words)
fputc(char(((line-1)>>8)&255), bin_data_out);
fputc(char((line-1)&255), bin_data_out);
sprintf(buf_string, "000001 => x\"%04x\",\n", line-1); fputs(buf_string, boot_out);
 
// xor-checksum
fputc(char(((xor_checksum)>>8)&255), bin_data_out);
fputc(char((xor_checksum)&255), bin_data_out);
sprintf(buf_string, "000002 => x\"%04x\",\n", xor_checksum); fputs(buf_string, boot_out);
 
// image name
for(i=0; i<10; i++)
fputc(char((image_name[i])&255), bin_data_out);
for(i=0; i<10; i+=2){
sprintf(buf_string, "%06d => x\"%04x\",\n", i/2+3, (((int)(image_name[i]&255))<<8)|(((int)(image_name[i+1]&255))));
fputs(buf_string, boot_out);
}
fclose(bin_data_out);
fclose(data_out);
fclose(data_in);
fclose(boot_out);
return line;
}
1879,7 → 1902,7
int p_size = 0;
int i = 0;
 
printf("ATLAS 2k Assembler, Version 2014.04.10\n");
printf("ATLAS 2k Assembler, Version 2014.04.14\n");
printf("by Stephan Nolting (stnolting@gmail.com), Hanover, Germany\n");
printf("www.opencores.org/project,atlas_core\n\n");
 
1901,13 → 1924,13
convert_strings("included.xasm", "job.xasm"); // convert strings into direct memory inits
pre_processor("job.xasm", "pre_processor.asm"); // erase comments & empty lines & get definitions
get_labels("pre_processor.asm"); // find and list labels
p_size = assemble("pre_processor.asm", "init.vhd", "out.bin"); // do the magic conversion
p_size = assemble("pre_processor.asm", "init.vhd", "out.bin", "boot_init.vhd"); // do the magic conversion
 
if (error_cnt == 0){
printf("\nAssembler completed without errors (%d warnings).\n", warning_cnt);
printf("Final image size: 0x%04X (%d) bytes\n", (p_size-1)*2, (p_size-1)*2);
printf("Image XOR checksum: 0x%04X\n", xor_checksum);
printf("Binary image name: ");
printf("\nAssembler completed without errors (%d warnings)\n", warning_cnt);
printf("Image size: 0x%04X (%d) bytes\n", (p_size-1)*2, (p_size-1)*2);
printf("XOR check sum: 0x%04X\n", xor_checksum);
printf("Image name: ");
if (image_name[0] != '\0'){
for(i=0; i<10;i++)
printf("%c", image_name[i]);
/atlas_core/trunk/rtl/BOOT_MEM.vhd
3,7 → 3,7
-- # **************************************************** #
-- # Initialized with boot loader. #
-- # **************************************************** #
-- # Last modified: 10.04.2014 #
-- # Last modified: 14.04.2014 #
-- # **************************************************** #
-- # by Stephan Nolting 4788, Hanover, Germany #
-- ########################################################
43,1024 → 43,1027
------------------------------------------------------
constant BOOT_MEM_FILE_C : mem_file_t :=
(
000000 => x"bc0e", -- B
000001 => x"bc04", -- B
000002 => x"bc03", -- B
000003 => x"bc02", -- B
000004 => x"bc01", -- B
000005 => x"c000", -- LDIL
000006 => x"cc00", -- LDIH
000007 => x"ec8a", -- MCR
000008 => x"cc19", -- LDIH
000009 => x"ed0f", -- MCR
000010 => x"c53a", -- LDIL
000011 => x"c907", -- LDIH
000012 => x"be85", -- BL
000013 => x"bc00", -- B
000014 => x"ec11", -- MRC
000015 => x"ec88", -- MCR
000016 => x"ec8a", -- MCR
000017 => x"c000", -- LDIL
000018 => x"ec0b", -- MCR
000019 => x"ec0e", -- MCR
000020 => x"c802", -- LDIH
000021 => x"ec08", -- MCR
000022 => x"c47f", -- LDIL
000023 => x"ec09", -- MCR
000024 => x"ec00", -- MRC
000025 => x"c080", -- LDIL
000026 => x"ccf8", -- LDIH
000027 => x"1c01", -- STSR
000028 => x"c030", -- LDIL
000029 => x"c800", -- LDIH
000030 => x"ed88", -- MCR
000031 => x"c002", -- LDIL
000032 => x"ed8b", -- MCR
000033 => x"c064", -- LDIL
000034 => x"ed8d", -- MCR
000035 => x"c801", -- LDIH
000036 => x"ed0f", -- MCR
000037 => x"ec17", -- MRC
000038 => x"ec97", -- MRC
000039 => x"c160", -- LDIL
000040 => x"c909", -- LDIH
000041 => x"c18f", -- LDIL
000042 => x"0923", -- ADD
000043 => x"29b3", -- CLR
000044 => x"2a44", -- CLR
000045 => x"100a", -- SUBS
000046 => x"149b", -- SBCS
000047 => x"9003", -- BMI
000048 => x"0241", -- INC
000049 => x"bdfc", -- B
000050 => x"ed49", -- MCR
000051 => x"ec22", -- MRC
000052 => x"d406", -- SBR
000053 => x"ed0a", -- MCR
000054 => x"be5d", -- BL
000055 => x"be5c", -- BL
000056 => x"c54c", -- LDIL
000057 => x"c905", -- LDIH
000058 => x"be57", -- BL
000059 => x"c13e", -- LDIL
000060 => x"c906", -- LDIH
000061 => x"be55", -- BL
000062 => x"ee11", -- MRC
000063 => x"be57", -- BL
000064 => x"be53", -- BL
000065 => x"c14e", -- LDIL
000066 => x"c906", -- LDIH
000067 => x"be4f", -- BL
000068 => x"ee97", -- MRC
000069 => x"ee17", -- MRC
000070 => x"be50", -- BL
000071 => x"0250", -- MOV
000072 => x"be4e", -- BL
000073 => x"be4a", -- BL
000074 => x"ec27", -- MRC
000075 => x"c083", -- LDIL
000076 => x"2001", -- AND
000077 => x"c330", -- LDIL
000078 => x"0b60", -- ADD
000079 => x"bc1c", -- B
000080 => x"be43", -- BL
000081 => x"c57a", -- LDIL
000082 => x"c906", -- LDIH
000083 => x"be3e", -- BL
000084 => x"c10a", -- LDIL
000085 => x"c907", -- LDIH
000086 => x"be3b", -- BL
000087 => x"c172", -- LDIL
000088 => x"c907", -- LDIH
000089 => x"be38", -- BL
000090 => x"c502", -- LDIL
000091 => x"c907", -- LDIH
000092 => x"be35", -- BL
000093 => x"c510", -- LDIL
000094 => x"c907", -- LDIH
000095 => x"be32", -- BL
000096 => x"c51a", -- LDIL
000097 => x"c907", -- LDIH
000098 => x"be2f", -- BL
000099 => x"c526", -- LDIL
000100 => x"c907", -- LDIH
000101 => x"be2d", -- BL
000102 => x"be2f", -- BL
000103 => x"0300", -- MOV
000104 => x"00e0", -- MOV
000105 => x"be2b", -- BL
000106 => x"be29", -- BL
000107 => x"c0b0", -- LDIL
000108 => x"181e", -- CMP
000109 => x"81e3", -- BEQ
000110 => x"c0b1", -- LDIL
000111 => x"181e", -- CMP
000112 => x"8078", -- BEQ
000113 => x"c0b2", -- LDIL
000114 => x"181e", -- CMP
000115 => x"8024", -- BEQ
000116 => x"c0b3", -- LDIL
000117 => x"181e", -- CMP
000118 => x"8015", -- BEQ
000119 => x"c2f4", -- LDIL
000120 => x"ca83", -- LDIH
000121 => x"c0f0", -- LDIL
000122 => x"181e", -- CMP
000123 => x"f705", -- RBAEQ
000124 => x"c6f2", -- LDIL
000125 => x"ca82", -- LDIH
000126 => x"c0e4", -- LDIL
000127 => x"181e", -- CMP
000128 => x"f705", -- RBAEQ
000129 => x"c68c", -- LDIL
000130 => x"ca85", -- LDIH
000131 => x"c0f7", -- LDIL
000132 => x"181e", -- CMP
000133 => x"f705", -- RBAEQ
000134 => x"c0f2", -- LDIL
000135 => x"181e", -- CMP
000136 => x"85db", -- BNE
000137 => x"2800", -- CLR
000138 => x"3400", -- GT
000139 => x"c15e", -- LDIL
000140 => x"c906", -- LDIH
000141 => x"be04", -- BL
000142 => x"2800", -- CLR
000143 => x"2100", -- STUB
000144 => x"bcb3", -- B
000145 => x"bca9", -- B
000146 => x"bca9", -- B
000147 => x"bca9", -- B
000148 => x"bca9", -- B
000149 => x"bca9", -- B
000150 => x"bcac", -- B
000151 => x"c15e", -- LDIL
000152 => x"c906", -- LDIH
000153 => x"bea1", -- BL
000154 => x"c100", -- LDIL
000155 => x"bea4", -- BL
000156 => x"3eb0", -- SFT
000157 => x"c101", -- LDIL
000158 => x"bea1", -- BL
000159 => x"26d3", -- ORR
000160 => x"c47e", -- LDIL
000161 => x"cc4a", -- LDIH
000162 => x"180d", -- CMP
000163 => x"849d", -- BNE
000164 => x"c102", -- LDIL
000165 => x"be9a", -- BL
000166 => x"3eb0", -- SFT
000167 => x"c103", -- LDIL
000168 => x"be97", -- BL
000169 => x"26d3", -- ORR
000170 => x"2055", -- STUB
000171 => x"c104", -- LDIL
000172 => x"be93", -- BL
000173 => x"3eb0", -- SFT
000174 => x"c105", -- LDIL
000175 => x"be90", -- BL
000176 => x"26d3", -- ORR
000177 => x"20d5", -- STUB
000178 => x"c106", -- LDIL
000179 => x"be8c", -- BL
000180 => x"3eb0", -- SFT
000181 => x"c107", -- LDIL
000182 => x"be89", -- BL
000183 => x"26d3", -- ORR
000184 => x"2155", -- STUB
000185 => x"c108", -- LDIL
000186 => x"be85", -- BL
000187 => x"3eb0", -- SFT
000188 => x"c109", -- LDIL
000189 => x"be82", -- BL
000190 => x"26d3", -- ORR
000191 => x"21d5", -- STUB
000192 => x"c10a", -- LDIL
000193 => x"be7e", -- BL
000194 => x"3eb0", -- SFT
000195 => x"c10b", -- LDIL
000196 => x"be7b", -- BL
000197 => x"26d3", -- ORR
000198 => x"2255", -- STUB
000199 => x"c10c", -- LDIL
000200 => x"be77", -- BL
000201 => x"3eb0", -- SFT
000202 => x"c10d", -- LDIL
000203 => x"be74", -- BL
000204 => x"26d3", -- ORR
000205 => x"22d5", -- STUB
000206 => x"c10e", -- LDIL
000207 => x"be70", -- BL
000208 => x"3eb0", -- SFT
000209 => x"c10f", -- LDIL
000210 => x"be6d", -- BL
000211 => x"26d3", -- ORR
000212 => x"2355", -- STUB
000213 => x"c300", -- LDIL
000214 => x"ecea", -- MCR
000215 => x"23e6", -- STUB
000216 => x"c010", -- LDIL
000217 => x"0960", -- ADD
000218 => x"be65", -- BL
000219 => x"3eb0", -- SFT
000220 => x"c011", -- LDIL
000221 => x"0960", -- ADD
000222 => x"be61", -- BL
000223 => x"26d3", -- ORR
000224 => x"7eea", -- STR
000225 => x"2477", -- LDUB
000226 => x"2805", -- EOR
000227 => x"2380", -- STUB
000228 => x"2400", -- LDUB
000229 => x"1868", -- CMP
000230 => x"85f2", -- BNE
000231 => x"bc41", -- B
000232 => x"c15e", -- LDIL
000233 => x"c906", -- LDIH
000234 => x"be50", -- BL
000235 => x"c17a", -- LDIL
000236 => x"c906", -- LDIH
000237 => x"be4d", -- BL
000238 => x"be50", -- BL
000239 => x"3c80", -- SFT
000240 => x"be4e", -- BL
000241 => x"2490", -- ORR
000242 => x"c47e", -- LDIL
000243 => x"cc4a", -- LDIH
000244 => x"1818", -- CMP
000245 => x"844b", -- BNE
000246 => x"be48", -- BL
000247 => x"3c80", -- SFT
000248 => x"be46", -- BL
000249 => x"2490", -- ORR
000250 => x"3c94", -- SFT
000251 => x"2011", -- STUB
000252 => x"be42", -- BL
000253 => x"3c80", -- SFT
000254 => x"be40", -- BL
000255 => x"2490", -- ORR
000256 => x"2091", -- STUB
000257 => x"be3d", -- BL
000258 => x"3c80", -- SFT
000259 => x"be3b", -- BL
000260 => x"2490", -- ORR
000261 => x"2111", -- STUB
000262 => x"be38", -- BL
000263 => x"3c80", -- SFT
000264 => x"be36", -- BL
000265 => x"2490", -- ORR
000266 => x"2191", -- STUB
000267 => x"be33", -- BL
000268 => x"3c80", -- SFT
000269 => x"be31", -- BL
000270 => x"2490", -- ORR
000271 => x"2211", -- STUB
000272 => x"be2e", -- BL
000273 => x"3c80", -- SFT
000274 => x"be2c", -- BL
000275 => x"2490", -- ORR
000276 => x"2291", -- STUB
000277 => x"be29", -- BL
000278 => x"3c80", -- SFT
000279 => x"be27", -- BL
000280 => x"2490", -- ORR
000281 => x"2311", -- STUB
000282 => x"2ad5", -- CLR
000283 => x"ecda", -- MCR
000284 => x"23d5", -- STUB
000285 => x"be21", -- BL
000286 => x"3c80", -- SFT
000287 => x"be1f", -- BL
000288 => x"2490", -- ORR
000289 => x"7cda", -- STR
000290 => x"2477", -- LDUB
000291 => x"2801", -- EOR
000292 => x"2380", -- STUB
000293 => x"2400", -- LDUB
000294 => x"1858", -- CMP
000295 => x"85f6", -- BNE
000296 => x"ec11", -- MRC
000297 => x"ec8a", -- MCR
000298 => x"c524", -- LDIL
000299 => x"c906", -- LDIH
000300 => x"be0e", -- BL
000301 => x"2477", -- LDUB
000302 => x"2491", -- LDUB
000303 => x"1809", -- CMP
000304 => x"8013", -- BEQ
000305 => x"c546", -- LDIL
000306 => x"c907", -- LDIH
000307 => x"be07", -- BL
000308 => x"c564", -- LDIL
000309 => x"c907", -- LDIH
000310 => x"be04", -- BL
000311 => x"be07", -- BL
000312 => x"2800", -- CLR
000313 => x"3400", -- GT
000314 => x"bcdd", -- B
000315 => x"bcdf", -- B
000316 => x"bceb", -- B
000317 => x"bcef", -- B
000318 => x"bcf3", -- B
000319 => x"bc79", -- B
000320 => x"bccd", -- B
000321 => x"bd22", -- B
000322 => x"bc77", -- B
000323 => x"c514", -- LDIL
000324 => x"c906", -- LDIH
000325 => x"bed5", -- BL
000326 => x"24aa", -- LDUBS
000327 => x"8024", -- BEQ
000328 => x"c0a2", -- LDIL
000329 => x"bee3", -- BL
000330 => x"24a2", -- LDUB
000331 => x"3c90", -- SFT
000332 => x"bee0", -- BL
000333 => x"3c90", -- SFT
000334 => x"bede", -- BL
000335 => x"24b3", -- LDUB
000336 => x"3c90", -- SFT
000337 => x"bedb", -- BL
000338 => x"3c90", -- SFT
000339 => x"bed9", -- BL
000340 => x"24c4", -- LDUB
000341 => x"3c90", -- SFT
000342 => x"bed6", -- BL
000343 => x"3c90", -- SFT
000344 => x"bed4", -- BL
000345 => x"24d5", -- LDUB
000346 => x"3c90", -- SFT
000347 => x"bed1", -- BL
000348 => x"3c90", -- SFT
000349 => x"becf", -- BL
000350 => x"24e6", -- LDUB
000351 => x"3c90", -- SFT
000352 => x"becc", -- BL
000353 => x"3c90", -- SFT
000354 => x"beca", -- BL
000355 => x"c0a2", -- LDIL
000356 => x"bec8", -- BL
000357 => x"bec2", -- BL
000358 => x"c564", -- LDIL
000359 => x"c906", -- LDIH
000360 => x"beb2", -- BL
000361 => x"2677", -- LDUB
000362 => x"be4f", -- BL
000363 => x"bebc", -- BL
000364 => x"bebb", -- BL
000365 => x"2800", -- CLR
000366 => x"d58e", -- SBR
000367 => x"d5bf", -- SBR
000368 => x"1c03", -- STSR
000369 => x"ed0f", -- MCR
000370 => x"ec88", -- MCR
000371 => x"ec88", -- MCR
000372 => x"ec8b", -- MCR
000373 => x"ec8c", -- MCR
000374 => x"ec8a", -- MCR
000375 => x"ec89", -- MCR
000376 => x"3400", -- GT
000377 => x"c538", -- LDIL
000378 => x"c906", -- LDIH
000379 => x"be9f", -- BL
000380 => x"beba", -- BL
000381 => x"beb4", -- BL
000382 => x"c08d", -- LDIL
000383 => x"1809", -- CMP
000384 => x"8006", -- BEQ
000385 => x"c088", -- LDIL
000386 => x"1809", -- CMP
000387 => x"85fa", -- BNE
000388 => x"bea3", -- BL
000389 => x"bdbc", -- B
000390 => x"ecca", -- MCR
000391 => x"bea0", -- BL
000392 => x"c280", -- LDIL
000393 => x"c00f", -- LDIL
000394 => x"2058", -- ANDS
000395 => x"840a", -- BNE
000396 => x"be9b", -- BL
000397 => x"c0a4", -- LDIL
000398 => x"be9e", -- BL
000399 => x"0250", -- MOV
000400 => x"becb", -- BL
000401 => x"c0ba", -- LDIL
000402 => x"be9a", -- BL
000403 => x"c0a0", -- LDIL
000404 => x"be98", -- BL
000405 => x"7a5a", -- LDR
000406 => x"c0a0", -- LDIL
000407 => x"be95", -- BL
000408 => x"bec3", -- BL
000409 => x"c00f", -- LDIL
000410 => x"2058", -- ANDS
000411 => x"8414", -- BNE
000412 => x"c0a0", -- LDIL
000413 => x"be8f", -- BL
000414 => x"be8e", -- BL
000415 => x"c010", -- LDIL
000416 => x"1250", -- SUB
000417 => x"c470", -- LDIL
000418 => x"2240", -- AND
000419 => x"78c9", -- LDR
000420 => x"3c90", -- SFT
000421 => x"c880", -- LDIH
000422 => x"c020", -- LDIL
000423 => x"1818", -- CMP
000424 => x"a402", -- BLS
000425 => x"c0ae", -- LDIL
000426 => x"be82", -- BL
000427 => x"c08f", -- LDIL
000428 => x"2014", -- AND
000429 => x"3409", -- TEQ
000430 => x"85f5", -- BNE
000431 => x"ec20", -- MRC
000432 => x"dc0f", -- STB
000433 => x"b804", -- BTS
000434 => x"c5fe", -- LDIL
000435 => x"343d", -- TEQ
000436 => x"85d5", -- BNE
000437 => x"be7c", -- BL
000438 => x"2800", -- CLR
000439 => x"3400", -- GT
000440 => x"bc5e", -- B
000441 => x"bca2", -- B
000442 => x"c001", -- LDIL
000443 => x"ed0c", -- MCR
000444 => x"c050", -- LDIL
000445 => x"c83f", -- LDIH
000446 => x"ed0a", -- MCR
000447 => x"c000", -- LDIL
000448 => x"c801", -- LDIH
000449 => x"beb8", -- BL
000450 => x"c16a", -- LDIL
000451 => x"c906", -- LDIH
000452 => x"be53", -- BL
000453 => x"c17a", -- LDIL
000454 => x"c906", -- LDIH
000455 => x"be50", -- BL
000456 => x"be69", -- BL
000457 => x"3c80", -- SFT
000458 => x"be67", -- BL
000459 => x"2410", -- ORR
000460 => x"c4fe", -- LDIL
000461 => x"ccca", -- LDIH
000462 => x"1809", -- CMP
000463 => x"843e", -- BNE
000464 => x"c100", -- LDIL
000465 => x"c5ca", -- LDIL
000466 => x"bead", -- BL
000467 => x"c101", -- LDIL
000468 => x"c5fe", -- LDIL
000469 => x"beaa", -- BL
000470 => x"be5b", -- BL
000471 => x"3c80", -- SFT
000472 => x"be59", -- BL
000473 => x"2690", -- ORR
000474 => x"3ed4", -- SFT
000475 => x"2055", -- STUB
000476 => x"c102", -- LDIL
000477 => x"3dd0", -- SFT
000478 => x"bea1", -- BL
000479 => x"c103", -- LDIL
000480 => x"01d0", -- MOV
000481 => x"be9e", -- BL
000482 => x"be4f", -- BL
000483 => x"3c80", -- SFT
000484 => x"be4d", -- BL
000485 => x"2690", -- ORR
000486 => x"20d5", -- STUB
000487 => x"c104", -- LDIL
000488 => x"3dd0", -- SFT
000489 => x"be96", -- BL
000490 => x"c105", -- LDIL
000491 => x"01d0", -- MOV
000492 => x"be93", -- BL
000493 => x"c106", -- LDIL
000494 => x"be43", -- BL
000495 => x"0180", -- MOV
000496 => x"be8f", -- BL
000497 => x"0121", -- INC
000498 => x"c010", -- LDIL
000499 => x"1828", -- CMP
000500 => x"85fa", -- BNE
000501 => x"c110", -- LDIL
000502 => x"2ad5", -- CLR
000503 => x"be3a", -- BL
000504 => x"0180", -- MOV
000505 => x"be86", -- BL
000506 => x"0121", -- INC
000507 => x"2400", -- LDUB
000508 => x"02d1", -- INC
000509 => x"1858", -- CMP
000510 => x"85f9", -- BNE
000511 => x"c001", -- LDIL
000512 => x"ed0c", -- MCR
000513 => x"c050", -- LDIL
000514 => x"c83f", -- LDIH
000515 => x"ed0a", -- MCR
000516 => x"c00c", -- LDIL
000517 => x"c801", -- LDIH
000518 => x"be73", -- BL
000519 => x"c524", -- LDIL
000520 => x"c906", -- LDIH
000521 => x"be0e", -- BL
000522 => x"c6a0", -- LDIL
000523 => x"ca80", -- LDIH
000524 => x"3450", -- GT
000525 => x"c52e", -- LDIL
000526 => x"c907", -- LDIH
000527 => x"be08", -- BL
000528 => x"c564", -- LDIL
000529 => x"c907", -- LDIH
000530 => x"be05", -- BL
000531 => x"be1e", -- BL
000532 => x"2800", -- CLR
000533 => x"3400", -- GT
000534 => x"bc9e", -- B
000535 => x"c5ff", -- LDIL
000536 => x"0270", -- MOV
000537 => x"bc03", -- B
000538 => x"29b3", -- CLR
000539 => x"0270", -- MOV
000540 => x"7829", -- LDR
000541 => x"c080", -- LDIL
000542 => x"ccff", -- LDIH
000543 => x"2081", -- AND
000544 => x"3c98", -- SFTS
000545 => x"8003", -- BEQ
000546 => x"be0a", -- BL
000547 => x"bdf9", -- B
000548 => x"03c0", -- MOV
000549 => x"343b", -- TEQ
000550 => x"f707", -- RBAEQ
000551 => x"0170", -- MOV
000552 => x"c08d", -- LDIL
000553 => x"be03", -- BL
000554 => x"c08a", -- LDIL
000555 => x"03a0", -- MOV
000556 => x"ec22", -- MRC
000557 => x"dc05", -- STB
000558 => x"b9fe", -- BTS
000559 => x"ed18", -- MCR
000560 => x"3470", -- RET
000561 => x"ec20", -- MRC
000562 => x"dc8f", -- STBI
000563 => x"b9fe", -- BTS
000564 => x"c800", -- LDIH
000565 => x"3470", -- RET
000566 => x"0170", -- MOV
000567 => x"c200", -- LDIL
000568 => x"c184", -- LDIL
000569 => x"bff8", -- BL
000570 => x"c0c6", -- LDIL
000571 => x"1809", -- CMP
000572 => x"9003", -- BMI
000573 => x"c0a0", -- LDIL
000574 => x"1001", -- SUB
000575 => x"c0b0", -- LDIL
000576 => x"1809", -- CMP
000577 => x"91f8", -- BMI
000578 => x"c0c6", -- LDIL
000579 => x"1818", -- CMP
000580 => x"91f5", -- BMI
000581 => x"c0b9", -- LDIL
000582 => x"1818", -- CMP
000583 => x"a404", -- BLS
000584 => x"c0c1", -- LDIL
000585 => x"1809", -- CMP
000586 => x"a1ef", -- BHI
000587 => x"0080", -- MOV
000588 => x"bfe0", -- BL
000589 => x"c030", -- LDIL
000590 => x"1090", -- SUB
000591 => x"c009", -- LDIL
000592 => x"1809", -- CMP
000593 => x"a402", -- BLS
000594 => x"0497", -- DEC
000595 => x"3e42", -- SFT
000596 => x"3e42", -- SFT
000597 => x"3e42", -- SFT
000598 => x"3e42", -- SFT
000599 => x"2641", -- ORR
000600 => x"05b9", -- DECS
000601 => x"85e0", -- BNE
000602 => x"3420", -- RET
000603 => x"0370", -- MOV
000604 => x"3d42", -- SFT
000605 => x"3d22", -- SFT
000606 => x"3d22", -- SFT
000607 => x"3d22", -- SFT
000608 => x"be0f", -- BL
000609 => x"bfcb", -- BL
000610 => x"3d40", -- SFT
000611 => x"be0c", -- BL
000612 => x"bfc8", -- BL
000613 => x"3d45", -- SFT
000614 => x"3d25", -- SFT
000615 => x"3d25", -- SFT
000616 => x"3d25", -- SFT
000617 => x"be06", -- BL
000618 => x"bfc2", -- BL
000619 => x"0140", -- MOV
000620 => x"be03", -- BL
000621 => x"bfbf", -- BL
000622 => x"3460", -- RET
000623 => x"c08f", -- LDIL
000624 => x"2121", -- AND
000625 => x"c089", -- LDIL
000626 => x"181a", -- CMP
000627 => x"8803", -- BCS
000628 => x"c0b0", -- LDIL
000629 => x"bc02", -- B
000630 => x"c0b7", -- LDIL
000631 => x"0892", -- ADD
000632 => x"3470", -- RET
000633 => x"ed0b", -- MCR
000634 => x"ec22", -- MRC
000635 => x"dc03", -- STB
000636 => x"b9fe", -- BTS
000637 => x"ec23", -- MRC
000638 => x"3470", -- RET
000639 => x"00f0", -- MOV
000640 => x"c050", -- LDIL
000641 => x"c837", -- LDIH
000642 => x"ed0a", -- MCR
000643 => x"c001", -- LDIL
000644 => x"ed0c", -- MCR
000645 => x"c006", -- LDIL
000646 => x"bff3", -- BL
000647 => x"c050", -- LDIL
000648 => x"c83f", -- LDIH
000649 => x"ed0a", -- MCR
000650 => x"c000", -- LDIL
000651 => x"c805", -- LDIH
000652 => x"bfed", -- BL
000653 => x"dc01", -- STB
000654 => x"b80a", -- BTS
000655 => x"c554", -- LDIL
000656 => x"c907", -- LDIH
000657 => x"bf86", -- BL
000658 => x"c564", -- LDIL
000659 => x"c907", -- LDIH
000660 => x"bf83", -- BL
000661 => x"bf9c", -- BL
000662 => x"2800", -- CLR
000663 => x"3400", -- GT
000664 => x"c040", -- LDIL
000665 => x"c83f", -- LDIH
000666 => x"ed0a", -- MCR
000667 => x"c001", -- LDIL
000668 => x"ed0c", -- MCR
000669 => x"3c20", -- SFT
000670 => x"c802", -- LDIH
000671 => x"bfda", -- BL
000672 => x"03a0", -- MOV
000673 => x"cb80", -- LDIH
000674 => x"3ff0", -- SFT
000675 => x"0030", -- MOV
000676 => x"c800", -- LDIH
000677 => x"2407", -- ORR
000678 => x"bfd3", -- BL
000679 => x"2800", -- CLR
000680 => x"ed0c", -- MCR
000681 => x"c050", -- LDIL
000682 => x"c83f", -- LDIH
000683 => x"ed0a", -- MCR
000684 => x"c001", -- LDIL
000685 => x"ed0c", -- MCR
000686 => x"c000", -- LDIL
000687 => x"c805", -- LDIH
000688 => x"bfc9", -- BL
000689 => x"dc00", -- STB
000690 => x"b9fc", -- BTS
000691 => x"3410", -- RET
000692 => x"00f0", -- MOV
000693 => x"c040", -- LDIL
000694 => x"c83f", -- LDIH
000695 => x"ed0a", -- MCR
000696 => x"c001", -- LDIL
000697 => x"ed0c", -- MCR
000698 => x"3c20", -- SFT
000699 => x"c803", -- LDIH
000700 => x"bfbd", -- BL
000701 => x"0020", -- MOV
000702 => x"c800", -- LDIH
000703 => x"3c00", -- SFT
000704 => x"bfb9", -- BL
000705 => x"29b3", -- CLR
000706 => x"ed3c", -- MCR
000707 => x"0180", -- MOV
000708 => x"c980", -- LDIH
000709 => x"3410", -- RET
000710 => x"c54e", -- LDIL
000711 => x"c906", -- LDIH
000712 => x"bf52", -- BL
000713 => x"bf6d", -- BL
000714 => x"edca", -- MCR
000715 => x"bf6b", -- BL
000716 => x"edc9", -- MCR
000717 => x"bf64", -- BL
000718 => x"c08d", -- LDIL
000719 => x"1809", -- CMP
000720 => x"8005", -- BEQ
000721 => x"c088", -- LDIL
000722 => x"1809", -- CMP
000723 => x"8009", -- BEQ
000724 => x"bdf9", -- B
000725 => x"be0b", -- BL
000726 => x"0300", -- MOV
000727 => x"c572", -- LDIL
000728 => x"c906", -- LDIH
000729 => x"bf41", -- BL
000730 => x"0260", -- MOV
000731 => x"bf80", -- BL
000732 => x"bf4b", -- BL
000733 => x"c6c6", -- LDIL
000734 => x"ca80", -- LDIH
000735 => x"3450", -- GT
000736 => x"e5b0", -- CDP
000737 => x"ec30", -- MRC
000738 => x"dc06", -- STB
000739 => x"b9fe", -- BTS
000740 => x"ec34", -- MRC
000741 => x"3470", -- RET
000742 => x"4174", -- .DW
000743 => x"6c61", -- .DW
000744 => x"732d", -- .DW
000745 => x"324b", -- .DW
000746 => x"2042", -- .DW
000747 => x"6f6f", -- .DW
000748 => x"746c", -- .DW
000749 => x"6f61", -- .DW
000750 => x"6465", -- .DW
000751 => x"7220", -- .DW
000752 => x"2d20", -- .DW
000753 => x"5632", -- .DW
000754 => x"3031", -- .DW
000755 => x"3430", -- .DW
000756 => x"3431", -- .DW
000757 => x"300d", -- .DW
000758 => x"0a62", -- .DW
000759 => x"7920", -- .DW
000760 => x"5374", -- .DW
000761 => x"6570", -- .DW
000762 => x"6861", -- .DW
000763 => x"6e20", -- .DW
000764 => x"4e6f", -- .DW
000765 => x"6c74", -- .DW
000766 => x"696e", -- .DW
000767 => x"672c", -- .DW
000768 => x"2073", -- .DW
000769 => x"746e", -- .DW
000770 => x"6f6c", -- .DW
000771 => x"7469", -- .DW
000772 => x"6e67", -- .DW
000773 => x"4067", -- .DW
000774 => x"6d61", -- .DW
000775 => x"696c", -- .DW
000776 => x"2e63", -- .DW
000777 => x"6f6d", -- .DW
000778 => x"0d0a", -- .DW
000779 => x"7777", -- .DW
000780 => x"772e", -- .DW
000781 => x"6f70", -- .DW
000782 => x"656e", -- .DW
000783 => x"636f", -- .DW
000784 => x"7265", -- .DW
000785 => x"732e", -- .DW
000786 => x"6f72", -- .DW
000787 => x"672f", -- .DW
000788 => x"7072", -- .DW
000789 => x"6f6a", -- .DW
000790 => x"6563", -- .DW
000791 => x"742c", -- .DW
000792 => x"6174", -- .DW
000793 => x"6c61", -- .DW
000794 => x"735f", -- .DW
000795 => x"636f", -- .DW
000796 => x"7265", -- .DW
000797 => x"0d0a", -- .DW
000798 => x"0000", -- .DW
000799 => x"426f", -- .DW
000800 => x"6f74", -- .DW
000801 => x"6c6f", -- .DW
000802 => x"6164", -- .DW
000803 => x"6572", -- .DW
000804 => x"2040", -- .DW
000805 => x"2030", -- .DW
000806 => x"7800", -- .DW
000807 => x"436c", -- .DW
000808 => x"6f63", -- .DW
000809 => x"6b20", -- .DW
000810 => x"2848", -- .DW
000811 => x"7a29", -- .DW
000812 => x"3a20", -- .DW
000813 => x"3078", -- .DW
000814 => x"0000", -- .DW
000815 => x"426f", -- .DW
000816 => x"6f74", -- .DW
000817 => x"696e", -- .DW
000818 => x"672e", -- .DW
000819 => x"2e2e", -- .DW
000820 => x"0000", -- .DW
000821 => x"4275", -- .DW
000822 => x"726e", -- .DW
000823 => x"696e", -- .DW
000824 => x"6720", -- .DW
000825 => x"4545", -- .DW
000826 => x"5052", -- .DW
000827 => x"4f4d", -- .DW
000828 => x"0000", -- .DW
000829 => x"5761", -- .DW
000830 => x"6974", -- .DW
000831 => x"696e", -- .DW
000832 => x"6720", -- .DW
000833 => x"666f", -- .DW
000834 => x"7220", -- .DW
000835 => x"696d", -- .DW
000836 => x"6167", -- .DW
000837 => x"6520", -- .DW
000838 => x"6461", -- .DW
000839 => x"7461", -- .DW
000840 => x"2e2e", -- .DW
000841 => x"2e00", -- .DW
000842 => x"5374", -- .DW
000843 => x"6172", -- .DW
000844 => x"7469", -- .DW
000845 => x"6e67", -- .DW
000846 => x"2069", -- .DW
000847 => x"6d61", -- .DW
000848 => x"6765", -- .DW
000849 => x"2000", -- .DW
000850 => x"446f", -- .DW
000851 => x"776e", -- .DW
000852 => x"6c6f", -- .DW
000853 => x"6164", -- .DW
000854 => x"2063", -- .DW
000855 => x"6f6d", -- .DW
000856 => x"706c", -- .DW
000857 => x"6574", -- .DW
000858 => x"6564", -- .DW
000859 => x"2100", -- .DW
000860 => x"456e", -- .DW
000861 => x"7465", -- .DW
000862 => x"7220", -- .DW
000863 => x"7061", -- .DW
000864 => x"6765", -- .DW
000865 => x"2028", -- .DW
000866 => x"3468", -- .DW
000867 => x"6578", -- .DW
000868 => x"293a", -- .DW
000869 => x"2030", -- .DW
000870 => x"7800", -- .DW
000871 => x"456e", -- .DW
000872 => x"7465", -- .DW
000873 => x"7220", -- .DW
000874 => x"6164", -- .DW
000875 => x"6472", -- .DW
000876 => x"2028", -- .DW
000877 => x"3868", -- .DW
000878 => x"6578", -- .DW
000879 => x"293a", -- .DW
000880 => x"2030", -- .DW
000881 => x"7800", -- .DW
000882 => x"4368", -- .DW
000883 => x"6563", -- .DW
000884 => x"6b73", -- .DW
000885 => x"756d", -- .DW
000886 => x"3a20", -- .DW
000887 => x"3078", -- .DW
000888 => x"0000", -- .DW
000889 => x"0d0a", -- .DW
000890 => x"2d3e", -- .DW
000891 => x"2030", -- .DW
000892 => x"7800", -- .DW
000893 => x"636d", -- .DW
000894 => x"642f", -- .DW
000895 => x"626f", -- .DW
000896 => x"6f74", -- .DW
000897 => x"2d73", -- .DW
000898 => x"7769", -- .DW
000899 => x"7463", -- .DW
000900 => x"6800", -- .DW
000901 => x"2030", -- .DW
000902 => x"2f27", -- .DW
000903 => x"3030", -- .DW
000904 => x"273a", -- .DW
000905 => x"2052", -- .DW
000906 => x"6573", -- .DW
000907 => x"7461", -- .DW
000908 => x"7274", -- .DW
000909 => x"2063", -- .DW
000910 => x"6f6e", -- .DW
000911 => x"736f", -- .DW
000912 => x"6c65", -- .DW
000913 => x"0d0a", -- .DW
000914 => x"2031", -- .DW
000915 => x"2f27", -- .DW
000916 => x"3031", -- .DW
000917 => x"273a", -- .DW
000918 => x"2042", -- .DW
000919 => x"6f6f", -- .DW
000920 => x"7420", -- .DW
000921 => x"6672", -- .DW
000922 => x"6f6d", -- .DW
000923 => x"2055", -- .DW
000924 => x"4152", -- .DW
000925 => x"540d", -- .DW
000926 => x"0a20", -- .DW
000927 => x"322f", -- .DW
000928 => x"2731", -- .DW
000929 => x"3027", -- .DW
000930 => x"3a20", -- .DW
000931 => x"426f", -- .DW
000932 => x"6f74", -- .DW
000933 => x"2066", -- .DW
000934 => x"726f", -- .DW
000935 => x"6d20", -- .DW
000936 => x"4545", -- .DW
000937 => x"5052", -- .DW
000938 => x"4f4d", -- .DW
000939 => x"0d0a", -- .DW
000940 => x"2033", -- .DW
000941 => x"2f27", -- .DW
000942 => x"3131", -- .DW
000943 => x"273a", -- .DW
000944 => x"2042", -- .DW
000945 => x"6f6f", -- .DW
000946 => x"7420", -- .DW
000947 => x"6672", -- .DW
000948 => x"6f6d", -- .DW
000949 => x"206d", -- .DW
000950 => x"656d", -- .DW
000951 => x"6f72", -- .DW
000952 => x"7900", -- .DW
000953 => x"2070", -- .DW
000954 => x"3a20", -- .DW
000955 => x"4275", -- .DW
000956 => x"726e", -- .DW
000957 => x"2045", -- .DW
000958 => x"4550", -- .DW
000959 => x"524f", -- .DW
000960 => x"4d00", -- .DW
000961 => x"2064", -- .DW
000962 => x"3a20", -- .DW
000963 => x"5241", -- .DW
000964 => x"4d20", -- .DW
000965 => x"6475", -- .DW
000966 => x"6d70", -- .DW
000967 => x"0000", -- .DW
000968 => x"2072", -- .DW
000969 => x"3a20", -- .DW
000970 => x"5265", -- .DW
000971 => x"7365", -- .DW
000972 => x"7400", -- .DW
000973 => x"2077", -- .DW
000974 => x"3a20", -- .DW
000975 => x"5742", -- .DW
000976 => x"2064", -- .DW
000977 => x"756d", -- .DW
000978 => x"7000", -- .DW
000979 => x"636d", -- .DW
000980 => x"643a", -- .DW
000981 => x"3e20", -- .DW
000982 => x"0000", -- .DW
000983 => x"494d", -- .DW
000984 => x"4147", -- .DW
000985 => x"4520", -- .DW
000986 => x"4552", -- .DW
000987 => x"5221", -- .DW
000988 => x"0000", -- .DW
000989 => x"0d0a", -- .DW
000990 => x"4952", -- .DW
000991 => x"5120", -- .DW
000992 => x"4552", -- .DW
000993 => x"5221", -- .DW
000994 => x"0000", -- .DW
000995 => x"4348", -- .DW
000996 => x"4543", -- .DW
000997 => x"4b53", -- .DW
000998 => x"554d", -- .DW
000999 => x"2045", -- .DW
001000 => x"5252", -- .DW
001001 => x"2100", -- .DW
001002 => x"5350", -- .DW
001003 => x"492f", -- .DW
001004 => x"4545", -- .DW
001005 => x"5052", -- .DW
001006 => x"4f4d", -- .DW
001007 => x"2045", -- .DW
001008 => x"5252", -- .DW
001009 => x"2100", -- .DW
001010 => x"5072", -- .DW
001011 => x"6573", -- .DW
001012 => x"7320", -- .DW
001013 => x"616e", -- .DW
001014 => x"7920", -- .DW
001015 => x"6b65", -- .DW
001016 => x"7900", -- .DW
others => x"0000" -- NOP
000000 => x"bc0e", -- B
000001 => x"bc04", -- B
000002 => x"bc03", -- B
000003 => x"bc02", -- B
000004 => x"bc01", -- B
000005 => x"c000", -- LDIL
000006 => x"cc00", -- LDIH
000007 => x"ec8a", -- MCR
000008 => x"cc19", -- LDIH
000009 => x"ed0f", -- MCR
000010 => x"c52a", -- LDIL
000011 => x"c907", -- LDIH
000012 => x"be86", -- BL
000013 => x"bc00", -- B
000014 => x"ec11", -- MRC
000015 => x"ec88", -- MCR
000016 => x"ec8a", -- MCR
000017 => x"c380", -- LDIL
000018 => x"cff8", -- LDIH
000019 => x"1c07", -- STSR
000020 => x"2800", -- CLR
000021 => x"ec08", -- MCR
000022 => x"ec0b", -- MCR
000023 => x"ec0e", -- MCR
000024 => x"ec00", -- MRC
000025 => x"ed88", -- MCR
000026 => x"c002", -- LDIL
000027 => x"ed8b", -- MCR
000028 => x"c064", -- LDIL
000029 => x"ed8d", -- MCR
000030 => x"c901", -- LDIH
000031 => x"ed2f", -- MCR
000032 => x"ec17", -- MRC
000033 => x"ec97", -- MRC
000034 => x"c160", -- LDIL
000035 => x"c909", -- LDIH
000036 => x"c18f", -- LDIL
000037 => x"0923", -- ADD
000038 => x"29b3", -- CLR
000039 => x"2a44", -- CLR
000040 => x"100a", -- SUBS
000041 => x"149b", -- SBCS
000042 => x"9003", -- BMI
000043 => x"0241", -- INC
000044 => x"bdfc", -- B
000045 => x"ed49", -- MCR
000046 => x"ec22", -- MRC
000047 => x"d406", -- SBR
000048 => x"ed0a", -- MCR
000049 => x"c538", -- LDIL
000050 => x"c905", -- LDIH
000051 => x"be5f", -- BL
000052 => x"c12e", -- LDIL
000053 => x"c906", -- LDIH
000054 => x"be5c", -- BL
000055 => x"ee11", -- MRC
000056 => x"be5e", -- BL
000057 => x"c13e", -- LDIL
000058 => x"c906", -- LDIH
000059 => x"be57", -- BL
000060 => x"ee97", -- MRC
000061 => x"ee17", -- MRC
000062 => x"be58", -- BL
000063 => x"0250", -- MOV
000064 => x"be56", -- BL
000065 => x"be52", -- BL
000066 => x"ec27", -- MRC
000067 => x"c083", -- LDIL
000068 => x"2001", -- AND
000069 => x"c330", -- LDIL
000070 => x"0b60", -- ADD
000071 => x"bc0f", -- B
000072 => x"c55e", -- LDIL
000073 => x"c906", -- LDIH
000074 => x"be48", -- BL
000075 => x"c14e", -- LDIL
000076 => x"c907", -- LDIH
000077 => x"be45", -- BL
000078 => x"c514", -- LDIL
000079 => x"c907", -- LDIH
000080 => x"be42", -- BL
000081 => x"be44", -- BL
000082 => x"0300", -- MOV
000083 => x"0080", -- MOV
000084 => x"be40", -- BL
000085 => x"be3e", -- BL
000086 => x"c0b0", -- LDIL
000087 => x"181e", -- CMP
000088 => x"81f0", -- BEQ
000089 => x"c0b1", -- LDIL
000090 => x"181e", -- CMP
000091 => x"809b", -- BEQ
000092 => x"c0b2", -- LDIL
000093 => x"181e", -- CMP
000094 => x"8064", -- BEQ
000095 => x"c0b3", -- LDIL
000096 => x"181e", -- CMP
000097 => x"802b", -- BEQ
000098 => x"c0b4", -- LDIL
000099 => x"181e", -- CMP
000100 => x"8033", -- BEQ
000101 => x"c0bf", -- LDIL
000102 => x"181e", -- CMP
000103 => x"8405", -- BNE
000104 => x"c102", -- LDIL
000105 => x"c901", -- LDIH
000106 => x"be28", -- BL
000107 => x"bde3", -- B
000108 => x"c2be", -- LDIL
000109 => x"ca83", -- LDIH
000110 => x"c0f0", -- LDIL
000111 => x"181e", -- CMP
000112 => x"f705", -- RBAEQ
000113 => x"c0e4", -- LDIL
000114 => x"181e", -- CMP
000115 => x"80f1", -- BEQ
000116 => x"c2e4", -- LDIL
000117 => x"ca85", -- LDIH
000118 => x"c0f7", -- LDIL
000119 => x"181e", -- CMP
000120 => x"f705", -- RBAEQ
000121 => x"c0f2", -- LDIL
000122 => x"181e", -- CMP
000123 => x"85d3", -- BNE
000124 => x"2800", -- CLR
000125 => x"c080", -- LDIL
000126 => x"cc80", -- LDIH
000127 => x"ec99", -- MCR
000128 => x"3400", -- GT
000129 => x"4b65", -- .DW
000130 => x"6570", -- .DW
000131 => x"696e", -- .DW
000132 => x"2720", -- .DW
000133 => x"6974", -- .DW
000134 => x"2063", -- .DW
000135 => x"6f75", -- .DW
000136 => x"6e74", -- .DW
000137 => x"7279", -- .DW
000138 => x"210d", -- .DW
000139 => x"0a00", -- .DW
000140 => x"c14e", -- LDIL
000141 => x"c906", -- LDIH
000142 => x"be04", -- BL
000143 => x"2800", -- CLR
000144 => x"2100", -- STUB
000145 => x"bca7", -- B
000146 => x"bc9c", -- B
000147 => x"bc9c", -- B
000148 => x"bc9c", -- B
000149 => x"bc9c", -- B
000150 => x"bc9f", -- B
000151 => x"c52e", -- LDIL
000152 => x"c906", -- LDIH
000153 => x"be95", -- BL
000154 => x"be9d", -- BL
000155 => x"edca", -- MCR
000156 => x"be9b", -- BL
000157 => x"edc9", -- MCR
000158 => x"c426", -- LDIL
000159 => x"c805", -- LDIH
000160 => x"3404", -- GTL
000161 => x"be8e", -- BL
000162 => x"be94", -- BL
000163 => x"c47e", -- LDIL
000164 => x"cc4a", -- LDIH
000165 => x"180e", -- CMP
000166 => x"848d", -- BNE
000167 => x"be8f", -- BL
000168 => x"3f64", -- SFT
000169 => x"2066", -- STUB
000170 => x"be8c", -- BL
000171 => x"20e6", -- STUB
000172 => x"be8a", -- BL
000173 => x"2166", -- STUB
000174 => x"be88", -- BL
000175 => x"21e6", -- STUB
000176 => x"be86", -- BL
000177 => x"2266", -- STUB
000178 => x"be84", -- BL
000179 => x"22e6", -- STUB
000180 => x"be82", -- BL
000181 => x"2366", -- STUB
000182 => x"c280", -- LDIL
000183 => x"ecda", -- MCR
000184 => x"ec5d", -- MCR
000185 => x"be7d", -- BL
000186 => x"7f5a", -- STR
000187 => x"ec05", -- MRC
000188 => x"2806", -- EOR
000189 => x"ec0d", -- MCR
000190 => x"2400", -- LDUB
000191 => x"1858", -- CMP
000192 => x"85f9", -- BNE
000193 => x"bc5a", -- B
000194 => x"c14e", -- LDIL
000195 => x"c906", -- LDIH
000196 => x"be6a", -- BL
000197 => x"c100", -- LDIL
000198 => x"be29", -- BL
000199 => x"c47e", -- LDIL
000200 => x"cc4a", -- LDIH
000201 => x"180d", -- CMP
000202 => x"8469", -- BNE
000203 => x"c102", -- LDIL
000204 => x"be23", -- BL
000205 => x"3ed4", -- SFT
000206 => x"2055", -- STUB
000207 => x"c104", -- LDIL
000208 => x"be1f", -- BL
000209 => x"20d5", -- STUB
000210 => x"c106", -- LDIL
000211 => x"be1c", -- BL
000212 => x"2155", -- STUB
000213 => x"c108", -- LDIL
000214 => x"be19", -- BL
000215 => x"21d5", -- STUB
000216 => x"c10a", -- LDIL
000217 => x"be16", -- BL
000218 => x"2255", -- STUB
000219 => x"c10c", -- LDIL
000220 => x"be13", -- BL
000221 => x"22d5", -- STUB
000222 => x"c10e", -- LDIL
000223 => x"be10", -- BL
000224 => x"2355", -- STUB
000225 => x"c200", -- LDIL
000226 => x"ecca", -- MCR
000227 => x"ec4d", -- MCR
000228 => x"c010", -- LDIL
000229 => x"0940", -- ADD
000230 => x"be09", -- BL
000231 => x"7eca", -- STR
000232 => x"ec05", -- MRC
000233 => x"2805", -- EOR
000234 => x"ec0d", -- MCR
000235 => x"2400", -- LDUB
000236 => x"1848", -- CMP
000237 => x"85f7", -- BNE
000238 => x"bc2d", -- B
000239 => x"0370", -- MOV
000240 => x"be42", -- BL
000241 => x"3eb0", -- SFT
000242 => x"0121", -- INC
000243 => x"be3f", -- BL
000244 => x"26d3", -- ORR
000245 => x"3460", -- RET
000246 => x"c166", -- LDIL
000247 => x"c906", -- LDIH
000248 => x"be36", -- BL
000249 => x"be38", -- BL
000250 => x"3c80", -- SFT
000251 => x"be36", -- BL
000252 => x"2490", -- ORR
000253 => x"c47e", -- LDIL
000254 => x"cc4a", -- LDIH
000255 => x"1818", -- CMP
000256 => x"8433", -- BNE
000257 => x"be27", -- BL
000258 => x"3c94", -- SFT
000259 => x"2011", -- STUB
000260 => x"be24", -- BL
000261 => x"2091", -- STUB
000262 => x"be22", -- BL
000263 => x"2111", -- STUB
000264 => x"be20", -- BL
000265 => x"2191", -- STUB
000266 => x"be1e", -- BL
000267 => x"2211", -- STUB
000268 => x"be1c", -- BL
000269 => x"2291", -- STUB
000270 => x"be1a", -- BL
000271 => x"2311", -- STUB
000272 => x"2ad5", -- CLR
000273 => x"ecda", -- MCR
000274 => x"ec5d", -- MCR
000275 => x"be15", -- BL
000276 => x"7cda", -- STR
000277 => x"ec05", -- MRC
000278 => x"2801", -- EOR
000279 => x"ec0d", -- MCR
000280 => x"2400", -- LDUB
000281 => x"1858", -- CMP
000282 => x"85f9", -- BNE
000283 => x"ec11", -- MRC
000284 => x"ec8a", -- MCR
000285 => x"c50c", -- LDIL
000286 => x"c906", -- LDIH
000287 => x"be0f", -- BL
000288 => x"ec05", -- MRC
000289 => x"2491", -- LDUB
000290 => x"1809", -- CMP
000291 => x"8015", -- BEQ
000292 => x"c538", -- LDIL
000293 => x"c907", -- LDIH
000294 => x"be08", -- BL
000295 => x"bccb", -- B
000296 => x"0370", -- MOV
000297 => x"be08", -- BL
000298 => x"3c80", -- SFT
000299 => x"be06", -- BL
000300 => x"2490", -- ORR
000301 => x"3460", -- RET
000302 => x"bcc7", -- B
000303 => x"bcd0", -- B
000304 => x"bcd4", -- B
000305 => x"bcd8", -- B
000306 => x"bc6b", -- B
000307 => x"bcbc", -- B
000308 => x"bd1a", -- B
000309 => x"bc69", -- B
000310 => x"bcbe", -- B
000311 => x"bcd7", -- B
000312 => x"c54c", -- LDIL
000313 => x"c906", -- LDIH
000314 => x"bebb", -- BL
000315 => x"ee05", -- MRC
000316 => x"bef7", -- BL
000317 => x"bec2", -- BL
000318 => x"c17c", -- LDIL
000319 => x"c906", -- LDIH
000320 => x"beb5", -- BL
000321 => x"24aa", -- LDUBS
000322 => x"8010", -- BEQ
000323 => x"c0a2", -- LDIL
000324 => x"bec0", -- BL
000325 => x"24a2", -- LDUB
000326 => x"be18", -- BL
000327 => x"24b3", -- LDUB
000328 => x"be16", -- BL
000329 => x"24c4", -- LDUB
000330 => x"be14", -- BL
000331 => x"24d5", -- LDUB
000332 => x"be12", -- BL
000333 => x"24e6", -- LDUB
000334 => x"be10", -- BL
000335 => x"c0a2", -- LDIL
000336 => x"beb4", -- BL
000337 => x"beae", -- BL
000338 => x"bead", -- BL
000339 => x"c080", -- LDIL
000340 => x"ccc0", -- LDIH
000341 => x"1c01", -- STSR
000342 => x"2800", -- CLR
000343 => x"ed0f", -- MCR
000344 => x"ec88", -- MCR
000345 => x"ec8b", -- MCR
000346 => x"ec8c", -- MCR
000347 => x"ec8a", -- MCR
000348 => x"ec89", -- MCR
000349 => x"3400", -- GT
000350 => x"0370", -- MOV
000351 => x"3c90", -- SFT
000352 => x"bea4", -- BL
000353 => x"3c90", -- SFT
000354 => x"bea2", -- BL
000355 => x"3460", -- RET
000356 => x"c520", -- LDIL
000357 => x"c906", -- LDIH
000358 => x"be8f", -- BL
000359 => x"bea7", -- BL
000360 => x"c526", -- LDIL
000361 => x"c905", -- LDIH
000362 => x"3424", -- GTL
000363 => x"ecca", -- MCR
000364 => x"be93", -- BL
000365 => x"c280", -- LDIL
000366 => x"c00f", -- LDIL
000367 => x"2058", -- ANDS
000368 => x"840a", -- BNE
000369 => x"be8e", -- BL
000370 => x"c0a4", -- LDIL
000371 => x"be91", -- BL
000372 => x"0250", -- MOV
000373 => x"bebe", -- BL
000374 => x"c0ba", -- LDIL
000375 => x"be8d", -- BL
000376 => x"c0a0", -- LDIL
000377 => x"be8b", -- BL
000378 => x"7a5a", -- LDR
000379 => x"c0a0", -- LDIL
000380 => x"be88", -- BL
000381 => x"beb6", -- BL
000382 => x"c00f", -- LDIL
000383 => x"2058", -- ANDS
000384 => x"8414", -- BNE
000385 => x"c0a0", -- LDIL
000386 => x"be82", -- BL
000387 => x"be81", -- BL
000388 => x"c010", -- LDIL
000389 => x"1250", -- SUB
000390 => x"c470", -- LDIL
000391 => x"2240", -- AND
000392 => x"78c9", -- LDR
000393 => x"3c90", -- SFT
000394 => x"c880", -- LDIH
000395 => x"c020", -- LDIL
000396 => x"1818", -- CMP
000397 => x"a402", -- BLS
000398 => x"c0ae", -- LDIL
000399 => x"be75", -- BL
000400 => x"c08f", -- LDIL
000401 => x"2014", -- AND
000402 => x"3409", -- TEQ
000403 => x"85f5", -- BNE
000404 => x"ec20", -- MRC
000405 => x"dc0f", -- STB
000406 => x"b804", -- BTS
000407 => x"c5fe", -- LDIL
000408 => x"343d", -- TEQ
000409 => x"85d5", -- BNE
000410 => x"be6f", -- BL
000411 => x"2800", -- CLR
000412 => x"3400", -- GT
000413 => x"bc56", -- B
000414 => x"bc95", -- B
000415 => x"c001", -- LDIL
000416 => x"ed0c", -- MCR
000417 => x"c050", -- LDIL
000418 => x"c83f", -- LDIH
000419 => x"ed0a", -- MCR
000420 => x"c000", -- LDIL
000421 => x"c801", -- LDIH
000422 => x"beab", -- BL
000423 => x"c158", -- LDIL
000424 => x"c906", -- LDIH
000425 => x"be4c", -- BL
000426 => x"c166", -- LDIL
000427 => x"c906", -- LDIH
000428 => x"be49", -- BL
000429 => x"be5c", -- BL
000430 => x"3c80", -- SFT
000431 => x"be5a", -- BL
000432 => x"2410", -- ORR
000433 => x"c4fe", -- LDIL
000434 => x"ccca", -- LDIH
000435 => x"1809", -- CMP
000436 => x"843b", -- BNE
000437 => x"c100", -- LDIL
000438 => x"c6fe", -- LDIL
000439 => x"ceca", -- LDIH
000440 => x"be30", -- BL
000441 => x"be50", -- BL
000442 => x"3c80", -- SFT
000443 => x"be4e", -- BL
000444 => x"2690", -- ORR
000445 => x"3ed4", -- SFT
000446 => x"2055", -- STUB
000447 => x"c102", -- LDIL
000448 => x"be28", -- BL
000449 => x"be48", -- BL
000450 => x"3c80", -- SFT
000451 => x"be46", -- BL
000452 => x"2690", -- ORR
000453 => x"20d5", -- STUB
000454 => x"c104", -- LDIL
000455 => x"be21", -- BL
000456 => x"c106", -- LDIL
000457 => x"be40", -- BL
000458 => x"0180", -- MOV
000459 => x"be8c", -- BL
000460 => x"0121", -- INC
000461 => x"c010", -- LDIL
000462 => x"1828", -- CMP
000463 => x"85fa", -- BNE
000464 => x"c110", -- LDIL
000465 => x"2ad5", -- CLR
000466 => x"be37", -- BL
000467 => x"0180", -- MOV
000468 => x"be83", -- BL
000469 => x"0121", -- INC
000470 => x"2400", -- LDUB
000471 => x"02d1", -- INC
000472 => x"1858", -- CMP
000473 => x"85f9", -- BNE
000474 => x"c001", -- LDIL
000475 => x"ed0c", -- MCR
000476 => x"c050", -- LDIL
000477 => x"c83f", -- LDIH
000478 => x"ed0a", -- MCR
000479 => x"c00c", -- LDIL
000480 => x"c801", -- LDIH
000481 => x"be70", -- BL
000482 => x"c50c", -- LDIL
000483 => x"c906", -- LDIH
000484 => x"be11", -- BL
000485 => x"c690", -- LDIL
000486 => x"ca80", -- LDIH
000487 => x"3450", -- GT
000488 => x"0370", -- MOV
000489 => x"3dd0", -- SFT
000490 => x"be6d", -- BL
000491 => x"0121", -- INC
000492 => x"01d0", -- MOV
000493 => x"be6a", -- BL
000494 => x"3460", -- RET
000495 => x"c51c", -- LDIL
000496 => x"c907", -- LDIH
000497 => x"be04", -- BL
000498 => x"bcba", -- B
000499 => x"bc94", -- B
000500 => x"bca5", -- B
000501 => x"01f0", -- MOV
000502 => x"7829", -- LDR
000503 => x"c080", -- LDIL
000504 => x"ccff", -- LDIH
000505 => x"2081", -- AND
000506 => x"3c98", -- SFTS
000507 => x"8003", -- BEQ
000508 => x"be08", -- BL
000509 => x"bdf9", -- B
000510 => x"3430", -- RET
000511 => x"0170", -- MOV
000512 => x"c08d", -- LDIL
000513 => x"be03", -- BL
000514 => x"c08a", -- LDIL
000515 => x"03a0", -- MOV
000516 => x"ec22", -- MRC
000517 => x"dc05", -- STB
000518 => x"b9fe", -- BTS
000519 => x"ed18", -- MCR
000520 => x"3470", -- RET
000521 => x"ec20", -- MRC
000522 => x"dc8f", -- STBI
000523 => x"b9fe", -- BTS
000524 => x"c800", -- LDIH
000525 => x"3470", -- RET
000526 => x"0170", -- MOV
000527 => x"c200", -- LDIL
000528 => x"c184", -- LDIL
000529 => x"bff8", -- BL
000530 => x"c0c6", -- LDIL
000531 => x"1809", -- CMP
000532 => x"9003", -- BMI
000533 => x"c0a0", -- LDIL
000534 => x"1001", -- SUB
000535 => x"c0b0", -- LDIL
000536 => x"1809", -- CMP
000537 => x"91f8", -- BMI
000538 => x"c0c6", -- LDIL
000539 => x"1818", -- CMP
000540 => x"91f5", -- BMI
000541 => x"c0b9", -- LDIL
000542 => x"1818", -- CMP
000543 => x"a404", -- BLS
000544 => x"c0c1", -- LDIL
000545 => x"1809", -- CMP
000546 => x"a1ef", -- BHI
000547 => x"0080", -- MOV
000548 => x"bfe0", -- BL
000549 => x"c030", -- LDIL
000550 => x"1090", -- SUB
000551 => x"c009", -- LDIL
000552 => x"1809", -- CMP
000553 => x"a402", -- BLS
000554 => x"0497", -- DEC
000555 => x"3e42", -- SFT
000556 => x"3e42", -- SFT
000557 => x"3e42", -- SFT
000558 => x"3e42", -- SFT
000559 => x"2641", -- ORR
000560 => x"05b9", -- DECS
000561 => x"85e0", -- BNE
000562 => x"3420", -- RET
000563 => x"0370", -- MOV
000564 => x"3d42", -- SFT
000565 => x"3d22", -- SFT
000566 => x"3d22", -- SFT
000567 => x"3d22", -- SFT
000568 => x"be0f", -- BL
000569 => x"bfcb", -- BL
000570 => x"3d40", -- SFT
000571 => x"be0c", -- BL
000572 => x"bfc8", -- BL
000573 => x"3d45", -- SFT
000574 => x"3d25", -- SFT
000575 => x"3d25", -- SFT
000576 => x"3d25", -- SFT
000577 => x"be06", -- BL
000578 => x"bfc2", -- BL
000579 => x"0140", -- MOV
000580 => x"be03", -- BL
000581 => x"bfbf", -- BL
000582 => x"3460", -- RET
000583 => x"c08f", -- LDIL
000584 => x"2121", -- AND
000585 => x"c089", -- LDIL
000586 => x"181a", -- CMP
000587 => x"8803", -- BCS
000588 => x"c0b0", -- LDIL
000589 => x"bc02", -- B
000590 => x"c0b7", -- LDIL
000591 => x"0892", -- ADD
000592 => x"3470", -- RET
000593 => x"ed0b", -- MCR
000594 => x"ec22", -- MRC
000595 => x"dc03", -- STB
000596 => x"b9fe", -- BTS
000597 => x"ec23", -- MRC
000598 => x"3470", -- RET
000599 => x"00f0", -- MOV
000600 => x"c050", -- LDIL
000601 => x"c837", -- LDIH
000602 => x"ed0a", -- MCR
000603 => x"c001", -- LDIL
000604 => x"ed0c", -- MCR
000605 => x"c006", -- LDIL
000606 => x"bff3", -- BL
000607 => x"c050", -- LDIL
000608 => x"c83f", -- LDIH
000609 => x"ed0a", -- MCR
000610 => x"c000", -- LDIL
000611 => x"c805", -- LDIH
000612 => x"bfed", -- BL
000613 => x"dc01", -- STB
000614 => x"b805", -- BTS
000615 => x"c548", -- LDIL
000616 => x"c907", -- LDIH
000617 => x"bf8c", -- BL
000618 => x"bc42", -- B
000619 => x"c040", -- LDIL
000620 => x"c83f", -- LDIH
000621 => x"ed0a", -- MCR
000622 => x"c001", -- LDIL
000623 => x"ed0c", -- MCR
000624 => x"3c20", -- SFT
000625 => x"c802", -- LDIH
000626 => x"bfdf", -- BL
000627 => x"03a0", -- MOV
000628 => x"cb80", -- LDIH
000629 => x"3ff0", -- SFT
000630 => x"0030", -- MOV
000631 => x"c800", -- LDIH
000632 => x"2407", -- ORR
000633 => x"bfd8", -- BL
000634 => x"2800", -- CLR
000635 => x"ed0c", -- MCR
000636 => x"c050", -- LDIL
000637 => x"c83f", -- LDIH
000638 => x"ed0a", -- MCR
000639 => x"c001", -- LDIL
000640 => x"ed0c", -- MCR
000641 => x"c000", -- LDIL
000642 => x"c805", -- LDIH
000643 => x"bfce", -- BL
000644 => x"dc00", -- STB
000645 => x"b9fc", -- BTS
000646 => x"3410", -- RET
000647 => x"00f0", -- MOV
000648 => x"c040", -- LDIL
000649 => x"c83f", -- LDIH
000650 => x"ed0a", -- MCR
000651 => x"c001", -- LDIL
000652 => x"ed0c", -- MCR
000653 => x"3c20", -- SFT
000654 => x"c803", -- LDIH
000655 => x"bfc2", -- BL
000656 => x"0020", -- MOV
000657 => x"c800", -- LDIH
000658 => x"3c00", -- SFT
000659 => x"bfbe", -- BL
000660 => x"29b3", -- CLR
000661 => x"ed3c", -- MCR
000662 => x"0180", -- MOV
000663 => x"c980", -- LDIH
000664 => x"3410", -- RET
000665 => x"e5b0", -- CDP
000666 => x"ec30", -- MRC
000667 => x"dc06", -- STB
000668 => x"b9fe", -- BTS
000669 => x"c306", -- LDIL
000670 => x"200e", -- ANDS
000671 => x"840a", -- BNE
000672 => x"ecb1", -- MRC
000673 => x"ef32", -- MRC
000674 => x"2800", -- CLR
000675 => x"009a", -- INCS
000676 => x"0f60", -- ADC
000677 => x"ed99", -- MCR
000678 => x"edea", -- MCR
000679 => x"ef34", -- MRC
000680 => x"3470", -- RET
000681 => x"c55a", -- LDIL
000682 => x"c907", -- LDIH
000683 => x"bf4a", -- BL
000684 => x"c568", -- LDIL
000685 => x"c907", -- LDIH
000686 => x"bf47", -- BL
000687 => x"bf5a", -- BL
000688 => x"2800", -- CLR
000689 => x"3400", -- GT
000690 => x"c52e", -- LDIL
000691 => x"c906", -- LDIH
000692 => x"bf41", -- BL
000693 => x"bf59", -- BL
000694 => x"edca", -- MCR
000695 => x"bf57", -- BL
000696 => x"edc9", -- MCR
000697 => x"be1a", -- BL
000698 => x"bf45", -- BL
000699 => x"c53c", -- LDIL
000700 => x"c906", -- LDIH
000701 => x"bf38", -- BL
000702 => x"bf50", -- BL
000703 => x"02c0", -- MOV
000704 => x"be13", -- BL
000705 => x"345d", -- TEQ
000706 => x"800d", -- BEQ
000707 => x"06d1", -- DEC
000708 => x"bf3b", -- BL
000709 => x"bfd4", -- BL
000710 => x"c558", -- LDIL
000711 => x"c906", -- LDIH
000712 => x"bf2d", -- BL
000713 => x"0260", -- MOV
000714 => x"bf69", -- BL
000715 => x"eca0", -- MRC
000716 => x"dc1f", -- STB
000717 => x"b802", -- BTS
000718 => x"bdf3", -- B
000719 => x"bf30", -- BL
000720 => x"c69c", -- LDIL
000721 => x"ca80", -- LDIH
000722 => x"3450", -- GT
000723 => x"0170", -- MOV
000724 => x"bf35", -- BL
000725 => x"c08d", -- LDIL
000726 => x"1809", -- CMP
000727 => x"f702", -- RBAEQ
000728 => x"c088", -- LDIL
000729 => x"1809", -- CMP
000730 => x"81f5", -- BEQ
000731 => x"bdf9", -- B
000732 => x"0d0a", -- .DW
000733 => x"0d0a", -- .DW
000734 => x"4174", -- .DW
000735 => x"6c61", -- .DW
000736 => x"732d", -- .DW
000737 => x"324b", -- .DW
000738 => x"2042", -- .DW
000739 => x"6f6f", -- .DW
000740 => x"746c", -- .DW
000741 => x"6f61", -- .DW
000742 => x"6465", -- .DW
000743 => x"7220", -- .DW
000744 => x"2d20", -- .DW
000745 => x"5632", -- .DW
000746 => x"3031", -- .DW
000747 => x"3430", -- .DW
000748 => x"3431", -- .DW
000749 => x"340d", -- .DW
000750 => x"0a62", -- .DW
000751 => x"7920", -- .DW
000752 => x"5374", -- .DW
000753 => x"6570", -- .DW
000754 => x"6861", -- .DW
000755 => x"6e20", -- .DW
000756 => x"4e6f", -- .DW
000757 => x"6c74", -- .DW
000758 => x"696e", -- .DW
000759 => x"672c", -- .DW
000760 => x"2073", -- .DW
000761 => x"746e", -- .DW
000762 => x"6f6c", -- .DW
000763 => x"7469", -- .DW
000764 => x"6e67", -- .DW
000765 => x"4067", -- .DW
000766 => x"6d61", -- .DW
000767 => x"696c", -- .DW
000768 => x"2e63", -- .DW
000769 => x"6f6d", -- .DW
000770 => x"0d0a", -- .DW
000771 => x"7777", -- .DW
000772 => x"772e", -- .DW
000773 => x"6f70", -- .DW
000774 => x"656e", -- .DW
000775 => x"636f", -- .DW
000776 => x"7265", -- .DW
000777 => x"732e", -- .DW
000778 => x"6f72", -- .DW
000779 => x"672f", -- .DW
000780 => x"7072", -- .DW
000781 => x"6f6a", -- .DW
000782 => x"6563", -- .DW
000783 => x"742c", -- .DW
000784 => x"6174", -- .DW
000785 => x"6c61", -- .DW
000786 => x"735f", -- .DW
000787 => x"636f", -- .DW
000788 => x"7265", -- .DW
000789 => x"0d0a", -- .DW
000790 => x"0000", -- .DW
000791 => x"0d0a", -- .DW
000792 => x"426f", -- .DW
000793 => x"6f74", -- .DW
000794 => x"2070", -- .DW
000795 => x"6167", -- .DW
000796 => x"653a", -- .DW
000797 => x"2030", -- .DW
000798 => x"7800", -- .DW
000799 => x"0d0a", -- .DW
000800 => x"436c", -- .DW
000801 => x"6f63", -- .DW
000802 => x"6b28", -- .DW
000803 => x"487a", -- .DW
000804 => x"293a", -- .DW
000805 => x"2030", -- .DW
000806 => x"7800", -- .DW
000807 => x"426f", -- .DW
000808 => x"6f74", -- .DW
000809 => x"696e", -- .DW
000810 => x"670d", -- .DW
000811 => x"0a00", -- .DW
000812 => x"4275", -- .DW
000813 => x"726e", -- .DW
000814 => x"2045", -- .DW
000815 => x"4550", -- .DW
000816 => x"524f", -- .DW
000817 => x"4d0d", -- .DW
000818 => x"0a00", -- .DW
000819 => x"5761", -- .DW
000820 => x"6974", -- .DW
000821 => x"696e", -- .DW
000822 => x"6720", -- .DW
000823 => x"666f", -- .DW
000824 => x"7220", -- .DW
000825 => x"6461", -- .DW
000826 => x"7461", -- .DW
000827 => x"2e2e", -- .DW
000828 => x"2e0d", -- .DW
000829 => x"0a00", -- .DW
000830 => x"5374", -- .DW
000831 => x"6172", -- .DW
000832 => x"7469", -- .DW
000833 => x"6e67", -- .DW
000834 => x"2069", -- .DW
000835 => x"6d61", -- .DW
000836 => x"6765", -- .DW
000837 => x"2000", -- .DW
000838 => x"446f", -- .DW
000839 => x"776e", -- .DW
000840 => x"6c6f", -- .DW
000841 => x"6164", -- .DW
000842 => x"2063", -- .DW
000843 => x"6f6d", -- .DW
000844 => x"706c", -- .DW
000845 => x"6574", -- .DW
000846 => x"650d", -- .DW
000847 => x"0a00", -- .DW
000848 => x"5061", -- .DW
000849 => x"6765", -- .DW
000850 => x"2028", -- .DW
000851 => x"3468", -- .DW
000852 => x"293a", -- .DW
000853 => x"2024", -- .DW
000854 => x"0000", -- .DW
000855 => x"4164", -- .DW
000856 => x"6472", -- .DW
000857 => x"2028", -- .DW
000858 => x"3868", -- .DW
000859 => x"293a", -- .DW
000860 => x"2024", -- .DW
000861 => x"0000", -- .DW
000862 => x"2377", -- .DW
000863 => x"6f72", -- .DW
000864 => x"6473", -- .DW
000865 => x"2028", -- .DW
000866 => x"3468", -- .DW
000867 => x"293a", -- .DW
000868 => x"2024", -- .DW
000869 => x"0000", -- .DW
000870 => x"4368", -- .DW
000871 => x"6563", -- .DW
000872 => x"6b73", -- .DW
000873 => x"756d", -- .DW
000874 => x"3a20", -- .DW
000875 => x"2400", -- .DW
000876 => x"202d", -- .DW
000877 => x"3e20", -- .DW
000878 => x"2400", -- .DW
000879 => x"0d0a", -- .DW
000880 => x"636d", -- .DW
000881 => x"642f", -- .DW
000882 => x"626f", -- .DW
000883 => x"6f74", -- .DW
000884 => x"2d73", -- .DW
000885 => x"7769", -- .DW
000886 => x"7463", -- .DW
000887 => x"683a", -- .DW
000888 => x"0d0a", -- .DW
000889 => x"2030", -- .DW
000890 => x"2f27", -- .DW
000891 => x"3030", -- .DW
000892 => x"273a", -- .DW
000893 => x"2052", -- .DW
000894 => x"6573", -- .DW
000895 => x"7461", -- .DW
000896 => x"7274", -- .DW
000897 => x"2063", -- .DW
000898 => x"6f6e", -- .DW
000899 => x"736f", -- .DW
000900 => x"6c65", -- .DW
000901 => x"0d0a", -- .DW
000902 => x"2031", -- .DW
000903 => x"2f27", -- .DW
000904 => x"3031", -- .DW
000905 => x"273a", -- .DW
000906 => x"2042", -- .DW
000907 => x"6f6f", -- .DW
000908 => x"7420", -- .DW
000909 => x"5541", -- .DW
000910 => x"5254", -- .DW
000911 => x"0d0a", -- .DW
000912 => x"2032", -- .DW
000913 => x"2f27", -- .DW
000914 => x"3130", -- .DW
000915 => x"273a", -- .DW
000916 => x"2042", -- .DW
000917 => x"6f6f", -- .DW
000918 => x"7420", -- .DW
000919 => x"4545", -- .DW
000920 => x"5052", -- .DW
000921 => x"4f4d", -- .DW
000922 => x"0d0a", -- .DW
000923 => x"2033", -- .DW
000924 => x"2f27", -- .DW
000925 => x"3131", -- .DW
000926 => x"273a", -- .DW
000927 => x"2042", -- .DW
000928 => x"6f6f", -- .DW
000929 => x"7420", -- .DW
000930 => x"6d65", -- .DW
000931 => x"6d6f", -- .DW
000932 => x"7279", -- .DW
000933 => x"0d0a", -- .DW
000934 => x"0000", -- .DW
000935 => x"2034", -- .DW
000936 => x"3a20", -- .DW
000937 => x"426f", -- .DW
000938 => x"6f74", -- .DW
000939 => x"2057", -- .DW
000940 => x"420d", -- .DW
000941 => x"0a20", -- .DW
000942 => x"703a", -- .DW
000943 => x"2042", -- .DW
000944 => x"7572", -- .DW
000945 => x"6e20", -- .DW
000946 => x"4545", -- .DW
000947 => x"5052", -- .DW
000948 => x"4f4d", -- .DW
000949 => x"0d0a", -- .DW
000950 => x"2064", -- .DW
000951 => x"3a20", -- .DW
000952 => x"5241", -- .DW
000953 => x"4d20", -- .DW
000954 => x"6475", -- .DW
000955 => x"6d70", -- .DW
000956 => x"0d0a", -- .DW
000957 => x"2072", -- .DW
000958 => x"3a20", -- .DW
000959 => x"5265", -- .DW
000960 => x"7365", -- .DW
000961 => x"740d", -- .DW
000962 => x"0a20", -- .DW
000963 => x"773a", -- .DW
000964 => x"2057", -- .DW
000965 => x"4220", -- .DW
000966 => x"6475", -- .DW
000967 => x"6d70", -- .DW
000968 => x"0d0a", -- .DW
000969 => x"0000", -- .DW
000970 => x"636d", -- .DW
000971 => x"643a", -- .DW
000972 => x"3e20", -- .DW
000973 => x"0000", -- .DW
000974 => x"494d", -- .DW
000975 => x"4147", -- .DW
000976 => x"4520", -- .DW
000977 => x"4552", -- .DW
000978 => x"5221", -- .DW
000979 => x"0d0a", -- .DW
000980 => x"0000", -- .DW
000981 => x"0d0a", -- .DW
000982 => x"4952", -- .DW
000983 => x"5120", -- .DW
000984 => x"4552", -- .DW
000985 => x"5221", -- .DW
000986 => x"0d0a", -- .DW
000987 => x"0000", -- .DW
000988 => x"4348", -- .DW
000989 => x"4543", -- .DW
000990 => x"4b53", -- .DW
000991 => x"554d", -- .DW
000992 => x"2045", -- .DW
000993 => x"5252", -- .DW
000994 => x"210d", -- .DW
000995 => x"0a00", -- .DW
000996 => x"5350", -- .DW
000997 => x"492f", -- .DW
000998 => x"4545", -- .DW
000999 => x"5052", -- .DW
001000 => x"4f4d", -- .DW
001001 => x"2045", -- .DW
001002 => x"5252", -- .DW
001003 => x"210d", -- .DW
001004 => x"0a00", -- .DW
001005 => x"5742", -- .DW
001006 => x"2042", -- .DW
001007 => x"5553", -- .DW
001008 => x"2045", -- .DW
001009 => x"5252", -- .DW
001010 => x"210d", -- .DW
001011 => x"0a00", -- .DW
001012 => x"5072", -- .DW
001013 => x"6573", -- .DW
001014 => x"7320", -- .DW
001015 => x"616e", -- .DW
001016 => x"7920", -- .DW
001017 => x"6b65", -- .DW
001018 => x"790d", -- .DW
001019 => x"0a00", -- .DW
others => x"0000" -- NOP
);
------------------------------------------------------
 
/atlas_core/trunk/rtl/COM_0_CORE.vhd
6,7 → 6,7
-- # -> Parallel IO (16 in, 16 out) #
-- # -> System IO (8 in, 8 out) #
-- # ***************************************************** #
-- # Last modified: 05.03.2014 #
-- # Last modified: 12.04.2014 #
-- # ***************************************************** #
-- # by Stephan Nolting 4788, Hanover, Germany #
-- #########################################################
77,9 → 77,9
constant spi_cr_cpha_c : natural := 2; -- R/W: edge offset: 0: first edge, 1: second edge
constant spi_cr_bsy_c : natural := 3; -- R: transceiver is busy when '1'
constant spi_cr_auto_cs_c : natural := 4; -- R/W: Auto apply CS when '1'
constant uart_tx_busy_c : natural := 5; -- R: UART transmitter is busy
constant uart_tx_busy_c : natural := 5; -- R: UART transmitter is busy
constant uart_en_c : natural := 6; -- R/W: UART enable
-- constant : natural := 7; -- reserved
constant uart_ry_ovf_c : natural := 7; -- R: UART Rx overflow corruption
constant spi_cr_ln_lsb_c : natural := 8; -- R/W: data length lsb
constant spi_cr_ln_msb_c : natural := 11; -- R/W: data length msb
constant spi_cr_prsc_lsb_c : natural := 12; -- R/W: SPI clock prescaler lsb
95,6 → 95,7
-- UART Transceiver --
signal UART_RX_SYNC : std_logic_vector(03 downto 0);
signal UART_TX_BSY_FLAG : std_logic;
signal UART_DCOR_FLAG : std_logic;
signal UART_RX_BSY_FLAG : std_logic;
signal UART_TX_SREG : std_logic_vector(09 downto 0);
signal UART_RX_SREG : std_logic_vector(09 downto 0);
191,7 → 192,7
-- Read Access -----------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
R_ACC: process(ADR_I, UART_TX_BSY_FLAG, UART_RX_READY, UART_RX_REG, UART_PRSC_REG, COM_CONFIG_REG,
SPI_BUSY_FLAG, SPI_CS_REG, SPI_RX_REG, PIO_OUT_DATA, PIO_IN_DATA, SYS_IO_I_FF)
SPI_BUSY_FLAG, SPI_CS_REG, SPI_RX_REG, PIO_OUT_DATA, PIO_IN_DATA, SYS_IO_I_FF, UART_DCOR_FLAG)
begin
case (ADR_I) is
when uart_rtx_sd_reg_c => DAT_O <= (others => '0');
198,9 → 199,10
DAT_O(7 downto 0) <= UART_RX_REG;
DAT_O(uart_rx_ready_c) <= UART_RX_READY;
when uart_prsc_reg_c => DAT_O <= UART_PRSC_REG;
when com_ctrl_reg_c => DAT_O <= COM_CONFIG_REG;
DAT_O(spi_cr_bsy_c) <= SPI_BUSY_FLAG;
DAT_O(uart_tx_busy_c) <= UART_TX_BSY_FLAG;
when com_ctrl_reg_c => DAT_O <= COM_CONFIG_REG;
DAT_O(spi_cr_bsy_c) <= SPI_BUSY_FLAG;
DAT_O(uart_tx_busy_c) <= UART_TX_BSY_FLAG;
DAT_O(uart_ry_ovf_c) <= UART_DCOR_FLAG;
when spi_data_reg_c => DAT_O <= SPI_RX_REG;
when spi_cs_reg_c => DAT_O <= x"00" & SPI_CS_REG;
when pio_in_reg_c => DAT_O <= PIO_IN_DATA;
220,13 → 222,16
if (RST_I = '1') then
UART_RX_READY <= '0';
UART_RX_READY_SYNC <= '0';
UART_DCOR_FLAG <= '0';
else
-- Ready Flag --
-- Ready flag and corruption flag --
UART_RX_READY_SYNC <= UART_RX_BSY_FLAG;
if (UART_RX_READY = '1') and (R_EN_I = '1') and (ADR_I = uart_rtx_sd_reg_c) and (ICE_I = '1') then
UART_RX_READY <= '0';
UART_RX_READY <= '0';
UART_DCOR_FLAG <= '0';
elsif (UART_RX_READY_SYNC = '1') and (UART_RX_BSY_FLAG = '0') then -- falling edge
UART_RX_READY <= '1';
UART_RX_READY <= '1';
UART_DCOR_FLAG <= UART_RX_READY;
end if;
end if;
end if;
/atlas_core/trunk/rtl/SYS_0_CORE.vhd
5,7 → 5,7
-- # -> High Precision Timer (16+16 bit) #
-- # -> Linear-Feedback Shift Register (16 bit) #
-- # ***************************************************** #
-- # Last modified: 29.01.2014 #
-- # Last modified: 13.04.2014 #
-- # ***************************************************** #
-- # by Stephan Nolting 4788, Hanover, Germany #
-- #########################################################
107,7 → 107,7
IRQ_SYNC_0 <= (others => '0');
IRQ_SYNC_1 <= (others => '0');
else
-- IRQ write access --
-- IRQ CTRL write access --
if (W_EN_I = '1') and (ICE_I = '1') and ((ADR_I = irq_sm_reg_c) or (ADR_I = irq_conf_reg_c)) then
if (ADR_I = irq_sm_reg_c) then
IRQ_MASK_REG <= DAT_I(15 downto 08);
168,7 → 168,7
TMR_THRES_ZERO <= '1' when (TMR_THR_REG = x"0000") else '0';
 
-- Timer IRQ --
TIMER_IRQ_O <= '1' when ((TMR_CNT_REG = TMR_THR_REG) and (TMR_THRES_ZERO = '0')) else '0';
TIMER_IRQ_O <= '1' when ((TMR_CNT_REG = TMR_THR_REG) and (TMR_THRES_ZERO = '0')) else '0';
 
 
 
/atlas_core/trunk/rtl/COM_1_CORE.vhd
1,10 → 1,10
-- #########################################################
-- # << ATLAS Project - Communication Controller 1 >> #
-- # ***************************************************** #
-- # Wishbone Bus Adapter #
-- # -> 32-bit address, 16-bit data #
-- # -> Variable Length Burst-Transfers #
-- # -> Bus access is pipelined #
-- # - Wishbone Bus Adapter #
-- # -> 32-bit address, 16-bit data #
-- # -> Variable Length Burst-Transfers #
-- # -> Bus access is pipelined #
-- # ***************************************************** #
-- # Last modified: 10.04.2014 #
-- # ***************************************************** #
49,6 → 49,7
WB_CYC_O : out std_logic; -- cycle enable
WB_STB_O : out std_logic; -- strobe
WB_ACK_I : in std_logic; -- acknowledge
-- WB_HALT_I : in std_logic; -- halt transfer
WB_ERR_I : in std_logic -- bus error
);
end COM_1_CORE;
142,7 → 143,7
TIMEOUT_IRQ_EN <= DAT_I(timeout_en_irq_c);
when base_adr_l_reg_c => BASE_ADR(15 downto 00) <= DAT_I;
when base_adr_h_reg_c => BASE_ADR(31 downto 16) <= DAT_I;
when adr_offset_c => ADR_OFFSET <= DAT_I;
when adr_offset_c => ADR_OFFSET <= DAT_I;
when timeout_val_c => TIMEOUT_VAL <= DAT_I;
when others => NULL;
end case;
219,7 → 220,7
ADR_OFFSET_COMP: process(ADR_OFFSET)
begin
WB_ADR_OFFSET(15 downto 0) <= ADR_OFFSET;
for i in 16 to 31 loop
for i in 16 to 31 loop -- sign extension
WB_ADR_OFFSET(i) <= ADR_OFFSET(15);
end loop;
end process ADR_OFFSET_COMP;
/atlas_core/trunk/doc/Atlas 2k Processor Documentary.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/atlas_core/trunk/software/bootloader/atlas2k_bootloader.asm
34,7 → 34,8
; usr_r4: Image name (4,5)
; usr_r5: Image name (6,7)
; usr_r6: Image name (8,9)
; usr_r7: Checksum computation
; usr_r7: GP global variable
; LFSR_data: Checksum computation
; *****************************************************************************************************************
; *****************************************************************************************************************
 
93,7 → 94,7
; print error message
ldil r2, low[string_err_irq]
ldih r2, high[string_err_irq]
bl uart_print_br__
bl uart_print__
 
b #+0 ; freeze
 
106,27 → 107,20
mcr #1, sys1_core, r0, #0
mcr #1, sys1_core, r0, #2
 
; disable lfsr and timer
ldil r0, #0x00
; init MSR
ldil r7, #0x00
ldih r7, #0xF8 ; sys_mode, prv_sys_mode, g_irq_en, int1_en, int0_en
stsr r7
 
; disable irq ctrl, lfsr and timer
CLR R0 ; ZERO
mcr #1, sys0_core, r0, #0 ; clear irq mask register
mcr #1, sys0_core, r0, #3 ; clear timer threshold - disable timer
mcr #1, sys0_core, r0, #6 ; clear lfsr polynomial register - disable lfsr
 
; setup IRQ controller (for network adapter)
ldih r0, #0b00000010 ; network adapter - channel 1
mcr #1, sys0_core, r0, #0 ; set irq mask register
ldil r0, #0xff
mcr #1, sys0_core, r0, #1 ; set irq config register - all rising edge
mrc #1, r0, sys0_core, #0 ; ack pending IRQs
 
; init MSR
ldil r1, #0x00
ldih r1, #0xF8 ; sys_mode, prv_sys_mode, g_irq_en, int1_en, int0_en
stsr r1
 
; setup Wishbone bus controller
ldil r0, #0b00110000 ; bus error and timeout error IRQ enable
ldih r0, #0 ; burst size = 1 word
mcr #1, com1_core, r0, #0 ; set WB ctrl reg
mcr #1, com1_core, r0, #0 ; set WB ctrl reg (burst size = 1, all options disabled)
ldil r0, #0x02 ; offset = 1 word
mcr #1, com1_core, r0, #3 ; set WB address offset reg
ldil r0, #100 ; timeout = 100 cycles
133,8 → 127,8
mcr #1, com1_core, r0, #5 ; set WB timeout reg
 
; alive LED
ldih r0, #0x01
mcr #1, com0_core, r0, #7 ; set system output
ldih r2, #0x01
mcr #1, com0_core, r2, #7 ; set system output
 
; get system clock frequency
mrc #1, r0, sys1_core, #7 ; clock low
163,11 → 157,9
mcr #1, com0_core, r0, #2 ; com ctrl reg
 
; print intro
bl uart_linebreak__
bl uart_linebreak__
ldil r2, low[string_intro0]
ldih r2, high[string_intro0]
bl uart_print_br__
bl uart_print__
 
; print boot page
ldil r2, low[string_intro3]
175,7 → 167,6
bl uart_print__
mrc #1, r4, sys1_core, #1 ; get sys i-page
bl print_hex_string__
bl uart_linebreak__
 
; print clock speed
ldil r2, low[string_intro4]
204,25 → 195,12
; -----------------------------------------------------------------------------------
start_console:
; print menu
bl uart_linebreak__
ldil r2, low[string_menu_hd]
ldih r2, high[string_menu_hd]
bl uart_print_br__
ldil r2, low[string_menu0]
ldih r2, high[string_menu0]
bl uart_print_br__
bl uart_print__
ldil r2, low[string_menup]
ldih r2, high[string_menup]
bl uart_print_br__
ldil r2, low[string_menud]
ldih r2, high[string_menud]
bl uart_print_br__
ldil r2, low[string_menur]
ldih r2, high[string_menur]
bl uart_print_br__
ldil r2, low[string_menuw]
ldih r2, high[string_menuw]
bl uart_print_br__
bl uart_print__
 
console_input:
ldil r2, low[string_menux]
233,7 → 211,7
console_wait:
bl uart_receivebyte__ ; wait for user input
mov r6, r0 ; backup for selector
mov r1, r6 ; backup for echo
mov r1, r0 ; backup for echo
bl uart_sendbyte__ ; echo selection
bl uart_linebreak__
 
255,6 → 233,18
cmp r1, r6
beq boot_memory ; boot from memory
 
ldil r1, #'4'
cmp r1, r6
beq boot_wishbone ; boot from wishbone device
 
ldil r1, #'?'
cmp r1, r6
bne #+5
ldil r2, low[keepin_it_country]
ldih r2, high[keepin_it_country]
bl uart_print__
b console_input
 
ldil r5, low[burn_eeprom]
ldih r5, high[burn_eeprom]
ldil r1, #'p'
261,27 → 251,28
cmp r1, r6
rbaeq r5 ; program eeprom
 
ldil r5, low[mem_dump]
ldih r5, high[mem_dump]
ldil r1, #'d'
cmp r1, r6
rbaeq r5 ; ram dump
beq mem_dump ; ram dump
 
ldil r5, low[wb_dump]
ldih r5, high[wb_dump]
ldil r1, #'w'
cmp r1, r6
rbaeq r5 ; ram dump
rbaeq r5 ; wishbone dump
 
ldil r1, #'r'
cmp r1, r6
bne console_input ; invalid input
 
; do 'hard' reset
; HARD restart - back to bootloader page
clr r0
ldil r1, #0x00
ldih r1, #0x80
mcr #1, sys1_core, r1, #1
gt r0
 
 
keepin_it_country: .stringz "Keepin' it country!\n"
; -----------------------------------------------------------------------------------
; Booting from memory
; -----------------------------------------------------------------------------------
288,7 → 279,7
boot_memory:
ldil r2, low[string_booting]
ldih r2, high[string_booting]
bl uart_print_br__
bl uart_print__
 
; print no image info on start-up
clr r0
300,7 → 291,6
; -----------------------------------------------------------------------------------
; Intermediate Brach Stops - Stop 2
; -----------------------------------------------------------------------------------
uart_print_br__: b uart_print_br_
uart_print__: b uart_print_
uart_linebreak__: b uart_linebreak_
uart_sendbyte__: b uart_sendbyte_
309,6 → 299,79
 
 
; -----------------------------------------------------------------------------------
; Booting from Wishbone device
; -----------------------------------------------------------------------------------
boot_wishbone:
; get and set base address
ldil r2, low[string_ewbadr]
ldih r2, high[string_ewbadr]
bl uart_print_
 
; get and set base address (32-bit)
bl receive_hex_word_
mcr #1, com1_core, r4, #2 ; set high part of base address
bl receive_hex_word_
mcr #1, com1_core, r4, #1 ; set low part of base address
ldil r0, low[user_wait] ; wait for user to acknowledge
ldih r0, high[user_wait]
gtl r0
bl uart_linebreak_
 
; get signature
bl wb_read_word__ ; get word from Wishbone
ldil r0, #0xFE
ldih r0, #0xCA
cmp r0, r6
bne signature_err_
 
; get size
bl wb_read_word__ ; get word from Wishbone
sft r6, r6, #lsl ; size in words!
stub r0, r6
 
; get checksum
bl wb_read_word__ ; get word from Wishbone
stub r1, r6
 
; get image name
bl wb_read_word__ ; get word from Wishbone
stub r2, r6
 
bl wb_read_word__ ; get word from Wishbone
stub r3, r6
 
bl wb_read_word__ ; get word from Wishbone
stub r4, r6
 
bl wb_read_word__ ; get word from Wishbone
stub r5, r6
 
bl wb_read_word__ ; get word from Wishbone
stub r6, r6
 
; download program
ldil r5, #0 ; base address MEMORY = 0x0000
mcr #1, sys1_core, r5, #2 ; set system d-page
mcr #1, sys0_core, r5, #5 ; set checksum = 0
 
boot_wishbone_loop:
bl wb_read_word__ ; get word
str r6, r5, +#2, post, ! ; save to data mem
 
; update checksum
mrc #1, r0, sys0_core, #5 ; get checksum
eor r0, r0, r6
mcr #1, sys0_core, r0, #5 ; set checksum
 
; check size counter
ldub r0, r0
cmp r5, r0 ; done?
bne boot_wishbone_loop
 
b download_completed
 
 
; -----------------------------------------------------------------------------------
; Booting from SPI EEPROM
; -----------------------------------------------------------------------------------
boot_eeprom:
315,15 → 378,11
; intro
ldil r2, low[string_booting]
ldih r2, high[string_booting]
bl uart_print_br_
bl uart_print_
 
; get signature
ldil r2, #0
bl spi_eeprom_read_byte__ ; read byte from eeprom
sft r5, r3, #swp
ldil r2, #1
bl spi_eeprom_read_byte__ ; read byte from eeprom
orr r5, r5, r3
bl eeprom_get_word ; get word from EEPROM
ldil r0, #0xFE
ldih r0, #0xCA
cmp r0, r5
331,102 → 390,77
 
; get size
ldil r2, #2
bl spi_eeprom_read_byte__ ; read byte from eeprom
sft r5, r3, #swp
ldil r2, #3
bl spi_eeprom_read_byte__ ; read byte from eeprom
orr r5, r5, r3
bl eeprom_get_word ; get word from EEPROM
sft r5, r5, #lsl ; size in words!
stub r0, r5
 
; get checksum
ldil r2, #4
bl spi_eeprom_read_byte__ ; read byte from eeprom
sft r5, r3, #swp
ldil r2, #5
bl spi_eeprom_read_byte__ ; read byte from eeprom
orr r5, r5, r3
bl eeprom_get_word ; get word from EEPROM
stub r1, r5
 
; get image name
ldil r2, #6
bl spi_eeprom_read_byte__ ; read byte from eeprom
sft r5, r3, #swp
ldil r2, #7
bl spi_eeprom_read_byte__ ; read byte from eeprom
orr r5, r5, r3
bl eeprom_get_word ; get word from EEPROM
stub r2, r5
 
ldil r2, #8
bl spi_eeprom_read_byte__ ; read byte from eeprom
sft r5, r3, #swp
ldil r2, #9
bl spi_eeprom_read_byte__ ; read byte from eeprom
orr r5, r5, r3
bl eeprom_get_word ; get word from EEPROM
stub r3, r5
 
ldil r2, #10
bl spi_eeprom_read_byte__ ; read byte from eeprom
sft r5, r3, #swp
ldil r2, #11
bl spi_eeprom_read_byte__ ; read byte from eeprom
orr r5, r5, r3
bl eeprom_get_word ; get word from EEPROM
stub r4, r5
 
ldil r2, #12
bl spi_eeprom_read_byte__ ; read byte from eeprom
sft r5, r3, #swp
ldil r2, #13
bl spi_eeprom_read_byte__ ; read byte from eeprom
orr r5, r5, r3
bl eeprom_get_word ; get word from EEPROM
stub r5, r5
 
ldil r2, #14
bl spi_eeprom_read_byte__ ; read byte from eeprom
sft r5, r3, #swp
ldil r2, #15
bl spi_eeprom_read_byte__ ; read byte from eeprom
orr r5, r5, r3
bl eeprom_get_word ; get word from EEPROM
stub r6, r5
 
; download program
ldil r6, #0 ; base address MEMORY = 0x0000
mcr #1, sys1_core, r6, #2 ; set system d-page
stub r7, r6 ; init checksum computation
ldil r4, #0 ; base address MEMORY = 0x0000
mcr #1, sys1_core, r4, #2 ; set system d-page
mcr #1, sys0_core, r4, #5 ; set checksum = 0
 
boot_eeprom_loop:
ldil r0, #16
add r2, r6, r0 ; high = base EEPROM = base MEM +16
bl spi_eeprom_read_byte__ ; get high-byte
sft r5, r3, #swp ; swap bytes
ldil r0, #16 ; base offset
add r2, r4, r0 ; access EEPROM = MEM_pnt +16
bl eeprom_get_word ; get word from (address in r2)
str r5, r4, +#2, post, ! ; save to data mem
 
ldil r0, #17
add r2, r6, r0 ; low = base EEPROM = base MEM +17
bl spi_eeprom_read_byte__ ; get low-byte
orr r5, r5, r3 ; construct word
 
str r5, r6, +#2, post, ! ; save to data mem
 
; update checksum
ldub r0, r7
mrc #1, r0, sys0_core, #5 ; get checksum
eor r0, r0, r5
stub r7, r0
mcr #1, sys0_core, r0, #5 ; set checksum
 
; check size counter
ldub r0, r0
cmp r6, r0 ; done?
cmp r4, r0 ; done?
bne boot_eeprom_loop
 
b download_completed
 
 
; get word from (address in r2)
eeprom_get_word:
mov r6, lr
bl spi_eeprom_read_byte__ ; read byte from eeprom
sft r5, r3, #swp
inc r2, r2, #1
bl spi_eeprom_read_byte__ ; read byte from eeprom
orr r5, r5, r3
ret r6
 
 
; -----------------------------------------------------------------------------------
; Booting from UART
; -----------------------------------------------------------------------------------
boot_uart: ldil r2, low[string_booting]
ldih r2, high[string_booting]
bl uart_print_br_
ldil r2, low[string_boot_wimd]
boot_uart: ldil r2, low[string_boot_wimd]
ldih r2, high[string_boot_wimd]
bl uart_print_br_
bl uart_print_
 
; check signature (2 byte)
bl uart_receivebyte_ ; get high-byte
439,69 → 473,48
bne signature_err_
 
; get program size (2 byte)
bl uart_receivebyte_ ; get high-byte
sft r1, r0, #swp ; swap bytes
bl uart_receivebyte_ ; get low-byte
orr r1, r1, r0 ; construct word
bl uart_get_word ; get a word from console
sft r1, r1, #lsl ; #bytes = 2*#words
stub r0, r1
 
; get checksum (2 byte)
bl uart_receivebyte_ ; get high-byte
sft r1, r0, #swp ; swap bytes
bl uart_receivebyte_ ; get low-byte
orr r1, r1, r0 ; construct word
bl uart_get_word ; get a word from console
stub r1, r1
 
; get image name (10 byte)
bl uart_receivebyte_ ; get high-byte
sft r1, r0, #swp ; swap bytes
bl uart_receivebyte_ ; get low-byte
orr r1, r1, r0 ; construct word
bl uart_get_word ; get a word from console
stub r2, r1
bl uart_receivebyte_ ; get high-byte
sft r1, r0, #swp ; swap bytes
bl uart_receivebyte_ ; get low-byte
orr r1, r1, r0 ; construct word
bl uart_get_word ; get a word from console
stub r3, r1
bl uart_receivebyte_ ; get high-byte
sft r1, r0, #swp ; swap bytes
bl uart_receivebyte_ ; get low-byte
orr r1, r1, r0 ; construct word
bl uart_get_word ; get a word from console
stub r4, r1
bl uart_receivebyte_ ; get high-byte
sft r1, r0, #swp ; swap bytes
bl uart_receivebyte_ ; get low-byte
orr r1, r1, r0 ; construct word
stub r5 r1
bl uart_receivebyte_ ; get high-byte
sft r1, r0, #swp ; swap bytes
bl uart_receivebyte_ ; get low-byte
orr r1, r1, r0 ; construct word
bl uart_get_word ; get a word from console
stub r5, r1
bl uart_get_word ; get a word from console
stub r6, r1
 
; init download
clr r5 ; address = 0x00000000
mcr #1, sys1_core, r5, #2 ; set system d-page
stub r7, r5 ; init checksum computation
mcr #1, sys0_core, r5, #5 ; set checksum = 0
 
; downloader
uart_downloader:
bl uart_receivebyte_ ; get high-byte
sft r1, r0, #swp ; swap bytes
bl uart_receivebyte_ ; get low-byte
orr r1, r1, r0 ; construct word
bl uart_get_word ; get a word from console
str r1, r5, +#2, post, ! ; save to data mem
 
; update checksum
ldub r0, r7
mrc #1, r0, sys0_core, #5 ; get checksum
eor r0, r0, r1
stub r7, r0
mcr #1, sys0_core, r0, #5 ; set checksum
 
ldub r0, r0
cmp r5, r0 ; done?
bne uart_downloader
 
 
; image download completed - prepare image launch
; ---------------------------------------------------
download_completed:
; re-init system d page
mrc #1, r0, sys1_core, #1 ; get sys i-page
510,10 → 523,10
; download completed
ldil r2, low[string_done]
ldih r2, high[string_done]
bl uart_print_br_
bl uart_print_
 
; transfer done - check checksum
ldub r0, r7
mrc #1, r0, sys0_core, #5 ; get checksum
ldub r1, r1
cmp r0, r1
beq start_image
521,19 → 534,23
; checksum error!
ldil r2, low[string_err_check]
ldih r2, high[string_err_check]
bl uart_print_br_
ldil r2, low[string_err_res]
ldih r2, high[string_err_res]
bl uart_print_br_
bl uart_receivebyte_ ; wait for any key input
clr r0
gt r0 ; restart
bl uart_print_
b resume_error_ ; resume error
 
 
; get a full word via console
uart_get_word:
mov r6, lr
bl uart_receivebyte_ ; get high-byte
sft r1, r0, #swp ; swap bytes
bl uart_receivebyte_ ; get low-byte
orr r1, r1, r0 ; construct word
ret r6
 
 
; -----------------------------------------------------------------------------------
; Intermediate Brach Stops - Stop 1
; -----------------------------------------------------------------------------------
uart_print_br_: b uart_print_br
uart_print_: b uart_print
uart_linebreak_: b uart_linebreak
uart_sendbyte_: b uart_sendbyte
542,6 → 559,8
signature_err_: b signature_err
console_input_: b console_input
print_hex_string_: b print_hex_string0
wb_read_word__: b wb_read_word_
receive_hex_word_: b receive_hex_word
 
 
; -----------------------------------------------------------------------------------
548,6 → 567,14
; Start image from memory
; -----------------------------------------------------------------------------------
start_image:
; print checksum
ldil r2, low[string_checksum]
ldih r2, high[string_checksum]
bl uart_print
mrc #1, r4, sys0_core, #5 ; get checksum
bl print_hex_string ; print computed checksum
bl uart_linebreak
 
ldil r2, low[string_start_im]
ldih r2, high[string_start_im]
bl uart_print
559,61 → 586,35
ldil r1, #34 ;'"'
bl uart_sendbyte
ldub r1, r2
sft r1, r1, #swp
bl uart_sendbyte
sft r1, r1, #swp
bl uart_sendbyte
bl start_image_print_name_sub
ldub r1, r3
sft r1, r1, #swp
bl uart_sendbyte
sft r1, r1, #swp
bl uart_sendbyte
bl start_image_print_name_sub
ldub r1, r4
sft r1, r1, #swp
bl uart_sendbyte
sft r1, r1, #swp
bl uart_sendbyte
bl start_image_print_name_sub
ldub r1, r5
sft r1, r1, #swp
bl uart_sendbyte
sft r1, r1, #swp
bl uart_sendbyte
bl start_image_print_name_sub
ldub r1, r6
sft r1, r1, #swp
bl uart_sendbyte
sft r1, r1, #swp
bl uart_sendbyte
bl start_image_print_name_sub
ldil r1, #34 ;'"'
bl uart_sendbyte
bl uart_linebreak
 
; print checksum
ldil r2, low[string_checksum]
ldih r2, high[string_checksum]
bl uart_print
ldub r4, r7 ; print computed checksum
bl print_hex_string0
 
; some final line breaks
; start the image
start_image_no_text:
bl uart_linebreak
bl uart_linebreak
 
; re-init MSR
ldil r1, #0x00
ldih r1, #0xC0 ; current/prev mode = sys
stsr r1
 
CLR R0 ; ZERO!
 
; re-init MSR
sbr r3, r0, #14 ; prv_sys_mode
sbr r3, r3, #15 ; sys_mode
stsr r3
 
; clear alive LED
mcr #1, com0_core, r0, #7 ; set system output
 
; set IRQ base address
mcr #1, sys1_core, r0, #0
 
; set mmu pages, address: 0x0000
mcr #1, sys1_core, r0, #0
mcr #1, sys1_core, r0, #0 ; irq base address
mcr #1, sys1_core, r0, #3
mcr #1, sys1_core, r0, #4
mcr #1, sys1_core, r0, #2 ; d-page - set first
621,6 → 622,15
gt r0 ; start image at 0x0000 & 0x0000
 
 
start_image_print_name_sub:
mov r6, lr
sft r1, r1, #swp
bl uart_sendbyte
sft r1, r1, #swp
bl uart_sendbyte
ret r6
 
 
; -----------------------------------------------------------------------------------
; RAM page dump via console
; -----------------------------------------------------------------------------------
632,18 → 642,11
bl receive_hex_word
 
; wait for enter/abort
mem_dump_wait:
bl uart_receivebyte
ldil r1, #0x0D ; CR - enter
cmp r0, r1
beq mem_dump_continue
ldil r1, #0x08 ; Backspace - abort
cmp r0, r1
bne mem_dump_wait
bl uart_linebreak
b console_input_ ; restart terminal prompt
ldil r2, low[user_wait]
ldih r2, high[user_wait]
gtl r2
 
mem_dump_continue:
; let's go
mcr #1, sys1_core, r4, #2 ; set d-page
bl uart_linebreak
 
660,7 → 663,7
ldil r1, #36 ; '$'
bl uart_sendbyte
mov r4, r5
bl print_hex_string ; print 4hex address
bl print_hex_string ; print 4hex byte address
ldil r1, #58 ; ':'
bl uart_sendbyte
ldil r1, #32 ; ' '
743,10 → 746,10
; we are ready! - waiting for image data...
ldil r2, low[string_prog_eep]
ldih r2, high[string_prog_eep]
bl uart_print_br
bl uart_print
ldil r2, low[string_boot_wimd]
ldih r2, high[string_boot_wimd]
bl uart_print_br
bl uart_print
 
; get signature
bl uart_receivebyte ; get high-byte
760,11 → 763,9
 
; write signature (2 bytes)
ldil r2, #0
ldil r3, #0xCA
bl spi_eeprom_write_byte
ldil r2, #1
ldil r3, #0xFE
bl spi_eeprom_write_byte
ldil r5, #0xFE
ldih r5, #0xCA
bl eeprom_write_word ; write word to eeprom
 
; get image size
bl uart_receivebyte ; get high-byte
776,11 → 777,7
 
; write image size (2 bytes)
ldil r2, #2
sft r3, r5, #swp
bl spi_eeprom_write_byte
ldil r2, #3
mov r3, r5
bl spi_eeprom_write_byte
bl eeprom_write_word ; write word to eeprom
 
; get checksum
bl uart_receivebyte ; get high-byte
791,11 → 788,7
 
; write checksum (2 bytes)
ldil r2, #4
sft r3, r5, #swp
bl spi_eeprom_write_byte
ldil r2, #5
mov r3, r5
bl spi_eeprom_write_byte
bl eeprom_write_word ; write word to eeprom
 
; write image name (10 bytes)
ldil r2, #6 ; base address
835,7 → 828,7
; we are done!
ldil r2, low[string_done]
ldih r2, high[string_done]
bl uart_print_br
bl uart_print
 
; return to main console
ldil r5, low[start_console]
843,6 → 836,17
gt r5
 
 
; write word in r5 to eeprom, address in r2
eeprom_write_word:
mov r6, lr
sft r3, r5, #swp
bl spi_eeprom_write_byte
inc r2, r2, #1
mov r3, r5
bl spi_eeprom_write_byte
ret r6
 
 
; -----------------------------------------------------------------------------------
; Signature error
; -----------------------------------------------------------------------------------
849,13 → 853,9
signature_err:
ldil r2, low[string_err_image]
ldih r2, high[string_err_image]
bl uart_print_br
ldil r2, low[string_err_res]
ldih r2, high[string_err_res]
bl uart_print_br
bl uart_receivebyte
clr r0
gt r0 ; restart
bl uart_print
resume_error_: ; interm. branch stop
b resume_error ; resume error
 
 
; *****************************************************************************************************************
866,29 → 866,17
; Intermediate Brach Stops
; -----------------------------------------------------------------------------------
spi_eeprom_read_byte0: b spi_eeprom_read_byte
wb_read_word_: b wb_read_word
 
 
; --------------------------------------------------------------------------------------------------------
; Print char-string (bytes) via CP1.COM_0.UART and send linebreak
; Arguments: r2 = address of string (string must be zero-terminated!)
; Results: -
; Used registers: r0, r1, r2, r3, r4, lr
uart_print_br:
; --------------------------------------------------------------------------------------------------------
ldil r3, #0xFF
mov r4, lr
b uart_print_loop
 
 
; --------------------------------------------------------------------------------------------------------
; Print char-string (bytes) via CP1.COM_0.UART
; Arguments: r2 = address of string (string must be zero-terminated!)
; Results: -
; Used registers: r0, r1, r2, r3, r4, lr
; Used registers: r0, r1, r2, r3, lr
uart_print:
; --------------------------------------------------------------------------------------------------------
clr r3
mov r4, lr
mov r3, lr
uart_print_loop:
ldr r0, r2, +#1, post, ! ; get one string byte
901,10 → 889,7
b uart_print_loop
 
uart_print_loop_end:
mov lr, r4
teq r3, r3 ; do linebreak?
rbaeq lr
; b uart_linebreak
ret r3
 
 
; --------------------------------------------------------------------------------------------------------
1055,18 → 1040,19
ret r6
 
; compute hex-char from 4-bit value of r2, result in r1
conv_hex_comp: ldil r1, #0x0f ; mask for lowest 4 bit
and r2, r2, r1
conv_hex_comp:
ldil r1, #0x0f ; mask for lowest 4 bit
and r2, r2, r1
 
ldil r1, #9
cmp r1, r2
bcs #+3
ldil r1, #9
cmp r1, r2
bcs #+3
 
ldil r1, #48 ; this is a '0'
b #+2
ldil r1, #55 ; this is an 'A'-10
add r1, r1, r2 ; resulting char in lower byte
ret lr
ldil r1, #48 ; this is a '0'
b #+2
ldil r1, #55 ; this is an 'A'-10
add r1, r1, r2 ; resulting char in lower byte
ret lr
 
 
; --------------------------------------------------------------------------------------------------------
1127,13 → 1113,8
; EEPROM ACCESS ERROR!
ldil r2, low[string_err_eep]
ldih r2, high[string_err_eep]
bl uart_print_br
ldil r2, low[string_err_res]
ldih r2, high[string_err_res]
bl uart_print_br
bl uart_receivebyte
clr r0
gt r0 ; restart
bl uart_print
b resume_error ; resume error
 
spi_eeprom_write:
; send write instruction and
1214,7 → 1195,7
; read data byte (16 bit trans)
; -------------------------------------------
mov r0, r2 ; copy address
ldih r0, #0x00 ; data tranfer dummy
ldih r0, #0x00 ; data transfer dummy
sft r0, r0, #swp ; swap data and address bytes
bl spi_trans ; iniatiate transmission
 
1226,7 → 1207,62
ret r1
 
 
; --------------------------------------------------------------------------------------------------------
; Reads 1 word from the Wishbone network (base address must be set before, word address increment)
; Arguments: -
; Results:
; r6 = data
; Used registers: r0, r1, r6 ,lr
wb_read_word:
; --------------------------------------------------------------------------------------------------------
cdp #1, com1_core, com1_core, #0 ; initiate read-transfer
 
mrc #1, r0, com1_core, #0 ; get WB status reg
stb r0, #6 ; busy flag -> t-flag
bts #-2 ; repeat until data is ready
 
; check word
ldil r6, #0b00000110 ; bus or timeout flag set?
ands r0, r0, r6
bne wb_read_word_err
 
; increment base address
mrc #1, r1, com1_core, #1 ; get WB base adr low
mrc #1, r6, com1_core, #2 ; get WB base adr high
clr r0
incs r1, r1, #2 ; inc 2 = one word
adc r6, r6, r0
mcr #1, com1_core, r1, #1 ; set low part of base address
mcr #1, com1_core, r6, #2 ; set high part of base address
 
mrc #1, r6, com1_core, #4 ; get data
ret lr
 
; WB access error (ERR or no ACK)
wb_read_word_err:
ldil r2, low[string_err_wb]
ldih r2, high[string_err_wb]
bl uart_print
; b resume_error
 
 
; -----------------------------------------------------------------------------------
; Fatal error! Press key to resume (restart bootloader)
; -----------------------------------------------------------------------------------
resume_error:
ldil r2, low[string_err_res]
ldih r2, high[string_err_res]
bl uart_print
bl uart_receivebyte ; wait for any key input
clr r0
gt r0 ; restart
 
 
; *****************************************************************************************************************
; Wishbone Access
; *****************************************************************************************************************
 
; -----------------------------------------------------------------------------------
; Wisbone Dump
; -----------------------------------------------------------------------------------
wb_dump: ldil r2, low[string_ewbadr]
1233,37 → 1269,43
ldih r2, high[string_ewbadr]
bl uart_print
 
; get and set address (32-bit)
; get and set base address (32-bit)
bl receive_hex_word
mcr #1, com1_core, r4, #2 ; set high part of base address
bl receive_hex_word
mcr #1, com1_core, r4, #1 ; set low part of base address
bl user_wait ; wait for user
bl uart_linebreak
 
wb_dump_wait:
; execute?
bl uart_receivebyte
ldil r1, #0x0D ; CR - enter
cmp r0, r1
beq wb_dump_proceed
; get number of entries (16-bit
ldil r2, low[string_ewbnum]
ldih r2, high[string_ewbnum]
bl uart_print
bl receive_hex_word
mov r5, r4
bl user_wait ; wait for user
 
; abort?
ldil r1, #0x08 ; Backspace - abort
cmp r0, r1
; download word from wishbone net
wb_dump_loop:
teq r5, r5
beq wb_dump_end
b wb_dump_wait
dec r5, r5, #1
 
; download word from wishbone net
wb_dump_proceed:
bl uart_linebreak
bl wb_read_word
mov r6, r0
 
; print it
ldil r2, low[string_data]
ldih r2, high[string_data]
ldil r2, low[string_wbhexpre]
ldih r2, high[string_wbhexpre]
bl uart_print
mov r4, r6
mov r4, r6 ; data from wishbone
bl print_hex_string
 
; user input?
mrc #1, r1, com0_core, #0 ; get uart status/data register
stb r1, #15 ; copy inverted uart rx_ready flag to T-flag
bts #+2
b wb_dump_loop
 
; return to main console
wb_dump_end:
bl uart_linebreak
1271,52 → 1313,44
ldih r5, high[console_input]
gt r5
 
; wait for user to cancel/proceed
user_wait: mov r2, lr
user_wait_: bl uart_receivebyte
ldil r1, #0x0D ; CR - enter
cmp r0, r1 ; execute?
rbaeq r2
ldil r1, #0x08 ; Backspace - abort
cmp r0, r1 ; abort?
beq wb_dump_end
b user_wait_
 
; --------------------------------------------------------------------------------------------------------
; Reads 1 word from the Wishbone network (base address must be set before, auto address increment)
; Arguments: -
; Results:
; r0 = data
; Used registers: r0 ,lr
wb_read_word:
; --------------------------------------------------------------------------------------------------------
cdp #1, com1_core, com1_core, #0 ; initiate read-transfer
mrc #1, r0, com1_core, #0 ; get WB status reg
stb r0, #6 ; busy flag -> t-flag
bts #-2 ; repeat until data is ready
 
mrc #1, r0, com1_core, #4 ; get data
ret lr
 
 
; *****************************************************************************************************************
; ROM: Text strings
; *****************************************************************************************************************
string_intro0: .stringz "\n\nAtlas-2K Bootloader - V20140414\nby Stephan Nolting, stnolting@gmail.com\nwww.opencores.org/project,atlas_core\n"
string_intro3: .stringz "\nBoot page: 0x"
string_intro4: .stringz "\nClock(Hz): 0x"
 
string_intro0: .stringz "Atlas-2K Bootloader - V20140410\nby Stephan Nolting, stnolting@gmail.com\nwww.opencores.org/project,atlas_core\n"
string_intro3: .stringz "Bootloader @ 0x"
string_intro4: .stringz "Clock (Hz): 0x"
 
string_booting: .stringz "Booting..."
string_prog_eep: .stringz "Burning EEPROM"
string_boot_wimd: .stringz "Waiting for image data..."
string_booting: .stringz "Booting\n"
string_prog_eep: .stringz "Burn EEPROM\n"
string_boot_wimd: .stringz "Waiting for data...\n"
string_start_im: .stringz "Starting image "
string_done: .stringz "Download completed!"
string_edpage: .stringz "Enter page (4hex): 0x"
string_ewbadr: .stringz "Enter addr (8hex): 0x"
string_checksum: .stringz "Checksum: 0x"
string_data: .stringz "\n-> 0x"
string_done: .stringz "Download complete\n"
string_edpage: .stringz "Page (4h): $"
string_ewbadr: .stringz "Addr (8h): $"
string_ewbnum: .stringz "#words (4h): $"
string_checksum: .stringz "Checksum: $"
string_wbhexpre: .stringz " -> $"
 
string_menu_hd: .stringz "cmd/boot-switch"
string_menu0: .stringz " 0/'00': Restart console\n 1/'01': Boot from UART\n 2/'10': Boot from EEPROM\n 3/'11': Boot from memory"
string_menup: .stringz " p: Burn EEPROM"
string_menud: .stringz " d: RAM dump"
string_menur: .stringz " r: Reset"
string_menuw: .stringz " w: WB dump"
 
string_menu0: .stringz "\ncmd/boot-switch:\n 0/'00': Restart console\n 1/'01': Boot UART\n 2/'10': Boot EEPROM\n 3/'11': Boot memory\n"
string_menup: .stringz " 4: Boot WB\n p: Burn EEPROM\n d: RAM dump\n r: Reset\n w: WB dump\n"
string_menux: .stringz "cmd:> "
 
string_err_image: .stringz "IMAGE ERR!"
string_err_irq: .stringz "\nIRQ ERR!"
string_err_check: .stringz "CHECKSUM ERR!"
string_err_eep: .stringz "SPI/EEPROM ERR!"
string_err_res: .stringz "Press any key"
string_err_image: .stringz "IMAGE ERR!\n"
string_err_irq: .stringz "\nIRQ ERR!\n"
string_err_check: .stringz "CHECKSUM ERR!\n"
string_err_eep: .stringz "SPI/EEPROM ERR!\n"
string_err_wb: .stringz "WB BUS ERR!\n"
string_err_res: .stringz "Press any key\n"

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